Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e3ec3a3d SB |
2 | /* |
3 | * Arasan Secure Digital Host Controller Interface. | |
4 | * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> | |
5 | * Copyright (c) 2012 Wind River Systems, Inc. | |
6 | * Copyright (C) 2013 Pengutronix e.K. | |
7 | * Copyright (C) 2013 Xilinx Inc. | |
8 | * | |
9 | * Based on sdhci-of-esdhc.c | |
10 | * | |
11 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
12 | * Copyright (c) 2009 MontaVista Software, Inc. | |
13 | * | |
14 | * Authors: Xiaobo Xie <X.Xie@freescale.com> | |
15 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
e3ec3a3d SB |
16 | */ |
17 | ||
c390f211 | 18 | #include <linux/clk-provider.h> |
3ea4666e | 19 | #include <linux/mfd/syscon.h> |
e3ec3a3d | 20 | #include <linux/module.h> |
308f3f8d | 21 | #include <linux/of_device.h> |
91aa3661 | 22 | #include <linux/phy/phy.h> |
3ea4666e | 23 | #include <linux/regmap.h> |
3794c542 | 24 | #include <linux/of.h> |
a5c8b2ae | 25 | #include <linux/firmware/xlnx-zynqmp.h> |
e3ec3a3d | 26 | |
84362d79 SL |
27 | #include "cqhci.h" |
28 | #include "sdhci-pltfm.h" | |
e3ec3a3d | 29 | |
84362d79 | 30 | #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 |
1a470721 MN |
31 | |
32 | #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8 | |
d338c6d0 MN |
33 | #define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF |
34 | ||
1a470721 | 35 | #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC |
d338c6d0 | 36 | #define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F |
1a470721 | 37 | |
84362d79 | 38 | #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 |
a05c8465 | 39 | #define VENDOR_ENHANCED_STROBE BIT(0) |
e3ec3a3d | 40 | |
b2db9c67 DA |
41 | #define PHY_CLK_TOO_SLOW_HZ 400000 |
42 | ||
1a470721 MN |
43 | #define SDHCI_ITAPDLY_CHGWIN 0x200 |
44 | #define SDHCI_ITAPDLY_ENABLE 0x100 | |
45 | #define SDHCI_OTAPDLY_ENABLE 0x40 | |
46 | ||
a5c8b2ae MN |
47 | /* Default settings for ZynqMP Clock Phases */ |
48 | #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0} | |
49 | #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0} | |
50 | ||
1a470721 MN |
51 | #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0} |
52 | #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0} | |
53 | ||
3ea4666e DA |
54 | /* |
55 | * On some SoCs the syscon area has a feature where the upper 16-bits of | |
56 | * each 32-bit register act as a write mask for the lower 16-bits. This allows | |
57 | * atomic updates of the register without locking. This macro is used on SoCs | |
58 | * that have that feature. | |
59 | */ | |
60 | #define HIWORD_UPDATE(val, mask, shift) \ | |
61 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
62 | ||
63 | /** | |
64 | * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map | |
65 | * | |
66 | * @reg: Offset within the syscon of the register containing this field | |
67 | * @width: Number of bits for this field | |
68 | * @shift: Bit offset within @reg of this field (or -1 if not avail) | |
69 | */ | |
70 | struct sdhci_arasan_soc_ctl_field { | |
71 | u32 reg; | |
72 | u16 width; | |
73 | s16 shift; | |
74 | }; | |
75 | ||
76 | /** | |
77 | * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers | |
78 | * | |
3ea4666e | 79 | * @baseclkfreq: Where to find corecfg_baseclkfreq |
b2ca77c9 | 80 | * @clockmultiplier: Where to find corecfg_clockmultiplier |
36c6aada | 81 | * @support64b: Where to find SUPPORT64B bit |
3ea4666e | 82 | * @hiword_update: If true, use HIWORD_UPDATE to access the syscon |
4908460e MN |
83 | * |
84 | * It's up to the licensee of the Arsan IP block to make these available | |
85 | * somewhere if needed. Presumably these will be scattered somewhere that's | |
86 | * accessible via the syscon API. | |
3ea4666e DA |
87 | */ |
88 | struct sdhci_arasan_soc_ctl_map { | |
89 | struct sdhci_arasan_soc_ctl_field baseclkfreq; | |
b2ca77c9 | 90 | struct sdhci_arasan_soc_ctl_field clockmultiplier; |
36c6aada | 91 | struct sdhci_arasan_soc_ctl_field support64b; |
3ea4666e DA |
92 | bool hiword_update; |
93 | }; | |
94 | ||
16ada730 MN |
95 | /** |
96 | * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller | |
97 | * | |
98 | * @sdcardclk_ops: The output clock related operations | |
99 | * @sampleclk_ops: The sample clock related operations | |
100 | */ | |
101 | struct sdhci_arasan_clk_ops { | |
102 | const struct clk_ops *sdcardclk_ops; | |
103 | const struct clk_ops *sampleclk_ops; | |
104 | }; | |
105 | ||
e1463618 | 106 | /** |
4908460e MN |
107 | * struct sdhci_arasan_clk_data - Arasan Controller Clock Data. |
108 | * | |
e1463618 MN |
109 | * @sdcardclk_hw: Struct for the clock we might provide to a PHY. |
110 | * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. | |
07a14d1d MN |
111 | * @sampleclk_hw: Struct for the clock we might provide to a PHY. |
112 | * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw. | |
f3dafc37 MN |
113 | * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes |
114 | * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes | |
115 | * @set_clk_delays: Function pointer for setting Clock Delays | |
a5c8b2ae | 116 | * @clk_of_data: Platform specific runtime clock data storage pointer |
e1463618 MN |
117 | */ |
118 | struct sdhci_arasan_clk_data { | |
119 | struct clk_hw sdcardclk_hw; | |
120 | struct clk *sdcardclk; | |
07a14d1d MN |
121 | struct clk_hw sampleclk_hw; |
122 | struct clk *sampleclk; | |
f3dafc37 MN |
123 | int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; |
124 | int clk_phase_out[MMC_TIMING_MMC_HS400 + 1]; | |
125 | void (*set_clk_delays)(struct sdhci_host *host); | |
a5c8b2ae MN |
126 | void *clk_of_data; |
127 | }; | |
128 | ||
e3ec3a3d | 129 | /** |
4908460e MN |
130 | * struct sdhci_arasan_data - Arasan Controller Data |
131 | * | |
c390f211 | 132 | * @host: Pointer to the main SDHCI host structure. |
3ea4666e DA |
133 | * @clk_ahb: Pointer to the AHB clock |
134 | * @phy: Pointer to the generic phy | |
b2db9c67 | 135 | * @is_phy_on: True if the PHY is on; false if not. |
4908460e | 136 | * @has_cqe: True if controller has command queuing engine. |
e1463618 | 137 | * @clk_data: Struct for the Arasan Controller Clock Data. |
16ada730 | 138 | * @clk_ops: Struct for the Arasan Controller Clock Operations. |
3ea4666e DA |
139 | * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. |
140 | * @soc_ctl_map: Map to get offsets into soc_ctl registers. | |
4908460e | 141 | * @quirks: Arasan deviations from spec. |
e3ec3a3d SB |
142 | */ |
143 | struct sdhci_arasan_data { | |
c390f211 | 144 | struct sdhci_host *host; |
e3ec3a3d | 145 | struct clk *clk_ahb; |
91aa3661 | 146 | struct phy *phy; |
b2db9c67 | 147 | bool is_phy_on; |
3ea4666e | 148 | |
84362d79 | 149 | bool has_cqe; |
e1463618 | 150 | struct sdhci_arasan_clk_data clk_data; |
16ada730 | 151 | const struct sdhci_arasan_clk_ops *clk_ops; |
c390f211 | 152 | |
3ea4666e DA |
153 | struct regmap *soc_ctl_base; |
154 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
4908460e | 155 | unsigned int quirks; |
3794c542 ZB |
156 | |
157 | /* Controller does not have CD wired and will not function normally without */ | |
158 | #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) | |
3f2c7d5d HG |
159 | /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the |
160 | * internal clock even when the clock isn't stable */ | |
161 | #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) | |
c0b4e411 MN |
162 | /* |
163 | * Some of the Arasan variations might not have timing requirements | |
164 | * met at 25MHz for Default Speed mode, those controllers work at | |
165 | * 19MHz instead | |
166 | */ | |
167 | #define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2) | |
3ea4666e DA |
168 | }; |
169 | ||
06b23ca0 FA |
170 | struct sdhci_arasan_of_data { |
171 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
172 | const struct sdhci_pltfm_data *pdata; | |
16ada730 | 173 | const struct sdhci_arasan_clk_ops *clk_ops; |
06b23ca0 FA |
174 | }; |
175 | ||
3ea4666e DA |
176 | static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { |
177 | .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, | |
b2ca77c9 | 178 | .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, |
3ea4666e | 179 | .hiword_update = true, |
e3ec3a3d SB |
180 | }; |
181 | ||
5c1a4f40 RVM |
182 | static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = { |
183 | .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 }, | |
184 | .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, | |
185 | .hiword_update = false, | |
186 | }; | |
187 | ||
d1807ad6 RVM |
188 | static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = { |
189 | .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 }, | |
190 | .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, | |
191 | .hiword_update = false, | |
192 | }; | |
193 | ||
36c6aada WAZ |
194 | static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = { |
195 | .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 }, | |
196 | .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, | |
197 | .support64b = { .reg = 0x4, .width = 1, .shift = 24 }, | |
198 | .hiword_update = false, | |
199 | }; | |
200 | ||
3ea4666e DA |
201 | /** |
202 | * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers | |
203 | * | |
4908460e MN |
204 | * @host: The sdhci_host |
205 | * @fld: The field to write to | |
206 | * @val: The value to write | |
207 | * | |
3ea4666e DA |
208 | * This function allows writing to fields in sdhci_arasan_soc_ctl_map. |
209 | * Note that if a field is specified as not available (shift < 0) then | |
210 | * this function will silently return an error code. It will be noisy | |
211 | * and print errors for any other (unexpected) errors. | |
212 | * | |
4908460e | 213 | * Return: 0 on success and error value on error |
3ea4666e DA |
214 | */ |
215 | static int sdhci_arasan_syscon_write(struct sdhci_host *host, | |
216 | const struct sdhci_arasan_soc_ctl_field *fld, | |
217 | u32 val) | |
218 | { | |
219 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
220 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
221 | struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; | |
222 | u32 reg = fld->reg; | |
223 | u16 width = fld->width; | |
224 | s16 shift = fld->shift; | |
225 | int ret; | |
226 | ||
227 | /* | |
228 | * Silently return errors for shift < 0 so caller doesn't have | |
229 | * to check for fields which are optional. For fields that | |
230 | * are required then caller needs to do something special | |
231 | * anyway. | |
232 | */ | |
233 | if (shift < 0) | |
234 | return -EINVAL; | |
235 | ||
236 | if (sdhci_arasan->soc_ctl_map->hiword_update) | |
237 | ret = regmap_write(soc_ctl_base, reg, | |
238 | HIWORD_UPDATE(val, GENMASK(width, 0), | |
239 | shift)); | |
240 | else | |
241 | ret = regmap_update_bits(soc_ctl_base, reg, | |
242 | GENMASK(shift + width, shift), | |
243 | val << shift); | |
244 | ||
245 | /* Yell about (unexpected) regmap errors */ | |
246 | if (ret) | |
247 | pr_warn("%s: Regmap write fail: %d\n", | |
248 | mmc_hostname(host->mmc), ret); | |
249 | ||
250 | return ret; | |
251 | } | |
252 | ||
802ac39a SL |
253 | static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) |
254 | { | |
255 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
256 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
f3dafc37 | 257 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; |
6fc09244 | 258 | bool ctrl_phy = false; |
802ac39a | 259 | |
b2db9c67 DA |
260 | if (!IS_ERR(sdhci_arasan->phy)) { |
261 | if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { | |
262 | /* | |
263 | * If PHY off, set clock to max speed and power PHY on. | |
264 | * | |
265 | * Although PHY docs apparently suggest power cycling | |
266 | * when changing the clock the PHY doesn't like to be | |
267 | * powered on while at low speeds like those used in ID | |
268 | * mode. Even worse is powering the PHY on while the | |
269 | * clock is off. | |
270 | * | |
271 | * To workaround the PHY limitations, the best we can | |
272 | * do is to power it on at a faster speed and then slam | |
273 | * through low speeds without power cycling. | |
274 | */ | |
275 | sdhci_set_clock(host, host->max_clk); | |
b2db9c67 | 276 | phy_power_on(sdhci_arasan->phy); |
b2db9c67 DA |
277 | sdhci_arasan->is_phy_on = true; |
278 | ||
279 | /* | |
280 | * We'll now fall through to the below case with | |
281 | * ctrl_phy = false (so we won't turn off/on). The | |
282 | * sdhci_set_clock() will set the real clock. | |
283 | */ | |
284 | } else if (clock > PHY_CLK_TOO_SLOW_HZ) { | |
285 | /* | |
286 | * At higher clock speeds the PHY is fine being power | |
287 | * cycled and docs say you _should_ power cycle when | |
288 | * changing clock speeds. | |
289 | */ | |
290 | ctrl_phy = true; | |
291 | } | |
292 | } | |
802ac39a | 293 | |
b2db9c67 | 294 | if (ctrl_phy && sdhci_arasan->is_phy_on) { |
802ac39a | 295 | phy_power_off(sdhci_arasan->phy); |
b2db9c67 | 296 | sdhci_arasan->is_phy_on = false; |
802ac39a SL |
297 | } |
298 | ||
c0b4e411 MN |
299 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) { |
300 | /* | |
301 | * Some of the Arasan variations might not have timing | |
302 | * requirements met at 25MHz for Default Speed mode, | |
303 | * those controllers work at 19MHz instead. | |
304 | */ | |
305 | if (clock == DEFAULT_SPEED_MAX_DTR) | |
306 | clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25; | |
307 | } | |
308 | ||
f3dafc37 MN |
309 | /* Set the Input and Output Clock Phase Delays */ |
310 | if (clk_data->set_clk_delays) | |
311 | clk_data->set_clk_delays(host); | |
312 | ||
802ac39a SL |
313 | sdhci_set_clock(host, clock); |
314 | ||
3f2c7d5d HG |
315 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) |
316 | /* | |
317 | * Some controllers immediately report SDHCI_CLOCK_INT_STABLE | |
318 | * after enabling the clock even though the clock is not | |
319 | * stable. Trying to use a clock without waiting here results | |
320 | * in EILSEQ while detecting some older/slower cards. The | |
321 | * chosen delay is the maximum delay from sdhci_set_clock. | |
322 | */ | |
323 | msleep(20); | |
324 | ||
6fc09244 | 325 | if (ctrl_phy) { |
802ac39a | 326 | phy_power_on(sdhci_arasan->phy); |
b2db9c67 | 327 | sdhci_arasan->is_phy_on = true; |
802ac39a SL |
328 | } |
329 | } | |
330 | ||
a05c8465 SL |
331 | static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, |
332 | struct mmc_ios *ios) | |
333 | { | |
334 | u32 vendor; | |
335 | struct sdhci_host *host = mmc_priv(mmc); | |
336 | ||
0daf72fe | 337 | vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); |
a05c8465 SL |
338 | if (ios->enhanced_strobe) |
339 | vendor |= VENDOR_ENHANCED_STROBE; | |
340 | else | |
341 | vendor &= ~VENDOR_ENHANCED_STROBE; | |
342 | ||
0daf72fe | 343 | sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); |
a05c8465 SL |
344 | } |
345 | ||
13d62fd2 | 346 | static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) |
3794c542 ZB |
347 | { |
348 | u8 ctrl; | |
349 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
350 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
351 | ||
352 | sdhci_reset(host, mask); | |
353 | ||
354 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { | |
355 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
356 | ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; | |
357 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
358 | } | |
359 | } | |
360 | ||
8a3bee9b SL |
361 | static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, |
362 | struct mmc_ios *ios) | |
363 | { | |
364 | switch (ios->signal_voltage) { | |
365 | case MMC_SIGNAL_VOLTAGE_180: | |
366 | /* | |
367 | * Plese don't switch to 1V8 as arasan,5.1 doesn't | |
368 | * actually refer to this setting to indicate the | |
369 | * signal voltage and the state machine will be broken | |
370 | * actually if we force to enable 1V8. That's something | |
371 | * like broken quirk but we could work around here. | |
372 | */ | |
373 | return 0; | |
374 | case MMC_SIGNAL_VOLTAGE_330: | |
375 | case MMC_SIGNAL_VOLTAGE_120: | |
376 | /* We don't support 3V3 and 1V2 */ | |
377 | break; | |
378 | } | |
379 | ||
380 | return -EINVAL; | |
381 | } | |
382 | ||
a81dae3a | 383 | static const struct sdhci_ops sdhci_arasan_ops = { |
802ac39a | 384 | .set_clock = sdhci_arasan_set_clock, |
e3ec3a3d | 385 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
8cc35289 | 386 | .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, |
2317f56c | 387 | .set_bus_width = sdhci_set_bus_width, |
3794c542 | 388 | .reset = sdhci_arasan_reset, |
96d7b78c | 389 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
c2c5252c | 390 | .set_power = sdhci_set_power_and_bus_voltage, |
e3ec3a3d SB |
391 | }; |
392 | ||
84362d79 SL |
393 | static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) |
394 | { | |
395 | int cmd_error = 0; | |
396 | int data_error = 0; | |
397 | ||
398 | if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) | |
399 | return intmask; | |
400 | ||
401 | cqhci_irq(host->mmc, intmask, cmd_error, data_error); | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
406 | static void sdhci_arasan_dumpregs(struct mmc_host *mmc) | |
407 | { | |
408 | sdhci_dumpregs(mmc_priv(mmc)); | |
409 | } | |
410 | ||
411 | static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) | |
412 | { | |
413 | struct sdhci_host *host = mmc_priv(mmc); | |
414 | u32 reg; | |
415 | ||
416 | reg = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
417 | while (reg & SDHCI_DATA_AVAILABLE) { | |
418 | sdhci_readl(host, SDHCI_BUFFER); | |
419 | reg = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
420 | } | |
421 | ||
422 | sdhci_cqe_enable(mmc); | |
423 | } | |
424 | ||
425 | static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { | |
426 | .enable = sdhci_arasan_cqe_enable, | |
427 | .disable = sdhci_cqe_disable, | |
428 | .dumpregs = sdhci_arasan_dumpregs, | |
429 | }; | |
430 | ||
431 | static const struct sdhci_ops sdhci_arasan_cqe_ops = { | |
432 | .set_clock = sdhci_arasan_set_clock, | |
433 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | |
434 | .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, | |
435 | .set_bus_width = sdhci_set_bus_width, | |
436 | .reset = sdhci_arasan_reset, | |
437 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
c2c5252c | 438 | .set_power = sdhci_set_power_and_bus_voltage, |
84362d79 SL |
439 | .irq = sdhci_arasan_cqhci_irq, |
440 | }; | |
441 | ||
442 | static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { | |
443 | .ops = &sdhci_arasan_cqe_ops, | |
444 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
445 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
446 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, | |
447 | }; | |
448 | ||
e3ec3a3d SB |
449 | #ifdef CONFIG_PM_SLEEP |
450 | /** | |
451 | * sdhci_arasan_suspend - Suspend method for the driver | |
452 | * @dev: Address of the device structure | |
e3ec3a3d SB |
453 | * |
454 | * Put the device in a low power state. | |
4908460e MN |
455 | * |
456 | * Return: 0 on success and error value on error | |
e3ec3a3d SB |
457 | */ |
458 | static int sdhci_arasan_suspend(struct device *dev) | |
459 | { | |
970f2d90 | 460 | struct sdhci_host *host = dev_get_drvdata(dev); |
e3ec3a3d | 461 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
89211418 | 462 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
463 | int ret; |
464 | ||
d38dcad4 AH |
465 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
466 | mmc_retune_needed(host->mmc); | |
467 | ||
84362d79 SL |
468 | if (sdhci_arasan->has_cqe) { |
469 | ret = cqhci_suspend(host->mmc); | |
470 | if (ret) | |
471 | return ret; | |
472 | } | |
473 | ||
e3ec3a3d SB |
474 | ret = sdhci_suspend_host(host); |
475 | if (ret) | |
476 | return ret; | |
477 | ||
b2db9c67 | 478 | if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { |
91aa3661 SL |
479 | ret = phy_power_off(sdhci_arasan->phy); |
480 | if (ret) { | |
481 | dev_err(dev, "Cannot power off phy.\n"); | |
482 | sdhci_resume_host(host); | |
483 | return ret; | |
484 | } | |
b2db9c67 | 485 | sdhci_arasan->is_phy_on = false; |
91aa3661 SL |
486 | } |
487 | ||
e3ec3a3d SB |
488 | clk_disable(pltfm_host->clk); |
489 | clk_disable(sdhci_arasan->clk_ahb); | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
494 | /** | |
495 | * sdhci_arasan_resume - Resume method for the driver | |
496 | * @dev: Address of the device structure | |
e3ec3a3d SB |
497 | * |
498 | * Resume operation after suspend | |
4908460e MN |
499 | * |
500 | * Return: 0 on success and error value on error | |
e3ec3a3d SB |
501 | */ |
502 | static int sdhci_arasan_resume(struct device *dev) | |
503 | { | |
970f2d90 | 504 | struct sdhci_host *host = dev_get_drvdata(dev); |
e3ec3a3d | 505 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
89211418 | 506 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
507 | int ret; |
508 | ||
509 | ret = clk_enable(sdhci_arasan->clk_ahb); | |
510 | if (ret) { | |
511 | dev_err(dev, "Cannot enable AHB clock.\n"); | |
512 | return ret; | |
513 | } | |
514 | ||
515 | ret = clk_enable(pltfm_host->clk); | |
516 | if (ret) { | |
517 | dev_err(dev, "Cannot enable SD clock.\n"); | |
e3ec3a3d SB |
518 | return ret; |
519 | } | |
520 | ||
b2db9c67 | 521 | if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { |
91aa3661 SL |
522 | ret = phy_power_on(sdhci_arasan->phy); |
523 | if (ret) { | |
524 | dev_err(dev, "Cannot power on phy.\n"); | |
525 | return ret; | |
526 | } | |
b2db9c67 | 527 | sdhci_arasan->is_phy_on = true; |
91aa3661 SL |
528 | } |
529 | ||
84362d79 SL |
530 | ret = sdhci_resume_host(host); |
531 | if (ret) { | |
532 | dev_err(dev, "Cannot resume host.\n"); | |
533 | return ret; | |
534 | } | |
535 | ||
536 | if (sdhci_arasan->has_cqe) | |
537 | return cqhci_resume(host->mmc); | |
538 | ||
539 | return 0; | |
e3ec3a3d SB |
540 | } |
541 | #endif /* ! CONFIG_PM_SLEEP */ | |
542 | ||
543 | static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, | |
544 | sdhci_arasan_resume); | |
545 | ||
c390f211 DA |
546 | /** |
547 | * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate | |
548 | * | |
4908460e MN |
549 | * @hw: Pointer to the hardware clock structure. |
550 | * @parent_rate: The parent rate (should be rate of clk_xin). | |
551 | * | |
c390f211 DA |
552 | * Return the current actual rate of the SD card clock. This can be used |
553 | * to communicate with out PHY. | |
554 | * | |
4908460e | 555 | * Return: The card clock rate. |
c390f211 DA |
556 | */ |
557 | static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, | |
558 | unsigned long parent_rate) | |
c390f211 | 559 | { |
e1463618 MN |
560 | struct sdhci_arasan_clk_data *clk_data = |
561 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
c390f211 | 562 | struct sdhci_arasan_data *sdhci_arasan = |
e1463618 | 563 | container_of(clk_data, struct sdhci_arasan_data, clk_data); |
c390f211 DA |
564 | struct sdhci_host *host = sdhci_arasan->host; |
565 | ||
566 | return host->mmc->actual_clock; | |
567 | } | |
568 | ||
569 | static const struct clk_ops arasan_sdcardclk_ops = { | |
570 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
571 | }; | |
572 | ||
07a14d1d MN |
573 | /** |
574 | * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate | |
575 | * | |
4908460e MN |
576 | * @hw: Pointer to the hardware clock structure. |
577 | * @parent_rate: The parent rate (should be rate of clk_xin). | |
578 | * | |
07a14d1d MN |
579 | * Return the current actual rate of the sampling clock. This can be used |
580 | * to communicate with out PHY. | |
581 | * | |
4908460e | 582 | * Return: The sample clock rate. |
07a14d1d MN |
583 | */ |
584 | static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw, | |
585 | unsigned long parent_rate) | |
07a14d1d MN |
586 | { |
587 | struct sdhci_arasan_clk_data *clk_data = | |
588 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
589 | struct sdhci_arasan_data *sdhci_arasan = | |
590 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
591 | struct sdhci_host *host = sdhci_arasan->host; | |
592 | ||
593 | return host->mmc->actual_clock; | |
594 | } | |
595 | ||
596 | static const struct clk_ops arasan_sampleclk_ops = { | |
597 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
598 | }; | |
599 | ||
a5c8b2ae MN |
600 | /** |
601 | * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays | |
602 | * | |
4908460e MN |
603 | * @hw: Pointer to the hardware clock structure. |
604 | * @degrees: The clock phase shift between 0 - 359. | |
605 | * | |
a5c8b2ae MN |
606 | * Set the SD Output Clock Tap Delays for Output path |
607 | * | |
a5c8b2ae MN |
608 | * Return: 0 on success and error value on error |
609 | */ | |
610 | static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) | |
a5c8b2ae MN |
611 | { |
612 | struct sdhci_arasan_clk_data *clk_data = | |
613 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
614 | struct sdhci_arasan_data *sdhci_arasan = | |
615 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
616 | struct sdhci_host *host = sdhci_arasan->host; | |
a5c8b2ae MN |
617 | const char *clk_name = clk_hw_get_name(hw); |
618 | u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; | |
619 | u8 tap_delay, tap_max = 0; | |
620 | int ret; | |
621 | ||
9e953432 MN |
622 | /* This is applicable for SDHCI_SPEC_300 and above */ |
623 | if (host->version < SDHCI_SPEC_300) | |
a5c8b2ae MN |
624 | return 0; |
625 | ||
626 | switch (host->timing) { | |
627 | case MMC_TIMING_MMC_HS: | |
628 | case MMC_TIMING_SD_HS: | |
629 | case MMC_TIMING_UHS_SDR25: | |
630 | case MMC_TIMING_UHS_DDR50: | |
631 | case MMC_TIMING_MMC_DDR52: | |
632 | /* For 50MHz clock, 30 Taps are available */ | |
633 | tap_max = 30; | |
634 | break; | |
635 | case MMC_TIMING_UHS_SDR50: | |
636 | /* For 100MHz clock, 15 Taps are available */ | |
637 | tap_max = 15; | |
638 | break; | |
639 | case MMC_TIMING_UHS_SDR104: | |
640 | case MMC_TIMING_MMC_HS200: | |
641 | /* For 200MHz clock, 8 Taps are available */ | |
642 | tap_max = 8; | |
a3096ec6 | 643 | break; |
a5c8b2ae MN |
644 | default: |
645 | break; | |
646 | } | |
647 | ||
648 | tap_delay = (degrees * tap_max) / 360; | |
649 | ||
650 | /* Set the Clock Phase */ | |
426c8d85 | 651 | ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay); |
a5c8b2ae MN |
652 | if (ret) |
653 | pr_err("Error setting Output Tap Delay\n"); | |
654 | ||
d06d60d5 MN |
655 | /* Release DLL Reset */ |
656 | zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE); | |
657 | ||
a5c8b2ae MN |
658 | return ret; |
659 | } | |
660 | ||
661 | static const struct clk_ops zynqmp_sdcardclk_ops = { | |
662 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
663 | .set_phase = sdhci_zynqmp_sdcardclk_set_phase, | |
664 | }; | |
665 | ||
666 | /** | |
667 | * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays | |
668 | * | |
4908460e MN |
669 | * @hw: Pointer to the hardware clock structure. |
670 | * @degrees: The clock phase shift between 0 - 359. | |
671 | * | |
a5c8b2ae MN |
672 | * Set the SD Input Clock Tap Delays for Input path |
673 | * | |
a5c8b2ae MN |
674 | * Return: 0 on success and error value on error |
675 | */ | |
676 | static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) | |
a5c8b2ae MN |
677 | { |
678 | struct sdhci_arasan_clk_data *clk_data = | |
679 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
680 | struct sdhci_arasan_data *sdhci_arasan = | |
681 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
682 | struct sdhci_host *host = sdhci_arasan->host; | |
a5c8b2ae MN |
683 | const char *clk_name = clk_hw_get_name(hw); |
684 | u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1; | |
685 | u8 tap_delay, tap_max = 0; | |
686 | int ret; | |
687 | ||
9e953432 MN |
688 | /* This is applicable for SDHCI_SPEC_300 and above */ |
689 | if (host->version < SDHCI_SPEC_300) | |
a5c8b2ae MN |
690 | return 0; |
691 | ||
d06d60d5 MN |
692 | /* Assert DLL Reset */ |
693 | zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT); | |
694 | ||
a5c8b2ae MN |
695 | switch (host->timing) { |
696 | case MMC_TIMING_MMC_HS: | |
697 | case MMC_TIMING_SD_HS: | |
698 | case MMC_TIMING_UHS_SDR25: | |
699 | case MMC_TIMING_UHS_DDR50: | |
700 | case MMC_TIMING_MMC_DDR52: | |
701 | /* For 50MHz clock, 120 Taps are available */ | |
702 | tap_max = 120; | |
703 | break; | |
704 | case MMC_TIMING_UHS_SDR50: | |
705 | /* For 100MHz clock, 60 Taps are available */ | |
706 | tap_max = 60; | |
707 | break; | |
708 | case MMC_TIMING_UHS_SDR104: | |
709 | case MMC_TIMING_MMC_HS200: | |
710 | /* For 200MHz clock, 30 Taps are available */ | |
711 | tap_max = 30; | |
a3096ec6 | 712 | break; |
a5c8b2ae MN |
713 | default: |
714 | break; | |
715 | } | |
716 | ||
717 | tap_delay = (degrees * tap_max) / 360; | |
718 | ||
719 | /* Set the Clock Phase */ | |
426c8d85 | 720 | ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay); |
a5c8b2ae MN |
721 | if (ret) |
722 | pr_err("Error setting Input Tap Delay\n"); | |
723 | ||
724 | return ret; | |
725 | } | |
726 | ||
727 | static const struct clk_ops zynqmp_sampleclk_ops = { | |
728 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
729 | .set_phase = sdhci_zynqmp_sampleclk_set_phase, | |
730 | }; | |
731 | ||
1a470721 MN |
732 | /** |
733 | * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays | |
734 | * | |
4908460e MN |
735 | * @hw: Pointer to the hardware clock structure. |
736 | * @degrees: The clock phase shift between 0 - 359. | |
737 | * | |
1a470721 MN |
738 | * Set the SD Output Clock Tap Delays for Output path |
739 | * | |
1a470721 MN |
740 | * Return: 0 on success and error value on error |
741 | */ | |
742 | static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees) | |
743 | { | |
744 | struct sdhci_arasan_clk_data *clk_data = | |
745 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
746 | struct sdhci_arasan_data *sdhci_arasan = | |
747 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
748 | struct sdhci_host *host = sdhci_arasan->host; | |
749 | u8 tap_delay, tap_max = 0; | |
1a470721 | 750 | |
9e953432 MN |
751 | /* This is applicable for SDHCI_SPEC_300 and above */ |
752 | if (host->version < SDHCI_SPEC_300) | |
1a470721 MN |
753 | return 0; |
754 | ||
755 | switch (host->timing) { | |
756 | case MMC_TIMING_MMC_HS: | |
757 | case MMC_TIMING_SD_HS: | |
758 | case MMC_TIMING_UHS_SDR25: | |
759 | case MMC_TIMING_UHS_DDR50: | |
760 | case MMC_TIMING_MMC_DDR52: | |
761 | /* For 50MHz clock, 30 Taps are available */ | |
762 | tap_max = 30; | |
763 | break; | |
764 | case MMC_TIMING_UHS_SDR50: | |
765 | /* For 100MHz clock, 15 Taps are available */ | |
766 | tap_max = 15; | |
767 | break; | |
768 | case MMC_TIMING_UHS_SDR104: | |
769 | case MMC_TIMING_MMC_HS200: | |
770 | /* For 200MHz clock, 8 Taps are available */ | |
771 | tap_max = 8; | |
a3096ec6 | 772 | break; |
1a470721 MN |
773 | default: |
774 | break; | |
775 | } | |
776 | ||
777 | tap_delay = (degrees * tap_max) / 360; | |
778 | ||
779 | /* Set the Clock Phase */ | |
780 | if (tap_delay) { | |
781 | u32 regval; | |
782 | ||
783 | regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); | |
784 | regval |= SDHCI_OTAPDLY_ENABLE; | |
785 | sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); | |
d338c6d0 | 786 | regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK; |
1a470721 MN |
787 | regval |= tap_delay; |
788 | sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); | |
789 | } | |
790 | ||
098c408b | 791 | return 0; |
1a470721 MN |
792 | } |
793 | ||
794 | static const struct clk_ops versal_sdcardclk_ops = { | |
795 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
796 | .set_phase = sdhci_versal_sdcardclk_set_phase, | |
797 | }; | |
798 | ||
799 | /** | |
800 | * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays | |
801 | * | |
4908460e MN |
802 | * @hw: Pointer to the hardware clock structure. |
803 | * @degrees: The clock phase shift between 0 - 359. | |
804 | * | |
1a470721 MN |
805 | * Set the SD Input Clock Tap Delays for Input path |
806 | * | |
1a470721 MN |
807 | * Return: 0 on success and error value on error |
808 | */ | |
809 | static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees) | |
810 | { | |
811 | struct sdhci_arasan_clk_data *clk_data = | |
812 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
813 | struct sdhci_arasan_data *sdhci_arasan = | |
814 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
815 | struct sdhci_host *host = sdhci_arasan->host; | |
816 | u8 tap_delay, tap_max = 0; | |
1a470721 | 817 | |
9e953432 MN |
818 | /* This is applicable for SDHCI_SPEC_300 and above */ |
819 | if (host->version < SDHCI_SPEC_300) | |
1a470721 MN |
820 | return 0; |
821 | ||
822 | switch (host->timing) { | |
823 | case MMC_TIMING_MMC_HS: | |
824 | case MMC_TIMING_SD_HS: | |
825 | case MMC_TIMING_UHS_SDR25: | |
826 | case MMC_TIMING_UHS_DDR50: | |
827 | case MMC_TIMING_MMC_DDR52: | |
828 | /* For 50MHz clock, 120 Taps are available */ | |
829 | tap_max = 120; | |
830 | break; | |
831 | case MMC_TIMING_UHS_SDR50: | |
832 | /* For 100MHz clock, 60 Taps are available */ | |
833 | tap_max = 60; | |
834 | break; | |
835 | case MMC_TIMING_UHS_SDR104: | |
836 | case MMC_TIMING_MMC_HS200: | |
837 | /* For 200MHz clock, 30 Taps are available */ | |
838 | tap_max = 30; | |
a3096ec6 | 839 | break; |
1a470721 MN |
840 | default: |
841 | break; | |
842 | } | |
843 | ||
844 | tap_delay = (degrees * tap_max) / 360; | |
845 | ||
846 | /* Set the Clock Phase */ | |
847 | if (tap_delay) { | |
848 | u32 regval; | |
849 | ||
850 | regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
851 | regval |= SDHCI_ITAPDLY_CHGWIN; | |
852 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
853 | regval |= SDHCI_ITAPDLY_ENABLE; | |
854 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
d338c6d0 | 855 | regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK; |
1a470721 MN |
856 | regval |= tap_delay; |
857 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
858 | regval &= ~SDHCI_ITAPDLY_CHGWIN; | |
859 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
860 | } | |
861 | ||
098c408b | 862 | return 0; |
1a470721 MN |
863 | } |
864 | ||
865 | static const struct clk_ops versal_sampleclk_ops = { | |
866 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
867 | .set_phase = sdhci_versal_sampleclk_set_phase, | |
868 | }; | |
869 | ||
8d2e3343 MN |
870 | static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) |
871 | { | |
8d2e3343 MN |
872 | u16 clk; |
873 | ||
874 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
875 | clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); | |
876 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
877 | ||
878 | /* Issue DLL Reset */ | |
426c8d85 | 879 | zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE); |
8d2e3343 MN |
880 | |
881 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
882 | ||
883 | sdhci_enable_clk(host, clk); | |
884 | } | |
885 | ||
886 | static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode) | |
887 | { | |
888 | struct sdhci_host *host = mmc_priv(mmc); | |
889 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
890 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
891 | struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; | |
892 | const char *clk_name = clk_hw_get_name(hw); | |
893 | u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : | |
894 | NODE_SD_1; | |
895 | int err; | |
896 | ||
897 | arasan_zynqmp_dll_reset(host, device_id); | |
898 | ||
899 | err = sdhci_execute_tuning(mmc, opcode); | |
900 | if (err) | |
901 | return err; | |
902 | ||
903 | arasan_zynqmp_dll_reset(host, device_id); | |
904 | ||
905 | return 0; | |
906 | } | |
907 | ||
b2ca77c9 SL |
908 | /** |
909 | * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier | |
910 | * | |
4908460e MN |
911 | * @host: The sdhci_host |
912 | * @value: The value to write | |
913 | * | |
b2ca77c9 SL |
914 | * The corecfg_clockmultiplier is supposed to contain clock multiplier |
915 | * value of programmable clock generator. | |
916 | * | |
917 | * NOTES: | |
918 | * - Many existing devices don't seem to do this and work fine. To keep | |
919 | * compatibility for old hardware where the device tree doesn't provide a | |
920 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
921 | * for this platform. | |
922 | * - The value of corecfg_clockmultiplier should sync with that of corresponding | |
923 | * value reading from sdhci_capability_register. So this function is called | |
924 | * once at probe time and never called again. | |
b2ca77c9 SL |
925 | */ |
926 | static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, | |
927 | u32 value) | |
928 | { | |
929 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
930 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
931 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
932 | sdhci_arasan->soc_ctl_map; | |
933 | ||
934 | /* Having a map is optional */ | |
935 | if (!soc_ctl_map) | |
936 | return; | |
937 | ||
938 | /* If we have a map, we expect to have a syscon */ | |
939 | if (!sdhci_arasan->soc_ctl_base) { | |
940 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
941 | mmc_hostname(host->mmc)); | |
942 | return; | |
943 | } | |
944 | ||
945 | sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); | |
946 | } | |
947 | ||
3ea4666e DA |
948 | /** |
949 | * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq | |
950 | * | |
4908460e MN |
951 | * @host: The sdhci_host |
952 | * | |
3ea4666e DA |
953 | * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This |
954 | * function can be used to make that happen. | |
955 | * | |
956 | * NOTES: | |
957 | * - Many existing devices don't seem to do this and work fine. To keep | |
958 | * compatibility for old hardware where the device tree doesn't provide a | |
959 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
960 | * for this platform. | |
961 | * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider | |
962 | * to achieve lower clock rates. That means that this function is called once | |
963 | * at probe time and never called again. | |
3ea4666e DA |
964 | */ |
965 | static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) | |
966 | { | |
967 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
968 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
969 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
970 | sdhci_arasan->soc_ctl_map; | |
971 | u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); | |
972 | ||
973 | /* Having a map is optional */ | |
974 | if (!soc_ctl_map) | |
975 | return; | |
976 | ||
977 | /* If we have a map, we expect to have a syscon */ | |
978 | if (!sdhci_arasan->soc_ctl_base) { | |
979 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
980 | mmc_hostname(host->mmc)); | |
981 | return; | |
982 | } | |
983 | ||
984 | sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); | |
985 | } | |
986 | ||
f3dafc37 MN |
987 | static void sdhci_arasan_set_clk_delays(struct sdhci_host *host) |
988 | { | |
989 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
990 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
991 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; | |
992 | ||
993 | clk_set_phase(clk_data->sampleclk, | |
994 | clk_data->clk_phase_in[host->timing]); | |
995 | clk_set_phase(clk_data->sdcardclk, | |
996 | clk_data->clk_phase_out[host->timing]); | |
997 | } | |
998 | ||
999 | static void arasan_dt_read_clk_phase(struct device *dev, | |
1000 | struct sdhci_arasan_clk_data *clk_data, | |
1001 | unsigned int timing, const char *prop) | |
1002 | { | |
1003 | struct device_node *np = dev->of_node; | |
1004 | ||
1005 | int clk_phase[2] = {0}; | |
1006 | ||
1007 | /* | |
1008 | * Read Tap Delay values from DT, if the DT does not contain the | |
1009 | * Tap Values then use the pre-defined values. | |
1010 | */ | |
1011 | if (of_property_read_variable_u32_array(np, prop, &clk_phase[0], | |
1012 | 2, 0)) { | |
1013 | dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n", | |
1014 | prop, clk_data->clk_phase_in[timing], | |
1015 | clk_data->clk_phase_out[timing]); | |
1016 | return; | |
1017 | } | |
1018 | ||
1019 | /* The values read are Input and Output Clock Delays in order */ | |
1020 | clk_data->clk_phase_in[timing] = clk_phase[0]; | |
1021 | clk_data->clk_phase_out[timing] = clk_phase[1]; | |
1022 | } | |
1023 | ||
1024 | /** | |
1025 | * arasan_dt_parse_clk_phases - Read Clock Delay values from DT | |
1026 | * | |
f3dafc37 MN |
1027 | * @dev: Pointer to our struct device. |
1028 | * @clk_data: Pointer to the Clock Data structure | |
4908460e MN |
1029 | * |
1030 | * Called at initialization to parse the values of Clock Delays. | |
f3dafc37 MN |
1031 | */ |
1032 | static void arasan_dt_parse_clk_phases(struct device *dev, | |
1033 | struct sdhci_arasan_clk_data *clk_data) | |
1034 | { | |
a5c8b2ae MN |
1035 | u32 mio_bank = 0; |
1036 | int i; | |
1037 | ||
f3dafc37 MN |
1038 | /* |
1039 | * This has been kept as a pointer and is assigned a function here. | |
1040 | * So that different controller variants can assign their own handling | |
1041 | * function. | |
1042 | */ | |
1043 | clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; | |
1044 | ||
a5c8b2ae | 1045 | if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { |
88e1d0b1 MN |
1046 | u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = |
1047 | ZYNQMP_ICLK_PHASE; | |
1048 | u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = | |
1049 | ZYNQMP_OCLK_PHASE; | |
a5c8b2ae MN |
1050 | |
1051 | of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); | |
1052 | if (mio_bank == 2) { | |
88e1d0b1 MN |
1053 | zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90; |
1054 | zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90; | |
a5c8b2ae MN |
1055 | } |
1056 | ||
1057 | for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { | |
88e1d0b1 MN |
1058 | clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; |
1059 | clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; | |
a5c8b2ae MN |
1060 | } |
1061 | } | |
1062 | ||
1a470721 | 1063 | if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { |
88e1d0b1 MN |
1064 | u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = |
1065 | VERSAL_ICLK_PHASE; | |
1066 | u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = | |
1067 | VERSAL_OCLK_PHASE; | |
1a470721 MN |
1068 | |
1069 | for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { | |
88e1d0b1 MN |
1070 | clk_data->clk_phase_in[i] = versal_iclk_phase[i]; |
1071 | clk_data->clk_phase_out[i] = versal_oclk_phase[i]; | |
1a470721 MN |
1072 | } |
1073 | } | |
1074 | ||
f3dafc37 MN |
1075 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY, |
1076 | "clk-phase-legacy"); | |
1077 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS, | |
1078 | "clk-phase-mmc-hs"); | |
1079 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS, | |
1080 | "clk-phase-sd-hs"); | |
1081 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12, | |
1082 | "clk-phase-uhs-sdr12"); | |
1083 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25, | |
1084 | "clk-phase-uhs-sdr25"); | |
1085 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50, | |
1086 | "clk-phase-uhs-sdr50"); | |
1087 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104, | |
1088 | "clk-phase-uhs-sdr104"); | |
1089 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, | |
1090 | "clk-phase-uhs-ddr50"); | |
1091 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52, | |
1092 | "clk-phase-mmc-ddr52"); | |
1093 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200, | |
1094 | "clk-phase-mmc-hs200"); | |
1095 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400, | |
1096 | "clk-phase-mmc-hs400"); | |
1097 | } | |
1098 | ||
37d3ee7c MN |
1099 | static const struct sdhci_pltfm_data sdhci_arasan_pdata = { |
1100 | .ops = &sdhci_arasan_ops, | |
1101 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
1102 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1103 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1104 | SDHCI_QUIRK2_STOP_WITH_TC, | |
1105 | }; | |
1106 | ||
16ada730 MN |
1107 | static const struct sdhci_arasan_clk_ops arasan_clk_ops = { |
1108 | .sdcardclk_ops = &arasan_sdcardclk_ops, | |
1109 | .sampleclk_ops = &arasan_sampleclk_ops, | |
1110 | }; | |
1111 | ||
37d3ee7c MN |
1112 | static struct sdhci_arasan_of_data sdhci_arasan_generic_data = { |
1113 | .pdata = &sdhci_arasan_pdata, | |
16ada730 | 1114 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1115 | }; |
1116 | ||
36c6aada WAZ |
1117 | static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = { |
1118 | .ops = &sdhci_arasan_cqe_ops, | |
1119 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | |
1120 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | | |
1121 | SDHCI_QUIRK_NO_LED | | |
1122 | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1123 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
1124 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
1125 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1126 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1127 | SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | | |
1128 | SDHCI_QUIRK2_STOP_WITH_TC | | |
1129 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA, | |
1130 | }; | |
1131 | ||
1132 | static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = { | |
1133 | .ops = &sdhci_arasan_ops, | |
1134 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | |
1135 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | | |
1136 | SDHCI_QUIRK_NO_LED | | |
1137 | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1138 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
1139 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
1140 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1141 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1142 | SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | | |
1143 | SDHCI_QUIRK2_STOP_WITH_TC | | |
1144 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA, | |
1145 | }; | |
1146 | ||
1147 | static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = { | |
1148 | .ops = &sdhci_arasan_ops, | |
1149 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | |
1150 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | | |
1151 | SDHCI_QUIRK_NO_LED | | |
1152 | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1153 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
1154 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
1155 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1156 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1157 | SDHCI_QUIRK2_HOST_OFF_CARD_ON | | |
1158 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA, | |
1159 | }; | |
1160 | ||
37d3ee7c MN |
1161 | static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = { |
1162 | .soc_ctl_map = &rk3399_soc_ctl_map, | |
1163 | .pdata = &sdhci_arasan_cqe_pdata, | |
16ada730 | 1164 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1165 | }; |
1166 | ||
1167 | static struct sdhci_arasan_of_data intel_lgm_emmc_data = { | |
1168 | .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map, | |
1169 | .pdata = &sdhci_arasan_cqe_pdata, | |
16ada730 | 1170 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1171 | }; |
1172 | ||
1173 | static struct sdhci_arasan_of_data intel_lgm_sdxc_data = { | |
1174 | .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map, | |
1175 | .pdata = &sdhci_arasan_cqe_pdata, | |
16ada730 | 1176 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1177 | }; |
1178 | ||
1179 | static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = { | |
1180 | .ops = &sdhci_arasan_ops, | |
1181 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1182 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1183 | SDHCI_QUIRK2_STOP_WITH_TC, | |
1184 | }; | |
1185 | ||
16ada730 MN |
1186 | static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = { |
1187 | .sdcardclk_ops = &zynqmp_sdcardclk_ops, | |
1188 | .sampleclk_ops = &zynqmp_sampleclk_ops, | |
1189 | }; | |
1190 | ||
37d3ee7c MN |
1191 | static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = { |
1192 | .pdata = &sdhci_arasan_zynqmp_pdata, | |
16ada730 MN |
1193 | .clk_ops = &zynqmp_clk_ops, |
1194 | }; | |
1195 | ||
1196 | static const struct sdhci_arasan_clk_ops versal_clk_ops = { | |
1197 | .sdcardclk_ops = &versal_sdcardclk_ops, | |
1198 | .sampleclk_ops = &versal_sampleclk_ops, | |
37d3ee7c MN |
1199 | }; |
1200 | ||
1201 | static struct sdhci_arasan_of_data sdhci_arasan_versal_data = { | |
1202 | .pdata = &sdhci_arasan_zynqmp_pdata, | |
16ada730 | 1203 | .clk_ops = &versal_clk_ops, |
37d3ee7c MN |
1204 | }; |
1205 | ||
36c6aada WAZ |
1206 | static struct sdhci_arasan_of_data intel_keembay_emmc_data = { |
1207 | .soc_ctl_map = &intel_keembay_soc_ctl_map, | |
1208 | .pdata = &sdhci_keembay_emmc_pdata, | |
a42a7ec9 | 1209 | .clk_ops = &arasan_clk_ops, |
36c6aada WAZ |
1210 | }; |
1211 | ||
1212 | static struct sdhci_arasan_of_data intel_keembay_sd_data = { | |
1213 | .soc_ctl_map = &intel_keembay_soc_ctl_map, | |
1214 | .pdata = &sdhci_keembay_sd_pdata, | |
a42a7ec9 | 1215 | .clk_ops = &arasan_clk_ops, |
36c6aada WAZ |
1216 | }; |
1217 | ||
1218 | static struct sdhci_arasan_of_data intel_keembay_sdio_data = { | |
1219 | .soc_ctl_map = &intel_keembay_soc_ctl_map, | |
1220 | .pdata = &sdhci_keembay_sdio_pdata, | |
a42a7ec9 | 1221 | .clk_ops = &arasan_clk_ops, |
36c6aada WAZ |
1222 | }; |
1223 | ||
37d3ee7c MN |
1224 | static const struct of_device_id sdhci_arasan_of_match[] = { |
1225 | /* SoC-specific compatible strings w/ soc_ctl_map */ | |
1226 | { | |
1227 | .compatible = "rockchip,rk3399-sdhci-5.1", | |
1228 | .data = &sdhci_arasan_rk3399_data, | |
1229 | }, | |
1230 | { | |
1231 | .compatible = "intel,lgm-sdhci-5.1-emmc", | |
1232 | .data = &intel_lgm_emmc_data, | |
1233 | }, | |
1234 | { | |
1235 | .compatible = "intel,lgm-sdhci-5.1-sdxc", | |
1236 | .data = &intel_lgm_sdxc_data, | |
1237 | }, | |
36c6aada WAZ |
1238 | { |
1239 | .compatible = "intel,keembay-sdhci-5.1-emmc", | |
1240 | .data = &intel_keembay_emmc_data, | |
1241 | }, | |
1242 | { | |
1243 | .compatible = "intel,keembay-sdhci-5.1-sd", | |
1244 | .data = &intel_keembay_sd_data, | |
1245 | }, | |
1246 | { | |
1247 | .compatible = "intel,keembay-sdhci-5.1-sdio", | |
1248 | .data = &intel_keembay_sdio_data, | |
1249 | }, | |
37d3ee7c MN |
1250 | /* Generic compatible below here */ |
1251 | { | |
1252 | .compatible = "arasan,sdhci-8.9a", | |
1253 | .data = &sdhci_arasan_generic_data, | |
1254 | }, | |
1255 | { | |
1256 | .compatible = "arasan,sdhci-5.1", | |
1257 | .data = &sdhci_arasan_generic_data, | |
1258 | }, | |
1259 | { | |
1260 | .compatible = "arasan,sdhci-4.9a", | |
1261 | .data = &sdhci_arasan_generic_data, | |
1262 | }, | |
1263 | { | |
1264 | .compatible = "xlnx,zynqmp-8.9a", | |
1265 | .data = &sdhci_arasan_zynqmp_data, | |
1266 | }, | |
1267 | { | |
1268 | .compatible = "xlnx,versal-8.9a", | |
1269 | .data = &sdhci_arasan_versal_data, | |
1270 | }, | |
1271 | { /* sentinel */ } | |
1272 | }; | |
1273 | MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); | |
1274 | ||
c390f211 | 1275 | /** |
07a14d1d | 1276 | * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use |
c390f211 | 1277 | * |
4908460e MN |
1278 | * @sdhci_arasan: Our private data structure. |
1279 | * @clk_xin: Pointer to the functional clock | |
1280 | * @dev: Pointer to our struct device. | |
1281 | * | |
c390f211 DA |
1282 | * Some PHY devices need to know what the actual card clock is. In order for |
1283 | * them to find out, we'll provide a clock through the common clock framework | |
1284 | * for them to query. | |
1285 | * | |
4908460e | 1286 | * Return: 0 on success and error value on error |
c390f211 | 1287 | */ |
07a14d1d MN |
1288 | static int |
1289 | sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan, | |
1290 | struct clk *clk_xin, | |
1291 | struct device *dev) | |
c390f211 | 1292 | { |
e1463618 | 1293 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; |
c390f211 DA |
1294 | struct device_node *np = dev->of_node; |
1295 | struct clk_init_data sdcardclk_init; | |
1296 | const char *parent_clk_name; | |
1297 | int ret; | |
1298 | ||
c390f211 DA |
1299 | ret = of_property_read_string_index(np, "clock-output-names", 0, |
1300 | &sdcardclk_init.name); | |
1301 | if (ret) { | |
1302 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
1303 | return ret; | |
1304 | } | |
1305 | ||
1306 | parent_clk_name = __clk_get_name(clk_xin); | |
1307 | sdcardclk_init.parent_names = &parent_clk_name; | |
1308 | sdcardclk_init.num_parents = 1; | |
1309 | sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; | |
16ada730 | 1310 | sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops; |
c390f211 | 1311 | |
e1463618 MN |
1312 | clk_data->sdcardclk_hw.init = &sdcardclk_init; |
1313 | clk_data->sdcardclk = | |
1314 | devm_clk_register(dev, &clk_data->sdcardclk_hw); | |
c99e1d0c CY |
1315 | if (IS_ERR(clk_data->sdcardclk)) |
1316 | return PTR_ERR(clk_data->sdcardclk); | |
e1463618 | 1317 | clk_data->sdcardclk_hw.init = NULL; |
c390f211 DA |
1318 | |
1319 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
e1463618 | 1320 | clk_data->sdcardclk); |
c390f211 | 1321 | if (ret) |
07a14d1d MN |
1322 | dev_err(dev, "Failed to add sdcard clock provider\n"); |
1323 | ||
1324 | return ret; | |
1325 | } | |
1326 | ||
1327 | /** | |
1328 | * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use | |
1329 | * | |
4908460e MN |
1330 | * @sdhci_arasan: Our private data structure. |
1331 | * @clk_xin: Pointer to the functional clock | |
1332 | * @dev: Pointer to our struct device. | |
1333 | * | |
07a14d1d MN |
1334 | * Some PHY devices need to know what the actual card clock is. In order for |
1335 | * them to find out, we'll provide a clock through the common clock framework | |
1336 | * for them to query. | |
1337 | * | |
4908460e | 1338 | * Return: 0 on success and error value on error |
07a14d1d MN |
1339 | */ |
1340 | static int | |
1341 | sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan, | |
1342 | struct clk *clk_xin, | |
1343 | struct device *dev) | |
1344 | { | |
1345 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; | |
1346 | struct device_node *np = dev->of_node; | |
1347 | struct clk_init_data sampleclk_init; | |
1348 | const char *parent_clk_name; | |
1349 | int ret; | |
1350 | ||
1351 | ret = of_property_read_string_index(np, "clock-output-names", 1, | |
1352 | &sampleclk_init.name); | |
1353 | if (ret) { | |
1354 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
1355 | return ret; | |
1356 | } | |
1357 | ||
1358 | parent_clk_name = __clk_get_name(clk_xin); | |
1359 | sampleclk_init.parent_names = &parent_clk_name; | |
1360 | sampleclk_init.num_parents = 1; | |
1361 | sampleclk_init.flags = CLK_GET_RATE_NOCACHE; | |
16ada730 | 1362 | sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops; |
07a14d1d MN |
1363 | |
1364 | clk_data->sampleclk_hw.init = &sampleclk_init; | |
1365 | clk_data->sampleclk = | |
1366 | devm_clk_register(dev, &clk_data->sampleclk_hw); | |
c99e1d0c CY |
1367 | if (IS_ERR(clk_data->sampleclk)) |
1368 | return PTR_ERR(clk_data->sampleclk); | |
07a14d1d MN |
1369 | clk_data->sampleclk_hw.init = NULL; |
1370 | ||
1371 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
1372 | clk_data->sampleclk); | |
1373 | if (ret) | |
1374 | dev_err(dev, "Failed to add sample clock provider\n"); | |
c390f211 DA |
1375 | |
1376 | return ret; | |
1377 | } | |
1378 | ||
1379 | /** | |
1380 | * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() | |
1381 | * | |
4908460e MN |
1382 | * @dev: Pointer to our struct device. |
1383 | * | |
c390f211 DA |
1384 | * Should be called any time we're exiting and sdhci_arasan_register_sdclk() |
1385 | * returned success. | |
c390f211 DA |
1386 | */ |
1387 | static void sdhci_arasan_unregister_sdclk(struct device *dev) | |
1388 | { | |
1389 | struct device_node *np = dev->of_node; | |
1390 | ||
1391 | if (!of_find_property(np, "#clock-cells", NULL)) | |
1392 | return; | |
1393 | ||
1394 | of_clk_del_provider(dev->of_node); | |
1395 | } | |
1396 | ||
36c6aada WAZ |
1397 | /** |
1398 | * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support) | |
973c7c99 MHZ |
1399 | * @host: The sdhci_host |
1400 | * @value: The value to write | |
36c6aada WAZ |
1401 | * |
1402 | * This should be set based on the System Address Bus. | |
1403 | * 0: the Core supports only 32-bit System Address Bus. | |
1404 | * 1: the Core supports 64-bit System Address Bus. | |
1405 | * | |
973c7c99 MHZ |
1406 | * NOTE: |
1407 | * For Keem Bay, it is required to clear this bit. Its default value is 1'b1. | |
1408 | * Keem Bay does not support 64-bit access. | |
36c6aada WAZ |
1409 | */ |
1410 | static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value) | |
1411 | { | |
1412 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1413 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
db845093 | 1414 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; |
36c6aada WAZ |
1415 | |
1416 | /* Having a map is optional */ | |
db845093 | 1417 | soc_ctl_map = sdhci_arasan->soc_ctl_map; |
36c6aada WAZ |
1418 | if (!soc_ctl_map) |
1419 | return; | |
1420 | ||
1421 | /* If we have a map, we expect to have a syscon */ | |
1422 | if (!sdhci_arasan->soc_ctl_base) { | |
1423 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
1424 | mmc_hostname(host->mmc)); | |
1425 | return; | |
1426 | } | |
1427 | ||
1428 | sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value); | |
1429 | } | |
1430 | ||
07a14d1d MN |
1431 | /** |
1432 | * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use | |
1433 | * | |
4908460e MN |
1434 | * @sdhci_arasan: Our private data structure. |
1435 | * @clk_xin: Pointer to the functional clock | |
1436 | * @dev: Pointer to our struct device. | |
1437 | * | |
07a14d1d MN |
1438 | * Some PHY devices need to know what the actual card clock is. In order for |
1439 | * them to find out, we'll provide a clock through the common clock framework | |
1440 | * for them to query. | |
1441 | * | |
1442 | * Note: without seriously re-architecting SDHCI's clock code and testing on | |
1443 | * all platforms, there's no way to create a totally beautiful clock here | |
1444 | * with all clock ops implemented. Instead, we'll just create a clock that can | |
1445 | * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock | |
1446 | * framework that we're doing things behind its back. This should be sufficient | |
1447 | * to create nice clean device tree bindings and later (if needed) we can try | |
1448 | * re-architecting SDHCI if we see some benefit to it. | |
1449 | * | |
4908460e | 1450 | * Return: 0 on success and error value on error |
07a14d1d MN |
1451 | */ |
1452 | static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, | |
1453 | struct clk *clk_xin, | |
1454 | struct device *dev) | |
1455 | { | |
1456 | struct device_node *np = dev->of_node; | |
1457 | u32 num_clks = 0; | |
1458 | int ret; | |
1459 | ||
1460 | /* Providing a clock to the PHY is optional; no error if missing */ | |
1461 | if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) | |
1462 | return 0; | |
1463 | ||
1464 | ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev); | |
1465 | if (ret) | |
1466 | return ret; | |
1467 | ||
1468 | if (num_clks) { | |
1469 | ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin, | |
1470 | dev); | |
1471 | if (ret) { | |
1472 | sdhci_arasan_unregister_sdclk(dev); | |
1473 | return ret; | |
1474 | } | |
1475 | } | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
84362d79 SL |
1480 | static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) |
1481 | { | |
1482 | struct sdhci_host *host = sdhci_arasan->host; | |
1483 | struct cqhci_host *cq_host; | |
1484 | bool dma64; | |
1485 | int ret; | |
1486 | ||
1487 | if (!sdhci_arasan->has_cqe) | |
1488 | return sdhci_add_host(host); | |
1489 | ||
1490 | ret = sdhci_setup_host(host); | |
1491 | if (ret) | |
1492 | return ret; | |
1493 | ||
1494 | cq_host = devm_kzalloc(host->mmc->parent, | |
1495 | sizeof(*cq_host), GFP_KERNEL); | |
1496 | if (!cq_host) { | |
1497 | ret = -ENOMEM; | |
1498 | goto cleanup; | |
1499 | } | |
1500 | ||
1501 | cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; | |
1502 | cq_host->ops = &sdhci_arasan_cqhci_ops; | |
1503 | ||
1504 | dma64 = host->flags & SDHCI_USE_64_BIT_DMA; | |
1505 | if (dma64) | |
1506 | cq_host->caps |= CQHCI_TASK_DESC_SZ_128; | |
1507 | ||
1508 | ret = cqhci_init(cq_host, host->mmc, dma64); | |
1509 | if (ret) | |
1510 | goto cleanup; | |
1511 | ||
1512 | ret = __sdhci_add_host(host); | |
1513 | if (ret) | |
1514 | goto cleanup; | |
1515 | ||
1516 | return 0; | |
1517 | ||
1518 | cleanup: | |
1519 | sdhci_cleanup_host(host); | |
1520 | return ret; | |
1521 | } | |
1522 | ||
e3ec3a3d SB |
1523 | static int sdhci_arasan_probe(struct platform_device *pdev) |
1524 | { | |
1525 | int ret; | |
3ea4666e | 1526 | struct device_node *node; |
e3ec3a3d SB |
1527 | struct clk *clk_xin; |
1528 | struct sdhci_host *host; | |
1529 | struct sdhci_pltfm_host *pltfm_host; | |
2ff0b85d MHZ |
1530 | struct device *dev = &pdev->dev; |
1531 | struct device_node *np = dev->of_node; | |
e3ec3a3d | 1532 | struct sdhci_arasan_data *sdhci_arasan; |
06b23ca0 | 1533 | const struct sdhci_arasan_of_data *data; |
84362d79 | 1534 | |
2ff0b85d | 1535 | data = of_device_get_match_data(dev); |
06b23ca0 | 1536 | host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); |
e3ec3a3d | 1537 | |
89211418 JZ |
1538 | if (IS_ERR(host)) |
1539 | return PTR_ERR(host); | |
1540 | ||
1541 | pltfm_host = sdhci_priv(host); | |
1542 | sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
c390f211 | 1543 | sdhci_arasan->host = host; |
e3ec3a3d | 1544 | |
06b23ca0 | 1545 | sdhci_arasan->soc_ctl_map = data->soc_ctl_map; |
16ada730 | 1546 | sdhci_arasan->clk_ops = data->clk_ops; |
3ea4666e | 1547 | |
80d41efe | 1548 | node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0); |
3ea4666e DA |
1549 | if (node) { |
1550 | sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); | |
1551 | of_node_put(node); | |
1552 | ||
1553 | if (IS_ERR(sdhci_arasan->soc_ctl_base)) { | |
2ff0b85d | 1554 | ret = dev_err_probe(dev, |
72ea817d KK |
1555 | PTR_ERR(sdhci_arasan->soc_ctl_base), |
1556 | "Can't get syscon\n"); | |
3ea4666e DA |
1557 | goto err_pltfm_free; |
1558 | } | |
1559 | } | |
1560 | ||
b2af3227 R |
1561 | sdhci_get_of_property(pdev); |
1562 | ||
2ff0b85d | 1563 | sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb"); |
e3ec3a3d | 1564 | if (IS_ERR(sdhci_arasan->clk_ahb)) { |
ffd68f35 MHZ |
1565 | ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb), |
1566 | "clk_ahb clock not found.\n"); | |
278d0962 | 1567 | goto err_pltfm_free; |
e3ec3a3d SB |
1568 | } |
1569 | ||
2ff0b85d | 1570 | clk_xin = devm_clk_get(dev, "clk_xin"); |
e3ec3a3d | 1571 | if (IS_ERR(clk_xin)) { |
ffd68f35 | 1572 | ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n"); |
278d0962 | 1573 | goto err_pltfm_free; |
e3ec3a3d SB |
1574 | } |
1575 | ||
1576 | ret = clk_prepare_enable(sdhci_arasan->clk_ahb); | |
1577 | if (ret) { | |
2ff0b85d | 1578 | dev_err(dev, "Unable to enable AHB clock.\n"); |
278d0962 | 1579 | goto err_pltfm_free; |
e3ec3a3d SB |
1580 | } |
1581 | ||
b2af3227 R |
1582 | /* If clock-frequency property is set, use the provided value */ |
1583 | if (pltfm_host->clock && | |
1584 | pltfm_host->clock != clk_get_rate(clk_xin)) { | |
1585 | ret = clk_set_rate(clk_xin, pltfm_host->clock); | |
1586 | if (ret) { | |
1587 | dev_err(&pdev->dev, "Failed to set SD clock rate\n"); | |
1588 | goto clk_dis_ahb; | |
1589 | } | |
1590 | } | |
1591 | ||
e3ec3a3d SB |
1592 | ret = clk_prepare_enable(clk_xin); |
1593 | if (ret) { | |
2ff0b85d | 1594 | dev_err(dev, "Unable to enable SD clock.\n"); |
e3ec3a3d SB |
1595 | goto clk_dis_ahb; |
1596 | } | |
1597 | ||
3794c542 ZB |
1598 | if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) |
1599 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; | |
1600 | ||
3f2c7d5d HG |
1601 | if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) |
1602 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; | |
1603 | ||
e3ec3a3d SB |
1604 | pltfm_host->clk = clk_xin; |
1605 | ||
80d41efe | 1606 | if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1")) |
b2ca77c9 SL |
1607 | sdhci_arasan_update_clockmultiplier(host, 0x0); |
1608 | ||
36c6aada WAZ |
1609 | if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || |
1610 | of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || | |
1611 | of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { | |
1612 | sdhci_arasan_update_clockmultiplier(host, 0x0); | |
1613 | sdhci_arasan_update_support64b(host, 0x0); | |
1614 | ||
1615 | host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; | |
1616 | } | |
1617 | ||
3ea4666e DA |
1618 | sdhci_arasan_update_baseclkfreq(host); |
1619 | ||
2ff0b85d | 1620 | ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev); |
c390f211 DA |
1621 | if (ret) |
1622 | goto clk_disable_all; | |
1623 | ||
a5c8b2ae | 1624 | if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { |
8d2e3343 MN |
1625 | host->mmc_host_ops.execute_tuning = |
1626 | arasan_zynqmp_execute_tuning; | |
c0b4e411 MN |
1627 | |
1628 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN; | |
a5c8b2ae MN |
1629 | } |
1630 | ||
2ff0b85d | 1631 | arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data); |
f3dafc37 | 1632 | |
16b23787 MS |
1633 | ret = mmc_of_parse(host->mmc); |
1634 | if (ret) { | |
ffd68f35 | 1635 | ret = dev_err_probe(dev, ret, "parsing dt failed.\n"); |
c390f211 | 1636 | goto unreg_clk; |
16b23787 MS |
1637 | } |
1638 | ||
91aa3661 | 1639 | sdhci_arasan->phy = ERR_PTR(-ENODEV); |
80d41efe | 1640 | if (of_device_is_compatible(np, "arasan,sdhci-5.1")) { |
2ff0b85d | 1641 | sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan"); |
91aa3661 | 1642 | if (IS_ERR(sdhci_arasan->phy)) { |
ffd68f35 MHZ |
1643 | ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy), |
1644 | "No phy for arasan,sdhci-5.1.\n"); | |
c390f211 | 1645 | goto unreg_clk; |
91aa3661 SL |
1646 | } |
1647 | ||
1648 | ret = phy_init(sdhci_arasan->phy); | |
1649 | if (ret < 0) { | |
2ff0b85d | 1650 | dev_err(dev, "phy_init err.\n"); |
c390f211 | 1651 | goto unreg_clk; |
91aa3661 SL |
1652 | } |
1653 | ||
a05c8465 SL |
1654 | host->mmc_host_ops.hs400_enhanced_strobe = |
1655 | sdhci_arasan_hs400_enhanced_strobe; | |
8a3bee9b SL |
1656 | host->mmc_host_ops.start_signal_voltage_switch = |
1657 | sdhci_arasan_voltage_switch; | |
84362d79 | 1658 | sdhci_arasan->has_cqe = true; |
7bda9482 CM |
1659 | host->mmc->caps2 |= MMC_CAP2_CQE; |
1660 | ||
1661 | if (!of_property_read_bool(np, "disable-cqe-dcmd")) | |
1662 | host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; | |
91aa3661 SL |
1663 | } |
1664 | ||
84362d79 | 1665 | ret = sdhci_arasan_add_host(sdhci_arasan); |
b1df9de7 | 1666 | if (ret) |
91aa3661 | 1667 | goto err_add_host; |
e3ec3a3d SB |
1668 | |
1669 | return 0; | |
1670 | ||
91aa3661 | 1671 | err_add_host: |
91aa3661 SL |
1672 | if (!IS_ERR(sdhci_arasan->phy)) |
1673 | phy_exit(sdhci_arasan->phy); | |
c390f211 | 1674 | unreg_clk: |
2ff0b85d | 1675 | sdhci_arasan_unregister_sdclk(dev); |
e3ec3a3d SB |
1676 | clk_disable_all: |
1677 | clk_disable_unprepare(clk_xin); | |
1678 | clk_dis_ahb: | |
1679 | clk_disable_unprepare(sdhci_arasan->clk_ahb); | |
278d0962 SL |
1680 | err_pltfm_free: |
1681 | sdhci_pltfm_free(pdev); | |
e3ec3a3d SB |
1682 | return ret; |
1683 | } | |
1684 | ||
1685 | static int sdhci_arasan_remove(struct platform_device *pdev) | |
1686 | { | |
0c7fe32e | 1687 | int ret; |
e3ec3a3d SB |
1688 | struct sdhci_host *host = platform_get_drvdata(pdev); |
1689 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 JZ |
1690 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
1691 | struct clk *clk_ahb = sdhci_arasan->clk_ahb; | |
e3ec3a3d | 1692 | |
91aa3661 | 1693 | if (!IS_ERR(sdhci_arasan->phy)) { |
b2db9c67 DA |
1694 | if (sdhci_arasan->is_phy_on) |
1695 | phy_power_off(sdhci_arasan->phy); | |
91aa3661 SL |
1696 | phy_exit(sdhci_arasan->phy); |
1697 | } | |
1698 | ||
c390f211 DA |
1699 | sdhci_arasan_unregister_sdclk(&pdev->dev); |
1700 | ||
0c7fe32e JZ |
1701 | ret = sdhci_pltfm_unregister(pdev); |
1702 | ||
89211418 | 1703 | clk_disable_unprepare(clk_ahb); |
e3ec3a3d | 1704 | |
0c7fe32e | 1705 | return ret; |
e3ec3a3d SB |
1706 | } |
1707 | ||
e3ec3a3d SB |
1708 | static struct platform_driver sdhci_arasan_driver = { |
1709 | .driver = { | |
1710 | .name = "sdhci-arasan", | |
21b2cec6 | 1711 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
e3ec3a3d SB |
1712 | .of_match_table = sdhci_arasan_of_match, |
1713 | .pm = &sdhci_arasan_dev_pm_ops, | |
1714 | }, | |
1715 | .probe = sdhci_arasan_probe, | |
1716 | .remove = sdhci_arasan_remove, | |
1717 | }; | |
1718 | ||
1719 | module_platform_driver(sdhci_arasan_driver); | |
1720 | ||
1721 | MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); | |
1722 | MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); | |
1723 | MODULE_LICENSE("GPL"); |