Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e3ec3a3d SB |
2 | /* |
3 | * Arasan Secure Digital Host Controller Interface. | |
4 | * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> | |
5 | * Copyright (c) 2012 Wind River Systems, Inc. | |
6 | * Copyright (C) 2013 Pengutronix e.K. | |
7 | * Copyright (C) 2013 Xilinx Inc. | |
8 | * | |
9 | * Based on sdhci-of-esdhc.c | |
10 | * | |
11 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
12 | * Copyright (c) 2009 MontaVista Software, Inc. | |
13 | * | |
14 | * Authors: Xiaobo Xie <X.Xie@freescale.com> | |
15 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
e3ec3a3d SB |
16 | */ |
17 | ||
c390f211 | 18 | #include <linux/clk-provider.h> |
3ea4666e | 19 | #include <linux/mfd/syscon.h> |
e3ec3a3d | 20 | #include <linux/module.h> |
308f3f8d | 21 | #include <linux/of_device.h> |
91aa3661 | 22 | #include <linux/phy/phy.h> |
3ea4666e | 23 | #include <linux/regmap.h> |
3794c542 | 24 | #include <linux/of.h> |
a5c8b2ae | 25 | #include <linux/firmware/xlnx-zynqmp.h> |
e3ec3a3d | 26 | |
84362d79 SL |
27 | #include "cqhci.h" |
28 | #include "sdhci-pltfm.h" | |
e3ec3a3d | 29 | |
84362d79 | 30 | #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 |
1a470721 MN |
31 | |
32 | #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8 | |
d338c6d0 MN |
33 | #define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF |
34 | ||
1a470721 | 35 | #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC |
d338c6d0 | 36 | #define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F |
1a470721 | 37 | |
84362d79 | 38 | #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 |
a05c8465 | 39 | #define VENDOR_ENHANCED_STROBE BIT(0) |
e3ec3a3d | 40 | |
b2db9c67 DA |
41 | #define PHY_CLK_TOO_SLOW_HZ 400000 |
42 | ||
1a470721 MN |
43 | #define SDHCI_ITAPDLY_CHGWIN 0x200 |
44 | #define SDHCI_ITAPDLY_ENABLE 0x100 | |
45 | #define SDHCI_OTAPDLY_ENABLE 0x40 | |
46 | ||
a5c8b2ae MN |
47 | /* Default settings for ZynqMP Clock Phases */ |
48 | #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0} | |
49 | #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0} | |
50 | ||
1a470721 MN |
51 | #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0} |
52 | #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0} | |
53 | ||
3ea4666e DA |
54 | /* |
55 | * On some SoCs the syscon area has a feature where the upper 16-bits of | |
56 | * each 32-bit register act as a write mask for the lower 16-bits. This allows | |
57 | * atomic updates of the register without locking. This macro is used on SoCs | |
58 | * that have that feature. | |
59 | */ | |
60 | #define HIWORD_UPDATE(val, mask, shift) \ | |
61 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
62 | ||
63 | /** | |
64 | * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map | |
65 | * | |
66 | * @reg: Offset within the syscon of the register containing this field | |
67 | * @width: Number of bits for this field | |
68 | * @shift: Bit offset within @reg of this field (or -1 if not avail) | |
69 | */ | |
70 | struct sdhci_arasan_soc_ctl_field { | |
71 | u32 reg; | |
72 | u16 width; | |
73 | s16 shift; | |
74 | }; | |
75 | ||
76 | /** | |
77 | * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers | |
78 | * | |
3ea4666e | 79 | * @baseclkfreq: Where to find corecfg_baseclkfreq |
b2ca77c9 | 80 | * @clockmultiplier: Where to find corecfg_clockmultiplier |
36c6aada | 81 | * @support64b: Where to find SUPPORT64B bit |
3ea4666e | 82 | * @hiword_update: If true, use HIWORD_UPDATE to access the syscon |
4908460e MN |
83 | * |
84 | * It's up to the licensee of the Arsan IP block to make these available | |
85 | * somewhere if needed. Presumably these will be scattered somewhere that's | |
86 | * accessible via the syscon API. | |
3ea4666e DA |
87 | */ |
88 | struct sdhci_arasan_soc_ctl_map { | |
89 | struct sdhci_arasan_soc_ctl_field baseclkfreq; | |
b2ca77c9 | 90 | struct sdhci_arasan_soc_ctl_field clockmultiplier; |
36c6aada | 91 | struct sdhci_arasan_soc_ctl_field support64b; |
3ea4666e DA |
92 | bool hiword_update; |
93 | }; | |
94 | ||
16ada730 MN |
95 | /** |
96 | * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller | |
97 | * | |
98 | * @sdcardclk_ops: The output clock related operations | |
99 | * @sampleclk_ops: The sample clock related operations | |
100 | */ | |
101 | struct sdhci_arasan_clk_ops { | |
102 | const struct clk_ops *sdcardclk_ops; | |
103 | const struct clk_ops *sampleclk_ops; | |
104 | }; | |
105 | ||
e1463618 | 106 | /** |
4908460e MN |
107 | * struct sdhci_arasan_clk_data - Arasan Controller Clock Data. |
108 | * | |
e1463618 MN |
109 | * @sdcardclk_hw: Struct for the clock we might provide to a PHY. |
110 | * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. | |
07a14d1d MN |
111 | * @sampleclk_hw: Struct for the clock we might provide to a PHY. |
112 | * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw. | |
f3dafc37 MN |
113 | * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes |
114 | * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes | |
115 | * @set_clk_delays: Function pointer for setting Clock Delays | |
a5c8b2ae | 116 | * @clk_of_data: Platform specific runtime clock data storage pointer |
e1463618 MN |
117 | */ |
118 | struct sdhci_arasan_clk_data { | |
119 | struct clk_hw sdcardclk_hw; | |
120 | struct clk *sdcardclk; | |
07a14d1d MN |
121 | struct clk_hw sampleclk_hw; |
122 | struct clk *sampleclk; | |
f3dafc37 MN |
123 | int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; |
124 | int clk_phase_out[MMC_TIMING_MMC_HS400 + 1]; | |
125 | void (*set_clk_delays)(struct sdhci_host *host); | |
a5c8b2ae MN |
126 | void *clk_of_data; |
127 | }; | |
128 | ||
e3ec3a3d | 129 | /** |
4908460e MN |
130 | * struct sdhci_arasan_data - Arasan Controller Data |
131 | * | |
c390f211 | 132 | * @host: Pointer to the main SDHCI host structure. |
3ea4666e DA |
133 | * @clk_ahb: Pointer to the AHB clock |
134 | * @phy: Pointer to the generic phy | |
b2db9c67 | 135 | * @is_phy_on: True if the PHY is on; false if not. |
4908460e | 136 | * @has_cqe: True if controller has command queuing engine. |
e1463618 | 137 | * @clk_data: Struct for the Arasan Controller Clock Data. |
16ada730 | 138 | * @clk_ops: Struct for the Arasan Controller Clock Operations. |
3ea4666e DA |
139 | * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. |
140 | * @soc_ctl_map: Map to get offsets into soc_ctl registers. | |
4908460e | 141 | * @quirks: Arasan deviations from spec. |
e3ec3a3d SB |
142 | */ |
143 | struct sdhci_arasan_data { | |
c390f211 | 144 | struct sdhci_host *host; |
e3ec3a3d | 145 | struct clk *clk_ahb; |
91aa3661 | 146 | struct phy *phy; |
b2db9c67 | 147 | bool is_phy_on; |
3ea4666e | 148 | |
84362d79 | 149 | bool has_cqe; |
e1463618 | 150 | struct sdhci_arasan_clk_data clk_data; |
16ada730 | 151 | const struct sdhci_arasan_clk_ops *clk_ops; |
c390f211 | 152 | |
3ea4666e DA |
153 | struct regmap *soc_ctl_base; |
154 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
4908460e | 155 | unsigned int quirks; |
3794c542 ZB |
156 | |
157 | /* Controller does not have CD wired and will not function normally without */ | |
158 | #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) | |
3f2c7d5d HG |
159 | /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the |
160 | * internal clock even when the clock isn't stable */ | |
161 | #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) | |
3ea4666e DA |
162 | }; |
163 | ||
06b23ca0 FA |
164 | struct sdhci_arasan_of_data { |
165 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
166 | const struct sdhci_pltfm_data *pdata; | |
16ada730 | 167 | const struct sdhci_arasan_clk_ops *clk_ops; |
06b23ca0 FA |
168 | }; |
169 | ||
3ea4666e DA |
170 | static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { |
171 | .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, | |
b2ca77c9 | 172 | .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, |
3ea4666e | 173 | .hiword_update = true, |
e3ec3a3d SB |
174 | }; |
175 | ||
5c1a4f40 RVM |
176 | static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = { |
177 | .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 }, | |
178 | .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, | |
179 | .hiword_update = false, | |
180 | }; | |
181 | ||
d1807ad6 RVM |
182 | static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = { |
183 | .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 }, | |
184 | .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, | |
185 | .hiword_update = false, | |
186 | }; | |
187 | ||
36c6aada WAZ |
188 | static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = { |
189 | .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 }, | |
190 | .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, | |
191 | .support64b = { .reg = 0x4, .width = 1, .shift = 24 }, | |
192 | .hiword_update = false, | |
193 | }; | |
194 | ||
3ea4666e DA |
195 | /** |
196 | * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers | |
197 | * | |
4908460e MN |
198 | * @host: The sdhci_host |
199 | * @fld: The field to write to | |
200 | * @val: The value to write | |
201 | * | |
3ea4666e DA |
202 | * This function allows writing to fields in sdhci_arasan_soc_ctl_map. |
203 | * Note that if a field is specified as not available (shift < 0) then | |
204 | * this function will silently return an error code. It will be noisy | |
205 | * and print errors for any other (unexpected) errors. | |
206 | * | |
4908460e | 207 | * Return: 0 on success and error value on error |
3ea4666e DA |
208 | */ |
209 | static int sdhci_arasan_syscon_write(struct sdhci_host *host, | |
210 | const struct sdhci_arasan_soc_ctl_field *fld, | |
211 | u32 val) | |
212 | { | |
213 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
214 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
215 | struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; | |
216 | u32 reg = fld->reg; | |
217 | u16 width = fld->width; | |
218 | s16 shift = fld->shift; | |
219 | int ret; | |
220 | ||
221 | /* | |
222 | * Silently return errors for shift < 0 so caller doesn't have | |
223 | * to check for fields which are optional. For fields that | |
224 | * are required then caller needs to do something special | |
225 | * anyway. | |
226 | */ | |
227 | if (shift < 0) | |
228 | return -EINVAL; | |
229 | ||
230 | if (sdhci_arasan->soc_ctl_map->hiword_update) | |
231 | ret = regmap_write(soc_ctl_base, reg, | |
232 | HIWORD_UPDATE(val, GENMASK(width, 0), | |
233 | shift)); | |
234 | else | |
235 | ret = regmap_update_bits(soc_ctl_base, reg, | |
236 | GENMASK(shift + width, shift), | |
237 | val << shift); | |
238 | ||
239 | /* Yell about (unexpected) regmap errors */ | |
240 | if (ret) | |
241 | pr_warn("%s: Regmap write fail: %d\n", | |
242 | mmc_hostname(host->mmc), ret); | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
802ac39a SL |
247 | static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) |
248 | { | |
249 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
250 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
f3dafc37 | 251 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; |
6fc09244 | 252 | bool ctrl_phy = false; |
802ac39a | 253 | |
b2db9c67 DA |
254 | if (!IS_ERR(sdhci_arasan->phy)) { |
255 | if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { | |
256 | /* | |
257 | * If PHY off, set clock to max speed and power PHY on. | |
258 | * | |
259 | * Although PHY docs apparently suggest power cycling | |
260 | * when changing the clock the PHY doesn't like to be | |
261 | * powered on while at low speeds like those used in ID | |
262 | * mode. Even worse is powering the PHY on while the | |
263 | * clock is off. | |
264 | * | |
265 | * To workaround the PHY limitations, the best we can | |
266 | * do is to power it on at a faster speed and then slam | |
267 | * through low speeds without power cycling. | |
268 | */ | |
269 | sdhci_set_clock(host, host->max_clk); | |
b2db9c67 | 270 | phy_power_on(sdhci_arasan->phy); |
b2db9c67 DA |
271 | sdhci_arasan->is_phy_on = true; |
272 | ||
273 | /* | |
274 | * We'll now fall through to the below case with | |
275 | * ctrl_phy = false (so we won't turn off/on). The | |
276 | * sdhci_set_clock() will set the real clock. | |
277 | */ | |
278 | } else if (clock > PHY_CLK_TOO_SLOW_HZ) { | |
279 | /* | |
280 | * At higher clock speeds the PHY is fine being power | |
281 | * cycled and docs say you _should_ power cycle when | |
282 | * changing clock speeds. | |
283 | */ | |
284 | ctrl_phy = true; | |
285 | } | |
286 | } | |
802ac39a | 287 | |
b2db9c67 | 288 | if (ctrl_phy && sdhci_arasan->is_phy_on) { |
802ac39a | 289 | phy_power_off(sdhci_arasan->phy); |
b2db9c67 | 290 | sdhci_arasan->is_phy_on = false; |
802ac39a SL |
291 | } |
292 | ||
f3dafc37 MN |
293 | /* Set the Input and Output Clock Phase Delays */ |
294 | if (clk_data->set_clk_delays) | |
295 | clk_data->set_clk_delays(host); | |
296 | ||
802ac39a SL |
297 | sdhci_set_clock(host, clock); |
298 | ||
3f2c7d5d HG |
299 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) |
300 | /* | |
301 | * Some controllers immediately report SDHCI_CLOCK_INT_STABLE | |
302 | * after enabling the clock even though the clock is not | |
303 | * stable. Trying to use a clock without waiting here results | |
304 | * in EILSEQ while detecting some older/slower cards. The | |
305 | * chosen delay is the maximum delay from sdhci_set_clock. | |
306 | */ | |
307 | msleep(20); | |
308 | ||
6fc09244 | 309 | if (ctrl_phy) { |
802ac39a | 310 | phy_power_on(sdhci_arasan->phy); |
b2db9c67 | 311 | sdhci_arasan->is_phy_on = true; |
802ac39a SL |
312 | } |
313 | } | |
314 | ||
a05c8465 SL |
315 | static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, |
316 | struct mmc_ios *ios) | |
317 | { | |
318 | u32 vendor; | |
319 | struct sdhci_host *host = mmc_priv(mmc); | |
320 | ||
0daf72fe | 321 | vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); |
a05c8465 SL |
322 | if (ios->enhanced_strobe) |
323 | vendor |= VENDOR_ENHANCED_STROBE; | |
324 | else | |
325 | vendor &= ~VENDOR_ENHANCED_STROBE; | |
326 | ||
0daf72fe | 327 | sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); |
a05c8465 SL |
328 | } |
329 | ||
13d62fd2 | 330 | static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) |
3794c542 ZB |
331 | { |
332 | u8 ctrl; | |
333 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
334 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
335 | ||
336 | sdhci_reset(host, mask); | |
337 | ||
338 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { | |
339 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
340 | ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; | |
341 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
342 | } | |
343 | } | |
344 | ||
8a3bee9b SL |
345 | static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, |
346 | struct mmc_ios *ios) | |
347 | { | |
348 | switch (ios->signal_voltage) { | |
349 | case MMC_SIGNAL_VOLTAGE_180: | |
350 | /* | |
351 | * Plese don't switch to 1V8 as arasan,5.1 doesn't | |
352 | * actually refer to this setting to indicate the | |
353 | * signal voltage and the state machine will be broken | |
354 | * actually if we force to enable 1V8. That's something | |
355 | * like broken quirk but we could work around here. | |
356 | */ | |
357 | return 0; | |
358 | case MMC_SIGNAL_VOLTAGE_330: | |
359 | case MMC_SIGNAL_VOLTAGE_120: | |
360 | /* We don't support 3V3 and 1V2 */ | |
361 | break; | |
362 | } | |
363 | ||
364 | return -EINVAL; | |
365 | } | |
366 | ||
a81dae3a | 367 | static const struct sdhci_ops sdhci_arasan_ops = { |
802ac39a | 368 | .set_clock = sdhci_arasan_set_clock, |
e3ec3a3d | 369 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
8cc35289 | 370 | .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, |
2317f56c | 371 | .set_bus_width = sdhci_set_bus_width, |
3794c542 | 372 | .reset = sdhci_arasan_reset, |
96d7b78c | 373 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
c2c5252c | 374 | .set_power = sdhci_set_power_and_bus_voltage, |
e3ec3a3d SB |
375 | }; |
376 | ||
84362d79 SL |
377 | static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) |
378 | { | |
379 | int cmd_error = 0; | |
380 | int data_error = 0; | |
381 | ||
382 | if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) | |
383 | return intmask; | |
384 | ||
385 | cqhci_irq(host->mmc, intmask, cmd_error, data_error); | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | static void sdhci_arasan_dumpregs(struct mmc_host *mmc) | |
391 | { | |
392 | sdhci_dumpregs(mmc_priv(mmc)); | |
393 | } | |
394 | ||
395 | static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) | |
396 | { | |
397 | struct sdhci_host *host = mmc_priv(mmc); | |
398 | u32 reg; | |
399 | ||
400 | reg = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
401 | while (reg & SDHCI_DATA_AVAILABLE) { | |
402 | sdhci_readl(host, SDHCI_BUFFER); | |
403 | reg = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
404 | } | |
405 | ||
406 | sdhci_cqe_enable(mmc); | |
407 | } | |
408 | ||
409 | static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { | |
410 | .enable = sdhci_arasan_cqe_enable, | |
411 | .disable = sdhci_cqe_disable, | |
412 | .dumpregs = sdhci_arasan_dumpregs, | |
413 | }; | |
414 | ||
415 | static const struct sdhci_ops sdhci_arasan_cqe_ops = { | |
416 | .set_clock = sdhci_arasan_set_clock, | |
417 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | |
418 | .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, | |
419 | .set_bus_width = sdhci_set_bus_width, | |
420 | .reset = sdhci_arasan_reset, | |
421 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
c2c5252c | 422 | .set_power = sdhci_set_power_and_bus_voltage, |
84362d79 SL |
423 | .irq = sdhci_arasan_cqhci_irq, |
424 | }; | |
425 | ||
426 | static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { | |
427 | .ops = &sdhci_arasan_cqe_ops, | |
428 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
429 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
430 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, | |
431 | }; | |
432 | ||
e3ec3a3d SB |
433 | #ifdef CONFIG_PM_SLEEP |
434 | /** | |
435 | * sdhci_arasan_suspend - Suspend method for the driver | |
436 | * @dev: Address of the device structure | |
e3ec3a3d SB |
437 | * |
438 | * Put the device in a low power state. | |
4908460e MN |
439 | * |
440 | * Return: 0 on success and error value on error | |
e3ec3a3d SB |
441 | */ |
442 | static int sdhci_arasan_suspend(struct device *dev) | |
443 | { | |
970f2d90 | 444 | struct sdhci_host *host = dev_get_drvdata(dev); |
e3ec3a3d | 445 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
89211418 | 446 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
447 | int ret; |
448 | ||
d38dcad4 AH |
449 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
450 | mmc_retune_needed(host->mmc); | |
451 | ||
84362d79 SL |
452 | if (sdhci_arasan->has_cqe) { |
453 | ret = cqhci_suspend(host->mmc); | |
454 | if (ret) | |
455 | return ret; | |
456 | } | |
457 | ||
e3ec3a3d SB |
458 | ret = sdhci_suspend_host(host); |
459 | if (ret) | |
460 | return ret; | |
461 | ||
b2db9c67 | 462 | if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { |
91aa3661 SL |
463 | ret = phy_power_off(sdhci_arasan->phy); |
464 | if (ret) { | |
465 | dev_err(dev, "Cannot power off phy.\n"); | |
466 | sdhci_resume_host(host); | |
467 | return ret; | |
468 | } | |
b2db9c67 | 469 | sdhci_arasan->is_phy_on = false; |
91aa3661 SL |
470 | } |
471 | ||
e3ec3a3d SB |
472 | clk_disable(pltfm_host->clk); |
473 | clk_disable(sdhci_arasan->clk_ahb); | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
478 | /** | |
479 | * sdhci_arasan_resume - Resume method for the driver | |
480 | * @dev: Address of the device structure | |
e3ec3a3d SB |
481 | * |
482 | * Resume operation after suspend | |
4908460e MN |
483 | * |
484 | * Return: 0 on success and error value on error | |
e3ec3a3d SB |
485 | */ |
486 | static int sdhci_arasan_resume(struct device *dev) | |
487 | { | |
970f2d90 | 488 | struct sdhci_host *host = dev_get_drvdata(dev); |
e3ec3a3d | 489 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
89211418 | 490 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
491 | int ret; |
492 | ||
493 | ret = clk_enable(sdhci_arasan->clk_ahb); | |
494 | if (ret) { | |
495 | dev_err(dev, "Cannot enable AHB clock.\n"); | |
496 | return ret; | |
497 | } | |
498 | ||
499 | ret = clk_enable(pltfm_host->clk); | |
500 | if (ret) { | |
501 | dev_err(dev, "Cannot enable SD clock.\n"); | |
e3ec3a3d SB |
502 | return ret; |
503 | } | |
504 | ||
b2db9c67 | 505 | if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { |
91aa3661 SL |
506 | ret = phy_power_on(sdhci_arasan->phy); |
507 | if (ret) { | |
508 | dev_err(dev, "Cannot power on phy.\n"); | |
509 | return ret; | |
510 | } | |
b2db9c67 | 511 | sdhci_arasan->is_phy_on = true; |
91aa3661 SL |
512 | } |
513 | ||
84362d79 SL |
514 | ret = sdhci_resume_host(host); |
515 | if (ret) { | |
516 | dev_err(dev, "Cannot resume host.\n"); | |
517 | return ret; | |
518 | } | |
519 | ||
520 | if (sdhci_arasan->has_cqe) | |
521 | return cqhci_resume(host->mmc); | |
522 | ||
523 | return 0; | |
e3ec3a3d SB |
524 | } |
525 | #endif /* ! CONFIG_PM_SLEEP */ | |
526 | ||
527 | static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, | |
528 | sdhci_arasan_resume); | |
529 | ||
c390f211 DA |
530 | /** |
531 | * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate | |
532 | * | |
4908460e MN |
533 | * @hw: Pointer to the hardware clock structure. |
534 | * @parent_rate: The parent rate (should be rate of clk_xin). | |
535 | * | |
c390f211 DA |
536 | * Return the current actual rate of the SD card clock. This can be used |
537 | * to communicate with out PHY. | |
538 | * | |
4908460e | 539 | * Return: The card clock rate. |
c390f211 DA |
540 | */ |
541 | static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, | |
542 | unsigned long parent_rate) | |
c390f211 | 543 | { |
e1463618 MN |
544 | struct sdhci_arasan_clk_data *clk_data = |
545 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
c390f211 | 546 | struct sdhci_arasan_data *sdhci_arasan = |
e1463618 | 547 | container_of(clk_data, struct sdhci_arasan_data, clk_data); |
c390f211 DA |
548 | struct sdhci_host *host = sdhci_arasan->host; |
549 | ||
550 | return host->mmc->actual_clock; | |
551 | } | |
552 | ||
553 | static const struct clk_ops arasan_sdcardclk_ops = { | |
554 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
555 | }; | |
556 | ||
07a14d1d MN |
557 | /** |
558 | * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate | |
559 | * | |
4908460e MN |
560 | * @hw: Pointer to the hardware clock structure. |
561 | * @parent_rate: The parent rate (should be rate of clk_xin). | |
562 | * | |
07a14d1d MN |
563 | * Return the current actual rate of the sampling clock. This can be used |
564 | * to communicate with out PHY. | |
565 | * | |
4908460e | 566 | * Return: The sample clock rate. |
07a14d1d MN |
567 | */ |
568 | static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw, | |
569 | unsigned long parent_rate) | |
07a14d1d MN |
570 | { |
571 | struct sdhci_arasan_clk_data *clk_data = | |
572 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
573 | struct sdhci_arasan_data *sdhci_arasan = | |
574 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
575 | struct sdhci_host *host = sdhci_arasan->host; | |
576 | ||
577 | return host->mmc->actual_clock; | |
578 | } | |
579 | ||
580 | static const struct clk_ops arasan_sampleclk_ops = { | |
581 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
582 | }; | |
583 | ||
a5c8b2ae MN |
584 | /** |
585 | * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays | |
586 | * | |
4908460e MN |
587 | * @hw: Pointer to the hardware clock structure. |
588 | * @degrees: The clock phase shift between 0 - 359. | |
589 | * | |
a5c8b2ae MN |
590 | * Set the SD Output Clock Tap Delays for Output path |
591 | * | |
a5c8b2ae MN |
592 | * Return: 0 on success and error value on error |
593 | */ | |
594 | static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) | |
a5c8b2ae MN |
595 | { |
596 | struct sdhci_arasan_clk_data *clk_data = | |
597 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
598 | struct sdhci_arasan_data *sdhci_arasan = | |
599 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
600 | struct sdhci_host *host = sdhci_arasan->host; | |
a5c8b2ae MN |
601 | const char *clk_name = clk_hw_get_name(hw); |
602 | u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; | |
603 | u8 tap_delay, tap_max = 0; | |
604 | int ret; | |
605 | ||
9e953432 MN |
606 | /* This is applicable for SDHCI_SPEC_300 and above */ |
607 | if (host->version < SDHCI_SPEC_300) | |
a5c8b2ae MN |
608 | return 0; |
609 | ||
610 | switch (host->timing) { | |
611 | case MMC_TIMING_MMC_HS: | |
612 | case MMC_TIMING_SD_HS: | |
613 | case MMC_TIMING_UHS_SDR25: | |
614 | case MMC_TIMING_UHS_DDR50: | |
615 | case MMC_TIMING_MMC_DDR52: | |
616 | /* For 50MHz clock, 30 Taps are available */ | |
617 | tap_max = 30; | |
618 | break; | |
619 | case MMC_TIMING_UHS_SDR50: | |
620 | /* For 100MHz clock, 15 Taps are available */ | |
621 | tap_max = 15; | |
622 | break; | |
623 | case MMC_TIMING_UHS_SDR104: | |
624 | case MMC_TIMING_MMC_HS200: | |
625 | /* For 200MHz clock, 8 Taps are available */ | |
626 | tap_max = 8; | |
a3096ec6 | 627 | break; |
a5c8b2ae MN |
628 | default: |
629 | break; | |
630 | } | |
631 | ||
632 | tap_delay = (degrees * tap_max) / 360; | |
633 | ||
634 | /* Set the Clock Phase */ | |
426c8d85 | 635 | ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay); |
a5c8b2ae MN |
636 | if (ret) |
637 | pr_err("Error setting Output Tap Delay\n"); | |
638 | ||
d06d60d5 MN |
639 | /* Release DLL Reset */ |
640 | zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE); | |
641 | ||
a5c8b2ae MN |
642 | return ret; |
643 | } | |
644 | ||
645 | static const struct clk_ops zynqmp_sdcardclk_ops = { | |
646 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
647 | .set_phase = sdhci_zynqmp_sdcardclk_set_phase, | |
648 | }; | |
649 | ||
650 | /** | |
651 | * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays | |
652 | * | |
4908460e MN |
653 | * @hw: Pointer to the hardware clock structure. |
654 | * @degrees: The clock phase shift between 0 - 359. | |
655 | * | |
a5c8b2ae MN |
656 | * Set the SD Input Clock Tap Delays for Input path |
657 | * | |
a5c8b2ae MN |
658 | * Return: 0 on success and error value on error |
659 | */ | |
660 | static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) | |
a5c8b2ae MN |
661 | { |
662 | struct sdhci_arasan_clk_data *clk_data = | |
663 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
664 | struct sdhci_arasan_data *sdhci_arasan = | |
665 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
666 | struct sdhci_host *host = sdhci_arasan->host; | |
a5c8b2ae MN |
667 | const char *clk_name = clk_hw_get_name(hw); |
668 | u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1; | |
669 | u8 tap_delay, tap_max = 0; | |
670 | int ret; | |
671 | ||
9e953432 MN |
672 | /* This is applicable for SDHCI_SPEC_300 and above */ |
673 | if (host->version < SDHCI_SPEC_300) | |
a5c8b2ae MN |
674 | return 0; |
675 | ||
d06d60d5 MN |
676 | /* Assert DLL Reset */ |
677 | zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT); | |
678 | ||
a5c8b2ae MN |
679 | switch (host->timing) { |
680 | case MMC_TIMING_MMC_HS: | |
681 | case MMC_TIMING_SD_HS: | |
682 | case MMC_TIMING_UHS_SDR25: | |
683 | case MMC_TIMING_UHS_DDR50: | |
684 | case MMC_TIMING_MMC_DDR52: | |
685 | /* For 50MHz clock, 120 Taps are available */ | |
686 | tap_max = 120; | |
687 | break; | |
688 | case MMC_TIMING_UHS_SDR50: | |
689 | /* For 100MHz clock, 60 Taps are available */ | |
690 | tap_max = 60; | |
691 | break; | |
692 | case MMC_TIMING_UHS_SDR104: | |
693 | case MMC_TIMING_MMC_HS200: | |
694 | /* For 200MHz clock, 30 Taps are available */ | |
695 | tap_max = 30; | |
a3096ec6 | 696 | break; |
a5c8b2ae MN |
697 | default: |
698 | break; | |
699 | } | |
700 | ||
701 | tap_delay = (degrees * tap_max) / 360; | |
702 | ||
703 | /* Set the Clock Phase */ | |
426c8d85 | 704 | ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay); |
a5c8b2ae MN |
705 | if (ret) |
706 | pr_err("Error setting Input Tap Delay\n"); | |
707 | ||
708 | return ret; | |
709 | } | |
710 | ||
711 | static const struct clk_ops zynqmp_sampleclk_ops = { | |
712 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
713 | .set_phase = sdhci_zynqmp_sampleclk_set_phase, | |
714 | }; | |
715 | ||
1a470721 MN |
716 | /** |
717 | * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays | |
718 | * | |
4908460e MN |
719 | * @hw: Pointer to the hardware clock structure. |
720 | * @degrees: The clock phase shift between 0 - 359. | |
721 | * | |
1a470721 MN |
722 | * Set the SD Output Clock Tap Delays for Output path |
723 | * | |
1a470721 MN |
724 | * Return: 0 on success and error value on error |
725 | */ | |
726 | static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees) | |
727 | { | |
728 | struct sdhci_arasan_clk_data *clk_data = | |
729 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
730 | struct sdhci_arasan_data *sdhci_arasan = | |
731 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
732 | struct sdhci_host *host = sdhci_arasan->host; | |
733 | u8 tap_delay, tap_max = 0; | |
1a470721 | 734 | |
9e953432 MN |
735 | /* This is applicable for SDHCI_SPEC_300 and above */ |
736 | if (host->version < SDHCI_SPEC_300) | |
1a470721 MN |
737 | return 0; |
738 | ||
739 | switch (host->timing) { | |
740 | case MMC_TIMING_MMC_HS: | |
741 | case MMC_TIMING_SD_HS: | |
742 | case MMC_TIMING_UHS_SDR25: | |
743 | case MMC_TIMING_UHS_DDR50: | |
744 | case MMC_TIMING_MMC_DDR52: | |
745 | /* For 50MHz clock, 30 Taps are available */ | |
746 | tap_max = 30; | |
747 | break; | |
748 | case MMC_TIMING_UHS_SDR50: | |
749 | /* For 100MHz clock, 15 Taps are available */ | |
750 | tap_max = 15; | |
751 | break; | |
752 | case MMC_TIMING_UHS_SDR104: | |
753 | case MMC_TIMING_MMC_HS200: | |
754 | /* For 200MHz clock, 8 Taps are available */ | |
755 | tap_max = 8; | |
a3096ec6 | 756 | break; |
1a470721 MN |
757 | default: |
758 | break; | |
759 | } | |
760 | ||
761 | tap_delay = (degrees * tap_max) / 360; | |
762 | ||
763 | /* Set the Clock Phase */ | |
764 | if (tap_delay) { | |
765 | u32 regval; | |
766 | ||
767 | regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); | |
768 | regval |= SDHCI_OTAPDLY_ENABLE; | |
769 | sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); | |
d338c6d0 | 770 | regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK; |
1a470721 MN |
771 | regval |= tap_delay; |
772 | sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); | |
773 | } | |
774 | ||
098c408b | 775 | return 0; |
1a470721 MN |
776 | } |
777 | ||
778 | static const struct clk_ops versal_sdcardclk_ops = { | |
779 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
780 | .set_phase = sdhci_versal_sdcardclk_set_phase, | |
781 | }; | |
782 | ||
783 | /** | |
784 | * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays | |
785 | * | |
4908460e MN |
786 | * @hw: Pointer to the hardware clock structure. |
787 | * @degrees: The clock phase shift between 0 - 359. | |
788 | * | |
1a470721 MN |
789 | * Set the SD Input Clock Tap Delays for Input path |
790 | * | |
1a470721 MN |
791 | * Return: 0 on success and error value on error |
792 | */ | |
793 | static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees) | |
794 | { | |
795 | struct sdhci_arasan_clk_data *clk_data = | |
796 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
797 | struct sdhci_arasan_data *sdhci_arasan = | |
798 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
799 | struct sdhci_host *host = sdhci_arasan->host; | |
800 | u8 tap_delay, tap_max = 0; | |
1a470721 | 801 | |
9e953432 MN |
802 | /* This is applicable for SDHCI_SPEC_300 and above */ |
803 | if (host->version < SDHCI_SPEC_300) | |
1a470721 MN |
804 | return 0; |
805 | ||
806 | switch (host->timing) { | |
807 | case MMC_TIMING_MMC_HS: | |
808 | case MMC_TIMING_SD_HS: | |
809 | case MMC_TIMING_UHS_SDR25: | |
810 | case MMC_TIMING_UHS_DDR50: | |
811 | case MMC_TIMING_MMC_DDR52: | |
812 | /* For 50MHz clock, 120 Taps are available */ | |
813 | tap_max = 120; | |
814 | break; | |
815 | case MMC_TIMING_UHS_SDR50: | |
816 | /* For 100MHz clock, 60 Taps are available */ | |
817 | tap_max = 60; | |
818 | break; | |
819 | case MMC_TIMING_UHS_SDR104: | |
820 | case MMC_TIMING_MMC_HS200: | |
821 | /* For 200MHz clock, 30 Taps are available */ | |
822 | tap_max = 30; | |
a3096ec6 | 823 | break; |
1a470721 MN |
824 | default: |
825 | break; | |
826 | } | |
827 | ||
828 | tap_delay = (degrees * tap_max) / 360; | |
829 | ||
830 | /* Set the Clock Phase */ | |
831 | if (tap_delay) { | |
832 | u32 regval; | |
833 | ||
834 | regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
835 | regval |= SDHCI_ITAPDLY_CHGWIN; | |
836 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
837 | regval |= SDHCI_ITAPDLY_ENABLE; | |
838 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
d338c6d0 | 839 | regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK; |
1a470721 MN |
840 | regval |= tap_delay; |
841 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
842 | regval &= ~SDHCI_ITAPDLY_CHGWIN; | |
843 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
844 | } | |
845 | ||
098c408b | 846 | return 0; |
1a470721 MN |
847 | } |
848 | ||
849 | static const struct clk_ops versal_sampleclk_ops = { | |
850 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
851 | .set_phase = sdhci_versal_sampleclk_set_phase, | |
852 | }; | |
853 | ||
8d2e3343 MN |
854 | static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) |
855 | { | |
8d2e3343 MN |
856 | u16 clk; |
857 | ||
858 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
859 | clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); | |
860 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
861 | ||
862 | /* Issue DLL Reset */ | |
426c8d85 | 863 | zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE); |
8d2e3343 MN |
864 | |
865 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
866 | ||
867 | sdhci_enable_clk(host, clk); | |
868 | } | |
869 | ||
870 | static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode) | |
871 | { | |
872 | struct sdhci_host *host = mmc_priv(mmc); | |
873 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
874 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
875 | struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; | |
876 | const char *clk_name = clk_hw_get_name(hw); | |
877 | u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : | |
878 | NODE_SD_1; | |
879 | int err; | |
880 | ||
881 | arasan_zynqmp_dll_reset(host, device_id); | |
882 | ||
883 | err = sdhci_execute_tuning(mmc, opcode); | |
884 | if (err) | |
885 | return err; | |
886 | ||
887 | arasan_zynqmp_dll_reset(host, device_id); | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
b2ca77c9 SL |
892 | /** |
893 | * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier | |
894 | * | |
4908460e MN |
895 | * @host: The sdhci_host |
896 | * @value: The value to write | |
897 | * | |
b2ca77c9 SL |
898 | * The corecfg_clockmultiplier is supposed to contain clock multiplier |
899 | * value of programmable clock generator. | |
900 | * | |
901 | * NOTES: | |
902 | * - Many existing devices don't seem to do this and work fine. To keep | |
903 | * compatibility for old hardware where the device tree doesn't provide a | |
904 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
905 | * for this platform. | |
906 | * - The value of corecfg_clockmultiplier should sync with that of corresponding | |
907 | * value reading from sdhci_capability_register. So this function is called | |
908 | * once at probe time and never called again. | |
b2ca77c9 SL |
909 | */ |
910 | static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, | |
911 | u32 value) | |
912 | { | |
913 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
914 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
915 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
916 | sdhci_arasan->soc_ctl_map; | |
917 | ||
918 | /* Having a map is optional */ | |
919 | if (!soc_ctl_map) | |
920 | return; | |
921 | ||
922 | /* If we have a map, we expect to have a syscon */ | |
923 | if (!sdhci_arasan->soc_ctl_base) { | |
924 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
925 | mmc_hostname(host->mmc)); | |
926 | return; | |
927 | } | |
928 | ||
929 | sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); | |
930 | } | |
931 | ||
3ea4666e DA |
932 | /** |
933 | * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq | |
934 | * | |
4908460e MN |
935 | * @host: The sdhci_host |
936 | * | |
3ea4666e DA |
937 | * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This |
938 | * function can be used to make that happen. | |
939 | * | |
940 | * NOTES: | |
941 | * - Many existing devices don't seem to do this and work fine. To keep | |
942 | * compatibility for old hardware where the device tree doesn't provide a | |
943 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
944 | * for this platform. | |
945 | * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider | |
946 | * to achieve lower clock rates. That means that this function is called once | |
947 | * at probe time and never called again. | |
3ea4666e DA |
948 | */ |
949 | static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) | |
950 | { | |
951 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
952 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
953 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
954 | sdhci_arasan->soc_ctl_map; | |
955 | u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); | |
956 | ||
957 | /* Having a map is optional */ | |
958 | if (!soc_ctl_map) | |
959 | return; | |
960 | ||
961 | /* If we have a map, we expect to have a syscon */ | |
962 | if (!sdhci_arasan->soc_ctl_base) { | |
963 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
964 | mmc_hostname(host->mmc)); | |
965 | return; | |
966 | } | |
967 | ||
968 | sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); | |
969 | } | |
970 | ||
f3dafc37 MN |
971 | static void sdhci_arasan_set_clk_delays(struct sdhci_host *host) |
972 | { | |
973 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
974 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
975 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; | |
976 | ||
977 | clk_set_phase(clk_data->sampleclk, | |
978 | clk_data->clk_phase_in[host->timing]); | |
979 | clk_set_phase(clk_data->sdcardclk, | |
980 | clk_data->clk_phase_out[host->timing]); | |
981 | } | |
982 | ||
983 | static void arasan_dt_read_clk_phase(struct device *dev, | |
984 | struct sdhci_arasan_clk_data *clk_data, | |
985 | unsigned int timing, const char *prop) | |
986 | { | |
987 | struct device_node *np = dev->of_node; | |
988 | ||
989 | int clk_phase[2] = {0}; | |
990 | ||
991 | /* | |
992 | * Read Tap Delay values from DT, if the DT does not contain the | |
993 | * Tap Values then use the pre-defined values. | |
994 | */ | |
995 | if (of_property_read_variable_u32_array(np, prop, &clk_phase[0], | |
996 | 2, 0)) { | |
997 | dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n", | |
998 | prop, clk_data->clk_phase_in[timing], | |
999 | clk_data->clk_phase_out[timing]); | |
1000 | return; | |
1001 | } | |
1002 | ||
1003 | /* The values read are Input and Output Clock Delays in order */ | |
1004 | clk_data->clk_phase_in[timing] = clk_phase[0]; | |
1005 | clk_data->clk_phase_out[timing] = clk_phase[1]; | |
1006 | } | |
1007 | ||
1008 | /** | |
1009 | * arasan_dt_parse_clk_phases - Read Clock Delay values from DT | |
1010 | * | |
f3dafc37 MN |
1011 | * @dev: Pointer to our struct device. |
1012 | * @clk_data: Pointer to the Clock Data structure | |
4908460e MN |
1013 | * |
1014 | * Called at initialization to parse the values of Clock Delays. | |
f3dafc37 MN |
1015 | */ |
1016 | static void arasan_dt_parse_clk_phases(struct device *dev, | |
1017 | struct sdhci_arasan_clk_data *clk_data) | |
1018 | { | |
a5c8b2ae MN |
1019 | u32 mio_bank = 0; |
1020 | int i; | |
1021 | ||
f3dafc37 MN |
1022 | /* |
1023 | * This has been kept as a pointer and is assigned a function here. | |
1024 | * So that different controller variants can assign their own handling | |
1025 | * function. | |
1026 | */ | |
1027 | clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; | |
1028 | ||
a5c8b2ae | 1029 | if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { |
88e1d0b1 MN |
1030 | u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = |
1031 | ZYNQMP_ICLK_PHASE; | |
1032 | u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = | |
1033 | ZYNQMP_OCLK_PHASE; | |
a5c8b2ae MN |
1034 | |
1035 | of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); | |
1036 | if (mio_bank == 2) { | |
88e1d0b1 MN |
1037 | zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90; |
1038 | zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90; | |
a5c8b2ae MN |
1039 | } |
1040 | ||
1041 | for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { | |
88e1d0b1 MN |
1042 | clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; |
1043 | clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; | |
a5c8b2ae MN |
1044 | } |
1045 | } | |
1046 | ||
1a470721 | 1047 | if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { |
88e1d0b1 MN |
1048 | u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = |
1049 | VERSAL_ICLK_PHASE; | |
1050 | u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = | |
1051 | VERSAL_OCLK_PHASE; | |
1a470721 MN |
1052 | |
1053 | for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { | |
88e1d0b1 MN |
1054 | clk_data->clk_phase_in[i] = versal_iclk_phase[i]; |
1055 | clk_data->clk_phase_out[i] = versal_oclk_phase[i]; | |
1a470721 MN |
1056 | } |
1057 | } | |
1058 | ||
f3dafc37 MN |
1059 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY, |
1060 | "clk-phase-legacy"); | |
1061 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS, | |
1062 | "clk-phase-mmc-hs"); | |
1063 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS, | |
1064 | "clk-phase-sd-hs"); | |
1065 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12, | |
1066 | "clk-phase-uhs-sdr12"); | |
1067 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25, | |
1068 | "clk-phase-uhs-sdr25"); | |
1069 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50, | |
1070 | "clk-phase-uhs-sdr50"); | |
1071 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104, | |
1072 | "clk-phase-uhs-sdr104"); | |
1073 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, | |
1074 | "clk-phase-uhs-ddr50"); | |
1075 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52, | |
1076 | "clk-phase-mmc-ddr52"); | |
1077 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200, | |
1078 | "clk-phase-mmc-hs200"); | |
1079 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400, | |
1080 | "clk-phase-mmc-hs400"); | |
1081 | } | |
1082 | ||
37d3ee7c MN |
1083 | static const struct sdhci_pltfm_data sdhci_arasan_pdata = { |
1084 | .ops = &sdhci_arasan_ops, | |
1085 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
1086 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1087 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1088 | SDHCI_QUIRK2_STOP_WITH_TC, | |
1089 | }; | |
1090 | ||
16ada730 MN |
1091 | static const struct sdhci_arasan_clk_ops arasan_clk_ops = { |
1092 | .sdcardclk_ops = &arasan_sdcardclk_ops, | |
1093 | .sampleclk_ops = &arasan_sampleclk_ops, | |
1094 | }; | |
1095 | ||
37d3ee7c MN |
1096 | static struct sdhci_arasan_of_data sdhci_arasan_generic_data = { |
1097 | .pdata = &sdhci_arasan_pdata, | |
16ada730 | 1098 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1099 | }; |
1100 | ||
36c6aada WAZ |
1101 | static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = { |
1102 | .ops = &sdhci_arasan_cqe_ops, | |
1103 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | |
1104 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | | |
1105 | SDHCI_QUIRK_NO_LED | | |
1106 | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1107 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
1108 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
1109 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1110 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1111 | SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | | |
1112 | SDHCI_QUIRK2_STOP_WITH_TC | | |
1113 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA, | |
1114 | }; | |
1115 | ||
1116 | static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = { | |
1117 | .ops = &sdhci_arasan_ops, | |
1118 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | |
1119 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | | |
1120 | SDHCI_QUIRK_NO_LED | | |
1121 | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1122 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
1123 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
1124 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1125 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1126 | SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | | |
1127 | SDHCI_QUIRK2_STOP_WITH_TC | | |
1128 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA, | |
1129 | }; | |
1130 | ||
1131 | static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = { | |
1132 | .ops = &sdhci_arasan_ops, | |
1133 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | |
1134 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | | |
1135 | SDHCI_QUIRK_NO_LED | | |
1136 | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1137 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
1138 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
1139 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1140 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1141 | SDHCI_QUIRK2_HOST_OFF_CARD_ON | | |
1142 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA, | |
1143 | }; | |
1144 | ||
37d3ee7c MN |
1145 | static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = { |
1146 | .soc_ctl_map = &rk3399_soc_ctl_map, | |
1147 | .pdata = &sdhci_arasan_cqe_pdata, | |
16ada730 | 1148 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1149 | }; |
1150 | ||
1151 | static struct sdhci_arasan_of_data intel_lgm_emmc_data = { | |
1152 | .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map, | |
1153 | .pdata = &sdhci_arasan_cqe_pdata, | |
16ada730 | 1154 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1155 | }; |
1156 | ||
1157 | static struct sdhci_arasan_of_data intel_lgm_sdxc_data = { | |
1158 | .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map, | |
1159 | .pdata = &sdhci_arasan_cqe_pdata, | |
16ada730 | 1160 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1161 | }; |
1162 | ||
1163 | static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = { | |
1164 | .ops = &sdhci_arasan_ops, | |
1165 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1166 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1167 | SDHCI_QUIRK2_STOP_WITH_TC, | |
1168 | }; | |
1169 | ||
16ada730 MN |
1170 | static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = { |
1171 | .sdcardclk_ops = &zynqmp_sdcardclk_ops, | |
1172 | .sampleclk_ops = &zynqmp_sampleclk_ops, | |
1173 | }; | |
1174 | ||
37d3ee7c MN |
1175 | static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = { |
1176 | .pdata = &sdhci_arasan_zynqmp_pdata, | |
16ada730 MN |
1177 | .clk_ops = &zynqmp_clk_ops, |
1178 | }; | |
1179 | ||
1180 | static const struct sdhci_arasan_clk_ops versal_clk_ops = { | |
1181 | .sdcardclk_ops = &versal_sdcardclk_ops, | |
1182 | .sampleclk_ops = &versal_sampleclk_ops, | |
37d3ee7c MN |
1183 | }; |
1184 | ||
1185 | static struct sdhci_arasan_of_data sdhci_arasan_versal_data = { | |
1186 | .pdata = &sdhci_arasan_zynqmp_pdata, | |
16ada730 | 1187 | .clk_ops = &versal_clk_ops, |
37d3ee7c MN |
1188 | }; |
1189 | ||
36c6aada WAZ |
1190 | static struct sdhci_arasan_of_data intel_keembay_emmc_data = { |
1191 | .soc_ctl_map = &intel_keembay_soc_ctl_map, | |
1192 | .pdata = &sdhci_keembay_emmc_pdata, | |
a42a7ec9 | 1193 | .clk_ops = &arasan_clk_ops, |
36c6aada WAZ |
1194 | }; |
1195 | ||
1196 | static struct sdhci_arasan_of_data intel_keembay_sd_data = { | |
1197 | .soc_ctl_map = &intel_keembay_soc_ctl_map, | |
1198 | .pdata = &sdhci_keembay_sd_pdata, | |
a42a7ec9 | 1199 | .clk_ops = &arasan_clk_ops, |
36c6aada WAZ |
1200 | }; |
1201 | ||
1202 | static struct sdhci_arasan_of_data intel_keembay_sdio_data = { | |
1203 | .soc_ctl_map = &intel_keembay_soc_ctl_map, | |
1204 | .pdata = &sdhci_keembay_sdio_pdata, | |
a42a7ec9 | 1205 | .clk_ops = &arasan_clk_ops, |
36c6aada WAZ |
1206 | }; |
1207 | ||
37d3ee7c MN |
1208 | static const struct of_device_id sdhci_arasan_of_match[] = { |
1209 | /* SoC-specific compatible strings w/ soc_ctl_map */ | |
1210 | { | |
1211 | .compatible = "rockchip,rk3399-sdhci-5.1", | |
1212 | .data = &sdhci_arasan_rk3399_data, | |
1213 | }, | |
1214 | { | |
1215 | .compatible = "intel,lgm-sdhci-5.1-emmc", | |
1216 | .data = &intel_lgm_emmc_data, | |
1217 | }, | |
1218 | { | |
1219 | .compatible = "intel,lgm-sdhci-5.1-sdxc", | |
1220 | .data = &intel_lgm_sdxc_data, | |
1221 | }, | |
36c6aada WAZ |
1222 | { |
1223 | .compatible = "intel,keembay-sdhci-5.1-emmc", | |
1224 | .data = &intel_keembay_emmc_data, | |
1225 | }, | |
1226 | { | |
1227 | .compatible = "intel,keembay-sdhci-5.1-sd", | |
1228 | .data = &intel_keembay_sd_data, | |
1229 | }, | |
1230 | { | |
1231 | .compatible = "intel,keembay-sdhci-5.1-sdio", | |
1232 | .data = &intel_keembay_sdio_data, | |
1233 | }, | |
37d3ee7c MN |
1234 | /* Generic compatible below here */ |
1235 | { | |
1236 | .compatible = "arasan,sdhci-8.9a", | |
1237 | .data = &sdhci_arasan_generic_data, | |
1238 | }, | |
1239 | { | |
1240 | .compatible = "arasan,sdhci-5.1", | |
1241 | .data = &sdhci_arasan_generic_data, | |
1242 | }, | |
1243 | { | |
1244 | .compatible = "arasan,sdhci-4.9a", | |
1245 | .data = &sdhci_arasan_generic_data, | |
1246 | }, | |
1247 | { | |
1248 | .compatible = "xlnx,zynqmp-8.9a", | |
1249 | .data = &sdhci_arasan_zynqmp_data, | |
1250 | }, | |
1251 | { | |
1252 | .compatible = "xlnx,versal-8.9a", | |
1253 | .data = &sdhci_arasan_versal_data, | |
1254 | }, | |
1255 | { /* sentinel */ } | |
1256 | }; | |
1257 | MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); | |
1258 | ||
c390f211 | 1259 | /** |
07a14d1d | 1260 | * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use |
c390f211 | 1261 | * |
4908460e MN |
1262 | * @sdhci_arasan: Our private data structure. |
1263 | * @clk_xin: Pointer to the functional clock | |
1264 | * @dev: Pointer to our struct device. | |
1265 | * | |
c390f211 DA |
1266 | * Some PHY devices need to know what the actual card clock is. In order for |
1267 | * them to find out, we'll provide a clock through the common clock framework | |
1268 | * for them to query. | |
1269 | * | |
4908460e | 1270 | * Return: 0 on success and error value on error |
c390f211 | 1271 | */ |
07a14d1d MN |
1272 | static int |
1273 | sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan, | |
1274 | struct clk *clk_xin, | |
1275 | struct device *dev) | |
c390f211 | 1276 | { |
e1463618 | 1277 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; |
c390f211 DA |
1278 | struct device_node *np = dev->of_node; |
1279 | struct clk_init_data sdcardclk_init; | |
1280 | const char *parent_clk_name; | |
1281 | int ret; | |
1282 | ||
c390f211 DA |
1283 | ret = of_property_read_string_index(np, "clock-output-names", 0, |
1284 | &sdcardclk_init.name); | |
1285 | if (ret) { | |
1286 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
1287 | return ret; | |
1288 | } | |
1289 | ||
1290 | parent_clk_name = __clk_get_name(clk_xin); | |
1291 | sdcardclk_init.parent_names = &parent_clk_name; | |
1292 | sdcardclk_init.num_parents = 1; | |
1293 | sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; | |
16ada730 | 1294 | sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops; |
c390f211 | 1295 | |
e1463618 MN |
1296 | clk_data->sdcardclk_hw.init = &sdcardclk_init; |
1297 | clk_data->sdcardclk = | |
1298 | devm_clk_register(dev, &clk_data->sdcardclk_hw); | |
c99e1d0c CY |
1299 | if (IS_ERR(clk_data->sdcardclk)) |
1300 | return PTR_ERR(clk_data->sdcardclk); | |
e1463618 | 1301 | clk_data->sdcardclk_hw.init = NULL; |
c390f211 DA |
1302 | |
1303 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
e1463618 | 1304 | clk_data->sdcardclk); |
c390f211 | 1305 | if (ret) |
07a14d1d MN |
1306 | dev_err(dev, "Failed to add sdcard clock provider\n"); |
1307 | ||
1308 | return ret; | |
1309 | } | |
1310 | ||
1311 | /** | |
1312 | * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use | |
1313 | * | |
4908460e MN |
1314 | * @sdhci_arasan: Our private data structure. |
1315 | * @clk_xin: Pointer to the functional clock | |
1316 | * @dev: Pointer to our struct device. | |
1317 | * | |
07a14d1d MN |
1318 | * Some PHY devices need to know what the actual card clock is. In order for |
1319 | * them to find out, we'll provide a clock through the common clock framework | |
1320 | * for them to query. | |
1321 | * | |
4908460e | 1322 | * Return: 0 on success and error value on error |
07a14d1d MN |
1323 | */ |
1324 | static int | |
1325 | sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan, | |
1326 | struct clk *clk_xin, | |
1327 | struct device *dev) | |
1328 | { | |
1329 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; | |
1330 | struct device_node *np = dev->of_node; | |
1331 | struct clk_init_data sampleclk_init; | |
1332 | const char *parent_clk_name; | |
1333 | int ret; | |
1334 | ||
1335 | ret = of_property_read_string_index(np, "clock-output-names", 1, | |
1336 | &sampleclk_init.name); | |
1337 | if (ret) { | |
1338 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
1339 | return ret; | |
1340 | } | |
1341 | ||
1342 | parent_clk_name = __clk_get_name(clk_xin); | |
1343 | sampleclk_init.parent_names = &parent_clk_name; | |
1344 | sampleclk_init.num_parents = 1; | |
1345 | sampleclk_init.flags = CLK_GET_RATE_NOCACHE; | |
16ada730 | 1346 | sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops; |
07a14d1d MN |
1347 | |
1348 | clk_data->sampleclk_hw.init = &sampleclk_init; | |
1349 | clk_data->sampleclk = | |
1350 | devm_clk_register(dev, &clk_data->sampleclk_hw); | |
c99e1d0c CY |
1351 | if (IS_ERR(clk_data->sampleclk)) |
1352 | return PTR_ERR(clk_data->sampleclk); | |
07a14d1d MN |
1353 | clk_data->sampleclk_hw.init = NULL; |
1354 | ||
1355 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
1356 | clk_data->sampleclk); | |
1357 | if (ret) | |
1358 | dev_err(dev, "Failed to add sample clock provider\n"); | |
c390f211 DA |
1359 | |
1360 | return ret; | |
1361 | } | |
1362 | ||
1363 | /** | |
1364 | * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() | |
1365 | * | |
4908460e MN |
1366 | * @dev: Pointer to our struct device. |
1367 | * | |
c390f211 DA |
1368 | * Should be called any time we're exiting and sdhci_arasan_register_sdclk() |
1369 | * returned success. | |
c390f211 DA |
1370 | */ |
1371 | static void sdhci_arasan_unregister_sdclk(struct device *dev) | |
1372 | { | |
1373 | struct device_node *np = dev->of_node; | |
1374 | ||
1375 | if (!of_find_property(np, "#clock-cells", NULL)) | |
1376 | return; | |
1377 | ||
1378 | of_clk_del_provider(dev->of_node); | |
1379 | } | |
1380 | ||
36c6aada WAZ |
1381 | /** |
1382 | * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support) | |
973c7c99 MHZ |
1383 | * @host: The sdhci_host |
1384 | * @value: The value to write | |
36c6aada WAZ |
1385 | * |
1386 | * This should be set based on the System Address Bus. | |
1387 | * 0: the Core supports only 32-bit System Address Bus. | |
1388 | * 1: the Core supports 64-bit System Address Bus. | |
1389 | * | |
973c7c99 MHZ |
1390 | * NOTE: |
1391 | * For Keem Bay, it is required to clear this bit. Its default value is 1'b1. | |
1392 | * Keem Bay does not support 64-bit access. | |
36c6aada WAZ |
1393 | */ |
1394 | static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value) | |
1395 | { | |
1396 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1397 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
1398 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
1399 | sdhci_arasan->soc_ctl_map; | |
1400 | ||
1401 | /* Having a map is optional */ | |
1402 | if (!soc_ctl_map) | |
1403 | return; | |
1404 | ||
1405 | /* If we have a map, we expect to have a syscon */ | |
1406 | if (!sdhci_arasan->soc_ctl_base) { | |
1407 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
1408 | mmc_hostname(host->mmc)); | |
1409 | return; | |
1410 | } | |
1411 | ||
1412 | sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value); | |
1413 | } | |
1414 | ||
07a14d1d MN |
1415 | /** |
1416 | * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use | |
1417 | * | |
4908460e MN |
1418 | * @sdhci_arasan: Our private data structure. |
1419 | * @clk_xin: Pointer to the functional clock | |
1420 | * @dev: Pointer to our struct device. | |
1421 | * | |
07a14d1d MN |
1422 | * Some PHY devices need to know what the actual card clock is. In order for |
1423 | * them to find out, we'll provide a clock through the common clock framework | |
1424 | * for them to query. | |
1425 | * | |
1426 | * Note: without seriously re-architecting SDHCI's clock code and testing on | |
1427 | * all platforms, there's no way to create a totally beautiful clock here | |
1428 | * with all clock ops implemented. Instead, we'll just create a clock that can | |
1429 | * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock | |
1430 | * framework that we're doing things behind its back. This should be sufficient | |
1431 | * to create nice clean device tree bindings and later (if needed) we can try | |
1432 | * re-architecting SDHCI if we see some benefit to it. | |
1433 | * | |
4908460e | 1434 | * Return: 0 on success and error value on error |
07a14d1d MN |
1435 | */ |
1436 | static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, | |
1437 | struct clk *clk_xin, | |
1438 | struct device *dev) | |
1439 | { | |
1440 | struct device_node *np = dev->of_node; | |
1441 | u32 num_clks = 0; | |
1442 | int ret; | |
1443 | ||
1444 | /* Providing a clock to the PHY is optional; no error if missing */ | |
1445 | if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) | |
1446 | return 0; | |
1447 | ||
1448 | ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev); | |
1449 | if (ret) | |
1450 | return ret; | |
1451 | ||
1452 | if (num_clks) { | |
1453 | ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin, | |
1454 | dev); | |
1455 | if (ret) { | |
1456 | sdhci_arasan_unregister_sdclk(dev); | |
1457 | return ret; | |
1458 | } | |
1459 | } | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | ||
84362d79 SL |
1464 | static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) |
1465 | { | |
1466 | struct sdhci_host *host = sdhci_arasan->host; | |
1467 | struct cqhci_host *cq_host; | |
1468 | bool dma64; | |
1469 | int ret; | |
1470 | ||
1471 | if (!sdhci_arasan->has_cqe) | |
1472 | return sdhci_add_host(host); | |
1473 | ||
1474 | ret = sdhci_setup_host(host); | |
1475 | if (ret) | |
1476 | return ret; | |
1477 | ||
1478 | cq_host = devm_kzalloc(host->mmc->parent, | |
1479 | sizeof(*cq_host), GFP_KERNEL); | |
1480 | if (!cq_host) { | |
1481 | ret = -ENOMEM; | |
1482 | goto cleanup; | |
1483 | } | |
1484 | ||
1485 | cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; | |
1486 | cq_host->ops = &sdhci_arasan_cqhci_ops; | |
1487 | ||
1488 | dma64 = host->flags & SDHCI_USE_64_BIT_DMA; | |
1489 | if (dma64) | |
1490 | cq_host->caps |= CQHCI_TASK_DESC_SZ_128; | |
1491 | ||
1492 | ret = cqhci_init(cq_host, host->mmc, dma64); | |
1493 | if (ret) | |
1494 | goto cleanup; | |
1495 | ||
1496 | ret = __sdhci_add_host(host); | |
1497 | if (ret) | |
1498 | goto cleanup; | |
1499 | ||
1500 | return 0; | |
1501 | ||
1502 | cleanup: | |
1503 | sdhci_cleanup_host(host); | |
1504 | return ret; | |
1505 | } | |
1506 | ||
e3ec3a3d SB |
1507 | static int sdhci_arasan_probe(struct platform_device *pdev) |
1508 | { | |
1509 | int ret; | |
3ea4666e DA |
1510 | const struct of_device_id *match; |
1511 | struct device_node *node; | |
e3ec3a3d SB |
1512 | struct clk *clk_xin; |
1513 | struct sdhci_host *host; | |
1514 | struct sdhci_pltfm_host *pltfm_host; | |
1515 | struct sdhci_arasan_data *sdhci_arasan; | |
3794c542 | 1516 | struct device_node *np = pdev->dev.of_node; |
06b23ca0 | 1517 | const struct sdhci_arasan_of_data *data; |
84362d79 | 1518 | |
06b23ca0 FA |
1519 | match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); |
1520 | data = match->data; | |
1521 | host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); | |
e3ec3a3d | 1522 | |
89211418 JZ |
1523 | if (IS_ERR(host)) |
1524 | return PTR_ERR(host); | |
1525 | ||
1526 | pltfm_host = sdhci_priv(host); | |
1527 | sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
c390f211 | 1528 | sdhci_arasan->host = host; |
e3ec3a3d | 1529 | |
06b23ca0 | 1530 | sdhci_arasan->soc_ctl_map = data->soc_ctl_map; |
16ada730 | 1531 | sdhci_arasan->clk_ops = data->clk_ops; |
3ea4666e DA |
1532 | |
1533 | node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); | |
1534 | if (node) { | |
1535 | sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); | |
1536 | of_node_put(node); | |
1537 | ||
1538 | if (IS_ERR(sdhci_arasan->soc_ctl_base)) { | |
72ea817d KK |
1539 | ret = dev_err_probe(&pdev->dev, |
1540 | PTR_ERR(sdhci_arasan->soc_ctl_base), | |
1541 | "Can't get syscon\n"); | |
3ea4666e DA |
1542 | goto err_pltfm_free; |
1543 | } | |
1544 | } | |
1545 | ||
e3ec3a3d SB |
1546 | sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); |
1547 | if (IS_ERR(sdhci_arasan->clk_ahb)) { | |
1548 | dev_err(&pdev->dev, "clk_ahb clock not found.\n"); | |
278d0962 SL |
1549 | ret = PTR_ERR(sdhci_arasan->clk_ahb); |
1550 | goto err_pltfm_free; | |
e3ec3a3d SB |
1551 | } |
1552 | ||
1553 | clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); | |
1554 | if (IS_ERR(clk_xin)) { | |
1555 | dev_err(&pdev->dev, "clk_xin clock not found.\n"); | |
278d0962 SL |
1556 | ret = PTR_ERR(clk_xin); |
1557 | goto err_pltfm_free; | |
e3ec3a3d SB |
1558 | } |
1559 | ||
1560 | ret = clk_prepare_enable(sdhci_arasan->clk_ahb); | |
1561 | if (ret) { | |
1562 | dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); | |
278d0962 | 1563 | goto err_pltfm_free; |
e3ec3a3d SB |
1564 | } |
1565 | ||
1566 | ret = clk_prepare_enable(clk_xin); | |
1567 | if (ret) { | |
1568 | dev_err(&pdev->dev, "Unable to enable SD clock.\n"); | |
1569 | goto clk_dis_ahb; | |
1570 | } | |
1571 | ||
e3ec3a3d | 1572 | sdhci_get_of_property(pdev); |
3794c542 ZB |
1573 | |
1574 | if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) | |
1575 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; | |
1576 | ||
3f2c7d5d HG |
1577 | if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) |
1578 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; | |
1579 | ||
e3ec3a3d SB |
1580 | pltfm_host->clk = clk_xin; |
1581 | ||
b2ca77c9 SL |
1582 | if (of_device_is_compatible(pdev->dev.of_node, |
1583 | "rockchip,rk3399-sdhci-5.1")) | |
1584 | sdhci_arasan_update_clockmultiplier(host, 0x0); | |
1585 | ||
36c6aada WAZ |
1586 | if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || |
1587 | of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || | |
1588 | of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { | |
1589 | sdhci_arasan_update_clockmultiplier(host, 0x0); | |
1590 | sdhci_arasan_update_support64b(host, 0x0); | |
1591 | ||
1592 | host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; | |
1593 | } | |
1594 | ||
3ea4666e DA |
1595 | sdhci_arasan_update_baseclkfreq(host); |
1596 | ||
c390f211 DA |
1597 | ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); |
1598 | if (ret) | |
1599 | goto clk_disable_all; | |
1600 | ||
a5c8b2ae | 1601 | if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { |
8d2e3343 MN |
1602 | host->mmc_host_ops.execute_tuning = |
1603 | arasan_zynqmp_execute_tuning; | |
a5c8b2ae MN |
1604 | } |
1605 | ||
f3dafc37 MN |
1606 | arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data); |
1607 | ||
16b23787 MS |
1608 | ret = mmc_of_parse(host->mmc); |
1609 | if (ret) { | |
60208a26 MS |
1610 | if (ret != -EPROBE_DEFER) |
1611 | dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); | |
c390f211 | 1612 | goto unreg_clk; |
16b23787 MS |
1613 | } |
1614 | ||
91aa3661 SL |
1615 | sdhci_arasan->phy = ERR_PTR(-ENODEV); |
1616 | if (of_device_is_compatible(pdev->dev.of_node, | |
1617 | "arasan,sdhci-5.1")) { | |
1618 | sdhci_arasan->phy = devm_phy_get(&pdev->dev, | |
1619 | "phy_arasan"); | |
1620 | if (IS_ERR(sdhci_arasan->phy)) { | |
1621 | ret = PTR_ERR(sdhci_arasan->phy); | |
1622 | dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); | |
c390f211 | 1623 | goto unreg_clk; |
91aa3661 SL |
1624 | } |
1625 | ||
1626 | ret = phy_init(sdhci_arasan->phy); | |
1627 | if (ret < 0) { | |
1628 | dev_err(&pdev->dev, "phy_init err.\n"); | |
c390f211 | 1629 | goto unreg_clk; |
91aa3661 SL |
1630 | } |
1631 | ||
a05c8465 SL |
1632 | host->mmc_host_ops.hs400_enhanced_strobe = |
1633 | sdhci_arasan_hs400_enhanced_strobe; | |
8a3bee9b SL |
1634 | host->mmc_host_ops.start_signal_voltage_switch = |
1635 | sdhci_arasan_voltage_switch; | |
84362d79 | 1636 | sdhci_arasan->has_cqe = true; |
7bda9482 CM |
1637 | host->mmc->caps2 |= MMC_CAP2_CQE; |
1638 | ||
1639 | if (!of_property_read_bool(np, "disable-cqe-dcmd")) | |
1640 | host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; | |
91aa3661 SL |
1641 | } |
1642 | ||
84362d79 | 1643 | ret = sdhci_arasan_add_host(sdhci_arasan); |
b1df9de7 | 1644 | if (ret) |
91aa3661 | 1645 | goto err_add_host; |
e3ec3a3d SB |
1646 | |
1647 | return 0; | |
1648 | ||
91aa3661 | 1649 | err_add_host: |
91aa3661 SL |
1650 | if (!IS_ERR(sdhci_arasan->phy)) |
1651 | phy_exit(sdhci_arasan->phy); | |
c390f211 DA |
1652 | unreg_clk: |
1653 | sdhci_arasan_unregister_sdclk(&pdev->dev); | |
e3ec3a3d SB |
1654 | clk_disable_all: |
1655 | clk_disable_unprepare(clk_xin); | |
1656 | clk_dis_ahb: | |
1657 | clk_disable_unprepare(sdhci_arasan->clk_ahb); | |
278d0962 SL |
1658 | err_pltfm_free: |
1659 | sdhci_pltfm_free(pdev); | |
e3ec3a3d SB |
1660 | return ret; |
1661 | } | |
1662 | ||
1663 | static int sdhci_arasan_remove(struct platform_device *pdev) | |
1664 | { | |
0c7fe32e | 1665 | int ret; |
e3ec3a3d SB |
1666 | struct sdhci_host *host = platform_get_drvdata(pdev); |
1667 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 JZ |
1668 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
1669 | struct clk *clk_ahb = sdhci_arasan->clk_ahb; | |
e3ec3a3d | 1670 | |
91aa3661 | 1671 | if (!IS_ERR(sdhci_arasan->phy)) { |
b2db9c67 DA |
1672 | if (sdhci_arasan->is_phy_on) |
1673 | phy_power_off(sdhci_arasan->phy); | |
91aa3661 SL |
1674 | phy_exit(sdhci_arasan->phy); |
1675 | } | |
1676 | ||
c390f211 DA |
1677 | sdhci_arasan_unregister_sdclk(&pdev->dev); |
1678 | ||
0c7fe32e JZ |
1679 | ret = sdhci_pltfm_unregister(pdev); |
1680 | ||
89211418 | 1681 | clk_disable_unprepare(clk_ahb); |
e3ec3a3d | 1682 | |
0c7fe32e | 1683 | return ret; |
e3ec3a3d SB |
1684 | } |
1685 | ||
e3ec3a3d SB |
1686 | static struct platform_driver sdhci_arasan_driver = { |
1687 | .driver = { | |
1688 | .name = "sdhci-arasan", | |
21b2cec6 | 1689 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
e3ec3a3d SB |
1690 | .of_match_table = sdhci_arasan_of_match, |
1691 | .pm = &sdhci_arasan_dev_pm_ops, | |
1692 | }, | |
1693 | .probe = sdhci_arasan_probe, | |
1694 | .remove = sdhci_arasan_remove, | |
1695 | }; | |
1696 | ||
1697 | module_platform_driver(sdhci_arasan_driver); | |
1698 | ||
1699 | MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); | |
1700 | MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); | |
1701 | MODULE_LICENSE("GPL"); |