Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e3ec3a3d SB |
2 | /* |
3 | * Arasan Secure Digital Host Controller Interface. | |
4 | * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> | |
5 | * Copyright (c) 2012 Wind River Systems, Inc. | |
6 | * Copyright (C) 2013 Pengutronix e.K. | |
7 | * Copyright (C) 2013 Xilinx Inc. | |
8 | * | |
9 | * Based on sdhci-of-esdhc.c | |
10 | * | |
11 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
12 | * Copyright (c) 2009 MontaVista Software, Inc. | |
13 | * | |
14 | * Authors: Xiaobo Xie <X.Xie@freescale.com> | |
15 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
e3ec3a3d SB |
16 | */ |
17 | ||
c390f211 | 18 | #include <linux/clk-provider.h> |
3ea4666e | 19 | #include <linux/mfd/syscon.h> |
e3ec3a3d | 20 | #include <linux/module.h> |
308f3f8d | 21 | #include <linux/of_device.h> |
91aa3661 | 22 | #include <linux/phy/phy.h> |
3ea4666e | 23 | #include <linux/regmap.h> |
3794c542 | 24 | #include <linux/of.h> |
a5c8b2ae | 25 | #include <linux/firmware/xlnx-zynqmp.h> |
e3ec3a3d | 26 | |
84362d79 SL |
27 | #include "cqhci.h" |
28 | #include "sdhci-pltfm.h" | |
e3ec3a3d | 29 | |
84362d79 SL |
30 | #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 |
31 | #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 | |
a05c8465 | 32 | #define VENDOR_ENHANCED_STROBE BIT(0) |
e3ec3a3d | 33 | |
b2db9c67 DA |
34 | #define PHY_CLK_TOO_SLOW_HZ 400000 |
35 | ||
a5c8b2ae MN |
36 | /* Default settings for ZynqMP Clock Phases */ |
37 | #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0} | |
38 | #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0} | |
39 | ||
3ea4666e DA |
40 | /* |
41 | * On some SoCs the syscon area has a feature where the upper 16-bits of | |
42 | * each 32-bit register act as a write mask for the lower 16-bits. This allows | |
43 | * atomic updates of the register without locking. This macro is used on SoCs | |
44 | * that have that feature. | |
45 | */ | |
46 | #define HIWORD_UPDATE(val, mask, shift) \ | |
47 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
48 | ||
49 | /** | |
50 | * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map | |
51 | * | |
52 | * @reg: Offset within the syscon of the register containing this field | |
53 | * @width: Number of bits for this field | |
54 | * @shift: Bit offset within @reg of this field (or -1 if not avail) | |
55 | */ | |
56 | struct sdhci_arasan_soc_ctl_field { | |
57 | u32 reg; | |
58 | u16 width; | |
59 | s16 shift; | |
60 | }; | |
61 | ||
62 | /** | |
63 | * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers | |
64 | * | |
65 | * It's up to the licensee of the Arsan IP block to make these available | |
66 | * somewhere if needed. Presumably these will be scattered somewhere that's | |
67 | * accessible via the syscon API. | |
68 | * | |
69 | * @baseclkfreq: Where to find corecfg_baseclkfreq | |
b2ca77c9 | 70 | * @clockmultiplier: Where to find corecfg_clockmultiplier |
3ea4666e DA |
71 | * @hiword_update: If true, use HIWORD_UPDATE to access the syscon |
72 | */ | |
73 | struct sdhci_arasan_soc_ctl_map { | |
74 | struct sdhci_arasan_soc_ctl_field baseclkfreq; | |
b2ca77c9 | 75 | struct sdhci_arasan_soc_ctl_field clockmultiplier; |
3ea4666e DA |
76 | bool hiword_update; |
77 | }; | |
78 | ||
e1463618 MN |
79 | /** |
80 | * struct sdhci_arasan_clk_data | |
81 | * @sdcardclk_hw: Struct for the clock we might provide to a PHY. | |
82 | * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. | |
07a14d1d MN |
83 | * @sampleclk_hw: Struct for the clock we might provide to a PHY. |
84 | * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw. | |
f3dafc37 MN |
85 | * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes |
86 | * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes | |
87 | * @set_clk_delays: Function pointer for setting Clock Delays | |
a5c8b2ae | 88 | * @clk_of_data: Platform specific runtime clock data storage pointer |
e1463618 MN |
89 | */ |
90 | struct sdhci_arasan_clk_data { | |
91 | struct clk_hw sdcardclk_hw; | |
92 | struct clk *sdcardclk; | |
07a14d1d MN |
93 | struct clk_hw sampleclk_hw; |
94 | struct clk *sampleclk; | |
f3dafc37 MN |
95 | int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; |
96 | int clk_phase_out[MMC_TIMING_MMC_HS400 + 1]; | |
97 | void (*set_clk_delays)(struct sdhci_host *host); | |
a5c8b2ae MN |
98 | void *clk_of_data; |
99 | }; | |
100 | ||
101 | struct sdhci_arasan_zynqmp_clk_data { | |
102 | const struct zynqmp_eemi_ops *eemi_ops; | |
e1463618 MN |
103 | }; |
104 | ||
e3ec3a3d SB |
105 | /** |
106 | * struct sdhci_arasan_data | |
c390f211 | 107 | * @host: Pointer to the main SDHCI host structure. |
3ea4666e DA |
108 | * @clk_ahb: Pointer to the AHB clock |
109 | * @phy: Pointer to the generic phy | |
b2db9c67 | 110 | * @is_phy_on: True if the PHY is on; false if not. |
e1463618 | 111 | * @clk_data: Struct for the Arasan Controller Clock Data. |
3ea4666e DA |
112 | * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. |
113 | * @soc_ctl_map: Map to get offsets into soc_ctl registers. | |
e3ec3a3d SB |
114 | */ |
115 | struct sdhci_arasan_data { | |
c390f211 | 116 | struct sdhci_host *host; |
e3ec3a3d | 117 | struct clk *clk_ahb; |
91aa3661 | 118 | struct phy *phy; |
b2db9c67 | 119 | bool is_phy_on; |
3ea4666e | 120 | |
84362d79 | 121 | bool has_cqe; |
e1463618 | 122 | struct sdhci_arasan_clk_data clk_data; |
c390f211 | 123 | |
3ea4666e DA |
124 | struct regmap *soc_ctl_base; |
125 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
3794c542 ZB |
126 | unsigned int quirks; /* Arasan deviations from spec */ |
127 | ||
128 | /* Controller does not have CD wired and will not function normally without */ | |
129 | #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) | |
3f2c7d5d HG |
130 | /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the |
131 | * internal clock even when the clock isn't stable */ | |
132 | #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) | |
3ea4666e DA |
133 | }; |
134 | ||
06b23ca0 FA |
135 | struct sdhci_arasan_of_data { |
136 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
137 | const struct sdhci_pltfm_data *pdata; | |
138 | }; | |
139 | ||
3ea4666e DA |
140 | static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { |
141 | .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, | |
b2ca77c9 | 142 | .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, |
3ea4666e | 143 | .hiword_update = true, |
e3ec3a3d SB |
144 | }; |
145 | ||
5c1a4f40 RVM |
146 | static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = { |
147 | .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 }, | |
148 | .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, | |
149 | .hiword_update = false, | |
150 | }; | |
151 | ||
d1807ad6 RVM |
152 | static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = { |
153 | .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 }, | |
154 | .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, | |
155 | .hiword_update = false, | |
156 | }; | |
157 | ||
3ea4666e DA |
158 | /** |
159 | * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers | |
160 | * | |
161 | * This function allows writing to fields in sdhci_arasan_soc_ctl_map. | |
162 | * Note that if a field is specified as not available (shift < 0) then | |
163 | * this function will silently return an error code. It will be noisy | |
164 | * and print errors for any other (unexpected) errors. | |
165 | * | |
166 | * @host: The sdhci_host | |
167 | * @fld: The field to write to | |
168 | * @val: The value to write | |
169 | */ | |
170 | static int sdhci_arasan_syscon_write(struct sdhci_host *host, | |
171 | const struct sdhci_arasan_soc_ctl_field *fld, | |
172 | u32 val) | |
173 | { | |
174 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
175 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
176 | struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; | |
177 | u32 reg = fld->reg; | |
178 | u16 width = fld->width; | |
179 | s16 shift = fld->shift; | |
180 | int ret; | |
181 | ||
182 | /* | |
183 | * Silently return errors for shift < 0 so caller doesn't have | |
184 | * to check for fields which are optional. For fields that | |
185 | * are required then caller needs to do something special | |
186 | * anyway. | |
187 | */ | |
188 | if (shift < 0) | |
189 | return -EINVAL; | |
190 | ||
191 | if (sdhci_arasan->soc_ctl_map->hiword_update) | |
192 | ret = regmap_write(soc_ctl_base, reg, | |
193 | HIWORD_UPDATE(val, GENMASK(width, 0), | |
194 | shift)); | |
195 | else | |
196 | ret = regmap_update_bits(soc_ctl_base, reg, | |
197 | GENMASK(shift + width, shift), | |
198 | val << shift); | |
199 | ||
200 | /* Yell about (unexpected) regmap errors */ | |
201 | if (ret) | |
202 | pr_warn("%s: Regmap write fail: %d\n", | |
203 | mmc_hostname(host->mmc), ret); | |
204 | ||
205 | return ret; | |
206 | } | |
207 | ||
802ac39a SL |
208 | static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) |
209 | { | |
210 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
211 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
f3dafc37 | 212 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; |
6fc09244 | 213 | bool ctrl_phy = false; |
802ac39a | 214 | |
b2db9c67 DA |
215 | if (!IS_ERR(sdhci_arasan->phy)) { |
216 | if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { | |
217 | /* | |
218 | * If PHY off, set clock to max speed and power PHY on. | |
219 | * | |
220 | * Although PHY docs apparently suggest power cycling | |
221 | * when changing the clock the PHY doesn't like to be | |
222 | * powered on while at low speeds like those used in ID | |
223 | * mode. Even worse is powering the PHY on while the | |
224 | * clock is off. | |
225 | * | |
226 | * To workaround the PHY limitations, the best we can | |
227 | * do is to power it on at a faster speed and then slam | |
228 | * through low speeds without power cycling. | |
229 | */ | |
230 | sdhci_set_clock(host, host->max_clk); | |
b2db9c67 | 231 | phy_power_on(sdhci_arasan->phy); |
b2db9c67 DA |
232 | sdhci_arasan->is_phy_on = true; |
233 | ||
234 | /* | |
235 | * We'll now fall through to the below case with | |
236 | * ctrl_phy = false (so we won't turn off/on). The | |
237 | * sdhci_set_clock() will set the real clock. | |
238 | */ | |
239 | } else if (clock > PHY_CLK_TOO_SLOW_HZ) { | |
240 | /* | |
241 | * At higher clock speeds the PHY is fine being power | |
242 | * cycled and docs say you _should_ power cycle when | |
243 | * changing clock speeds. | |
244 | */ | |
245 | ctrl_phy = true; | |
246 | } | |
247 | } | |
802ac39a | 248 | |
b2db9c67 | 249 | if (ctrl_phy && sdhci_arasan->is_phy_on) { |
802ac39a | 250 | phy_power_off(sdhci_arasan->phy); |
b2db9c67 | 251 | sdhci_arasan->is_phy_on = false; |
802ac39a SL |
252 | } |
253 | ||
f3dafc37 MN |
254 | /* Set the Input and Output Clock Phase Delays */ |
255 | if (clk_data->set_clk_delays) | |
256 | clk_data->set_clk_delays(host); | |
257 | ||
802ac39a SL |
258 | sdhci_set_clock(host, clock); |
259 | ||
3f2c7d5d HG |
260 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) |
261 | /* | |
262 | * Some controllers immediately report SDHCI_CLOCK_INT_STABLE | |
263 | * after enabling the clock even though the clock is not | |
264 | * stable. Trying to use a clock without waiting here results | |
265 | * in EILSEQ while detecting some older/slower cards. The | |
266 | * chosen delay is the maximum delay from sdhci_set_clock. | |
267 | */ | |
268 | msleep(20); | |
269 | ||
6fc09244 | 270 | if (ctrl_phy) { |
802ac39a | 271 | phy_power_on(sdhci_arasan->phy); |
b2db9c67 | 272 | sdhci_arasan->is_phy_on = true; |
802ac39a SL |
273 | } |
274 | } | |
275 | ||
a05c8465 SL |
276 | static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, |
277 | struct mmc_ios *ios) | |
278 | { | |
279 | u32 vendor; | |
280 | struct sdhci_host *host = mmc_priv(mmc); | |
281 | ||
0daf72fe | 282 | vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); |
a05c8465 SL |
283 | if (ios->enhanced_strobe) |
284 | vendor |= VENDOR_ENHANCED_STROBE; | |
285 | else | |
286 | vendor &= ~VENDOR_ENHANCED_STROBE; | |
287 | ||
0daf72fe | 288 | sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); |
a05c8465 SL |
289 | } |
290 | ||
13d62fd2 | 291 | static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) |
3794c542 ZB |
292 | { |
293 | u8 ctrl; | |
294 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
295 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
296 | ||
297 | sdhci_reset(host, mask); | |
298 | ||
299 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { | |
300 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
301 | ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; | |
302 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
303 | } | |
304 | } | |
305 | ||
8a3bee9b SL |
306 | static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, |
307 | struct mmc_ios *ios) | |
308 | { | |
309 | switch (ios->signal_voltage) { | |
310 | case MMC_SIGNAL_VOLTAGE_180: | |
311 | /* | |
312 | * Plese don't switch to 1V8 as arasan,5.1 doesn't | |
313 | * actually refer to this setting to indicate the | |
314 | * signal voltage and the state machine will be broken | |
315 | * actually if we force to enable 1V8. That's something | |
316 | * like broken quirk but we could work around here. | |
317 | */ | |
318 | return 0; | |
319 | case MMC_SIGNAL_VOLTAGE_330: | |
320 | case MMC_SIGNAL_VOLTAGE_120: | |
321 | /* We don't support 3V3 and 1V2 */ | |
322 | break; | |
323 | } | |
324 | ||
325 | return -EINVAL; | |
326 | } | |
327 | ||
a81dae3a | 328 | static const struct sdhci_ops sdhci_arasan_ops = { |
802ac39a | 329 | .set_clock = sdhci_arasan_set_clock, |
e3ec3a3d | 330 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
8cc35289 | 331 | .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, |
2317f56c | 332 | .set_bus_width = sdhci_set_bus_width, |
3794c542 | 333 | .reset = sdhci_arasan_reset, |
96d7b78c | 334 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
c2c5252c | 335 | .set_power = sdhci_set_power_and_bus_voltage, |
e3ec3a3d SB |
336 | }; |
337 | ||
a81dae3a | 338 | static const struct sdhci_pltfm_data sdhci_arasan_pdata = { |
e3ec3a3d | 339 | .ops = &sdhci_arasan_ops, |
2d532d45 SG |
340 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
341 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
57aac337 PE |
342 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | |
343 | SDHCI_QUIRK2_STOP_WITH_TC, | |
e3ec3a3d SB |
344 | }; |
345 | ||
06b23ca0 FA |
346 | static struct sdhci_arasan_of_data sdhci_arasan_data = { |
347 | .pdata = &sdhci_arasan_pdata, | |
348 | }; | |
349 | ||
2a2b8216 MN |
350 | static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = { |
351 | .ops = &sdhci_arasan_ops, | |
352 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
353 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
354 | SDHCI_QUIRK2_STOP_WITH_TC, | |
355 | }; | |
356 | ||
357 | static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = { | |
358 | .pdata = &sdhci_arasan_zynqmp_pdata, | |
359 | }; | |
360 | ||
84362d79 SL |
361 | static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) |
362 | { | |
363 | int cmd_error = 0; | |
364 | int data_error = 0; | |
365 | ||
366 | if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) | |
367 | return intmask; | |
368 | ||
369 | cqhci_irq(host->mmc, intmask, cmd_error, data_error); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static void sdhci_arasan_dumpregs(struct mmc_host *mmc) | |
375 | { | |
376 | sdhci_dumpregs(mmc_priv(mmc)); | |
377 | } | |
378 | ||
379 | static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) | |
380 | { | |
381 | struct sdhci_host *host = mmc_priv(mmc); | |
382 | u32 reg; | |
383 | ||
384 | reg = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
385 | while (reg & SDHCI_DATA_AVAILABLE) { | |
386 | sdhci_readl(host, SDHCI_BUFFER); | |
387 | reg = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
388 | } | |
389 | ||
390 | sdhci_cqe_enable(mmc); | |
391 | } | |
392 | ||
393 | static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { | |
394 | .enable = sdhci_arasan_cqe_enable, | |
395 | .disable = sdhci_cqe_disable, | |
396 | .dumpregs = sdhci_arasan_dumpregs, | |
397 | }; | |
398 | ||
399 | static const struct sdhci_ops sdhci_arasan_cqe_ops = { | |
400 | .set_clock = sdhci_arasan_set_clock, | |
401 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | |
402 | .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, | |
403 | .set_bus_width = sdhci_set_bus_width, | |
404 | .reset = sdhci_arasan_reset, | |
405 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
c2c5252c | 406 | .set_power = sdhci_set_power_and_bus_voltage, |
84362d79 SL |
407 | .irq = sdhci_arasan_cqhci_irq, |
408 | }; | |
409 | ||
410 | static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { | |
411 | .ops = &sdhci_arasan_cqe_ops, | |
412 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
413 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
414 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, | |
415 | }; | |
416 | ||
06b23ca0 FA |
417 | static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = { |
418 | .soc_ctl_map = &rk3399_soc_ctl_map, | |
419 | .pdata = &sdhci_arasan_cqe_pdata, | |
420 | }; | |
421 | ||
5c1a4f40 RVM |
422 | static struct sdhci_arasan_of_data intel_lgm_emmc_data = { |
423 | .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map, | |
424 | .pdata = &sdhci_arasan_cqe_pdata, | |
425 | }; | |
426 | ||
d1807ad6 RVM |
427 | static struct sdhci_arasan_of_data intel_lgm_sdxc_data = { |
428 | .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map, | |
429 | .pdata = &sdhci_arasan_cqe_pdata, | |
430 | }; | |
431 | ||
e3ec3a3d SB |
432 | #ifdef CONFIG_PM_SLEEP |
433 | /** | |
434 | * sdhci_arasan_suspend - Suspend method for the driver | |
435 | * @dev: Address of the device structure | |
436 | * Returns 0 on success and error value on error | |
437 | * | |
438 | * Put the device in a low power state. | |
439 | */ | |
440 | static int sdhci_arasan_suspend(struct device *dev) | |
441 | { | |
970f2d90 | 442 | struct sdhci_host *host = dev_get_drvdata(dev); |
e3ec3a3d | 443 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
89211418 | 444 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
445 | int ret; |
446 | ||
d38dcad4 AH |
447 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
448 | mmc_retune_needed(host->mmc); | |
449 | ||
84362d79 SL |
450 | if (sdhci_arasan->has_cqe) { |
451 | ret = cqhci_suspend(host->mmc); | |
452 | if (ret) | |
453 | return ret; | |
454 | } | |
455 | ||
e3ec3a3d SB |
456 | ret = sdhci_suspend_host(host); |
457 | if (ret) | |
458 | return ret; | |
459 | ||
b2db9c67 | 460 | if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { |
91aa3661 SL |
461 | ret = phy_power_off(sdhci_arasan->phy); |
462 | if (ret) { | |
463 | dev_err(dev, "Cannot power off phy.\n"); | |
464 | sdhci_resume_host(host); | |
465 | return ret; | |
466 | } | |
b2db9c67 | 467 | sdhci_arasan->is_phy_on = false; |
91aa3661 SL |
468 | } |
469 | ||
e3ec3a3d SB |
470 | clk_disable(pltfm_host->clk); |
471 | clk_disable(sdhci_arasan->clk_ahb); | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | /** | |
477 | * sdhci_arasan_resume - Resume method for the driver | |
478 | * @dev: Address of the device structure | |
479 | * Returns 0 on success and error value on error | |
480 | * | |
481 | * Resume operation after suspend | |
482 | */ | |
483 | static int sdhci_arasan_resume(struct device *dev) | |
484 | { | |
970f2d90 | 485 | struct sdhci_host *host = dev_get_drvdata(dev); |
e3ec3a3d | 486 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
89211418 | 487 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
488 | int ret; |
489 | ||
490 | ret = clk_enable(sdhci_arasan->clk_ahb); | |
491 | if (ret) { | |
492 | dev_err(dev, "Cannot enable AHB clock.\n"); | |
493 | return ret; | |
494 | } | |
495 | ||
496 | ret = clk_enable(pltfm_host->clk); | |
497 | if (ret) { | |
498 | dev_err(dev, "Cannot enable SD clock.\n"); | |
e3ec3a3d SB |
499 | return ret; |
500 | } | |
501 | ||
b2db9c67 | 502 | if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { |
91aa3661 SL |
503 | ret = phy_power_on(sdhci_arasan->phy); |
504 | if (ret) { | |
505 | dev_err(dev, "Cannot power on phy.\n"); | |
506 | return ret; | |
507 | } | |
b2db9c67 | 508 | sdhci_arasan->is_phy_on = true; |
91aa3661 SL |
509 | } |
510 | ||
84362d79 SL |
511 | ret = sdhci_resume_host(host); |
512 | if (ret) { | |
513 | dev_err(dev, "Cannot resume host.\n"); | |
514 | return ret; | |
515 | } | |
516 | ||
517 | if (sdhci_arasan->has_cqe) | |
518 | return cqhci_resume(host->mmc); | |
519 | ||
520 | return 0; | |
e3ec3a3d SB |
521 | } |
522 | #endif /* ! CONFIG_PM_SLEEP */ | |
523 | ||
524 | static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, | |
525 | sdhci_arasan_resume); | |
526 | ||
3ea4666e DA |
527 | static const struct of_device_id sdhci_arasan_of_match[] = { |
528 | /* SoC-specific compatible strings w/ soc_ctl_map */ | |
529 | { | |
530 | .compatible = "rockchip,rk3399-sdhci-5.1", | |
06b23ca0 | 531 | .data = &sdhci_arasan_rk3399_data, |
3ea4666e | 532 | }, |
5c1a4f40 RVM |
533 | { |
534 | .compatible = "intel,lgm-sdhci-5.1-emmc", | |
535 | .data = &intel_lgm_emmc_data, | |
536 | }, | |
d1807ad6 RVM |
537 | { |
538 | .compatible = "intel,lgm-sdhci-5.1-sdxc", | |
539 | .data = &intel_lgm_sdxc_data, | |
540 | }, | |
3ea4666e | 541 | /* Generic compatible below here */ |
06b23ca0 FA |
542 | { |
543 | .compatible = "arasan,sdhci-8.9a", | |
544 | .data = &sdhci_arasan_data, | |
545 | }, | |
546 | { | |
547 | .compatible = "arasan,sdhci-5.1", | |
548 | .data = &sdhci_arasan_data, | |
549 | }, | |
550 | { | |
551 | .compatible = "arasan,sdhci-4.9a", | |
552 | .data = &sdhci_arasan_data, | |
553 | }, | |
a5c8b2ae MN |
554 | { |
555 | .compatible = "xlnx,zynqmp-8.9a", | |
2a2b8216 | 556 | .data = &sdhci_arasan_zynqmp_data, |
a5c8b2ae | 557 | }, |
3ea4666e DA |
558 | { /* sentinel */ } |
559 | }; | |
560 | MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); | |
561 | ||
c390f211 DA |
562 | /** |
563 | * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate | |
564 | * | |
565 | * Return the current actual rate of the SD card clock. This can be used | |
566 | * to communicate with out PHY. | |
567 | * | |
568 | * @hw: Pointer to the hardware clock structure. | |
569 | * @parent_rate The parent rate (should be rate of clk_xin). | |
570 | * Returns the card clock rate. | |
571 | */ | |
572 | static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, | |
573 | unsigned long parent_rate) | |
574 | ||
575 | { | |
e1463618 MN |
576 | struct sdhci_arasan_clk_data *clk_data = |
577 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
c390f211 | 578 | struct sdhci_arasan_data *sdhci_arasan = |
e1463618 | 579 | container_of(clk_data, struct sdhci_arasan_data, clk_data); |
c390f211 DA |
580 | struct sdhci_host *host = sdhci_arasan->host; |
581 | ||
582 | return host->mmc->actual_clock; | |
583 | } | |
584 | ||
585 | static const struct clk_ops arasan_sdcardclk_ops = { | |
586 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
587 | }; | |
588 | ||
07a14d1d MN |
589 | /** |
590 | * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate | |
591 | * | |
592 | * Return the current actual rate of the sampling clock. This can be used | |
593 | * to communicate with out PHY. | |
594 | * | |
595 | * @hw: Pointer to the hardware clock structure. | |
596 | * @parent_rate The parent rate (should be rate of clk_xin). | |
597 | * Returns the sample clock rate. | |
598 | */ | |
599 | static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw, | |
600 | unsigned long parent_rate) | |
601 | ||
602 | { | |
603 | struct sdhci_arasan_clk_data *clk_data = | |
604 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
605 | struct sdhci_arasan_data *sdhci_arasan = | |
606 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
607 | struct sdhci_host *host = sdhci_arasan->host; | |
608 | ||
609 | return host->mmc->actual_clock; | |
610 | } | |
611 | ||
612 | static const struct clk_ops arasan_sampleclk_ops = { | |
613 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
614 | }; | |
615 | ||
a5c8b2ae MN |
616 | /** |
617 | * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays | |
618 | * | |
619 | * Set the SD Output Clock Tap Delays for Output path | |
620 | * | |
621 | * @hw: Pointer to the hardware clock structure. | |
622 | * @degrees The clock phase shift between 0 - 359. | |
623 | * Return: 0 on success and error value on error | |
624 | */ | |
625 | static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) | |
626 | ||
627 | { | |
628 | struct sdhci_arasan_clk_data *clk_data = | |
629 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
630 | struct sdhci_arasan_data *sdhci_arasan = | |
631 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
632 | struct sdhci_host *host = sdhci_arasan->host; | |
633 | struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = | |
634 | clk_data->clk_of_data; | |
635 | const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; | |
636 | const char *clk_name = clk_hw_get_name(hw); | |
637 | u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; | |
638 | u8 tap_delay, tap_max = 0; | |
639 | int ret; | |
640 | ||
641 | /* | |
642 | * This is applicable for SDHCI_SPEC_300 and above | |
643 | * ZynqMP does not set phase for <=25MHz clock. | |
644 | * If degrees is zero, no need to do anything. | |
645 | */ | |
646 | if (host->version < SDHCI_SPEC_300 || | |
647 | host->timing == MMC_TIMING_LEGACY || | |
648 | host->timing == MMC_TIMING_UHS_SDR12 || !degrees) | |
649 | return 0; | |
650 | ||
651 | switch (host->timing) { | |
652 | case MMC_TIMING_MMC_HS: | |
653 | case MMC_TIMING_SD_HS: | |
654 | case MMC_TIMING_UHS_SDR25: | |
655 | case MMC_TIMING_UHS_DDR50: | |
656 | case MMC_TIMING_MMC_DDR52: | |
657 | /* For 50MHz clock, 30 Taps are available */ | |
658 | tap_max = 30; | |
659 | break; | |
660 | case MMC_TIMING_UHS_SDR50: | |
661 | /* For 100MHz clock, 15 Taps are available */ | |
662 | tap_max = 15; | |
663 | break; | |
664 | case MMC_TIMING_UHS_SDR104: | |
665 | case MMC_TIMING_MMC_HS200: | |
666 | /* For 200MHz clock, 8 Taps are available */ | |
667 | tap_max = 8; | |
668 | default: | |
669 | break; | |
670 | } | |
671 | ||
672 | tap_delay = (degrees * tap_max) / 360; | |
673 | ||
674 | /* Set the Clock Phase */ | |
675 | ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY, | |
676 | PM_TAPDELAY_OUTPUT, tap_delay, NULL); | |
677 | if (ret) | |
678 | pr_err("Error setting Output Tap Delay\n"); | |
679 | ||
680 | return ret; | |
681 | } | |
682 | ||
683 | static const struct clk_ops zynqmp_sdcardclk_ops = { | |
684 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
685 | .set_phase = sdhci_zynqmp_sdcardclk_set_phase, | |
686 | }; | |
687 | ||
688 | /** | |
689 | * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays | |
690 | * | |
691 | * Set the SD Input Clock Tap Delays for Input path | |
692 | * | |
693 | * @hw: Pointer to the hardware clock structure. | |
694 | * @degrees The clock phase shift between 0 - 359. | |
695 | * Return: 0 on success and error value on error | |
696 | */ | |
697 | static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) | |
698 | ||
699 | { | |
700 | struct sdhci_arasan_clk_data *clk_data = | |
701 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
702 | struct sdhci_arasan_data *sdhci_arasan = | |
703 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
704 | struct sdhci_host *host = sdhci_arasan->host; | |
705 | struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = | |
706 | clk_data->clk_of_data; | |
707 | const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; | |
708 | const char *clk_name = clk_hw_get_name(hw); | |
709 | u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1; | |
710 | u8 tap_delay, tap_max = 0; | |
711 | int ret; | |
712 | ||
713 | /* | |
714 | * This is applicable for SDHCI_SPEC_300 and above | |
715 | * ZynqMP does not set phase for <=25MHz clock. | |
716 | * If degrees is zero, no need to do anything. | |
717 | */ | |
718 | if (host->version < SDHCI_SPEC_300 || | |
719 | host->timing == MMC_TIMING_LEGACY || | |
720 | host->timing == MMC_TIMING_UHS_SDR12 || !degrees) | |
721 | return 0; | |
722 | ||
723 | switch (host->timing) { | |
724 | case MMC_TIMING_MMC_HS: | |
725 | case MMC_TIMING_SD_HS: | |
726 | case MMC_TIMING_UHS_SDR25: | |
727 | case MMC_TIMING_UHS_DDR50: | |
728 | case MMC_TIMING_MMC_DDR52: | |
729 | /* For 50MHz clock, 120 Taps are available */ | |
730 | tap_max = 120; | |
731 | break; | |
732 | case MMC_TIMING_UHS_SDR50: | |
733 | /* For 100MHz clock, 60 Taps are available */ | |
734 | tap_max = 60; | |
735 | break; | |
736 | case MMC_TIMING_UHS_SDR104: | |
737 | case MMC_TIMING_MMC_HS200: | |
738 | /* For 200MHz clock, 30 Taps are available */ | |
739 | tap_max = 30; | |
740 | default: | |
741 | break; | |
742 | } | |
743 | ||
744 | tap_delay = (degrees * tap_max) / 360; | |
745 | ||
746 | /* Set the Clock Phase */ | |
747 | ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY, | |
748 | PM_TAPDELAY_INPUT, tap_delay, NULL); | |
749 | if (ret) | |
750 | pr_err("Error setting Input Tap Delay\n"); | |
751 | ||
752 | return ret; | |
753 | } | |
754 | ||
755 | static const struct clk_ops zynqmp_sampleclk_ops = { | |
756 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
757 | .set_phase = sdhci_zynqmp_sampleclk_set_phase, | |
758 | }; | |
759 | ||
8d2e3343 MN |
760 | static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) |
761 | { | |
762 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
763 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
764 | struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = | |
765 | sdhci_arasan->clk_data.clk_of_data; | |
766 | const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; | |
767 | u16 clk; | |
768 | ||
769 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
770 | clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); | |
771 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
772 | ||
773 | /* Issue DLL Reset */ | |
774 | eemi_ops->ioctl(deviceid, IOCTL_SD_DLL_RESET, | |
775 | PM_DLL_RESET_PULSE, 0, NULL); | |
776 | ||
777 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
778 | ||
779 | sdhci_enable_clk(host, clk); | |
780 | } | |
781 | ||
782 | static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode) | |
783 | { | |
784 | struct sdhci_host *host = mmc_priv(mmc); | |
785 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
786 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
787 | struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; | |
788 | const char *clk_name = clk_hw_get_name(hw); | |
789 | u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : | |
790 | NODE_SD_1; | |
791 | int err; | |
792 | ||
793 | arasan_zynqmp_dll_reset(host, device_id); | |
794 | ||
795 | err = sdhci_execute_tuning(mmc, opcode); | |
796 | if (err) | |
797 | return err; | |
798 | ||
799 | arasan_zynqmp_dll_reset(host, device_id); | |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
b2ca77c9 SL |
804 | /** |
805 | * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier | |
806 | * | |
807 | * The corecfg_clockmultiplier is supposed to contain clock multiplier | |
808 | * value of programmable clock generator. | |
809 | * | |
810 | * NOTES: | |
811 | * - Many existing devices don't seem to do this and work fine. To keep | |
812 | * compatibility for old hardware where the device tree doesn't provide a | |
813 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
814 | * for this platform. | |
815 | * - The value of corecfg_clockmultiplier should sync with that of corresponding | |
816 | * value reading from sdhci_capability_register. So this function is called | |
817 | * once at probe time and never called again. | |
818 | * | |
819 | * @host: The sdhci_host | |
820 | */ | |
821 | static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, | |
822 | u32 value) | |
823 | { | |
824 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
825 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
826 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
827 | sdhci_arasan->soc_ctl_map; | |
828 | ||
829 | /* Having a map is optional */ | |
830 | if (!soc_ctl_map) | |
831 | return; | |
832 | ||
833 | /* If we have a map, we expect to have a syscon */ | |
834 | if (!sdhci_arasan->soc_ctl_base) { | |
835 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
836 | mmc_hostname(host->mmc)); | |
837 | return; | |
838 | } | |
839 | ||
840 | sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); | |
841 | } | |
842 | ||
3ea4666e DA |
843 | /** |
844 | * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq | |
845 | * | |
846 | * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This | |
847 | * function can be used to make that happen. | |
848 | * | |
849 | * NOTES: | |
850 | * - Many existing devices don't seem to do this and work fine. To keep | |
851 | * compatibility for old hardware where the device tree doesn't provide a | |
852 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
853 | * for this platform. | |
854 | * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider | |
855 | * to achieve lower clock rates. That means that this function is called once | |
856 | * at probe time and never called again. | |
857 | * | |
858 | * @host: The sdhci_host | |
859 | */ | |
860 | static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) | |
861 | { | |
862 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
863 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
864 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
865 | sdhci_arasan->soc_ctl_map; | |
866 | u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); | |
867 | ||
868 | /* Having a map is optional */ | |
869 | if (!soc_ctl_map) | |
870 | return; | |
871 | ||
872 | /* If we have a map, we expect to have a syscon */ | |
873 | if (!sdhci_arasan->soc_ctl_base) { | |
874 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
875 | mmc_hostname(host->mmc)); | |
876 | return; | |
877 | } | |
878 | ||
879 | sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); | |
880 | } | |
881 | ||
f3dafc37 MN |
882 | static void sdhci_arasan_set_clk_delays(struct sdhci_host *host) |
883 | { | |
884 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
885 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
886 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; | |
887 | ||
888 | clk_set_phase(clk_data->sampleclk, | |
889 | clk_data->clk_phase_in[host->timing]); | |
890 | clk_set_phase(clk_data->sdcardclk, | |
891 | clk_data->clk_phase_out[host->timing]); | |
892 | } | |
893 | ||
894 | static void arasan_dt_read_clk_phase(struct device *dev, | |
895 | struct sdhci_arasan_clk_data *clk_data, | |
896 | unsigned int timing, const char *prop) | |
897 | { | |
898 | struct device_node *np = dev->of_node; | |
899 | ||
900 | int clk_phase[2] = {0}; | |
901 | ||
902 | /* | |
903 | * Read Tap Delay values from DT, if the DT does not contain the | |
904 | * Tap Values then use the pre-defined values. | |
905 | */ | |
906 | if (of_property_read_variable_u32_array(np, prop, &clk_phase[0], | |
907 | 2, 0)) { | |
908 | dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n", | |
909 | prop, clk_data->clk_phase_in[timing], | |
910 | clk_data->clk_phase_out[timing]); | |
911 | return; | |
912 | } | |
913 | ||
914 | /* The values read are Input and Output Clock Delays in order */ | |
915 | clk_data->clk_phase_in[timing] = clk_phase[0]; | |
916 | clk_data->clk_phase_out[timing] = clk_phase[1]; | |
917 | } | |
918 | ||
919 | /** | |
920 | * arasan_dt_parse_clk_phases - Read Clock Delay values from DT | |
921 | * | |
922 | * Called at initialization to parse the values of Clock Delays. | |
923 | * | |
924 | * @dev: Pointer to our struct device. | |
925 | * @clk_data: Pointer to the Clock Data structure | |
926 | */ | |
927 | static void arasan_dt_parse_clk_phases(struct device *dev, | |
928 | struct sdhci_arasan_clk_data *clk_data) | |
929 | { | |
a5c8b2ae MN |
930 | int *iclk_phase, *oclk_phase; |
931 | u32 mio_bank = 0; | |
932 | int i; | |
933 | ||
f3dafc37 MN |
934 | /* |
935 | * This has been kept as a pointer and is assigned a function here. | |
936 | * So that different controller variants can assign their own handling | |
937 | * function. | |
938 | */ | |
939 | clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; | |
940 | ||
a5c8b2ae MN |
941 | if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { |
942 | iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ICLK_PHASE; | |
943 | oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OCLK_PHASE; | |
944 | ||
945 | of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); | |
946 | if (mio_bank == 2) { | |
947 | oclk_phase[MMC_TIMING_UHS_SDR104] = 90; | |
948 | oclk_phase[MMC_TIMING_MMC_HS200] = 90; | |
949 | } | |
950 | ||
951 | for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { | |
952 | clk_data->clk_phase_in[i] = iclk_phase[i]; | |
953 | clk_data->clk_phase_out[i] = oclk_phase[i]; | |
954 | } | |
955 | } | |
956 | ||
f3dafc37 MN |
957 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY, |
958 | "clk-phase-legacy"); | |
959 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS, | |
960 | "clk-phase-mmc-hs"); | |
961 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS, | |
962 | "clk-phase-sd-hs"); | |
963 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12, | |
964 | "clk-phase-uhs-sdr12"); | |
965 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25, | |
966 | "clk-phase-uhs-sdr25"); | |
967 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50, | |
968 | "clk-phase-uhs-sdr50"); | |
969 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104, | |
970 | "clk-phase-uhs-sdr104"); | |
971 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, | |
972 | "clk-phase-uhs-ddr50"); | |
973 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52, | |
974 | "clk-phase-mmc-ddr52"); | |
975 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200, | |
976 | "clk-phase-mmc-hs200"); | |
977 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400, | |
978 | "clk-phase-mmc-hs400"); | |
979 | } | |
980 | ||
c390f211 | 981 | /** |
07a14d1d | 982 | * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use |
c390f211 DA |
983 | * |
984 | * Some PHY devices need to know what the actual card clock is. In order for | |
985 | * them to find out, we'll provide a clock through the common clock framework | |
986 | * for them to query. | |
987 | * | |
c390f211 DA |
988 | * @sdhci_arasan: Our private data structure. |
989 | * @clk_xin: Pointer to the functional clock | |
990 | * @dev: Pointer to our struct device. | |
991 | * Returns 0 on success and error value on error | |
992 | */ | |
07a14d1d MN |
993 | static int |
994 | sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan, | |
995 | struct clk *clk_xin, | |
996 | struct device *dev) | |
c390f211 | 997 | { |
e1463618 | 998 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; |
c390f211 DA |
999 | struct device_node *np = dev->of_node; |
1000 | struct clk_init_data sdcardclk_init; | |
1001 | const char *parent_clk_name; | |
1002 | int ret; | |
1003 | ||
c390f211 DA |
1004 | ret = of_property_read_string_index(np, "clock-output-names", 0, |
1005 | &sdcardclk_init.name); | |
1006 | if (ret) { | |
1007 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
1008 | return ret; | |
1009 | } | |
1010 | ||
1011 | parent_clk_name = __clk_get_name(clk_xin); | |
1012 | sdcardclk_init.parent_names = &parent_clk_name; | |
1013 | sdcardclk_init.num_parents = 1; | |
1014 | sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; | |
a5c8b2ae MN |
1015 | if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) |
1016 | sdcardclk_init.ops = &zynqmp_sdcardclk_ops; | |
1017 | else | |
1018 | sdcardclk_init.ops = &arasan_sdcardclk_ops; | |
c390f211 | 1019 | |
e1463618 MN |
1020 | clk_data->sdcardclk_hw.init = &sdcardclk_init; |
1021 | clk_data->sdcardclk = | |
1022 | devm_clk_register(dev, &clk_data->sdcardclk_hw); | |
1023 | clk_data->sdcardclk_hw.init = NULL; | |
c390f211 DA |
1024 | |
1025 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
e1463618 | 1026 | clk_data->sdcardclk); |
c390f211 | 1027 | if (ret) |
07a14d1d MN |
1028 | dev_err(dev, "Failed to add sdcard clock provider\n"); |
1029 | ||
1030 | return ret; | |
1031 | } | |
1032 | ||
1033 | /** | |
1034 | * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use | |
1035 | * | |
1036 | * Some PHY devices need to know what the actual card clock is. In order for | |
1037 | * them to find out, we'll provide a clock through the common clock framework | |
1038 | * for them to query. | |
1039 | * | |
1040 | * @sdhci_arasan: Our private data structure. | |
1041 | * @clk_xin: Pointer to the functional clock | |
1042 | * @dev: Pointer to our struct device. | |
1043 | * Returns 0 on success and error value on error | |
1044 | */ | |
1045 | static int | |
1046 | sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan, | |
1047 | struct clk *clk_xin, | |
1048 | struct device *dev) | |
1049 | { | |
1050 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; | |
1051 | struct device_node *np = dev->of_node; | |
1052 | struct clk_init_data sampleclk_init; | |
1053 | const char *parent_clk_name; | |
1054 | int ret; | |
1055 | ||
1056 | ret = of_property_read_string_index(np, "clock-output-names", 1, | |
1057 | &sampleclk_init.name); | |
1058 | if (ret) { | |
1059 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | parent_clk_name = __clk_get_name(clk_xin); | |
1064 | sampleclk_init.parent_names = &parent_clk_name; | |
1065 | sampleclk_init.num_parents = 1; | |
1066 | sampleclk_init.flags = CLK_GET_RATE_NOCACHE; | |
a5c8b2ae MN |
1067 | if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) |
1068 | sampleclk_init.ops = &zynqmp_sampleclk_ops; | |
1069 | else | |
1070 | sampleclk_init.ops = &arasan_sampleclk_ops; | |
07a14d1d MN |
1071 | |
1072 | clk_data->sampleclk_hw.init = &sampleclk_init; | |
1073 | clk_data->sampleclk = | |
1074 | devm_clk_register(dev, &clk_data->sampleclk_hw); | |
1075 | clk_data->sampleclk_hw.init = NULL; | |
1076 | ||
1077 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
1078 | clk_data->sampleclk); | |
1079 | if (ret) | |
1080 | dev_err(dev, "Failed to add sample clock provider\n"); | |
c390f211 DA |
1081 | |
1082 | return ret; | |
1083 | } | |
1084 | ||
1085 | /** | |
1086 | * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() | |
1087 | * | |
1088 | * Should be called any time we're exiting and sdhci_arasan_register_sdclk() | |
1089 | * returned success. | |
1090 | * | |
1091 | * @dev: Pointer to our struct device. | |
1092 | */ | |
1093 | static void sdhci_arasan_unregister_sdclk(struct device *dev) | |
1094 | { | |
1095 | struct device_node *np = dev->of_node; | |
1096 | ||
1097 | if (!of_find_property(np, "#clock-cells", NULL)) | |
1098 | return; | |
1099 | ||
1100 | of_clk_del_provider(dev->of_node); | |
1101 | } | |
1102 | ||
07a14d1d MN |
1103 | /** |
1104 | * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use | |
1105 | * | |
1106 | * Some PHY devices need to know what the actual card clock is. In order for | |
1107 | * them to find out, we'll provide a clock through the common clock framework | |
1108 | * for them to query. | |
1109 | * | |
1110 | * Note: without seriously re-architecting SDHCI's clock code and testing on | |
1111 | * all platforms, there's no way to create a totally beautiful clock here | |
1112 | * with all clock ops implemented. Instead, we'll just create a clock that can | |
1113 | * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock | |
1114 | * framework that we're doing things behind its back. This should be sufficient | |
1115 | * to create nice clean device tree bindings and later (if needed) we can try | |
1116 | * re-architecting SDHCI if we see some benefit to it. | |
1117 | * | |
1118 | * @sdhci_arasan: Our private data structure. | |
1119 | * @clk_xin: Pointer to the functional clock | |
1120 | * @dev: Pointer to our struct device. | |
1121 | * Returns 0 on success and error value on error | |
1122 | */ | |
1123 | static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, | |
1124 | struct clk *clk_xin, | |
1125 | struct device *dev) | |
1126 | { | |
1127 | struct device_node *np = dev->of_node; | |
1128 | u32 num_clks = 0; | |
1129 | int ret; | |
1130 | ||
1131 | /* Providing a clock to the PHY is optional; no error if missing */ | |
1132 | if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) | |
1133 | return 0; | |
1134 | ||
1135 | ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev); | |
1136 | if (ret) | |
1137 | return ret; | |
1138 | ||
1139 | if (num_clks) { | |
1140 | ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin, | |
1141 | dev); | |
1142 | if (ret) { | |
1143 | sdhci_arasan_unregister_sdclk(dev); | |
1144 | return ret; | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | return 0; | |
1149 | } | |
1150 | ||
84362d79 SL |
1151 | static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) |
1152 | { | |
1153 | struct sdhci_host *host = sdhci_arasan->host; | |
1154 | struct cqhci_host *cq_host; | |
1155 | bool dma64; | |
1156 | int ret; | |
1157 | ||
1158 | if (!sdhci_arasan->has_cqe) | |
1159 | return sdhci_add_host(host); | |
1160 | ||
1161 | ret = sdhci_setup_host(host); | |
1162 | if (ret) | |
1163 | return ret; | |
1164 | ||
1165 | cq_host = devm_kzalloc(host->mmc->parent, | |
1166 | sizeof(*cq_host), GFP_KERNEL); | |
1167 | if (!cq_host) { | |
1168 | ret = -ENOMEM; | |
1169 | goto cleanup; | |
1170 | } | |
1171 | ||
1172 | cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; | |
1173 | cq_host->ops = &sdhci_arasan_cqhci_ops; | |
1174 | ||
1175 | dma64 = host->flags & SDHCI_USE_64_BIT_DMA; | |
1176 | if (dma64) | |
1177 | cq_host->caps |= CQHCI_TASK_DESC_SZ_128; | |
1178 | ||
1179 | ret = cqhci_init(cq_host, host->mmc, dma64); | |
1180 | if (ret) | |
1181 | goto cleanup; | |
1182 | ||
1183 | ret = __sdhci_add_host(host); | |
1184 | if (ret) | |
1185 | goto cleanup; | |
1186 | ||
1187 | return 0; | |
1188 | ||
1189 | cleanup: | |
1190 | sdhci_cleanup_host(host); | |
1191 | return ret; | |
1192 | } | |
1193 | ||
e3ec3a3d SB |
1194 | static int sdhci_arasan_probe(struct platform_device *pdev) |
1195 | { | |
1196 | int ret; | |
3ea4666e DA |
1197 | const struct of_device_id *match; |
1198 | struct device_node *node; | |
e3ec3a3d SB |
1199 | struct clk *clk_xin; |
1200 | struct sdhci_host *host; | |
1201 | struct sdhci_pltfm_host *pltfm_host; | |
1202 | struct sdhci_arasan_data *sdhci_arasan; | |
3794c542 | 1203 | struct device_node *np = pdev->dev.of_node; |
06b23ca0 | 1204 | const struct sdhci_arasan_of_data *data; |
84362d79 | 1205 | |
06b23ca0 FA |
1206 | match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); |
1207 | data = match->data; | |
1208 | host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); | |
e3ec3a3d | 1209 | |
89211418 JZ |
1210 | if (IS_ERR(host)) |
1211 | return PTR_ERR(host); | |
1212 | ||
1213 | pltfm_host = sdhci_priv(host); | |
1214 | sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
c390f211 | 1215 | sdhci_arasan->host = host; |
e3ec3a3d | 1216 | |
06b23ca0 | 1217 | sdhci_arasan->soc_ctl_map = data->soc_ctl_map; |
3ea4666e DA |
1218 | |
1219 | node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); | |
1220 | if (node) { | |
1221 | sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); | |
1222 | of_node_put(node); | |
1223 | ||
1224 | if (IS_ERR(sdhci_arasan->soc_ctl_base)) { | |
1225 | ret = PTR_ERR(sdhci_arasan->soc_ctl_base); | |
1226 | if (ret != -EPROBE_DEFER) | |
1227 | dev_err(&pdev->dev, "Can't get syscon: %d\n", | |
1228 | ret); | |
1229 | goto err_pltfm_free; | |
1230 | } | |
1231 | } | |
1232 | ||
e3ec3a3d SB |
1233 | sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); |
1234 | if (IS_ERR(sdhci_arasan->clk_ahb)) { | |
1235 | dev_err(&pdev->dev, "clk_ahb clock not found.\n"); | |
278d0962 SL |
1236 | ret = PTR_ERR(sdhci_arasan->clk_ahb); |
1237 | goto err_pltfm_free; | |
e3ec3a3d SB |
1238 | } |
1239 | ||
1240 | clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); | |
1241 | if (IS_ERR(clk_xin)) { | |
1242 | dev_err(&pdev->dev, "clk_xin clock not found.\n"); | |
278d0962 SL |
1243 | ret = PTR_ERR(clk_xin); |
1244 | goto err_pltfm_free; | |
e3ec3a3d SB |
1245 | } |
1246 | ||
1247 | ret = clk_prepare_enable(sdhci_arasan->clk_ahb); | |
1248 | if (ret) { | |
1249 | dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); | |
278d0962 | 1250 | goto err_pltfm_free; |
e3ec3a3d SB |
1251 | } |
1252 | ||
1253 | ret = clk_prepare_enable(clk_xin); | |
1254 | if (ret) { | |
1255 | dev_err(&pdev->dev, "Unable to enable SD clock.\n"); | |
1256 | goto clk_dis_ahb; | |
1257 | } | |
1258 | ||
e3ec3a3d | 1259 | sdhci_get_of_property(pdev); |
3794c542 ZB |
1260 | |
1261 | if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) | |
1262 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; | |
1263 | ||
3f2c7d5d HG |
1264 | if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) |
1265 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; | |
1266 | ||
e3ec3a3d SB |
1267 | pltfm_host->clk = clk_xin; |
1268 | ||
b2ca77c9 SL |
1269 | if (of_device_is_compatible(pdev->dev.of_node, |
1270 | "rockchip,rk3399-sdhci-5.1")) | |
1271 | sdhci_arasan_update_clockmultiplier(host, 0x0); | |
1272 | ||
3ea4666e DA |
1273 | sdhci_arasan_update_baseclkfreq(host); |
1274 | ||
c390f211 DA |
1275 | ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); |
1276 | if (ret) | |
1277 | goto clk_disable_all; | |
1278 | ||
a5c8b2ae MN |
1279 | if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { |
1280 | struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data; | |
1281 | const struct zynqmp_eemi_ops *eemi_ops; | |
1282 | ||
1283 | zynqmp_clk_data = devm_kzalloc(&pdev->dev, | |
1284 | sizeof(*zynqmp_clk_data), | |
1285 | GFP_KERNEL); | |
1286 | eemi_ops = zynqmp_pm_get_eemi_ops(); | |
1287 | if (IS_ERR(eemi_ops)) { | |
1288 | ret = PTR_ERR(eemi_ops); | |
1289 | goto unreg_clk; | |
1290 | } | |
1291 | ||
1292 | zynqmp_clk_data->eemi_ops = eemi_ops; | |
1293 | sdhci_arasan->clk_data.clk_of_data = zynqmp_clk_data; | |
8d2e3343 MN |
1294 | host->mmc_host_ops.execute_tuning = |
1295 | arasan_zynqmp_execute_tuning; | |
a5c8b2ae MN |
1296 | } |
1297 | ||
f3dafc37 MN |
1298 | arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data); |
1299 | ||
16b23787 MS |
1300 | ret = mmc_of_parse(host->mmc); |
1301 | if (ret) { | |
60208a26 MS |
1302 | if (ret != -EPROBE_DEFER) |
1303 | dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); | |
c390f211 | 1304 | goto unreg_clk; |
16b23787 MS |
1305 | } |
1306 | ||
91aa3661 SL |
1307 | sdhci_arasan->phy = ERR_PTR(-ENODEV); |
1308 | if (of_device_is_compatible(pdev->dev.of_node, | |
1309 | "arasan,sdhci-5.1")) { | |
1310 | sdhci_arasan->phy = devm_phy_get(&pdev->dev, | |
1311 | "phy_arasan"); | |
1312 | if (IS_ERR(sdhci_arasan->phy)) { | |
1313 | ret = PTR_ERR(sdhci_arasan->phy); | |
1314 | dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); | |
c390f211 | 1315 | goto unreg_clk; |
91aa3661 SL |
1316 | } |
1317 | ||
1318 | ret = phy_init(sdhci_arasan->phy); | |
1319 | if (ret < 0) { | |
1320 | dev_err(&pdev->dev, "phy_init err.\n"); | |
c390f211 | 1321 | goto unreg_clk; |
91aa3661 SL |
1322 | } |
1323 | ||
a05c8465 SL |
1324 | host->mmc_host_ops.hs400_enhanced_strobe = |
1325 | sdhci_arasan_hs400_enhanced_strobe; | |
8a3bee9b SL |
1326 | host->mmc_host_ops.start_signal_voltage_switch = |
1327 | sdhci_arasan_voltage_switch; | |
84362d79 | 1328 | sdhci_arasan->has_cqe = true; |
7bda9482 CM |
1329 | host->mmc->caps2 |= MMC_CAP2_CQE; |
1330 | ||
1331 | if (!of_property_read_bool(np, "disable-cqe-dcmd")) | |
1332 | host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; | |
91aa3661 SL |
1333 | } |
1334 | ||
84362d79 | 1335 | ret = sdhci_arasan_add_host(sdhci_arasan); |
b1df9de7 | 1336 | if (ret) |
91aa3661 | 1337 | goto err_add_host; |
e3ec3a3d SB |
1338 | |
1339 | return 0; | |
1340 | ||
91aa3661 | 1341 | err_add_host: |
91aa3661 SL |
1342 | if (!IS_ERR(sdhci_arasan->phy)) |
1343 | phy_exit(sdhci_arasan->phy); | |
c390f211 DA |
1344 | unreg_clk: |
1345 | sdhci_arasan_unregister_sdclk(&pdev->dev); | |
e3ec3a3d SB |
1346 | clk_disable_all: |
1347 | clk_disable_unprepare(clk_xin); | |
1348 | clk_dis_ahb: | |
1349 | clk_disable_unprepare(sdhci_arasan->clk_ahb); | |
278d0962 SL |
1350 | err_pltfm_free: |
1351 | sdhci_pltfm_free(pdev); | |
e3ec3a3d SB |
1352 | return ret; |
1353 | } | |
1354 | ||
1355 | static int sdhci_arasan_remove(struct platform_device *pdev) | |
1356 | { | |
0c7fe32e | 1357 | int ret; |
e3ec3a3d SB |
1358 | struct sdhci_host *host = platform_get_drvdata(pdev); |
1359 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 JZ |
1360 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
1361 | struct clk *clk_ahb = sdhci_arasan->clk_ahb; | |
e3ec3a3d | 1362 | |
91aa3661 | 1363 | if (!IS_ERR(sdhci_arasan->phy)) { |
b2db9c67 DA |
1364 | if (sdhci_arasan->is_phy_on) |
1365 | phy_power_off(sdhci_arasan->phy); | |
91aa3661 SL |
1366 | phy_exit(sdhci_arasan->phy); |
1367 | } | |
1368 | ||
c390f211 DA |
1369 | sdhci_arasan_unregister_sdclk(&pdev->dev); |
1370 | ||
0c7fe32e JZ |
1371 | ret = sdhci_pltfm_unregister(pdev); |
1372 | ||
89211418 | 1373 | clk_disable_unprepare(clk_ahb); |
e3ec3a3d | 1374 | |
0c7fe32e | 1375 | return ret; |
e3ec3a3d SB |
1376 | } |
1377 | ||
e3ec3a3d SB |
1378 | static struct platform_driver sdhci_arasan_driver = { |
1379 | .driver = { | |
1380 | .name = "sdhci-arasan", | |
e3ec3a3d SB |
1381 | .of_match_table = sdhci_arasan_of_match, |
1382 | .pm = &sdhci_arasan_dev_pm_ops, | |
1383 | }, | |
1384 | .probe = sdhci_arasan_probe, | |
1385 | .remove = sdhci_arasan_remove, | |
1386 | }; | |
1387 | ||
1388 | module_platform_driver(sdhci_arasan_driver); | |
1389 | ||
1390 | MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); | |
1391 | MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); | |
1392 | MODULE_LICENSE("GPL"); |