Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e3ec3a3d SB |
2 | /* |
3 | * Arasan Secure Digital Host Controller Interface. | |
4 | * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> | |
5 | * Copyright (c) 2012 Wind River Systems, Inc. | |
6 | * Copyright (C) 2013 Pengutronix e.K. | |
7 | * Copyright (C) 2013 Xilinx Inc. | |
8 | * | |
9 | * Based on sdhci-of-esdhc.c | |
10 | * | |
11 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
12 | * Copyright (c) 2009 MontaVista Software, Inc. | |
13 | * | |
14 | * Authors: Xiaobo Xie <X.Xie@freescale.com> | |
15 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
e3ec3a3d SB |
16 | */ |
17 | ||
c390f211 | 18 | #include <linux/clk-provider.h> |
3ea4666e | 19 | #include <linux/mfd/syscon.h> |
e3ec3a3d | 20 | #include <linux/module.h> |
308f3f8d | 21 | #include <linux/of_device.h> |
91aa3661 | 22 | #include <linux/phy/phy.h> |
3ea4666e | 23 | #include <linux/regmap.h> |
3794c542 | 24 | #include <linux/of.h> |
a5c8b2ae | 25 | #include <linux/firmware/xlnx-zynqmp.h> |
e3ec3a3d | 26 | |
84362d79 SL |
27 | #include "cqhci.h" |
28 | #include "sdhci-pltfm.h" | |
e3ec3a3d | 29 | |
84362d79 | 30 | #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 |
1a470721 MN |
31 | |
32 | #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8 | |
d338c6d0 MN |
33 | #define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF |
34 | ||
1a470721 | 35 | #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC |
d338c6d0 | 36 | #define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F |
1a470721 | 37 | |
84362d79 | 38 | #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 |
a05c8465 | 39 | #define VENDOR_ENHANCED_STROBE BIT(0) |
e3ec3a3d | 40 | |
b2db9c67 DA |
41 | #define PHY_CLK_TOO_SLOW_HZ 400000 |
42 | ||
1a470721 MN |
43 | #define SDHCI_ITAPDLY_CHGWIN 0x200 |
44 | #define SDHCI_ITAPDLY_ENABLE 0x100 | |
45 | #define SDHCI_OTAPDLY_ENABLE 0x40 | |
46 | ||
a5c8b2ae MN |
47 | /* Default settings for ZynqMP Clock Phases */ |
48 | #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0} | |
49 | #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0} | |
50 | ||
1a470721 MN |
51 | #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0} |
52 | #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0} | |
53 | ||
3ea4666e DA |
54 | /* |
55 | * On some SoCs the syscon area has a feature where the upper 16-bits of | |
56 | * each 32-bit register act as a write mask for the lower 16-bits. This allows | |
57 | * atomic updates of the register without locking. This macro is used on SoCs | |
58 | * that have that feature. | |
59 | */ | |
60 | #define HIWORD_UPDATE(val, mask, shift) \ | |
61 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
62 | ||
63 | /** | |
64 | * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map | |
65 | * | |
66 | * @reg: Offset within the syscon of the register containing this field | |
67 | * @width: Number of bits for this field | |
68 | * @shift: Bit offset within @reg of this field (or -1 if not avail) | |
69 | */ | |
70 | struct sdhci_arasan_soc_ctl_field { | |
71 | u32 reg; | |
72 | u16 width; | |
73 | s16 shift; | |
74 | }; | |
75 | ||
76 | /** | |
77 | * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers | |
78 | * | |
3ea4666e | 79 | * @baseclkfreq: Where to find corecfg_baseclkfreq |
b2ca77c9 | 80 | * @clockmultiplier: Where to find corecfg_clockmultiplier |
36c6aada | 81 | * @support64b: Where to find SUPPORT64B bit |
3ea4666e | 82 | * @hiword_update: If true, use HIWORD_UPDATE to access the syscon |
4908460e MN |
83 | * |
84 | * It's up to the licensee of the Arsan IP block to make these available | |
85 | * somewhere if needed. Presumably these will be scattered somewhere that's | |
86 | * accessible via the syscon API. | |
3ea4666e DA |
87 | */ |
88 | struct sdhci_arasan_soc_ctl_map { | |
89 | struct sdhci_arasan_soc_ctl_field baseclkfreq; | |
b2ca77c9 | 90 | struct sdhci_arasan_soc_ctl_field clockmultiplier; |
36c6aada | 91 | struct sdhci_arasan_soc_ctl_field support64b; |
3ea4666e DA |
92 | bool hiword_update; |
93 | }; | |
94 | ||
16ada730 MN |
95 | /** |
96 | * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller | |
97 | * | |
98 | * @sdcardclk_ops: The output clock related operations | |
99 | * @sampleclk_ops: The sample clock related operations | |
100 | */ | |
101 | struct sdhci_arasan_clk_ops { | |
102 | const struct clk_ops *sdcardclk_ops; | |
103 | const struct clk_ops *sampleclk_ops; | |
104 | }; | |
105 | ||
e1463618 | 106 | /** |
4908460e MN |
107 | * struct sdhci_arasan_clk_data - Arasan Controller Clock Data. |
108 | * | |
e1463618 MN |
109 | * @sdcardclk_hw: Struct for the clock we might provide to a PHY. |
110 | * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. | |
07a14d1d MN |
111 | * @sampleclk_hw: Struct for the clock we might provide to a PHY. |
112 | * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw. | |
f3dafc37 MN |
113 | * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes |
114 | * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes | |
115 | * @set_clk_delays: Function pointer for setting Clock Delays | |
a5c8b2ae | 116 | * @clk_of_data: Platform specific runtime clock data storage pointer |
e1463618 MN |
117 | */ |
118 | struct sdhci_arasan_clk_data { | |
119 | struct clk_hw sdcardclk_hw; | |
120 | struct clk *sdcardclk; | |
07a14d1d MN |
121 | struct clk_hw sampleclk_hw; |
122 | struct clk *sampleclk; | |
f3dafc37 MN |
123 | int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; |
124 | int clk_phase_out[MMC_TIMING_MMC_HS400 + 1]; | |
125 | void (*set_clk_delays)(struct sdhci_host *host); | |
a5c8b2ae MN |
126 | void *clk_of_data; |
127 | }; | |
128 | ||
e3ec3a3d | 129 | /** |
4908460e MN |
130 | * struct sdhci_arasan_data - Arasan Controller Data |
131 | * | |
c390f211 | 132 | * @host: Pointer to the main SDHCI host structure. |
3ea4666e DA |
133 | * @clk_ahb: Pointer to the AHB clock |
134 | * @phy: Pointer to the generic phy | |
b2db9c67 | 135 | * @is_phy_on: True if the PHY is on; false if not. |
4908460e | 136 | * @has_cqe: True if controller has command queuing engine. |
e1463618 | 137 | * @clk_data: Struct for the Arasan Controller Clock Data. |
16ada730 | 138 | * @clk_ops: Struct for the Arasan Controller Clock Operations. |
3ea4666e DA |
139 | * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. |
140 | * @soc_ctl_map: Map to get offsets into soc_ctl registers. | |
4908460e | 141 | * @quirks: Arasan deviations from spec. |
e3ec3a3d SB |
142 | */ |
143 | struct sdhci_arasan_data { | |
c390f211 | 144 | struct sdhci_host *host; |
e3ec3a3d | 145 | struct clk *clk_ahb; |
91aa3661 | 146 | struct phy *phy; |
b2db9c67 | 147 | bool is_phy_on; |
3ea4666e | 148 | |
84362d79 | 149 | bool has_cqe; |
e1463618 | 150 | struct sdhci_arasan_clk_data clk_data; |
16ada730 | 151 | const struct sdhci_arasan_clk_ops *clk_ops; |
c390f211 | 152 | |
3ea4666e DA |
153 | struct regmap *soc_ctl_base; |
154 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
4908460e | 155 | unsigned int quirks; |
3794c542 ZB |
156 | |
157 | /* Controller does not have CD wired and will not function normally without */ | |
158 | #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) | |
3f2c7d5d HG |
159 | /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the |
160 | * internal clock even when the clock isn't stable */ | |
161 | #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) | |
c0b4e411 MN |
162 | /* |
163 | * Some of the Arasan variations might not have timing requirements | |
164 | * met at 25MHz for Default Speed mode, those controllers work at | |
165 | * 19MHz instead | |
166 | */ | |
167 | #define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2) | |
3ea4666e DA |
168 | }; |
169 | ||
06b23ca0 FA |
170 | struct sdhci_arasan_of_data { |
171 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
172 | const struct sdhci_pltfm_data *pdata; | |
16ada730 | 173 | const struct sdhci_arasan_clk_ops *clk_ops; |
06b23ca0 FA |
174 | }; |
175 | ||
3ea4666e DA |
176 | static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { |
177 | .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, | |
b2ca77c9 | 178 | .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, |
3ea4666e | 179 | .hiword_update = true, |
e3ec3a3d SB |
180 | }; |
181 | ||
5c1a4f40 RVM |
182 | static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = { |
183 | .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 }, | |
184 | .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, | |
185 | .hiword_update = false, | |
186 | }; | |
187 | ||
d1807ad6 RVM |
188 | static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = { |
189 | .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 }, | |
190 | .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, | |
191 | .hiword_update = false, | |
192 | }; | |
193 | ||
36c6aada WAZ |
194 | static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = { |
195 | .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 }, | |
196 | .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, | |
197 | .support64b = { .reg = 0x4, .width = 1, .shift = 24 }, | |
198 | .hiword_update = false, | |
199 | }; | |
200 | ||
3ea4666e DA |
201 | /** |
202 | * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers | |
203 | * | |
4908460e MN |
204 | * @host: The sdhci_host |
205 | * @fld: The field to write to | |
206 | * @val: The value to write | |
207 | * | |
3ea4666e DA |
208 | * This function allows writing to fields in sdhci_arasan_soc_ctl_map. |
209 | * Note that if a field is specified as not available (shift < 0) then | |
210 | * this function will silently return an error code. It will be noisy | |
211 | * and print errors for any other (unexpected) errors. | |
212 | * | |
4908460e | 213 | * Return: 0 on success and error value on error |
3ea4666e DA |
214 | */ |
215 | static int sdhci_arasan_syscon_write(struct sdhci_host *host, | |
216 | const struct sdhci_arasan_soc_ctl_field *fld, | |
217 | u32 val) | |
218 | { | |
219 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
220 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
221 | struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; | |
222 | u32 reg = fld->reg; | |
223 | u16 width = fld->width; | |
224 | s16 shift = fld->shift; | |
225 | int ret; | |
226 | ||
227 | /* | |
228 | * Silently return errors for shift < 0 so caller doesn't have | |
229 | * to check for fields which are optional. For fields that | |
230 | * are required then caller needs to do something special | |
231 | * anyway. | |
232 | */ | |
233 | if (shift < 0) | |
234 | return -EINVAL; | |
235 | ||
236 | if (sdhci_arasan->soc_ctl_map->hiword_update) | |
237 | ret = regmap_write(soc_ctl_base, reg, | |
238 | HIWORD_UPDATE(val, GENMASK(width, 0), | |
239 | shift)); | |
240 | else | |
241 | ret = regmap_update_bits(soc_ctl_base, reg, | |
242 | GENMASK(shift + width, shift), | |
243 | val << shift); | |
244 | ||
245 | /* Yell about (unexpected) regmap errors */ | |
246 | if (ret) | |
247 | pr_warn("%s: Regmap write fail: %d\n", | |
248 | mmc_hostname(host->mmc), ret); | |
249 | ||
250 | return ret; | |
251 | } | |
252 | ||
802ac39a SL |
253 | static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) |
254 | { | |
255 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
256 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
f3dafc37 | 257 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; |
6fc09244 | 258 | bool ctrl_phy = false; |
802ac39a | 259 | |
b2db9c67 DA |
260 | if (!IS_ERR(sdhci_arasan->phy)) { |
261 | if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { | |
262 | /* | |
263 | * If PHY off, set clock to max speed and power PHY on. | |
264 | * | |
265 | * Although PHY docs apparently suggest power cycling | |
266 | * when changing the clock the PHY doesn't like to be | |
267 | * powered on while at low speeds like those used in ID | |
268 | * mode. Even worse is powering the PHY on while the | |
269 | * clock is off. | |
270 | * | |
271 | * To workaround the PHY limitations, the best we can | |
272 | * do is to power it on at a faster speed and then slam | |
273 | * through low speeds without power cycling. | |
274 | */ | |
275 | sdhci_set_clock(host, host->max_clk); | |
66bad6ed MN |
276 | if (phy_power_on(sdhci_arasan->phy)) { |
277 | pr_err("%s: Cannot power on phy.\n", | |
278 | mmc_hostname(host->mmc)); | |
279 | return; | |
280 | } | |
281 | ||
b2db9c67 DA |
282 | sdhci_arasan->is_phy_on = true; |
283 | ||
284 | /* | |
285 | * We'll now fall through to the below case with | |
286 | * ctrl_phy = false (so we won't turn off/on). The | |
287 | * sdhci_set_clock() will set the real clock. | |
288 | */ | |
289 | } else if (clock > PHY_CLK_TOO_SLOW_HZ) { | |
290 | /* | |
291 | * At higher clock speeds the PHY is fine being power | |
292 | * cycled and docs say you _should_ power cycle when | |
293 | * changing clock speeds. | |
294 | */ | |
295 | ctrl_phy = true; | |
296 | } | |
297 | } | |
802ac39a | 298 | |
b2db9c67 | 299 | if (ctrl_phy && sdhci_arasan->is_phy_on) { |
802ac39a | 300 | phy_power_off(sdhci_arasan->phy); |
b2db9c67 | 301 | sdhci_arasan->is_phy_on = false; |
802ac39a SL |
302 | } |
303 | ||
c0b4e411 MN |
304 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) { |
305 | /* | |
306 | * Some of the Arasan variations might not have timing | |
307 | * requirements met at 25MHz for Default Speed mode, | |
308 | * those controllers work at 19MHz instead. | |
309 | */ | |
310 | if (clock == DEFAULT_SPEED_MAX_DTR) | |
311 | clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25; | |
312 | } | |
313 | ||
f3dafc37 MN |
314 | /* Set the Input and Output Clock Phase Delays */ |
315 | if (clk_data->set_clk_delays) | |
316 | clk_data->set_clk_delays(host); | |
317 | ||
802ac39a SL |
318 | sdhci_set_clock(host, clock); |
319 | ||
3f2c7d5d HG |
320 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) |
321 | /* | |
322 | * Some controllers immediately report SDHCI_CLOCK_INT_STABLE | |
323 | * after enabling the clock even though the clock is not | |
324 | * stable. Trying to use a clock without waiting here results | |
325 | * in EILSEQ while detecting some older/slower cards. The | |
326 | * chosen delay is the maximum delay from sdhci_set_clock. | |
327 | */ | |
328 | msleep(20); | |
329 | ||
6fc09244 | 330 | if (ctrl_phy) { |
66bad6ed MN |
331 | if (phy_power_on(sdhci_arasan->phy)) { |
332 | pr_err("%s: Cannot power on phy.\n", | |
333 | mmc_hostname(host->mmc)); | |
334 | return; | |
335 | } | |
336 | ||
b2db9c67 | 337 | sdhci_arasan->is_phy_on = true; |
802ac39a SL |
338 | } |
339 | } | |
340 | ||
a05c8465 SL |
341 | static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, |
342 | struct mmc_ios *ios) | |
343 | { | |
344 | u32 vendor; | |
345 | struct sdhci_host *host = mmc_priv(mmc); | |
346 | ||
0daf72fe | 347 | vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); |
a05c8465 SL |
348 | if (ios->enhanced_strobe) |
349 | vendor |= VENDOR_ENHANCED_STROBE; | |
350 | else | |
351 | vendor &= ~VENDOR_ENHANCED_STROBE; | |
352 | ||
0daf72fe | 353 | sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); |
a05c8465 SL |
354 | } |
355 | ||
13d62fd2 | 356 | static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) |
3794c542 ZB |
357 | { |
358 | u8 ctrl; | |
359 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
360 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
361 | ||
362 | sdhci_reset(host, mask); | |
363 | ||
364 | if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { | |
365 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
366 | ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; | |
367 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
368 | } | |
369 | } | |
370 | ||
8a3bee9b SL |
371 | static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, |
372 | struct mmc_ios *ios) | |
373 | { | |
374 | switch (ios->signal_voltage) { | |
375 | case MMC_SIGNAL_VOLTAGE_180: | |
376 | /* | |
377 | * Plese don't switch to 1V8 as arasan,5.1 doesn't | |
378 | * actually refer to this setting to indicate the | |
379 | * signal voltage and the state machine will be broken | |
380 | * actually if we force to enable 1V8. That's something | |
381 | * like broken quirk but we could work around here. | |
382 | */ | |
383 | return 0; | |
384 | case MMC_SIGNAL_VOLTAGE_330: | |
385 | case MMC_SIGNAL_VOLTAGE_120: | |
386 | /* We don't support 3V3 and 1V2 */ | |
387 | break; | |
388 | } | |
389 | ||
390 | return -EINVAL; | |
391 | } | |
392 | ||
a81dae3a | 393 | static const struct sdhci_ops sdhci_arasan_ops = { |
802ac39a | 394 | .set_clock = sdhci_arasan_set_clock, |
e3ec3a3d | 395 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
8cc35289 | 396 | .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, |
2317f56c | 397 | .set_bus_width = sdhci_set_bus_width, |
3794c542 | 398 | .reset = sdhci_arasan_reset, |
96d7b78c | 399 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
c2c5252c | 400 | .set_power = sdhci_set_power_and_bus_voltage, |
e3ec3a3d SB |
401 | }; |
402 | ||
84362d79 SL |
403 | static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) |
404 | { | |
405 | int cmd_error = 0; | |
406 | int data_error = 0; | |
407 | ||
408 | if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) | |
409 | return intmask; | |
410 | ||
411 | cqhci_irq(host->mmc, intmask, cmd_error, data_error); | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
416 | static void sdhci_arasan_dumpregs(struct mmc_host *mmc) | |
417 | { | |
418 | sdhci_dumpregs(mmc_priv(mmc)); | |
419 | } | |
420 | ||
421 | static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) | |
422 | { | |
423 | struct sdhci_host *host = mmc_priv(mmc); | |
424 | u32 reg; | |
425 | ||
426 | reg = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
427 | while (reg & SDHCI_DATA_AVAILABLE) { | |
428 | sdhci_readl(host, SDHCI_BUFFER); | |
429 | reg = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
430 | } | |
431 | ||
432 | sdhci_cqe_enable(mmc); | |
433 | } | |
434 | ||
435 | static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { | |
436 | .enable = sdhci_arasan_cqe_enable, | |
437 | .disable = sdhci_cqe_disable, | |
438 | .dumpregs = sdhci_arasan_dumpregs, | |
439 | }; | |
440 | ||
441 | static const struct sdhci_ops sdhci_arasan_cqe_ops = { | |
442 | .set_clock = sdhci_arasan_set_clock, | |
443 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | |
444 | .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, | |
445 | .set_bus_width = sdhci_set_bus_width, | |
446 | .reset = sdhci_arasan_reset, | |
447 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
c2c5252c | 448 | .set_power = sdhci_set_power_and_bus_voltage, |
84362d79 SL |
449 | .irq = sdhci_arasan_cqhci_irq, |
450 | }; | |
451 | ||
452 | static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { | |
453 | .ops = &sdhci_arasan_cqe_ops, | |
454 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
455 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
456 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, | |
457 | }; | |
458 | ||
e3ec3a3d SB |
459 | #ifdef CONFIG_PM_SLEEP |
460 | /** | |
461 | * sdhci_arasan_suspend - Suspend method for the driver | |
462 | * @dev: Address of the device structure | |
e3ec3a3d SB |
463 | * |
464 | * Put the device in a low power state. | |
4908460e MN |
465 | * |
466 | * Return: 0 on success and error value on error | |
e3ec3a3d SB |
467 | */ |
468 | static int sdhci_arasan_suspend(struct device *dev) | |
469 | { | |
970f2d90 | 470 | struct sdhci_host *host = dev_get_drvdata(dev); |
e3ec3a3d | 471 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
89211418 | 472 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
473 | int ret; |
474 | ||
d38dcad4 AH |
475 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
476 | mmc_retune_needed(host->mmc); | |
477 | ||
84362d79 SL |
478 | if (sdhci_arasan->has_cqe) { |
479 | ret = cqhci_suspend(host->mmc); | |
480 | if (ret) | |
481 | return ret; | |
482 | } | |
483 | ||
e3ec3a3d SB |
484 | ret = sdhci_suspend_host(host); |
485 | if (ret) | |
486 | return ret; | |
487 | ||
b2db9c67 | 488 | if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { |
91aa3661 SL |
489 | ret = phy_power_off(sdhci_arasan->phy); |
490 | if (ret) { | |
491 | dev_err(dev, "Cannot power off phy.\n"); | |
66bad6ed MN |
492 | if (sdhci_resume_host(host)) |
493 | dev_err(dev, "Cannot resume host.\n"); | |
494 | ||
91aa3661 SL |
495 | return ret; |
496 | } | |
b2db9c67 | 497 | sdhci_arasan->is_phy_on = false; |
91aa3661 SL |
498 | } |
499 | ||
e3ec3a3d SB |
500 | clk_disable(pltfm_host->clk); |
501 | clk_disable(sdhci_arasan->clk_ahb); | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | /** | |
507 | * sdhci_arasan_resume - Resume method for the driver | |
508 | * @dev: Address of the device structure | |
e3ec3a3d SB |
509 | * |
510 | * Resume operation after suspend | |
4908460e MN |
511 | * |
512 | * Return: 0 on success and error value on error | |
e3ec3a3d SB |
513 | */ |
514 | static int sdhci_arasan_resume(struct device *dev) | |
515 | { | |
970f2d90 | 516 | struct sdhci_host *host = dev_get_drvdata(dev); |
e3ec3a3d | 517 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
89211418 | 518 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
519 | int ret; |
520 | ||
521 | ret = clk_enable(sdhci_arasan->clk_ahb); | |
522 | if (ret) { | |
523 | dev_err(dev, "Cannot enable AHB clock.\n"); | |
524 | return ret; | |
525 | } | |
526 | ||
527 | ret = clk_enable(pltfm_host->clk); | |
528 | if (ret) { | |
529 | dev_err(dev, "Cannot enable SD clock.\n"); | |
e3ec3a3d SB |
530 | return ret; |
531 | } | |
532 | ||
b2db9c67 | 533 | if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { |
91aa3661 SL |
534 | ret = phy_power_on(sdhci_arasan->phy); |
535 | if (ret) { | |
536 | dev_err(dev, "Cannot power on phy.\n"); | |
537 | return ret; | |
538 | } | |
b2db9c67 | 539 | sdhci_arasan->is_phy_on = true; |
91aa3661 SL |
540 | } |
541 | ||
84362d79 SL |
542 | ret = sdhci_resume_host(host); |
543 | if (ret) { | |
544 | dev_err(dev, "Cannot resume host.\n"); | |
545 | return ret; | |
546 | } | |
547 | ||
548 | if (sdhci_arasan->has_cqe) | |
549 | return cqhci_resume(host->mmc); | |
550 | ||
551 | return 0; | |
e3ec3a3d SB |
552 | } |
553 | #endif /* ! CONFIG_PM_SLEEP */ | |
554 | ||
555 | static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, | |
556 | sdhci_arasan_resume); | |
557 | ||
c390f211 DA |
558 | /** |
559 | * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate | |
560 | * | |
4908460e MN |
561 | * @hw: Pointer to the hardware clock structure. |
562 | * @parent_rate: The parent rate (should be rate of clk_xin). | |
563 | * | |
c390f211 DA |
564 | * Return the current actual rate of the SD card clock. This can be used |
565 | * to communicate with out PHY. | |
566 | * | |
4908460e | 567 | * Return: The card clock rate. |
c390f211 DA |
568 | */ |
569 | static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, | |
570 | unsigned long parent_rate) | |
c390f211 | 571 | { |
e1463618 MN |
572 | struct sdhci_arasan_clk_data *clk_data = |
573 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
c390f211 | 574 | struct sdhci_arasan_data *sdhci_arasan = |
e1463618 | 575 | container_of(clk_data, struct sdhci_arasan_data, clk_data); |
c390f211 DA |
576 | struct sdhci_host *host = sdhci_arasan->host; |
577 | ||
578 | return host->mmc->actual_clock; | |
579 | } | |
580 | ||
581 | static const struct clk_ops arasan_sdcardclk_ops = { | |
582 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
583 | }; | |
584 | ||
07a14d1d MN |
585 | /** |
586 | * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate | |
587 | * | |
4908460e MN |
588 | * @hw: Pointer to the hardware clock structure. |
589 | * @parent_rate: The parent rate (should be rate of clk_xin). | |
590 | * | |
07a14d1d MN |
591 | * Return the current actual rate of the sampling clock. This can be used |
592 | * to communicate with out PHY. | |
593 | * | |
4908460e | 594 | * Return: The sample clock rate. |
07a14d1d MN |
595 | */ |
596 | static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw, | |
597 | unsigned long parent_rate) | |
07a14d1d MN |
598 | { |
599 | struct sdhci_arasan_clk_data *clk_data = | |
600 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
601 | struct sdhci_arasan_data *sdhci_arasan = | |
602 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
603 | struct sdhci_host *host = sdhci_arasan->host; | |
604 | ||
605 | return host->mmc->actual_clock; | |
606 | } | |
607 | ||
608 | static const struct clk_ops arasan_sampleclk_ops = { | |
609 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
610 | }; | |
611 | ||
a5c8b2ae MN |
612 | /** |
613 | * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays | |
614 | * | |
4908460e MN |
615 | * @hw: Pointer to the hardware clock structure. |
616 | * @degrees: The clock phase shift between 0 - 359. | |
617 | * | |
a5c8b2ae MN |
618 | * Set the SD Output Clock Tap Delays for Output path |
619 | * | |
a5c8b2ae MN |
620 | * Return: 0 on success and error value on error |
621 | */ | |
622 | static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) | |
a5c8b2ae MN |
623 | { |
624 | struct sdhci_arasan_clk_data *clk_data = | |
625 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
626 | struct sdhci_arasan_data *sdhci_arasan = | |
627 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
628 | struct sdhci_host *host = sdhci_arasan->host; | |
a5c8b2ae MN |
629 | const char *clk_name = clk_hw_get_name(hw); |
630 | u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; | |
631 | u8 tap_delay, tap_max = 0; | |
632 | int ret; | |
633 | ||
9e953432 MN |
634 | /* This is applicable for SDHCI_SPEC_300 and above */ |
635 | if (host->version < SDHCI_SPEC_300) | |
a5c8b2ae MN |
636 | return 0; |
637 | ||
638 | switch (host->timing) { | |
639 | case MMC_TIMING_MMC_HS: | |
640 | case MMC_TIMING_SD_HS: | |
641 | case MMC_TIMING_UHS_SDR25: | |
642 | case MMC_TIMING_UHS_DDR50: | |
643 | case MMC_TIMING_MMC_DDR52: | |
644 | /* For 50MHz clock, 30 Taps are available */ | |
645 | tap_max = 30; | |
646 | break; | |
647 | case MMC_TIMING_UHS_SDR50: | |
648 | /* For 100MHz clock, 15 Taps are available */ | |
649 | tap_max = 15; | |
650 | break; | |
651 | case MMC_TIMING_UHS_SDR104: | |
652 | case MMC_TIMING_MMC_HS200: | |
653 | /* For 200MHz clock, 8 Taps are available */ | |
654 | tap_max = 8; | |
a3096ec6 | 655 | break; |
a5c8b2ae MN |
656 | default: |
657 | break; | |
658 | } | |
659 | ||
660 | tap_delay = (degrees * tap_max) / 360; | |
661 | ||
662 | /* Set the Clock Phase */ | |
426c8d85 | 663 | ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay); |
a5c8b2ae MN |
664 | if (ret) |
665 | pr_err("Error setting Output Tap Delay\n"); | |
666 | ||
d06d60d5 MN |
667 | /* Release DLL Reset */ |
668 | zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE); | |
669 | ||
a5c8b2ae MN |
670 | return ret; |
671 | } | |
672 | ||
673 | static const struct clk_ops zynqmp_sdcardclk_ops = { | |
674 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
675 | .set_phase = sdhci_zynqmp_sdcardclk_set_phase, | |
676 | }; | |
677 | ||
678 | /** | |
679 | * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays | |
680 | * | |
4908460e MN |
681 | * @hw: Pointer to the hardware clock structure. |
682 | * @degrees: The clock phase shift between 0 - 359. | |
683 | * | |
a5c8b2ae MN |
684 | * Set the SD Input Clock Tap Delays for Input path |
685 | * | |
a5c8b2ae MN |
686 | * Return: 0 on success and error value on error |
687 | */ | |
688 | static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) | |
a5c8b2ae MN |
689 | { |
690 | struct sdhci_arasan_clk_data *clk_data = | |
691 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
692 | struct sdhci_arasan_data *sdhci_arasan = | |
693 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
694 | struct sdhci_host *host = sdhci_arasan->host; | |
a5c8b2ae MN |
695 | const char *clk_name = clk_hw_get_name(hw); |
696 | u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1; | |
697 | u8 tap_delay, tap_max = 0; | |
698 | int ret; | |
699 | ||
9e953432 MN |
700 | /* This is applicable for SDHCI_SPEC_300 and above */ |
701 | if (host->version < SDHCI_SPEC_300) | |
a5c8b2ae MN |
702 | return 0; |
703 | ||
d06d60d5 MN |
704 | /* Assert DLL Reset */ |
705 | zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT); | |
706 | ||
a5c8b2ae MN |
707 | switch (host->timing) { |
708 | case MMC_TIMING_MMC_HS: | |
709 | case MMC_TIMING_SD_HS: | |
710 | case MMC_TIMING_UHS_SDR25: | |
711 | case MMC_TIMING_UHS_DDR50: | |
712 | case MMC_TIMING_MMC_DDR52: | |
713 | /* For 50MHz clock, 120 Taps are available */ | |
714 | tap_max = 120; | |
715 | break; | |
716 | case MMC_TIMING_UHS_SDR50: | |
717 | /* For 100MHz clock, 60 Taps are available */ | |
718 | tap_max = 60; | |
719 | break; | |
720 | case MMC_TIMING_UHS_SDR104: | |
721 | case MMC_TIMING_MMC_HS200: | |
722 | /* For 200MHz clock, 30 Taps are available */ | |
723 | tap_max = 30; | |
a3096ec6 | 724 | break; |
a5c8b2ae MN |
725 | default: |
726 | break; | |
727 | } | |
728 | ||
729 | tap_delay = (degrees * tap_max) / 360; | |
730 | ||
731 | /* Set the Clock Phase */ | |
426c8d85 | 732 | ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay); |
a5c8b2ae MN |
733 | if (ret) |
734 | pr_err("Error setting Input Tap Delay\n"); | |
735 | ||
736 | return ret; | |
737 | } | |
738 | ||
739 | static const struct clk_ops zynqmp_sampleclk_ops = { | |
740 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
741 | .set_phase = sdhci_zynqmp_sampleclk_set_phase, | |
742 | }; | |
743 | ||
1a470721 MN |
744 | /** |
745 | * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays | |
746 | * | |
4908460e MN |
747 | * @hw: Pointer to the hardware clock structure. |
748 | * @degrees: The clock phase shift between 0 - 359. | |
749 | * | |
1a470721 MN |
750 | * Set the SD Output Clock Tap Delays for Output path |
751 | * | |
1a470721 MN |
752 | * Return: 0 on success and error value on error |
753 | */ | |
754 | static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees) | |
755 | { | |
756 | struct sdhci_arasan_clk_data *clk_data = | |
757 | container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); | |
758 | struct sdhci_arasan_data *sdhci_arasan = | |
759 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
760 | struct sdhci_host *host = sdhci_arasan->host; | |
761 | u8 tap_delay, tap_max = 0; | |
1a470721 | 762 | |
9e953432 MN |
763 | /* This is applicable for SDHCI_SPEC_300 and above */ |
764 | if (host->version < SDHCI_SPEC_300) | |
1a470721 MN |
765 | return 0; |
766 | ||
767 | switch (host->timing) { | |
768 | case MMC_TIMING_MMC_HS: | |
769 | case MMC_TIMING_SD_HS: | |
770 | case MMC_TIMING_UHS_SDR25: | |
771 | case MMC_TIMING_UHS_DDR50: | |
772 | case MMC_TIMING_MMC_DDR52: | |
773 | /* For 50MHz clock, 30 Taps are available */ | |
774 | tap_max = 30; | |
775 | break; | |
776 | case MMC_TIMING_UHS_SDR50: | |
777 | /* For 100MHz clock, 15 Taps are available */ | |
778 | tap_max = 15; | |
779 | break; | |
780 | case MMC_TIMING_UHS_SDR104: | |
781 | case MMC_TIMING_MMC_HS200: | |
782 | /* For 200MHz clock, 8 Taps are available */ | |
783 | tap_max = 8; | |
a3096ec6 | 784 | break; |
1a470721 MN |
785 | default: |
786 | break; | |
787 | } | |
788 | ||
789 | tap_delay = (degrees * tap_max) / 360; | |
790 | ||
791 | /* Set the Clock Phase */ | |
792 | if (tap_delay) { | |
793 | u32 regval; | |
794 | ||
795 | regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); | |
796 | regval |= SDHCI_OTAPDLY_ENABLE; | |
797 | sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); | |
d338c6d0 | 798 | regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK; |
1a470721 MN |
799 | regval |= tap_delay; |
800 | sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); | |
801 | } | |
802 | ||
098c408b | 803 | return 0; |
1a470721 MN |
804 | } |
805 | ||
806 | static const struct clk_ops versal_sdcardclk_ops = { | |
807 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
808 | .set_phase = sdhci_versal_sdcardclk_set_phase, | |
809 | }; | |
810 | ||
811 | /** | |
812 | * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays | |
813 | * | |
4908460e MN |
814 | * @hw: Pointer to the hardware clock structure. |
815 | * @degrees: The clock phase shift between 0 - 359. | |
816 | * | |
1a470721 MN |
817 | * Set the SD Input Clock Tap Delays for Input path |
818 | * | |
1a470721 MN |
819 | * Return: 0 on success and error value on error |
820 | */ | |
821 | static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees) | |
822 | { | |
823 | struct sdhci_arasan_clk_data *clk_data = | |
824 | container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); | |
825 | struct sdhci_arasan_data *sdhci_arasan = | |
826 | container_of(clk_data, struct sdhci_arasan_data, clk_data); | |
827 | struct sdhci_host *host = sdhci_arasan->host; | |
828 | u8 tap_delay, tap_max = 0; | |
1a470721 | 829 | |
9e953432 MN |
830 | /* This is applicable for SDHCI_SPEC_300 and above */ |
831 | if (host->version < SDHCI_SPEC_300) | |
1a470721 MN |
832 | return 0; |
833 | ||
834 | switch (host->timing) { | |
835 | case MMC_TIMING_MMC_HS: | |
836 | case MMC_TIMING_SD_HS: | |
837 | case MMC_TIMING_UHS_SDR25: | |
838 | case MMC_TIMING_UHS_DDR50: | |
839 | case MMC_TIMING_MMC_DDR52: | |
840 | /* For 50MHz clock, 120 Taps are available */ | |
841 | tap_max = 120; | |
842 | break; | |
843 | case MMC_TIMING_UHS_SDR50: | |
844 | /* For 100MHz clock, 60 Taps are available */ | |
845 | tap_max = 60; | |
846 | break; | |
847 | case MMC_TIMING_UHS_SDR104: | |
848 | case MMC_TIMING_MMC_HS200: | |
849 | /* For 200MHz clock, 30 Taps are available */ | |
850 | tap_max = 30; | |
a3096ec6 | 851 | break; |
1a470721 MN |
852 | default: |
853 | break; | |
854 | } | |
855 | ||
856 | tap_delay = (degrees * tap_max) / 360; | |
857 | ||
858 | /* Set the Clock Phase */ | |
859 | if (tap_delay) { | |
860 | u32 regval; | |
861 | ||
862 | regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
863 | regval |= SDHCI_ITAPDLY_CHGWIN; | |
864 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
865 | regval |= SDHCI_ITAPDLY_ENABLE; | |
866 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
d338c6d0 | 867 | regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK; |
1a470721 MN |
868 | regval |= tap_delay; |
869 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
870 | regval &= ~SDHCI_ITAPDLY_CHGWIN; | |
871 | sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); | |
872 | } | |
873 | ||
098c408b | 874 | return 0; |
1a470721 MN |
875 | } |
876 | ||
877 | static const struct clk_ops versal_sampleclk_ops = { | |
878 | .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, | |
879 | .set_phase = sdhci_versal_sampleclk_set_phase, | |
880 | }; | |
881 | ||
8d2e3343 MN |
882 | static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) |
883 | { | |
8d2e3343 MN |
884 | u16 clk; |
885 | ||
886 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
887 | clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); | |
888 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
889 | ||
890 | /* Issue DLL Reset */ | |
426c8d85 | 891 | zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE); |
8d2e3343 MN |
892 | |
893 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
894 | ||
895 | sdhci_enable_clk(host, clk); | |
896 | } | |
897 | ||
898 | static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode) | |
899 | { | |
900 | struct sdhci_host *host = mmc_priv(mmc); | |
901 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
902 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
903 | struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; | |
904 | const char *clk_name = clk_hw_get_name(hw); | |
905 | u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : | |
906 | NODE_SD_1; | |
907 | int err; | |
908 | ||
256e4e4e MN |
909 | /* ZynqMP SD controller does not perform auto tuning in DDR50 mode */ |
910 | if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) | |
911 | return 0; | |
912 | ||
8d2e3343 MN |
913 | arasan_zynqmp_dll_reset(host, device_id); |
914 | ||
915 | err = sdhci_execute_tuning(mmc, opcode); | |
916 | if (err) | |
917 | return err; | |
918 | ||
919 | arasan_zynqmp_dll_reset(host, device_id); | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
b2ca77c9 SL |
924 | /** |
925 | * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier | |
926 | * | |
4908460e MN |
927 | * @host: The sdhci_host |
928 | * @value: The value to write | |
929 | * | |
b2ca77c9 SL |
930 | * The corecfg_clockmultiplier is supposed to contain clock multiplier |
931 | * value of programmable clock generator. | |
932 | * | |
933 | * NOTES: | |
934 | * - Many existing devices don't seem to do this and work fine. To keep | |
935 | * compatibility for old hardware where the device tree doesn't provide a | |
936 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
937 | * for this platform. | |
938 | * - The value of corecfg_clockmultiplier should sync with that of corresponding | |
939 | * value reading from sdhci_capability_register. So this function is called | |
940 | * once at probe time and never called again. | |
b2ca77c9 SL |
941 | */ |
942 | static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, | |
943 | u32 value) | |
944 | { | |
945 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
946 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
947 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
948 | sdhci_arasan->soc_ctl_map; | |
949 | ||
950 | /* Having a map is optional */ | |
951 | if (!soc_ctl_map) | |
952 | return; | |
953 | ||
954 | /* If we have a map, we expect to have a syscon */ | |
955 | if (!sdhci_arasan->soc_ctl_base) { | |
956 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
957 | mmc_hostname(host->mmc)); | |
958 | return; | |
959 | } | |
960 | ||
961 | sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); | |
962 | } | |
963 | ||
3ea4666e DA |
964 | /** |
965 | * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq | |
966 | * | |
4908460e MN |
967 | * @host: The sdhci_host |
968 | * | |
3ea4666e DA |
969 | * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This |
970 | * function can be used to make that happen. | |
971 | * | |
972 | * NOTES: | |
973 | * - Many existing devices don't seem to do this and work fine. To keep | |
974 | * compatibility for old hardware where the device tree doesn't provide a | |
975 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
976 | * for this platform. | |
977 | * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider | |
978 | * to achieve lower clock rates. That means that this function is called once | |
979 | * at probe time and never called again. | |
3ea4666e DA |
980 | */ |
981 | static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) | |
982 | { | |
983 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
984 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
985 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
986 | sdhci_arasan->soc_ctl_map; | |
987 | u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); | |
988 | ||
989 | /* Having a map is optional */ | |
990 | if (!soc_ctl_map) | |
991 | return; | |
992 | ||
993 | /* If we have a map, we expect to have a syscon */ | |
994 | if (!sdhci_arasan->soc_ctl_base) { | |
995 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
996 | mmc_hostname(host->mmc)); | |
997 | return; | |
998 | } | |
999 | ||
1000 | sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); | |
1001 | } | |
1002 | ||
f3dafc37 MN |
1003 | static void sdhci_arasan_set_clk_delays(struct sdhci_host *host) |
1004 | { | |
1005 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1006 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
1007 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; | |
1008 | ||
1009 | clk_set_phase(clk_data->sampleclk, | |
1010 | clk_data->clk_phase_in[host->timing]); | |
1011 | clk_set_phase(clk_data->sdcardclk, | |
1012 | clk_data->clk_phase_out[host->timing]); | |
1013 | } | |
1014 | ||
1015 | static void arasan_dt_read_clk_phase(struct device *dev, | |
1016 | struct sdhci_arasan_clk_data *clk_data, | |
1017 | unsigned int timing, const char *prop) | |
1018 | { | |
1019 | struct device_node *np = dev->of_node; | |
1020 | ||
1021 | int clk_phase[2] = {0}; | |
1022 | ||
1023 | /* | |
1024 | * Read Tap Delay values from DT, if the DT does not contain the | |
1025 | * Tap Values then use the pre-defined values. | |
1026 | */ | |
1027 | if (of_property_read_variable_u32_array(np, prop, &clk_phase[0], | |
1028 | 2, 0)) { | |
1029 | dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n", | |
1030 | prop, clk_data->clk_phase_in[timing], | |
1031 | clk_data->clk_phase_out[timing]); | |
1032 | return; | |
1033 | } | |
1034 | ||
1035 | /* The values read are Input and Output Clock Delays in order */ | |
1036 | clk_data->clk_phase_in[timing] = clk_phase[0]; | |
1037 | clk_data->clk_phase_out[timing] = clk_phase[1]; | |
1038 | } | |
1039 | ||
1040 | /** | |
1041 | * arasan_dt_parse_clk_phases - Read Clock Delay values from DT | |
1042 | * | |
f3dafc37 MN |
1043 | * @dev: Pointer to our struct device. |
1044 | * @clk_data: Pointer to the Clock Data structure | |
4908460e MN |
1045 | * |
1046 | * Called at initialization to parse the values of Clock Delays. | |
f3dafc37 MN |
1047 | */ |
1048 | static void arasan_dt_parse_clk_phases(struct device *dev, | |
1049 | struct sdhci_arasan_clk_data *clk_data) | |
1050 | { | |
a5c8b2ae MN |
1051 | u32 mio_bank = 0; |
1052 | int i; | |
1053 | ||
f3dafc37 MN |
1054 | /* |
1055 | * This has been kept as a pointer and is assigned a function here. | |
1056 | * So that different controller variants can assign their own handling | |
1057 | * function. | |
1058 | */ | |
1059 | clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; | |
1060 | ||
a5c8b2ae | 1061 | if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { |
88e1d0b1 MN |
1062 | u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = |
1063 | ZYNQMP_ICLK_PHASE; | |
1064 | u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = | |
1065 | ZYNQMP_OCLK_PHASE; | |
a5c8b2ae MN |
1066 | |
1067 | of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); | |
1068 | if (mio_bank == 2) { | |
88e1d0b1 MN |
1069 | zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90; |
1070 | zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90; | |
a5c8b2ae MN |
1071 | } |
1072 | ||
1073 | for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { | |
88e1d0b1 MN |
1074 | clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; |
1075 | clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; | |
a5c8b2ae MN |
1076 | } |
1077 | } | |
1078 | ||
1a470721 | 1079 | if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { |
88e1d0b1 MN |
1080 | u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = |
1081 | VERSAL_ICLK_PHASE; | |
1082 | u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = | |
1083 | VERSAL_OCLK_PHASE; | |
1a470721 MN |
1084 | |
1085 | for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { | |
88e1d0b1 MN |
1086 | clk_data->clk_phase_in[i] = versal_iclk_phase[i]; |
1087 | clk_data->clk_phase_out[i] = versal_oclk_phase[i]; | |
1a470721 MN |
1088 | } |
1089 | } | |
1090 | ||
f3dafc37 MN |
1091 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY, |
1092 | "clk-phase-legacy"); | |
1093 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS, | |
1094 | "clk-phase-mmc-hs"); | |
1095 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS, | |
1096 | "clk-phase-sd-hs"); | |
1097 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12, | |
1098 | "clk-phase-uhs-sdr12"); | |
1099 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25, | |
1100 | "clk-phase-uhs-sdr25"); | |
1101 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50, | |
1102 | "clk-phase-uhs-sdr50"); | |
1103 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104, | |
1104 | "clk-phase-uhs-sdr104"); | |
1105 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, | |
1106 | "clk-phase-uhs-ddr50"); | |
1107 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52, | |
1108 | "clk-phase-mmc-ddr52"); | |
1109 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200, | |
1110 | "clk-phase-mmc-hs200"); | |
1111 | arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400, | |
1112 | "clk-phase-mmc-hs400"); | |
1113 | } | |
1114 | ||
37d3ee7c MN |
1115 | static const struct sdhci_pltfm_data sdhci_arasan_pdata = { |
1116 | .ops = &sdhci_arasan_ops, | |
1117 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
1118 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1119 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1120 | SDHCI_QUIRK2_STOP_WITH_TC, | |
1121 | }; | |
1122 | ||
16ada730 MN |
1123 | static const struct sdhci_arasan_clk_ops arasan_clk_ops = { |
1124 | .sdcardclk_ops = &arasan_sdcardclk_ops, | |
1125 | .sampleclk_ops = &arasan_sampleclk_ops, | |
1126 | }; | |
1127 | ||
37d3ee7c MN |
1128 | static struct sdhci_arasan_of_data sdhci_arasan_generic_data = { |
1129 | .pdata = &sdhci_arasan_pdata, | |
16ada730 | 1130 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1131 | }; |
1132 | ||
36c6aada WAZ |
1133 | static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = { |
1134 | .ops = &sdhci_arasan_cqe_ops, | |
1135 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | |
1136 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | | |
1137 | SDHCI_QUIRK_NO_LED | | |
1138 | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1139 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
1140 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
1141 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1142 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1143 | SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | | |
1144 | SDHCI_QUIRK2_STOP_WITH_TC | | |
1145 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA, | |
1146 | }; | |
1147 | ||
1148 | static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = { | |
1149 | .ops = &sdhci_arasan_ops, | |
1150 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | |
1151 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | | |
1152 | SDHCI_QUIRK_NO_LED | | |
1153 | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1154 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
1155 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
1156 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1157 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1158 | SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | | |
1159 | SDHCI_QUIRK2_STOP_WITH_TC | | |
1160 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA, | |
1161 | }; | |
1162 | ||
1163 | static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = { | |
1164 | .ops = &sdhci_arasan_ops, | |
1165 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | |
1166 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | | |
1167 | SDHCI_QUIRK_NO_LED | | |
1168 | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1169 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
1170 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
1171 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1172 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1173 | SDHCI_QUIRK2_HOST_OFF_CARD_ON | | |
1174 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA, | |
1175 | }; | |
1176 | ||
37d3ee7c MN |
1177 | static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = { |
1178 | .soc_ctl_map = &rk3399_soc_ctl_map, | |
1179 | .pdata = &sdhci_arasan_cqe_pdata, | |
16ada730 | 1180 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1181 | }; |
1182 | ||
1183 | static struct sdhci_arasan_of_data intel_lgm_emmc_data = { | |
1184 | .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map, | |
1185 | .pdata = &sdhci_arasan_cqe_pdata, | |
16ada730 | 1186 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1187 | }; |
1188 | ||
1189 | static struct sdhci_arasan_of_data intel_lgm_sdxc_data = { | |
1190 | .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map, | |
1191 | .pdata = &sdhci_arasan_cqe_pdata, | |
16ada730 | 1192 | .clk_ops = &arasan_clk_ops, |
37d3ee7c MN |
1193 | }; |
1194 | ||
1195 | static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = { | |
1196 | .ops = &sdhci_arasan_ops, | |
1197 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
1198 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | | |
1199 | SDHCI_QUIRK2_STOP_WITH_TC, | |
1200 | }; | |
1201 | ||
16ada730 MN |
1202 | static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = { |
1203 | .sdcardclk_ops = &zynqmp_sdcardclk_ops, | |
1204 | .sampleclk_ops = &zynqmp_sampleclk_ops, | |
1205 | }; | |
1206 | ||
37d3ee7c MN |
1207 | static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = { |
1208 | .pdata = &sdhci_arasan_zynqmp_pdata, | |
16ada730 MN |
1209 | .clk_ops = &zynqmp_clk_ops, |
1210 | }; | |
1211 | ||
1212 | static const struct sdhci_arasan_clk_ops versal_clk_ops = { | |
1213 | .sdcardclk_ops = &versal_sdcardclk_ops, | |
1214 | .sampleclk_ops = &versal_sampleclk_ops, | |
37d3ee7c MN |
1215 | }; |
1216 | ||
1217 | static struct sdhci_arasan_of_data sdhci_arasan_versal_data = { | |
1218 | .pdata = &sdhci_arasan_zynqmp_pdata, | |
16ada730 | 1219 | .clk_ops = &versal_clk_ops, |
37d3ee7c MN |
1220 | }; |
1221 | ||
36c6aada WAZ |
1222 | static struct sdhci_arasan_of_data intel_keembay_emmc_data = { |
1223 | .soc_ctl_map = &intel_keembay_soc_ctl_map, | |
1224 | .pdata = &sdhci_keembay_emmc_pdata, | |
a42a7ec9 | 1225 | .clk_ops = &arasan_clk_ops, |
36c6aada WAZ |
1226 | }; |
1227 | ||
1228 | static struct sdhci_arasan_of_data intel_keembay_sd_data = { | |
1229 | .soc_ctl_map = &intel_keembay_soc_ctl_map, | |
1230 | .pdata = &sdhci_keembay_sd_pdata, | |
a42a7ec9 | 1231 | .clk_ops = &arasan_clk_ops, |
36c6aada WAZ |
1232 | }; |
1233 | ||
1234 | static struct sdhci_arasan_of_data intel_keembay_sdio_data = { | |
1235 | .soc_ctl_map = &intel_keembay_soc_ctl_map, | |
1236 | .pdata = &sdhci_keembay_sdio_pdata, | |
a42a7ec9 | 1237 | .clk_ops = &arasan_clk_ops, |
36c6aada WAZ |
1238 | }; |
1239 | ||
37d3ee7c MN |
1240 | static const struct of_device_id sdhci_arasan_of_match[] = { |
1241 | /* SoC-specific compatible strings w/ soc_ctl_map */ | |
1242 | { | |
1243 | .compatible = "rockchip,rk3399-sdhci-5.1", | |
1244 | .data = &sdhci_arasan_rk3399_data, | |
1245 | }, | |
1246 | { | |
1247 | .compatible = "intel,lgm-sdhci-5.1-emmc", | |
1248 | .data = &intel_lgm_emmc_data, | |
1249 | }, | |
1250 | { | |
1251 | .compatible = "intel,lgm-sdhci-5.1-sdxc", | |
1252 | .data = &intel_lgm_sdxc_data, | |
1253 | }, | |
36c6aada WAZ |
1254 | { |
1255 | .compatible = "intel,keembay-sdhci-5.1-emmc", | |
1256 | .data = &intel_keembay_emmc_data, | |
1257 | }, | |
1258 | { | |
1259 | .compatible = "intel,keembay-sdhci-5.1-sd", | |
1260 | .data = &intel_keembay_sd_data, | |
1261 | }, | |
1262 | { | |
1263 | .compatible = "intel,keembay-sdhci-5.1-sdio", | |
1264 | .data = &intel_keembay_sdio_data, | |
1265 | }, | |
37d3ee7c MN |
1266 | /* Generic compatible below here */ |
1267 | { | |
1268 | .compatible = "arasan,sdhci-8.9a", | |
1269 | .data = &sdhci_arasan_generic_data, | |
1270 | }, | |
1271 | { | |
1272 | .compatible = "arasan,sdhci-5.1", | |
1273 | .data = &sdhci_arasan_generic_data, | |
1274 | }, | |
1275 | { | |
1276 | .compatible = "arasan,sdhci-4.9a", | |
1277 | .data = &sdhci_arasan_generic_data, | |
1278 | }, | |
1279 | { | |
1280 | .compatible = "xlnx,zynqmp-8.9a", | |
1281 | .data = &sdhci_arasan_zynqmp_data, | |
1282 | }, | |
1283 | { | |
1284 | .compatible = "xlnx,versal-8.9a", | |
1285 | .data = &sdhci_arasan_versal_data, | |
1286 | }, | |
1287 | { /* sentinel */ } | |
1288 | }; | |
1289 | MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); | |
1290 | ||
c390f211 | 1291 | /** |
07a14d1d | 1292 | * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use |
c390f211 | 1293 | * |
4908460e MN |
1294 | * @sdhci_arasan: Our private data structure. |
1295 | * @clk_xin: Pointer to the functional clock | |
1296 | * @dev: Pointer to our struct device. | |
1297 | * | |
c390f211 DA |
1298 | * Some PHY devices need to know what the actual card clock is. In order for |
1299 | * them to find out, we'll provide a clock through the common clock framework | |
1300 | * for them to query. | |
1301 | * | |
4908460e | 1302 | * Return: 0 on success and error value on error |
c390f211 | 1303 | */ |
07a14d1d MN |
1304 | static int |
1305 | sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan, | |
1306 | struct clk *clk_xin, | |
1307 | struct device *dev) | |
c390f211 | 1308 | { |
e1463618 | 1309 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; |
c390f211 DA |
1310 | struct device_node *np = dev->of_node; |
1311 | struct clk_init_data sdcardclk_init; | |
1312 | const char *parent_clk_name; | |
1313 | int ret; | |
1314 | ||
c390f211 DA |
1315 | ret = of_property_read_string_index(np, "clock-output-names", 0, |
1316 | &sdcardclk_init.name); | |
1317 | if (ret) { | |
1318 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
1319 | return ret; | |
1320 | } | |
1321 | ||
1322 | parent_clk_name = __clk_get_name(clk_xin); | |
1323 | sdcardclk_init.parent_names = &parent_clk_name; | |
1324 | sdcardclk_init.num_parents = 1; | |
1325 | sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; | |
16ada730 | 1326 | sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops; |
c390f211 | 1327 | |
e1463618 MN |
1328 | clk_data->sdcardclk_hw.init = &sdcardclk_init; |
1329 | clk_data->sdcardclk = | |
1330 | devm_clk_register(dev, &clk_data->sdcardclk_hw); | |
c99e1d0c CY |
1331 | if (IS_ERR(clk_data->sdcardclk)) |
1332 | return PTR_ERR(clk_data->sdcardclk); | |
e1463618 | 1333 | clk_data->sdcardclk_hw.init = NULL; |
c390f211 DA |
1334 | |
1335 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
e1463618 | 1336 | clk_data->sdcardclk); |
c390f211 | 1337 | if (ret) |
07a14d1d MN |
1338 | dev_err(dev, "Failed to add sdcard clock provider\n"); |
1339 | ||
1340 | return ret; | |
1341 | } | |
1342 | ||
1343 | /** | |
1344 | * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use | |
1345 | * | |
4908460e MN |
1346 | * @sdhci_arasan: Our private data structure. |
1347 | * @clk_xin: Pointer to the functional clock | |
1348 | * @dev: Pointer to our struct device. | |
1349 | * | |
07a14d1d MN |
1350 | * Some PHY devices need to know what the actual card clock is. In order for |
1351 | * them to find out, we'll provide a clock through the common clock framework | |
1352 | * for them to query. | |
1353 | * | |
4908460e | 1354 | * Return: 0 on success and error value on error |
07a14d1d MN |
1355 | */ |
1356 | static int | |
1357 | sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan, | |
1358 | struct clk *clk_xin, | |
1359 | struct device *dev) | |
1360 | { | |
1361 | struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; | |
1362 | struct device_node *np = dev->of_node; | |
1363 | struct clk_init_data sampleclk_init; | |
1364 | const char *parent_clk_name; | |
1365 | int ret; | |
1366 | ||
1367 | ret = of_property_read_string_index(np, "clock-output-names", 1, | |
1368 | &sampleclk_init.name); | |
1369 | if (ret) { | |
1370 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
1371 | return ret; | |
1372 | } | |
1373 | ||
1374 | parent_clk_name = __clk_get_name(clk_xin); | |
1375 | sampleclk_init.parent_names = &parent_clk_name; | |
1376 | sampleclk_init.num_parents = 1; | |
1377 | sampleclk_init.flags = CLK_GET_RATE_NOCACHE; | |
16ada730 | 1378 | sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops; |
07a14d1d MN |
1379 | |
1380 | clk_data->sampleclk_hw.init = &sampleclk_init; | |
1381 | clk_data->sampleclk = | |
1382 | devm_clk_register(dev, &clk_data->sampleclk_hw); | |
c99e1d0c CY |
1383 | if (IS_ERR(clk_data->sampleclk)) |
1384 | return PTR_ERR(clk_data->sampleclk); | |
07a14d1d MN |
1385 | clk_data->sampleclk_hw.init = NULL; |
1386 | ||
1387 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
1388 | clk_data->sampleclk); | |
1389 | if (ret) | |
1390 | dev_err(dev, "Failed to add sample clock provider\n"); | |
c390f211 DA |
1391 | |
1392 | return ret; | |
1393 | } | |
1394 | ||
1395 | /** | |
1396 | * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() | |
1397 | * | |
4908460e MN |
1398 | * @dev: Pointer to our struct device. |
1399 | * | |
c390f211 DA |
1400 | * Should be called any time we're exiting and sdhci_arasan_register_sdclk() |
1401 | * returned success. | |
c390f211 DA |
1402 | */ |
1403 | static void sdhci_arasan_unregister_sdclk(struct device *dev) | |
1404 | { | |
1405 | struct device_node *np = dev->of_node; | |
1406 | ||
1407 | if (!of_find_property(np, "#clock-cells", NULL)) | |
1408 | return; | |
1409 | ||
1410 | of_clk_del_provider(dev->of_node); | |
1411 | } | |
1412 | ||
36c6aada WAZ |
1413 | /** |
1414 | * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support) | |
973c7c99 MHZ |
1415 | * @host: The sdhci_host |
1416 | * @value: The value to write | |
36c6aada WAZ |
1417 | * |
1418 | * This should be set based on the System Address Bus. | |
1419 | * 0: the Core supports only 32-bit System Address Bus. | |
1420 | * 1: the Core supports 64-bit System Address Bus. | |
1421 | * | |
973c7c99 MHZ |
1422 | * NOTE: |
1423 | * For Keem Bay, it is required to clear this bit. Its default value is 1'b1. | |
1424 | * Keem Bay does not support 64-bit access. | |
36c6aada WAZ |
1425 | */ |
1426 | static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value) | |
1427 | { | |
1428 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1429 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
db845093 | 1430 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; |
36c6aada WAZ |
1431 | |
1432 | /* Having a map is optional */ | |
db845093 | 1433 | soc_ctl_map = sdhci_arasan->soc_ctl_map; |
36c6aada WAZ |
1434 | if (!soc_ctl_map) |
1435 | return; | |
1436 | ||
1437 | /* If we have a map, we expect to have a syscon */ | |
1438 | if (!sdhci_arasan->soc_ctl_base) { | |
1439 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
1440 | mmc_hostname(host->mmc)); | |
1441 | return; | |
1442 | } | |
1443 | ||
1444 | sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value); | |
1445 | } | |
1446 | ||
07a14d1d MN |
1447 | /** |
1448 | * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use | |
1449 | * | |
4908460e MN |
1450 | * @sdhci_arasan: Our private data structure. |
1451 | * @clk_xin: Pointer to the functional clock | |
1452 | * @dev: Pointer to our struct device. | |
1453 | * | |
07a14d1d MN |
1454 | * Some PHY devices need to know what the actual card clock is. In order for |
1455 | * them to find out, we'll provide a clock through the common clock framework | |
1456 | * for them to query. | |
1457 | * | |
1458 | * Note: without seriously re-architecting SDHCI's clock code and testing on | |
1459 | * all platforms, there's no way to create a totally beautiful clock here | |
1460 | * with all clock ops implemented. Instead, we'll just create a clock that can | |
1461 | * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock | |
1462 | * framework that we're doing things behind its back. This should be sufficient | |
1463 | * to create nice clean device tree bindings and later (if needed) we can try | |
1464 | * re-architecting SDHCI if we see some benefit to it. | |
1465 | * | |
4908460e | 1466 | * Return: 0 on success and error value on error |
07a14d1d MN |
1467 | */ |
1468 | static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, | |
1469 | struct clk *clk_xin, | |
1470 | struct device *dev) | |
1471 | { | |
1472 | struct device_node *np = dev->of_node; | |
1473 | u32 num_clks = 0; | |
1474 | int ret; | |
1475 | ||
1476 | /* Providing a clock to the PHY is optional; no error if missing */ | |
1477 | if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) | |
1478 | return 0; | |
1479 | ||
1480 | ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev); | |
1481 | if (ret) | |
1482 | return ret; | |
1483 | ||
1484 | if (num_clks) { | |
1485 | ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin, | |
1486 | dev); | |
1487 | if (ret) { | |
1488 | sdhci_arasan_unregister_sdclk(dev); | |
1489 | return ret; | |
1490 | } | |
1491 | } | |
1492 | ||
1493 | return 0; | |
1494 | } | |
1495 | ||
84362d79 SL |
1496 | static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) |
1497 | { | |
1498 | struct sdhci_host *host = sdhci_arasan->host; | |
1499 | struct cqhci_host *cq_host; | |
1500 | bool dma64; | |
1501 | int ret; | |
1502 | ||
1503 | if (!sdhci_arasan->has_cqe) | |
1504 | return sdhci_add_host(host); | |
1505 | ||
1506 | ret = sdhci_setup_host(host); | |
1507 | if (ret) | |
1508 | return ret; | |
1509 | ||
1510 | cq_host = devm_kzalloc(host->mmc->parent, | |
1511 | sizeof(*cq_host), GFP_KERNEL); | |
1512 | if (!cq_host) { | |
1513 | ret = -ENOMEM; | |
1514 | goto cleanup; | |
1515 | } | |
1516 | ||
1517 | cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; | |
1518 | cq_host->ops = &sdhci_arasan_cqhci_ops; | |
1519 | ||
1520 | dma64 = host->flags & SDHCI_USE_64_BIT_DMA; | |
1521 | if (dma64) | |
1522 | cq_host->caps |= CQHCI_TASK_DESC_SZ_128; | |
1523 | ||
1524 | ret = cqhci_init(cq_host, host->mmc, dma64); | |
1525 | if (ret) | |
1526 | goto cleanup; | |
1527 | ||
1528 | ret = __sdhci_add_host(host); | |
1529 | if (ret) | |
1530 | goto cleanup; | |
1531 | ||
1532 | return 0; | |
1533 | ||
1534 | cleanup: | |
1535 | sdhci_cleanup_host(host); | |
1536 | return ret; | |
1537 | } | |
1538 | ||
e3ec3a3d SB |
1539 | static int sdhci_arasan_probe(struct platform_device *pdev) |
1540 | { | |
1541 | int ret; | |
3ea4666e | 1542 | struct device_node *node; |
e3ec3a3d SB |
1543 | struct clk *clk_xin; |
1544 | struct sdhci_host *host; | |
1545 | struct sdhci_pltfm_host *pltfm_host; | |
2ff0b85d MHZ |
1546 | struct device *dev = &pdev->dev; |
1547 | struct device_node *np = dev->of_node; | |
e3ec3a3d | 1548 | struct sdhci_arasan_data *sdhci_arasan; |
06b23ca0 | 1549 | const struct sdhci_arasan_of_data *data; |
84362d79 | 1550 | |
2ff0b85d | 1551 | data = of_device_get_match_data(dev); |
06b23ca0 | 1552 | host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); |
e3ec3a3d | 1553 | |
89211418 JZ |
1554 | if (IS_ERR(host)) |
1555 | return PTR_ERR(host); | |
1556 | ||
1557 | pltfm_host = sdhci_priv(host); | |
1558 | sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
c390f211 | 1559 | sdhci_arasan->host = host; |
e3ec3a3d | 1560 | |
06b23ca0 | 1561 | sdhci_arasan->soc_ctl_map = data->soc_ctl_map; |
16ada730 | 1562 | sdhci_arasan->clk_ops = data->clk_ops; |
3ea4666e | 1563 | |
80d41efe | 1564 | node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0); |
3ea4666e DA |
1565 | if (node) { |
1566 | sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); | |
1567 | of_node_put(node); | |
1568 | ||
1569 | if (IS_ERR(sdhci_arasan->soc_ctl_base)) { | |
2ff0b85d | 1570 | ret = dev_err_probe(dev, |
72ea817d KK |
1571 | PTR_ERR(sdhci_arasan->soc_ctl_base), |
1572 | "Can't get syscon\n"); | |
3ea4666e DA |
1573 | goto err_pltfm_free; |
1574 | } | |
1575 | } | |
1576 | ||
b2af3227 R |
1577 | sdhci_get_of_property(pdev); |
1578 | ||
2ff0b85d | 1579 | sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb"); |
e3ec3a3d | 1580 | if (IS_ERR(sdhci_arasan->clk_ahb)) { |
ffd68f35 MHZ |
1581 | ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb), |
1582 | "clk_ahb clock not found.\n"); | |
278d0962 | 1583 | goto err_pltfm_free; |
e3ec3a3d SB |
1584 | } |
1585 | ||
2ff0b85d | 1586 | clk_xin = devm_clk_get(dev, "clk_xin"); |
e3ec3a3d | 1587 | if (IS_ERR(clk_xin)) { |
ffd68f35 | 1588 | ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n"); |
278d0962 | 1589 | goto err_pltfm_free; |
e3ec3a3d SB |
1590 | } |
1591 | ||
1592 | ret = clk_prepare_enable(sdhci_arasan->clk_ahb); | |
1593 | if (ret) { | |
2ff0b85d | 1594 | dev_err(dev, "Unable to enable AHB clock.\n"); |
278d0962 | 1595 | goto err_pltfm_free; |
e3ec3a3d SB |
1596 | } |
1597 | ||
b2af3227 R |
1598 | /* If clock-frequency property is set, use the provided value */ |
1599 | if (pltfm_host->clock && | |
1600 | pltfm_host->clock != clk_get_rate(clk_xin)) { | |
1601 | ret = clk_set_rate(clk_xin, pltfm_host->clock); | |
1602 | if (ret) { | |
1603 | dev_err(&pdev->dev, "Failed to set SD clock rate\n"); | |
1604 | goto clk_dis_ahb; | |
1605 | } | |
1606 | } | |
1607 | ||
e3ec3a3d SB |
1608 | ret = clk_prepare_enable(clk_xin); |
1609 | if (ret) { | |
2ff0b85d | 1610 | dev_err(dev, "Unable to enable SD clock.\n"); |
e3ec3a3d SB |
1611 | goto clk_dis_ahb; |
1612 | } | |
1613 | ||
3794c542 ZB |
1614 | if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) |
1615 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; | |
1616 | ||
3f2c7d5d HG |
1617 | if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) |
1618 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; | |
1619 | ||
e3ec3a3d SB |
1620 | pltfm_host->clk = clk_xin; |
1621 | ||
80d41efe | 1622 | if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1")) |
b2ca77c9 SL |
1623 | sdhci_arasan_update_clockmultiplier(host, 0x0); |
1624 | ||
36c6aada WAZ |
1625 | if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || |
1626 | of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || | |
1627 | of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { | |
1628 | sdhci_arasan_update_clockmultiplier(host, 0x0); | |
1629 | sdhci_arasan_update_support64b(host, 0x0); | |
1630 | ||
1631 | host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; | |
1632 | } | |
1633 | ||
3ea4666e DA |
1634 | sdhci_arasan_update_baseclkfreq(host); |
1635 | ||
2ff0b85d | 1636 | ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev); |
c390f211 DA |
1637 | if (ret) |
1638 | goto clk_disable_all; | |
1639 | ||
a5c8b2ae | 1640 | if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { |
8d2e3343 MN |
1641 | host->mmc_host_ops.execute_tuning = |
1642 | arasan_zynqmp_execute_tuning; | |
c0b4e411 MN |
1643 | |
1644 | sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN; | |
25a91664 | 1645 | host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; |
a5c8b2ae MN |
1646 | } |
1647 | ||
2ff0b85d | 1648 | arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data); |
f3dafc37 | 1649 | |
16b23787 MS |
1650 | ret = mmc_of_parse(host->mmc); |
1651 | if (ret) { | |
ffd68f35 | 1652 | ret = dev_err_probe(dev, ret, "parsing dt failed.\n"); |
c390f211 | 1653 | goto unreg_clk; |
16b23787 MS |
1654 | } |
1655 | ||
91aa3661 | 1656 | sdhci_arasan->phy = ERR_PTR(-ENODEV); |
80d41efe | 1657 | if (of_device_is_compatible(np, "arasan,sdhci-5.1")) { |
2ff0b85d | 1658 | sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan"); |
91aa3661 | 1659 | if (IS_ERR(sdhci_arasan->phy)) { |
ffd68f35 MHZ |
1660 | ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy), |
1661 | "No phy for arasan,sdhci-5.1.\n"); | |
c390f211 | 1662 | goto unreg_clk; |
91aa3661 SL |
1663 | } |
1664 | ||
1665 | ret = phy_init(sdhci_arasan->phy); | |
1666 | if (ret < 0) { | |
2ff0b85d | 1667 | dev_err(dev, "phy_init err.\n"); |
c390f211 | 1668 | goto unreg_clk; |
91aa3661 SL |
1669 | } |
1670 | ||
a05c8465 SL |
1671 | host->mmc_host_ops.hs400_enhanced_strobe = |
1672 | sdhci_arasan_hs400_enhanced_strobe; | |
8a3bee9b SL |
1673 | host->mmc_host_ops.start_signal_voltage_switch = |
1674 | sdhci_arasan_voltage_switch; | |
84362d79 | 1675 | sdhci_arasan->has_cqe = true; |
7bda9482 CM |
1676 | host->mmc->caps2 |= MMC_CAP2_CQE; |
1677 | ||
1678 | if (!of_property_read_bool(np, "disable-cqe-dcmd")) | |
1679 | host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; | |
91aa3661 SL |
1680 | } |
1681 | ||
84362d79 | 1682 | ret = sdhci_arasan_add_host(sdhci_arasan); |
b1df9de7 | 1683 | if (ret) |
91aa3661 | 1684 | goto err_add_host; |
e3ec3a3d SB |
1685 | |
1686 | return 0; | |
1687 | ||
91aa3661 | 1688 | err_add_host: |
91aa3661 SL |
1689 | if (!IS_ERR(sdhci_arasan->phy)) |
1690 | phy_exit(sdhci_arasan->phy); | |
c390f211 | 1691 | unreg_clk: |
2ff0b85d | 1692 | sdhci_arasan_unregister_sdclk(dev); |
e3ec3a3d SB |
1693 | clk_disable_all: |
1694 | clk_disable_unprepare(clk_xin); | |
1695 | clk_dis_ahb: | |
1696 | clk_disable_unprepare(sdhci_arasan->clk_ahb); | |
278d0962 SL |
1697 | err_pltfm_free: |
1698 | sdhci_pltfm_free(pdev); | |
e3ec3a3d SB |
1699 | return ret; |
1700 | } | |
1701 | ||
1702 | static int sdhci_arasan_remove(struct platform_device *pdev) | |
1703 | { | |
0c7fe32e | 1704 | int ret; |
e3ec3a3d SB |
1705 | struct sdhci_host *host = platform_get_drvdata(pdev); |
1706 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 JZ |
1707 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
1708 | struct clk *clk_ahb = sdhci_arasan->clk_ahb; | |
e3ec3a3d | 1709 | |
91aa3661 | 1710 | if (!IS_ERR(sdhci_arasan->phy)) { |
b2db9c67 DA |
1711 | if (sdhci_arasan->is_phy_on) |
1712 | phy_power_off(sdhci_arasan->phy); | |
91aa3661 SL |
1713 | phy_exit(sdhci_arasan->phy); |
1714 | } | |
1715 | ||
c390f211 DA |
1716 | sdhci_arasan_unregister_sdclk(&pdev->dev); |
1717 | ||
0c7fe32e JZ |
1718 | ret = sdhci_pltfm_unregister(pdev); |
1719 | ||
89211418 | 1720 | clk_disable_unprepare(clk_ahb); |
e3ec3a3d | 1721 | |
0c7fe32e | 1722 | return ret; |
e3ec3a3d SB |
1723 | } |
1724 | ||
e3ec3a3d SB |
1725 | static struct platform_driver sdhci_arasan_driver = { |
1726 | .driver = { | |
1727 | .name = "sdhci-arasan", | |
21b2cec6 | 1728 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
e3ec3a3d SB |
1729 | .of_match_table = sdhci_arasan_of_match, |
1730 | .pm = &sdhci_arasan_dev_pm_ops, | |
1731 | }, | |
1732 | .probe = sdhci_arasan_probe, | |
1733 | .remove = sdhci_arasan_remove, | |
1734 | }; | |
1735 | ||
1736 | module_platform_driver(sdhci_arasan_driver); | |
1737 | ||
1738 | MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); | |
1739 | MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); | |
1740 | MODULE_LICENSE("GPL"); |