projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
dt-bindings: sdhci-msm: Add xo value
[linux-2.6-block.git] / drivers / mmc / host / sdhci-msm.c
CommitLineData
0eb0d9f4
GD		 1/*
2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
3 *
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/of_device.h>
0eb0d9f4 19#include <linux/delay.h>
415b5a75 20#include <linux/mmc/mmc.h>
67e6db11 21#include <linux/pm_runtime.h>
415b5a75 22#include <linux/slab.h>
0eb0d9f4
GD		 23
24#include "sdhci-pltfm.h"
25
3a3ad3e9
GD		 26#define CORE_MCI_VERSION 0x50
27#define CORE_VERSION_MAJOR_SHIFT 28
28#define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
29#define CORE_VERSION_MINOR_MASK 0xff
30
0eb0d9f4
GD		 31#define CORE_HC_MODE 0x78
32#define HC_MODE_EN 0x1
33#define CORE_POWER 0x0
34#define CORE_SW_RST BIT(7)
35
ad81d387
GD		 36#define CORE_PWRCTL_STATUS 0xdc
37#define CORE_PWRCTL_MASK 0xe0
38#define CORE_PWRCTL_CLEAR 0xe4
39#define CORE_PWRCTL_CTL 0xe8
40#define CORE_PWRCTL_BUS_OFF BIT(0)
41#define CORE_PWRCTL_BUS_ON BIT(1)
42#define CORE_PWRCTL_IO_LOW BIT(2)
43#define CORE_PWRCTL_IO_HIGH BIT(3)
44#define CORE_PWRCTL_BUS_SUCCESS BIT(0)
45#define CORE_PWRCTL_IO_SUCCESS BIT(2)
46#define REQ_BUS_OFF BIT(0)
47#define REQ_BUS_ON BIT(1)
48#define REQ_IO_LOW BIT(2)
49#define REQ_IO_HIGH BIT(3)
50#define INT_MASK 0xf
415b5a75
GD		 51#define MAX_PHASES 16
52#define CORE_DLL_LOCK BIT(7)
53#define CORE_DLL_EN BIT(16)
54#define CORE_CDR_EN BIT(17)
55#define CORE_CK_OUT_EN BIT(18)
56#define CORE_CDR_EXT_EN BIT(19)
57#define CORE_DLL_PDN BIT(29)
58#define CORE_DLL_RST BIT(30)
59#define CORE_DLL_CONFIG 0x100
60#define CORE_DLL_STATUS 0x108
61
62#define CORE_VENDOR_SPEC 0x10c
63#define CORE_CLK_PWRSAVE BIT(1)
64
3a3ad3e9
GD		 65#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
66
415b5a75
GD		 67#define CDR_SELEXT_SHIFT 20
68#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
69#define CMUX_SHIFT_PHASE_SHIFT 24
70#define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
71
67e6db11 72#define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
0eb0d9f4
GD		 73struct sdhci_msm_host {
74 struct platform_device *pdev;
75 void __iomem *core_mem; /* MSM SDCC mapped address */
ad81d387 76 int pwr_irq; /* power irq */
0eb0d9f4
GD		 77 struct clk *clk; /* main SD/MMC bus clock */
78 struct clk *pclk; /* SDHC peripheral bus clock */
79 struct clk *bus_clk; /* SDHC bus voter clock */
80 struct mmc_host *mmc;
0eb0d9f4
GD		 81};
82
83/* Platform specific tuning */
415b5a75
GD		 84static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
85{
86 u32 wait_cnt = 50;
87 u8 ck_out_en;
88 struct mmc_host *mmc = host->mmc;
89
90 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
91 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
92 CORE_CK_OUT_EN);
93
94 while (ck_out_en != poll) {
95 if (--wait_cnt == 0) {
96 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
97 mmc_hostname(mmc), poll);
98 return -ETIMEDOUT;
99 }
100 udelay(1);
101
102 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
103 CORE_CK_OUT_EN);
104 }
105
106 return 0;
107}
108
109static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
110{
111 int rc;
112 static const u8 grey_coded_phase_table[] = {
113 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
114 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
115 };
116 unsigned long flags;
117 u32 config;
118 struct mmc_host *mmc = host->mmc;
119
120 spin_lock_irqsave(&host->lock, flags);
121
122 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
123 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
124 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
125 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
126
127 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
128 rc = msm_dll_poll_ck_out_en(host, 0);
129 if (rc)
130 goto err_out;
131
132 /*
133 * Write the selected DLL clock output phase (0 ... 15)
134 * to CDR_SELEXT bit field of DLL_CONFIG register.
135 */
136 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
137 config &= ~CDR_SELEXT_MASK;
138 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
139 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
140
29301f40
RH		 141 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
142 config |= CORE_CK_OUT_EN;
143 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75
GD		 144
145 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
146 rc = msm_dll_poll_ck_out_en(host, 1);
147 if (rc)
148 goto err_out;
149
150 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
151 config |= CORE_CDR_EN;
152 config &= ~CORE_CDR_EXT_EN;
153 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
154 goto out;
155
156err_out:
157 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
158 mmc_hostname(mmc), phase);
159out:
160 spin_unlock_irqrestore(&host->lock, flags);
161 return rc;
162}
163
164/*
165 * Find out the greatest range of consecuitive selected
166 * DLL clock output phases that can be used as sampling
167 * setting for SD3.0 UHS-I card read operation (in SDR104
168 * timing mode) or for eMMC4.5 card read operation (in HS200
169 * timing mode).
170 * Select the 3/4 of the range and configure the DLL with the
171 * selected DLL clock output phase.
172 */
173
174static int msm_find_most_appropriate_phase(struct sdhci_host *host,
175 u8 *phase_table, u8 total_phases)
176{
177 int ret;
178 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
179 u8 phases_per_row[MAX_PHASES] = { 0 };
180 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
181 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
182 bool phase_0_found = false, phase_15_found = false;
183 struct mmc_host *mmc = host->mmc;
184
185 if (!total_phases || (total_phases > MAX_PHASES)) {
186 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
187 mmc_hostname(mmc), total_phases);
188 return -EINVAL;
189 }
190
191 for (cnt = 0; cnt < total_phases; cnt++) {
192 ranges[row_index][col_index] = phase_table[cnt];
193 phases_per_row[row_index] += 1;
194 col_index++;
195
196 if ((cnt + 1) == total_phases) {
197 continue;
198 /* check if next phase in phase_table is consecutive or not */
199 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
200 row_index++;
201 col_index = 0;
202 }
203 }
204
205 if (row_index >= MAX_PHASES)
206 return -EINVAL;
207
208 /* Check if phase-0 is present in first valid window? */
209 if (!ranges[0][0]) {
210 phase_0_found = true;
211 phase_0_raw_index = 0;
212 /* Check if cycle exist between 2 valid windows */
213 for (cnt = 1; cnt <= row_index; cnt++) {
214 if (phases_per_row[cnt]) {
215 for (i = 0; i < phases_per_row[cnt]; i++) {
216 if (ranges[cnt][i] == 15) {
217 phase_15_found = true;
218 phase_15_raw_index = cnt;
219 break;
220 }
221 }
222 }
223 }
224 }
225
226 /* If 2 valid windows form cycle then merge them as single window */
227 if (phase_0_found && phase_15_found) {
228 /* number of phases in raw where phase 0 is present */
229 u8 phases_0 = phases_per_row[phase_0_raw_index];
230 /* number of phases in raw where phase 15 is present */
231 u8 phases_15 = phases_per_row[phase_15_raw_index];
232
233 if (phases_0 + phases_15 >= MAX_PHASES)
234 /*
235 * If there are more than 1 phase windows then total
236 * number of phases in both the windows should not be
237 * more than or equal to MAX_PHASES.
238 */
239 return -EINVAL;
240
241 /* Merge 2 cyclic windows */
242 i = phases_15;
243 for (cnt = 0; cnt < phases_0; cnt++) {
244 ranges[phase_15_raw_index][i] =
245 ranges[phase_0_raw_index][cnt];
246 if (++i >= MAX_PHASES)
247 break;
248 }
249
250 phases_per_row[phase_0_raw_index] = 0;
251 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
252 }
253
254 for (cnt = 0; cnt <= row_index; cnt++) {
255 if (phases_per_row[cnt] > curr_max) {
256 curr_max = phases_per_row[cnt];
257 selected_row_index = cnt;
258 }
259 }
260
261 i = (curr_max * 3) / 4;
262 if (i)
263 i--;
264
265 ret = ranges[selected_row_index][i];
266
267 if (ret >= MAX_PHASES) {
268 ret = -EINVAL;
269 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
270 mmc_hostname(mmc), ret);
271 }
272
273 return ret;
274}
275
276static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
0eb0d9f4 277{
415b5a75
GD		 278 u32 mclk_freq = 0, config;
279
280 /* Program the MCLK value to MCLK_FREQ bit field */
281 if (host->clock <= 112000000)
282 mclk_freq = 0;
283 else if (host->clock <= 125000000)
284 mclk_freq = 1;
285 else if (host->clock <= 137000000)
286 mclk_freq = 2;
287 else if (host->clock <= 150000000)
288 mclk_freq = 3;
289 else if (host->clock <= 162000000)
290 mclk_freq = 4;
291 else if (host->clock <= 175000000)
292 mclk_freq = 5;
293 else if (host->clock <= 187000000)
294 mclk_freq = 6;
295 else if (host->clock <= 200000000)
296 mclk_freq = 7;
297
298 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
299 config &= ~CMUX_SHIFT_PHASE_MASK;
300 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
301 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
302}
303
304/* Initialize the DLL (Programmable Delay Line) */
305static int msm_init_cm_dll(struct sdhci_host *host)
306{
307 struct mmc_host *mmc = host->mmc;
308 int wait_cnt = 50;
309 unsigned long flags;
29301f40 310 u32 config;
415b5a75
GD		 311
312 spin_lock_irqsave(&host->lock, flags);
313
0eb0d9f4 314 /*
415b5a75
GD		 315 * Make sure that clock is always enabled when DLL
316 * tuning is in progress. Keeping PWRSAVE ON may
317 * turn off the clock.
0eb0d9f4 318 */
29301f40
RH		 319 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
320 config &= ~CORE_CLK_PWRSAVE;
321 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
415b5a75 322
29301f40
RH		 323 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
324 config |= CORE_DLL_RST;
325 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75 326
29301f40
RH		 327 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
328 config |= CORE_DLL_PDN;
329 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75
GD		 330 msm_cm_dll_set_freq(host);
331
29301f40
RH		 332 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
333 config &= ~CORE_DLL_RST;
334 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75 335
29301f40
RH		 336 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
337 config &= ~CORE_DLL_PDN;
338 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75 339
29301f40
RH		 340 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
341 config |= CORE_DLL_EN;
342 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75 343
29301f40
RH		 344 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
345 config |= CORE_CK_OUT_EN;
346 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75
GD		 347
348 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
349 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
350 CORE_DLL_LOCK)) {
351 /* max. wait for 50us sec for LOCK bit to be set */
352 if (--wait_cnt == 0) {
353 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
354 mmc_hostname(mmc));
355 spin_unlock_irqrestore(&host->lock, flags);
356 return -ETIMEDOUT;
357 }
358 udelay(1);
359 }
360
361 spin_unlock_irqrestore(&host->lock, flags);
0eb0d9f4
GD		 362 return 0;
363}
364
415b5a75
GD		 365static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
366{
367 int tuning_seq_cnt = 3;
33d73935 368 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
415b5a75
GD		 369 int rc;
370 struct mmc_host *mmc = host->mmc;
371 struct mmc_ios ios = host->mmc->ios;
372
373 /*
374 * Tuning is required for SDR104, HS200 and HS400 cards and
375 * if clock frequency is greater than 100MHz in these modes.
376 */
377 if (host->clock <= 100 * 1000 * 1000 ||
378 !((ios.timing == MMC_TIMING_MMC_HS200) ||
379 (ios.timing == MMC_TIMING_UHS_SDR104)))
380 return 0;
381
415b5a75
GD		 382retry:
383 /* First of all reset the tuning block */
384 rc = msm_init_cm_dll(host);
385 if (rc)
33d73935 386 return rc;
415b5a75
GD		 387
388 phase = 0;
389 do {
415b5a75
GD		 390 /* Set the phase in delay line hw block */
391 rc = msm_config_cm_dll_phase(host, phase);
392 if (rc)
33d73935 393 return rc;
415b5a75 394
9979dbe5 395 rc = mmc_send_tuning(mmc, opcode, NULL);
33d73935 396 if (!rc) {
415b5a75
GD		 397 /* Tuning is successful at this tuning point */
398 tuned_phases[tuned_phase_cnt++] = phase;
399 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
400 mmc_hostname(mmc), phase);
401 }
402 } while (++phase < ARRAY_SIZE(tuned_phases));
403
404 if (tuned_phase_cnt) {
405 rc = msm_find_most_appropriate_phase(host, tuned_phases,
406 tuned_phase_cnt);
407 if (rc < 0)
33d73935 408 return rc;
415b5a75
GD		 409 else
410 phase = rc;
411
412 /*
413 * Finally set the selected phase in delay
414 * line hw block.
415 */
416 rc = msm_config_cm_dll_phase(host, phase);
417 if (rc)
33d73935 418 return rc;
415b5a75
GD		 419 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
420 mmc_hostname(mmc), phase);
421 } else {
422 if (--tuning_seq_cnt)
423 goto retry;
424 /* Tuning failed */
425 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
426 mmc_hostname(mmc));
427 rc = -EIO;
428 }
429
415b5a75
GD		 430 return rc;
431}
432
ee320674
RH		 433static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
434 unsigned int uhs)
435{
436 struct mmc_host *mmc = host->mmc;
437 u16 ctrl_2;
438
439 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
440 /* Select Bus Speed Mode for host */
441 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
442 switch (uhs) {
443 case MMC_TIMING_UHS_SDR12:
444 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
445 break;
446 case MMC_TIMING_UHS_SDR25:
447 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
448 break;
449 case MMC_TIMING_UHS_SDR50:
450 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
451 break;
452 case MMC_TIMING_MMC_HS200:
453 case MMC_TIMING_UHS_SDR104:
454 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
455 break;
456 case MMC_TIMING_UHS_DDR50:
457 case MMC_TIMING_MMC_DDR52:
458 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
459 break;
460 }
461
462 /*
463 * When clock frequency is less than 100MHz, the feedback clock must be
464 * provided and DLL must not be used so that tuning can be skipped. To
465 * provide feedback clock, the mode selection can be any value less
466 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
467 */
468 if (host->clock <= 100000000 &&
469 (uhs == MMC_TIMING_MMC_HS400 ||
470 uhs == MMC_TIMING_MMC_HS200 ||
471 uhs == MMC_TIMING_UHS_SDR104))
472 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
473
474 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
475 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
476 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
477}
478
ad81d387
GD		 479static void sdhci_msm_voltage_switch(struct sdhci_host *host)
480{
481 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
482 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
483 u32 irq_status, irq_ack = 0;
484
485 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
486 irq_status &= INT_MASK;
487
488 writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
489
490 if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))
491 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
492 if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))
493 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
494
495 /*
496 * The driver has to acknowledge the interrupt, switch voltages and
497 * report back if it succeded or not to this register. The voltage
498 * switches are handled by the sdhci core, so just report success.
499 */
500 writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
501}
502
503static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
504{
505 struct sdhci_host *host = (struct sdhci_host *)data;
506
507 sdhci_msm_voltage_switch(host);
508
509 return IRQ_HANDLED;
510}
511
0eb0d9f4
GD		 512static const struct of_device_id sdhci_msm_dt_match[] = {
513 { .compatible = "qcom,sdhci-msm-v4" },
514 {},
515};
516
517MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
518
a50396a4 519static const struct sdhci_ops sdhci_msm_ops = {
0eb0d9f4 520 .platform_execute_tuning = sdhci_msm_execute_tuning,
ed1761d7
SB		 521 .reset = sdhci_reset,
522 .set_clock = sdhci_set_clock,
523 .set_bus_width = sdhci_set_bus_width,
ee320674 524 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
ad81d387 525 .voltage_switch = sdhci_msm_voltage_switch,
0eb0d9f4
GD		 526};
527
a50396a4
JZ		 528static const struct sdhci_pltfm_data sdhci_msm_pdata = {
529 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
9718f84b 530 SDHCI_QUIRK_NO_CARD_NO_RESET |
a50396a4
JZ		 531 SDHCI_QUIRK_SINGLE_POWER_WRITE,
532 .ops = &sdhci_msm_ops,
533};
534
0eb0d9f4
GD		 535static int sdhci_msm_probe(struct platform_device *pdev)
536{
537 struct sdhci_host *host;
538 struct sdhci_pltfm_host *pltfm_host;
539 struct sdhci_msm_host *msm_host;
540 struct resource *core_memres;
541 int ret;
3a3ad3e9 542 u16 host_version, core_minor;
29301f40 543 u32 core_version, config;
3a3ad3e9 544 u8 core_major;
0eb0d9f4 545
6f699531 546 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
0eb0d9f4
GD		 547 if (IS_ERR(host))
548 return PTR_ERR(host);
549
550 pltfm_host = sdhci_priv(host);
6f699531 551 msm_host = sdhci_pltfm_priv(pltfm_host);
0eb0d9f4
GD		 552 msm_host->mmc = host->mmc;
553 msm_host->pdev = pdev;
554
555 ret = mmc_of_parse(host->mmc);
556 if (ret)
557 goto pltfm_free;
558
559 sdhci_get_of_property(pdev);
560
561 /* Setup SDCC bus voter clock. */
562 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
563 if (!IS_ERR(msm_host->bus_clk)) {
564 /* Vote for max. clk rate for max. performance */
565 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
566 if (ret)
567 goto pltfm_free;
568 ret = clk_prepare_enable(msm_host->bus_clk);
569 if (ret)
570 goto pltfm_free;
571 }
572
573 /* Setup main peripheral bus clock */
574 msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
575 if (IS_ERR(msm_host->pclk)) {
576 ret = PTR_ERR(msm_host->pclk);
2801b95e 577 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
0eb0d9f4
GD		 578 goto bus_clk_disable;
579 }
580
581 ret = clk_prepare_enable(msm_host->pclk);
582 if (ret)
583 goto bus_clk_disable;
584
585 /* Setup SDC MMC clock */
586 msm_host->clk = devm_clk_get(&pdev->dev, "core");
587 if (IS_ERR(msm_host->clk)) {
588 ret = PTR_ERR(msm_host->clk);
589 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
590 goto pclk_disable;
591 }
592
951b8c87
II		 593 /* Vote for maximum clock rate for maximum performance */
594 ret = clk_set_rate(msm_host->clk, INT_MAX);
595 if (ret)
596 dev_warn(&pdev->dev, "core clock boost failed\n");
597
0eb0d9f4
GD		 598 ret = clk_prepare_enable(msm_host->clk);
599 if (ret)
600 goto pclk_disable;
601
602 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
603 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
604
605 if (IS_ERR(msm_host->core_mem)) {
606 dev_err(&pdev->dev, "Failed to remap registers\n");
607 ret = PTR_ERR(msm_host->core_mem);
608 goto clk_disable;
609 }
610
29301f40
RH		 611 config = readl_relaxed(msm_host->core_mem + CORE_POWER);
612 config |= CORE_SW_RST;
613 writel_relaxed(config, msm_host->core_mem + CORE_POWER);
0eb0d9f4
GD		 614
615 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
616 usleep_range(1000, 5000);
617 if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
618 dev_err(&pdev->dev, "Stuck in reset\n");
619 ret = -ETIMEDOUT;
620 goto clk_disable;
621 }
622
623 /* Set HC_MODE_EN bit in HC_MODE register */
624 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
625
0eb0d9f4
GD		 626 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
627 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
628 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
629 SDHCI_VENDOR_VER_SHIFT));
630
3a3ad3e9
GD		 631 core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
632 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
633 CORE_VERSION_MAJOR_SHIFT;
634 core_minor = core_version & CORE_VERSION_MINOR_MASK;
635 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
636 core_version, core_major, core_minor);
637
638 /*
639 * Support for some capabilities is not advertised by newer
640 * controller versions and must be explicitly enabled.
641 */
642 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
29301f40
RH		 643 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
644 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
645 writel_relaxed(config, host->ioaddr +
3a3ad3e9
GD		 646 CORE_VENDOR_SPEC_CAPABILITIES0);
647 }
648
ad81d387
GD		 649 /* Setup IRQ for handling power/voltage tasks with PMIC */
650 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
651 if (msm_host->pwr_irq < 0) {
652 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
653 msm_host->pwr_irq);
d1f63f0c 654 ret = msm_host->pwr_irq;
ad81d387
GD		 655 goto clk_disable;
656 }
657
658 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
659 sdhci_msm_pwr_irq, IRQF_ONESHOT,
660 dev_name(&pdev->dev), host);
661 if (ret) {
662 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
663 goto clk_disable;
664 }
665
67e6db11
PG		 666 pm_runtime_get_noresume(&pdev->dev);
667 pm_runtime_set_active(&pdev->dev);
668 pm_runtime_enable(&pdev->dev);
669 pm_runtime_set_autosuspend_delay(&pdev->dev,
670 MSM_MMC_AUTOSUSPEND_DELAY_MS);
671 pm_runtime_use_autosuspend(&pdev->dev);
672
0eb0d9f4
GD		 673 ret = sdhci_add_host(host);
674 if (ret)
67e6db11
PG		 675 goto pm_runtime_disable;
676
677 pm_runtime_mark_last_busy(&pdev->dev);
678 pm_runtime_put_autosuspend(&pdev->dev);
0eb0d9f4
GD		 679
680 return 0;
681
67e6db11
PG		 682pm_runtime_disable:
683 pm_runtime_disable(&pdev->dev);
684 pm_runtime_set_suspended(&pdev->dev);
685 pm_runtime_put_noidle(&pdev->dev);
0eb0d9f4
GD		 686clk_disable:
687 clk_disable_unprepare(msm_host->clk);
688pclk_disable:
689 clk_disable_unprepare(msm_host->pclk);
690bus_clk_disable:
691 if (!IS_ERR(msm_host->bus_clk))
692 clk_disable_unprepare(msm_host->bus_clk);
693pltfm_free:
694 sdhci_pltfm_free(pdev);
695 return ret;
696}
697
698static int sdhci_msm_remove(struct platform_device *pdev)
699{
700 struct sdhci_host *host = platform_get_drvdata(pdev);
701 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
6f699531 702 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
0eb0d9f4
GD		 703 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
704 0xffffffff);
705
706 sdhci_remove_host(host, dead);
67e6db11
PG		 707
708 pm_runtime_get_sync(&pdev->dev);
709 pm_runtime_disable(&pdev->dev);
710 pm_runtime_put_noidle(&pdev->dev);
711
0eb0d9f4
GD		 712 clk_disable_unprepare(msm_host->clk);
713 clk_disable_unprepare(msm_host->pclk);
714 if (!IS_ERR(msm_host->bus_clk))
715 clk_disable_unprepare(msm_host->bus_clk);
6f699531 716 sdhci_pltfm_free(pdev);
0eb0d9f4
GD		 717 return 0;
718}
719
67e6db11
PG		 720#ifdef CONFIG_PM
721static int sdhci_msm_runtime_suspend(struct device *dev)
722{
723 struct sdhci_host *host = dev_get_drvdata(dev);
724 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
725 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
726
727 clk_disable_unprepare(msm_host->clk);
728 clk_disable_unprepare(msm_host->pclk);
729
730 return 0;
731}
732
733static int sdhci_msm_runtime_resume(struct device *dev)
734{
735 struct sdhci_host *host = dev_get_drvdata(dev);
736 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
737 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
738 int ret;
739
740 ret = clk_prepare_enable(msm_host->clk);
741 if (ret) {
742 dev_err(dev, "clk_enable failed for core_clk: %d\n", ret);
743 return ret;
744 }
745 ret = clk_prepare_enable(msm_host->pclk);
746 if (ret) {
747 dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret);
748 clk_disable_unprepare(msm_host->clk);
749 return ret;
750 }
751
752 return 0;
753}
754#endif
755
756static const struct dev_pm_ops sdhci_msm_pm_ops = {
757 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
758 pm_runtime_force_resume)
759 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
760 sdhci_msm_runtime_resume,
761 NULL)
762};
763
0eb0d9f4
GD		 764static struct platform_driver sdhci_msm_driver = {
765 .probe = sdhci_msm_probe,
766 .remove = sdhci_msm_remove,
767 .driver = {
768 .name = "sdhci_msm",
0eb0d9f4 769 .of_match_table = sdhci_msm_dt_match,
67e6db11 770 .pm = &sdhci_msm_pm_ops,
0eb0d9f4
GD		 771 },
772};
773
774module_platform_driver(sdhci_msm_driver);
775
776MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
777MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)