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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0eb0d9f4 GD |
2 | /* |
3 | * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver | |
4 | * | |
5 | * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. | |
0eb0d9f4 GD |
6 | */ |
7 | ||
8 | #include <linux/module.h> | |
9 | #include <linux/of_device.h> | |
0eb0d9f4 | 10 | #include <linux/delay.h> |
415b5a75 | 11 | #include <linux/mmc/mmc.h> |
67e6db11 | 12 | #include <linux/pm_runtime.h> |
0472f8d3 | 13 | #include <linux/pm_opp.h> |
415b5a75 | 14 | #include <linux/slab.h> |
cc392c58 | 15 | #include <linux/iopoll.h> |
c93767cf | 16 | #include <linux/qcom_scm.h> |
ac06fba1 | 17 | #include <linux/regulator/consumer.h> |
b4fc8278 | 18 | #include <linux/interconnect.h> |
b5c833b7 | 19 | #include <linux/pinctrl/consumer.h> |
3e5a8e84 | 20 | #include <linux/reset.h> |
0eb0d9f4 GD |
21 | |
22 | #include "sdhci-pltfm.h" | |
87a8df0d | 23 | #include "cqhci.h" |
0eb0d9f4 | 24 | |
3a3ad3e9 GD |
25 | #define CORE_MCI_VERSION 0x50 |
26 | #define CORE_VERSION_MAJOR_SHIFT 28 | |
27 | #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) | |
28 | #define CORE_VERSION_MINOR_MASK 0xff | |
29 | ||
52884f8f BA |
30 | #define CORE_MCI_GENERICS 0x70 |
31 | #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29) | |
32 | ||
0eb0d9f4 GD |
33 | #define HC_MODE_EN 0x1 |
34 | #define CORE_POWER 0x0 | |
35 | #define CORE_SW_RST BIT(7) | |
ff06ce41 | 36 | #define FF_CLK_SW_RST_DIS BIT(13) |
0eb0d9f4 | 37 | |
ad81d387 GD |
38 | #define CORE_PWRCTL_BUS_OFF BIT(0) |
39 | #define CORE_PWRCTL_BUS_ON BIT(1) | |
40 | #define CORE_PWRCTL_IO_LOW BIT(2) | |
41 | #define CORE_PWRCTL_IO_HIGH BIT(3) | |
42 | #define CORE_PWRCTL_BUS_SUCCESS BIT(0) | |
92a21738 | 43 | #define CORE_PWRCTL_BUS_FAIL BIT(1) |
ad81d387 | 44 | #define CORE_PWRCTL_IO_SUCCESS BIT(2) |
92a21738 | 45 | #define CORE_PWRCTL_IO_FAIL BIT(3) |
ad81d387 GD |
46 | #define REQ_BUS_OFF BIT(0) |
47 | #define REQ_BUS_ON BIT(1) | |
48 | #define REQ_IO_LOW BIT(2) | |
49 | #define REQ_IO_HIGH BIT(3) | |
50 | #define INT_MASK 0xf | |
415b5a75 GD |
51 | #define MAX_PHASES 16 |
52 | #define CORE_DLL_LOCK BIT(7) | |
02e4293d | 53 | #define CORE_DDR_DLL_LOCK BIT(11) |
415b5a75 GD |
54 | #define CORE_DLL_EN BIT(16) |
55 | #define CORE_CDR_EN BIT(17) | |
56 | #define CORE_CK_OUT_EN BIT(18) | |
57 | #define CORE_CDR_EXT_EN BIT(19) | |
58 | #define CORE_DLL_PDN BIT(29) | |
59 | #define CORE_DLL_RST BIT(30) | |
cc392c58 | 60 | #define CORE_CMD_DAT_TRACK_SEL BIT(0) |
415b5a75 | 61 | |
02e4293d | 62 | #define CORE_DDR_CAL_EN BIT(0) |
83736352 VG |
63 | #define CORE_FLL_CYCLE_CNT BIT(18) |
64 | #define CORE_DLL_CLOCK_DISABLE BIT(21) | |
65 | ||
5c30f340 VB |
66 | #define DLL_USR_CTL_POR_VAL 0x10800 |
67 | #define ENABLE_DLL_LOCK_STATUS BIT(26) | |
68 | #define FINE_TUNE_MODE_EN BIT(27) | |
69 | #define BIAS_OK_SIGNAL BIT(29) | |
70 | ||
04816e67 SG |
71 | #define DLL_CONFIG_3_LOW_FREQ_VAL 0x08 |
72 | #define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10 | |
73 | ||
946932d9 | 74 | #define CORE_VENDOR_SPEC_POR_VAL 0xa9c |
415b5a75 | 75 | #define CORE_CLK_PWRSAVE BIT(1) |
ff06ce41 VG |
76 | #define CORE_HC_MCLK_SEL_DFLT (2 << 8) |
77 | #define CORE_HC_MCLK_SEL_HS400 (3 << 8) | |
78 | #define CORE_HC_MCLK_SEL_MASK (3 << 8) | |
946932d9 VB |
79 | #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15) |
80 | #define CORE_IO_PAD_PWR_SWITCH BIT(16) | |
ff06ce41 VG |
81 | #define CORE_HC_SELECT_IN_EN BIT(18) |
82 | #define CORE_HC_SELECT_IN_HS400 (6 << 19) | |
83 | #define CORE_HC_SELECT_IN_MASK (7 << 19) | |
415b5a75 | 84 | |
946932d9 VB |
85 | #define CORE_3_0V_SUPPORT BIT(25) |
86 | #define CORE_1_8V_SUPPORT BIT(26) | |
5c132323 | 87 | #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT) |
ac06fba1 | 88 | |
cc392c58 RH |
89 | #define CORE_CSR_CDC_CTLR_CFG0 0x130 |
90 | #define CORE_SW_TRIG_FULL_CALIB BIT(16) | |
91 | #define CORE_HW_AUTOCAL_ENA BIT(17) | |
92 | ||
93 | #define CORE_CSR_CDC_CTLR_CFG1 0x134 | |
94 | #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138 | |
95 | #define CORE_TIMER_ENA BIT(16) | |
96 | ||
97 | #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C | |
98 | #define CORE_CSR_CDC_REFCOUNT_CFG 0x140 | |
99 | #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144 | |
100 | #define CORE_CDC_OFFSET_CFG 0x14C | |
101 | #define CORE_CSR_CDC_DELAY_CFG 0x150 | |
102 | #define CORE_CDC_SLAVE_DDA_CFG 0x160 | |
103 | #define CORE_CSR_CDC_STATUS0 0x164 | |
104 | #define CORE_CALIBRATION_DONE BIT(0) | |
105 | ||
106 | #define CORE_CDC_ERROR_CODE_MASK 0x7000000 | |
107 | ||
108 | #define CORE_CSR_CDC_GEN_CFG 0x178 | |
109 | #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0) | |
110 | #define CORE_CDC_SWITCH_RC_EN BIT(1) | |
111 | ||
cc392c58 | 112 | #define CORE_CDC_T4_DLY_SEL BIT(0) |
44bf2312 | 113 | #define CORE_CMDIN_RCLK_EN BIT(1) |
cc392c58 | 114 | #define CORE_START_CDC_TRAFFIC BIT(6) |
bc99266b | 115 | |
02e4293d RH |
116 | #define CORE_PWRSAVE_DLL BIT(3) |
117 | ||
fa56ac97 | 118 | #define DDR_CONFIG_POR_VAL 0x80040873 |
cc392c58 | 119 | |
3a3ad3e9 | 120 | |
abf270e5 | 121 | #define INVALID_TUNING_PHASE -1 |
80031bde | 122 | #define SDHCI_MSM_MIN_CLOCK 400000 |
ff06ce41 | 123 | #define CORE_FREQ_100MHZ (100 * 1000 * 1000) |
80031bde | 124 | |
415b5a75 GD |
125 | #define CDR_SELEXT_SHIFT 20 |
126 | #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) | |
127 | #define CMUX_SHIFT_PHASE_SHIFT 24 | |
128 | #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) | |
129 | ||
67e6db11 | 130 | #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50 |
c0309b38 VV |
131 | |
132 | /* Timeout value to avoid infinite waiting for pwr_irq */ | |
133 | #define MSM_PWR_IRQ_TIMEOUT_MS 5000 | |
134 | ||
92a21738 VB |
135 | /* Max load for eMMC Vdd-io supply */ |
136 | #define MMC_VQMMC_MAX_LOAD_UA 325000 | |
137 | ||
bc99266b SL |
138 | #define msm_host_readl(msm_host, host, offset) \ |
139 | msm_host->var_ops->msm_readl_relaxed(host, offset) | |
140 | ||
141 | #define msm_host_writel(msm_host, val, host, offset) \ | |
142 | msm_host->var_ops->msm_writel_relaxed(val, host, offset) | |
143 | ||
87a8df0d RH |
144 | /* CQHCI vendor specific registers */ |
145 | #define CQHCI_VENDOR_CFG1 0xA00 | |
146 | #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13) | |
147 | ||
f1535888 SL |
148 | struct sdhci_msm_offset { |
149 | u32 core_hc_mode; | |
150 | u32 core_mci_data_cnt; | |
151 | u32 core_mci_status; | |
152 | u32 core_mci_fifo_cnt; | |
153 | u32 core_mci_version; | |
154 | u32 core_generics; | |
155 | u32 core_testbus_config; | |
156 | u32 core_testbus_sel2_bit; | |
157 | u32 core_testbus_ena; | |
158 | u32 core_testbus_sel2; | |
159 | u32 core_pwrctl_status; | |
160 | u32 core_pwrctl_mask; | |
161 | u32 core_pwrctl_clear; | |
162 | u32 core_pwrctl_ctl; | |
163 | u32 core_sdcc_debug_reg; | |
164 | u32 core_dll_config; | |
165 | u32 core_dll_status; | |
166 | u32 core_vendor_spec; | |
167 | u32 core_vendor_spec_adma_err_addr0; | |
168 | u32 core_vendor_spec_adma_err_addr1; | |
169 | u32 core_vendor_spec_func2; | |
170 | u32 core_vendor_spec_capabilities0; | |
171 | u32 core_ddr_200_cfg; | |
172 | u32 core_vendor_spec3; | |
173 | u32 core_dll_config_2; | |
fa56ac97 VB |
174 | u32 core_dll_config_3; |
175 | u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */ | |
f1535888 | 176 | u32 core_ddr_config; |
5c30f340 | 177 | u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */ |
f1535888 SL |
178 | }; |
179 | ||
180 | static const struct sdhci_msm_offset sdhci_msm_v5_offset = { | |
181 | .core_mci_data_cnt = 0x35c, | |
182 | .core_mci_status = 0x324, | |
183 | .core_mci_fifo_cnt = 0x308, | |
184 | .core_mci_version = 0x318, | |
185 | .core_generics = 0x320, | |
186 | .core_testbus_config = 0x32c, | |
187 | .core_testbus_sel2_bit = 3, | |
188 | .core_testbus_ena = (1 << 31), | |
189 | .core_testbus_sel2 = (1 << 3), | |
190 | .core_pwrctl_status = 0x240, | |
191 | .core_pwrctl_mask = 0x244, | |
192 | .core_pwrctl_clear = 0x248, | |
193 | .core_pwrctl_ctl = 0x24c, | |
194 | .core_sdcc_debug_reg = 0x358, | |
195 | .core_dll_config = 0x200, | |
196 | .core_dll_status = 0x208, | |
197 | .core_vendor_spec = 0x20c, | |
198 | .core_vendor_spec_adma_err_addr0 = 0x214, | |
199 | .core_vendor_spec_adma_err_addr1 = 0x218, | |
200 | .core_vendor_spec_func2 = 0x210, | |
201 | .core_vendor_spec_capabilities0 = 0x21c, | |
202 | .core_ddr_200_cfg = 0x224, | |
203 | .core_vendor_spec3 = 0x250, | |
204 | .core_dll_config_2 = 0x254, | |
fa56ac97 VB |
205 | .core_dll_config_3 = 0x258, |
206 | .core_ddr_config = 0x25c, | |
5c30f340 | 207 | .core_dll_usr_ctl = 0x388, |
f1535888 SL |
208 | }; |
209 | ||
210 | static const struct sdhci_msm_offset sdhci_msm_mci_offset = { | |
211 | .core_hc_mode = 0x78, | |
212 | .core_mci_data_cnt = 0x30, | |
213 | .core_mci_status = 0x34, | |
214 | .core_mci_fifo_cnt = 0x44, | |
215 | .core_mci_version = 0x050, | |
216 | .core_generics = 0x70, | |
217 | .core_testbus_config = 0x0cc, | |
218 | .core_testbus_sel2_bit = 4, | |
219 | .core_testbus_ena = (1 << 3), | |
220 | .core_testbus_sel2 = (1 << 4), | |
221 | .core_pwrctl_status = 0xdc, | |
222 | .core_pwrctl_mask = 0xe0, | |
223 | .core_pwrctl_clear = 0xe4, | |
224 | .core_pwrctl_ctl = 0xe8, | |
225 | .core_sdcc_debug_reg = 0x124, | |
226 | .core_dll_config = 0x100, | |
227 | .core_dll_status = 0x108, | |
228 | .core_vendor_spec = 0x10c, | |
229 | .core_vendor_spec_adma_err_addr0 = 0x114, | |
230 | .core_vendor_spec_adma_err_addr1 = 0x118, | |
231 | .core_vendor_spec_func2 = 0x110, | |
232 | .core_vendor_spec_capabilities0 = 0x11c, | |
233 | .core_ddr_200_cfg = 0x184, | |
234 | .core_vendor_spec3 = 0x1b0, | |
235 | .core_dll_config_2 = 0x1b4, | |
fa56ac97 VB |
236 | .core_ddr_config_old = 0x1b8, |
237 | .core_ddr_config = 0x1bc, | |
f1535888 SL |
238 | }; |
239 | ||
6ed4bb43 VV |
240 | struct sdhci_msm_variant_ops { |
241 | u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset); | |
242 | void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host, | |
243 | u32 offset); | |
244 | }; | |
245 | ||
246 | /* | |
247 | * From V5, register spaces have changed. Wrap this info in a structure | |
248 | * and choose the data_structure based on version info mentioned in DT. | |
249 | */ | |
250 | struct sdhci_msm_variant_info { | |
251 | bool mci_removed; | |
21f1e2d4 | 252 | bool restore_dll_config; |
6ed4bb43 VV |
253 | const struct sdhci_msm_variant_ops *var_ops; |
254 | const struct sdhci_msm_offset *offset; | |
255 | }; | |
256 | ||
0eb0d9f4 GD |
257 | struct sdhci_msm_host { |
258 | struct platform_device *pdev; | |
259 | void __iomem *core_mem; /* MSM SDCC mapped address */ | |
c93767cf | 260 | void __iomem *ice_mem; /* MSM ICE mapped address (if available) */ |
ad81d387 | 261 | int pwr_irq; /* power irq */ |
0eb0d9f4 | 262 | struct clk *bus_clk; /* SDHC bus voter clock */ |
83736352 | 263 | struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ |
c93767cf EB |
264 | /* core, iface, cal, sleep, and ice clocks */ |
265 | struct clk_bulk_data bulk_clks[5]; | |
edc609fd | 266 | unsigned long clk_rate; |
0eb0d9f4 | 267 | struct mmc_host *mmc; |
83736352 | 268 | bool use_14lpp_dll_reset; |
ff06ce41 VG |
269 | bool tuning_done; |
270 | bool calibration_done; | |
abf270e5 | 271 | u8 saved_tuning_phase; |
02e4293d | 272 | bool use_cdclp533; |
c0309b38 VV |
273 | u32 curr_pwr_state; |
274 | u32 curr_io_level; | |
275 | wait_queue_head_t pwr_irq_wait; | |
276 | bool pwr_irq_flag; | |
ac06fba1 | 277 | u32 caps_0; |
6ed4bb43 | 278 | bool mci_removed; |
21f1e2d4 | 279 | bool restore_dll_config; |
6ed4bb43 VV |
280 | const struct sdhci_msm_variant_ops *var_ops; |
281 | const struct sdhci_msm_offset *offset; | |
a89e7bcb LP |
282 | bool use_cdr; |
283 | u32 transfer_mode; | |
fa56ac97 | 284 | bool updated_ddr_cfg; |
5c30f340 | 285 | bool uses_tassadar_dll; |
03591160 | 286 | u32 dll_config; |
1dfbe3ff | 287 | u32 ddr_config; |
92a21738 | 288 | bool vqmmc_enabled; |
0eb0d9f4 GD |
289 | }; |
290 | ||
bc99266b SL |
291 | static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host) |
292 | { | |
293 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
294 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
295 | ||
296 | return msm_host->offset; | |
297 | } | |
298 | ||
6ed4bb43 VV |
299 | /* |
300 | * APIs to read/write to vendor specific registers which were there in the | |
301 | * core_mem region before MCI was removed. | |
302 | */ | |
303 | static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host, | |
304 | u32 offset) | |
305 | { | |
306 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
307 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
308 | ||
309 | return readl_relaxed(msm_host->core_mem + offset); | |
310 | } | |
311 | ||
312 | static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host, | |
313 | u32 offset) | |
314 | { | |
315 | return readl_relaxed(host->ioaddr + offset); | |
316 | } | |
317 | ||
318 | static void sdhci_msm_mci_variant_writel_relaxed(u32 val, | |
319 | struct sdhci_host *host, u32 offset) | |
320 | { | |
321 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
322 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
323 | ||
324 | writel_relaxed(val, msm_host->core_mem + offset); | |
325 | } | |
326 | ||
327 | static void sdhci_msm_v5_variant_writel_relaxed(u32 val, | |
328 | struct sdhci_host *host, u32 offset) | |
329 | { | |
330 | writel_relaxed(val, host->ioaddr + offset); | |
331 | } | |
332 | ||
f16c8fd4 | 333 | static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host) |
0fb8a3d4 RH |
334 | { |
335 | struct mmc_ios ios = host->mmc->ios; | |
336 | /* | |
337 | * The SDHC requires internal clock frequency to be double the | |
338 | * actual clock that will be set for DDR mode. The controller | |
339 | * uses the faster clock(100/400MHz) for some of its parts and | |
340 | * send the actual required clock (50/200MHz) to the card. | |
341 | */ | |
342 | if (ios.timing == MMC_TIMING_UHS_DDR50 || | |
343 | ios.timing == MMC_TIMING_MMC_DDR52 || | |
d7507aa1 RH |
344 | ios.timing == MMC_TIMING_MMC_HS400 || |
345 | host->flags & SDHCI_HS400_TUNING) | |
f16c8fd4 DA |
346 | return 2; |
347 | return 1; | |
0fb8a3d4 RH |
348 | } |
349 | ||
350 | static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host, | |
351 | unsigned int clock) | |
352 | { | |
353 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
354 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
355 | struct mmc_ios curr_ios = host->mmc->ios; | |
e4bf91f6 | 356 | struct clk *core_clk = msm_host->bulk_clks[0].clk; |
a8cd989e | 357 | unsigned long achieved_rate; |
f16c8fd4 DA |
358 | unsigned int desired_rate; |
359 | unsigned int mult; | |
0fb8a3d4 RH |
360 | int rc; |
361 | ||
f16c8fd4 DA |
362 | mult = msm_get_clock_mult_for_bus_mode(host); |
363 | desired_rate = clock * mult; | |
364 | rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate); | |
0fb8a3d4 RH |
365 | if (rc) { |
366 | pr_err("%s: Failed to set clock at rate %u at timing %d\n", | |
f16c8fd4 | 367 | mmc_hostname(host->mmc), desired_rate, curr_ios.timing); |
0fb8a3d4 RH |
368 | return; |
369 | } | |
a8cd989e DA |
370 | |
371 | /* | |
372 | * Qualcomm clock drivers by default round clock _up_ if they can't | |
373 | * make the requested rate. This is not good for SD. Yell if we | |
374 | * encounter it. | |
375 | */ | |
376 | achieved_rate = clk_get_rate(core_clk); | |
f16c8fd4 | 377 | if (achieved_rate > desired_rate) |
a8cd989e | 378 | pr_warn("%s: Card appears overclocked; req %u Hz, actual %lu Hz\n", |
f16c8fd4 DA |
379 | mmc_hostname(host->mmc), desired_rate, achieved_rate); |
380 | host->mmc->actual_clock = achieved_rate / mult; | |
381 | ||
382 | /* Stash the rate we requested to use in sdhci_msm_runtime_resume() */ | |
383 | msm_host->clk_rate = desired_rate; | |
a8cd989e | 384 | |
0fb8a3d4 | 385 | pr_debug("%s: Setting clock at rate %lu at timing %d\n", |
a8cd989e | 386 | mmc_hostname(host->mmc), achieved_rate, curr_ios.timing); |
0fb8a3d4 RH |
387 | } |
388 | ||
0eb0d9f4 | 389 | /* Platform specific tuning */ |
415b5a75 GD |
390 | static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) |
391 | { | |
392 | u32 wait_cnt = 50; | |
393 | u8 ck_out_en; | |
394 | struct mmc_host *mmc = host->mmc; | |
bc99266b SL |
395 | const struct sdhci_msm_offset *msm_offset = |
396 | sdhci_priv_msm_offset(host); | |
415b5a75 GD |
397 | |
398 | /* Poll for CK_OUT_EN bit. max. poll time = 50us */ | |
bc99266b SL |
399 | ck_out_en = !!(readl_relaxed(host->ioaddr + |
400 | msm_offset->core_dll_config) & CORE_CK_OUT_EN); | |
415b5a75 GD |
401 | |
402 | while (ck_out_en != poll) { | |
403 | if (--wait_cnt == 0) { | |
404 | dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", | |
405 | mmc_hostname(mmc), poll); | |
406 | return -ETIMEDOUT; | |
407 | } | |
408 | udelay(1); | |
409 | ||
bc99266b SL |
410 | ck_out_en = !!(readl_relaxed(host->ioaddr + |
411 | msm_offset->core_dll_config) & CORE_CK_OUT_EN); | |
415b5a75 GD |
412 | } |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) | |
418 | { | |
419 | int rc; | |
420 | static const u8 grey_coded_phase_table[] = { | |
421 | 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, | |
422 | 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8 | |
423 | }; | |
424 | unsigned long flags; | |
425 | u32 config; | |
426 | struct mmc_host *mmc = host->mmc; | |
bc99266b SL |
427 | const struct sdhci_msm_offset *msm_offset = |
428 | sdhci_priv_msm_offset(host); | |
415b5a75 | 429 | |
abf270e5 RH |
430 | if (phase > 0xf) |
431 | return -EINVAL; | |
432 | ||
415b5a75 GD |
433 | spin_lock_irqsave(&host->lock, flags); |
434 | ||
bc99266b | 435 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
436 | config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); |
437 | config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); | |
bc99266b | 438 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
439 | |
440 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ | |
441 | rc = msm_dll_poll_ck_out_en(host, 0); | |
442 | if (rc) | |
443 | goto err_out; | |
444 | ||
445 | /* | |
446 | * Write the selected DLL clock output phase (0 ... 15) | |
447 | * to CDR_SELEXT bit field of DLL_CONFIG register. | |
448 | */ | |
bc99266b | 449 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
450 | config &= ~CDR_SELEXT_MASK; |
451 | config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; | |
bc99266b | 452 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 | 453 | |
bc99266b | 454 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
29301f40 | 455 | config |= CORE_CK_OUT_EN; |
bc99266b | 456 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
457 | |
458 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ | |
459 | rc = msm_dll_poll_ck_out_en(host, 1); | |
460 | if (rc) | |
461 | goto err_out; | |
462 | ||
bc99266b | 463 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
464 | config |= CORE_CDR_EN; |
465 | config &= ~CORE_CDR_EXT_EN; | |
bc99266b | 466 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
467 | goto out; |
468 | ||
469 | err_out: | |
470 | dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", | |
471 | mmc_hostname(mmc), phase); | |
472 | out: | |
473 | spin_unlock_irqrestore(&host->lock, flags); | |
474 | return rc; | |
475 | } | |
476 | ||
477 | /* | |
478 | * Find out the greatest range of consecuitive selected | |
479 | * DLL clock output phases that can be used as sampling | |
480 | * setting for SD3.0 UHS-I card read operation (in SDR104 | |
ff06ce41 VG |
481 | * timing mode) or for eMMC4.5 card read operation (in |
482 | * HS400/HS200 timing mode). | |
415b5a75 GD |
483 | * Select the 3/4 of the range and configure the DLL with the |
484 | * selected DLL clock output phase. | |
485 | */ | |
486 | ||
487 | static int msm_find_most_appropriate_phase(struct sdhci_host *host, | |
488 | u8 *phase_table, u8 total_phases) | |
489 | { | |
490 | int ret; | |
491 | u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; | |
492 | u8 phases_per_row[MAX_PHASES] = { 0 }; | |
493 | int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; | |
494 | int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; | |
495 | bool phase_0_found = false, phase_15_found = false; | |
496 | struct mmc_host *mmc = host->mmc; | |
497 | ||
498 | if (!total_phases || (total_phases > MAX_PHASES)) { | |
499 | dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", | |
500 | mmc_hostname(mmc), total_phases); | |
501 | return -EINVAL; | |
502 | } | |
503 | ||
504 | for (cnt = 0; cnt < total_phases; cnt++) { | |
505 | ranges[row_index][col_index] = phase_table[cnt]; | |
506 | phases_per_row[row_index] += 1; | |
507 | col_index++; | |
508 | ||
509 | if ((cnt + 1) == total_phases) { | |
510 | continue; | |
511 | /* check if next phase in phase_table is consecutive or not */ | |
512 | } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { | |
513 | row_index++; | |
514 | col_index = 0; | |
515 | } | |
516 | } | |
517 | ||
518 | if (row_index >= MAX_PHASES) | |
519 | return -EINVAL; | |
520 | ||
521 | /* Check if phase-0 is present in first valid window? */ | |
522 | if (!ranges[0][0]) { | |
523 | phase_0_found = true; | |
524 | phase_0_raw_index = 0; | |
525 | /* Check if cycle exist between 2 valid windows */ | |
526 | for (cnt = 1; cnt <= row_index; cnt++) { | |
527 | if (phases_per_row[cnt]) { | |
528 | for (i = 0; i < phases_per_row[cnt]; i++) { | |
529 | if (ranges[cnt][i] == 15) { | |
530 | phase_15_found = true; | |
531 | phase_15_raw_index = cnt; | |
532 | break; | |
533 | } | |
534 | } | |
535 | } | |
536 | } | |
537 | } | |
538 | ||
539 | /* If 2 valid windows form cycle then merge them as single window */ | |
540 | if (phase_0_found && phase_15_found) { | |
541 | /* number of phases in raw where phase 0 is present */ | |
542 | u8 phases_0 = phases_per_row[phase_0_raw_index]; | |
543 | /* number of phases in raw where phase 15 is present */ | |
544 | u8 phases_15 = phases_per_row[phase_15_raw_index]; | |
545 | ||
546 | if (phases_0 + phases_15 >= MAX_PHASES) | |
547 | /* | |
548 | * If there are more than 1 phase windows then total | |
549 | * number of phases in both the windows should not be | |
550 | * more than or equal to MAX_PHASES. | |
551 | */ | |
552 | return -EINVAL; | |
553 | ||
554 | /* Merge 2 cyclic windows */ | |
555 | i = phases_15; | |
556 | for (cnt = 0; cnt < phases_0; cnt++) { | |
557 | ranges[phase_15_raw_index][i] = | |
558 | ranges[phase_0_raw_index][cnt]; | |
559 | if (++i >= MAX_PHASES) | |
560 | break; | |
561 | } | |
562 | ||
563 | phases_per_row[phase_0_raw_index] = 0; | |
564 | phases_per_row[phase_15_raw_index] = phases_15 + phases_0; | |
565 | } | |
566 | ||
567 | for (cnt = 0; cnt <= row_index; cnt++) { | |
568 | if (phases_per_row[cnt] > curr_max) { | |
569 | curr_max = phases_per_row[cnt]; | |
570 | selected_row_index = cnt; | |
571 | } | |
572 | } | |
573 | ||
574 | i = (curr_max * 3) / 4; | |
575 | if (i) | |
576 | i--; | |
577 | ||
578 | ret = ranges[selected_row_index][i]; | |
579 | ||
580 | if (ret >= MAX_PHASES) { | |
581 | ret = -EINVAL; | |
582 | dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", | |
583 | mmc_hostname(mmc), ret); | |
584 | } | |
585 | ||
586 | return ret; | |
587 | } | |
588 | ||
589 | static inline void msm_cm_dll_set_freq(struct sdhci_host *host) | |
0eb0d9f4 | 590 | { |
415b5a75 | 591 | u32 mclk_freq = 0, config; |
bc99266b SL |
592 | const struct sdhci_msm_offset *msm_offset = |
593 | sdhci_priv_msm_offset(host); | |
415b5a75 GD |
594 | |
595 | /* Program the MCLK value to MCLK_FREQ bit field */ | |
596 | if (host->clock <= 112000000) | |
597 | mclk_freq = 0; | |
598 | else if (host->clock <= 125000000) | |
599 | mclk_freq = 1; | |
600 | else if (host->clock <= 137000000) | |
601 | mclk_freq = 2; | |
602 | else if (host->clock <= 150000000) | |
603 | mclk_freq = 3; | |
604 | else if (host->clock <= 162000000) | |
605 | mclk_freq = 4; | |
606 | else if (host->clock <= 175000000) | |
607 | mclk_freq = 5; | |
608 | else if (host->clock <= 187000000) | |
609 | mclk_freq = 6; | |
610 | else if (host->clock <= 200000000) | |
611 | mclk_freq = 7; | |
612 | ||
bc99266b | 613 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
614 | config &= ~CMUX_SHIFT_PHASE_MASK; |
615 | config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT; | |
bc99266b | 616 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
617 | } |
618 | ||
619 | /* Initialize the DLL (Programmable Delay Line) */ | |
620 | static int msm_init_cm_dll(struct sdhci_host *host) | |
621 | { | |
622 | struct mmc_host *mmc = host->mmc; | |
83736352 VG |
623 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
624 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
415b5a75 | 625 | int wait_cnt = 50; |
5e6b6651 | 626 | unsigned long flags, xo_clk = 0; |
29301f40 | 627 | u32 config; |
bc99266b SL |
628 | const struct sdhci_msm_offset *msm_offset = |
629 | msm_host->offset; | |
415b5a75 | 630 | |
5e6b6651 JRO |
631 | if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk)) |
632 | xo_clk = clk_get_rate(msm_host->xo_clk); | |
633 | ||
415b5a75 GD |
634 | spin_lock_irqsave(&host->lock, flags); |
635 | ||
0eb0d9f4 | 636 | /* |
415b5a75 GD |
637 | * Make sure that clock is always enabled when DLL |
638 | * tuning is in progress. Keeping PWRSAVE ON may | |
639 | * turn off the clock. | |
0eb0d9f4 | 640 | */ |
bc99266b | 641 | config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); |
29301f40 | 642 | config &= ~CORE_CLK_PWRSAVE; |
bc99266b | 643 | writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); |
415b5a75 | 644 | |
3ec2d511 VB |
645 | if (msm_host->dll_config) |
646 | writel_relaxed(msm_host->dll_config, | |
647 | host->ioaddr + msm_offset->core_dll_config); | |
03591160 | 648 | |
83736352 | 649 | if (msm_host->use_14lpp_dll_reset) { |
bc99266b SL |
650 | config = readl_relaxed(host->ioaddr + |
651 | msm_offset->core_dll_config); | |
83736352 | 652 | config &= ~CORE_CK_OUT_EN; |
bc99266b SL |
653 | writel_relaxed(config, host->ioaddr + |
654 | msm_offset->core_dll_config); | |
83736352 | 655 | |
bc99266b SL |
656 | config = readl_relaxed(host->ioaddr + |
657 | msm_offset->core_dll_config_2); | |
83736352 | 658 | config |= CORE_DLL_CLOCK_DISABLE; |
bc99266b SL |
659 | writel_relaxed(config, host->ioaddr + |
660 | msm_offset->core_dll_config_2); | |
83736352 VG |
661 | } |
662 | ||
bc99266b SL |
663 | config = readl_relaxed(host->ioaddr + |
664 | msm_offset->core_dll_config); | |
29301f40 | 665 | config |= CORE_DLL_RST; |
bc99266b SL |
666 | writel_relaxed(config, host->ioaddr + |
667 | msm_offset->core_dll_config); | |
415b5a75 | 668 | |
bc99266b SL |
669 | config = readl_relaxed(host->ioaddr + |
670 | msm_offset->core_dll_config); | |
29301f40 | 671 | config |= CORE_DLL_PDN; |
bc99266b SL |
672 | writel_relaxed(config, host->ioaddr + |
673 | msm_offset->core_dll_config); | |
03591160 SG |
674 | |
675 | if (!msm_host->dll_config) | |
676 | msm_cm_dll_set_freq(host); | |
415b5a75 | 677 | |
83736352 VG |
678 | if (msm_host->use_14lpp_dll_reset && |
679 | !IS_ERR_OR_NULL(msm_host->xo_clk)) { | |
680 | u32 mclk_freq = 0; | |
681 | ||
bc99266b SL |
682 | config = readl_relaxed(host->ioaddr + |
683 | msm_offset->core_dll_config_2); | |
83736352 VG |
684 | config &= CORE_FLL_CYCLE_CNT; |
685 | if (config) | |
686 | mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), | |
5e6b6651 | 687 | xo_clk); |
83736352 VG |
688 | else |
689 | mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), | |
5e6b6651 | 690 | xo_clk); |
83736352 | 691 | |
bc99266b SL |
692 | config = readl_relaxed(host->ioaddr + |
693 | msm_offset->core_dll_config_2); | |
83736352 VG |
694 | config &= ~(0xFF << 10); |
695 | config |= mclk_freq << 10; | |
696 | ||
bc99266b SL |
697 | writel_relaxed(config, host->ioaddr + |
698 | msm_offset->core_dll_config_2); | |
83736352 VG |
699 | /* wait for 5us before enabling DLL clock */ |
700 | udelay(5); | |
701 | } | |
702 | ||
bc99266b SL |
703 | config = readl_relaxed(host->ioaddr + |
704 | msm_offset->core_dll_config); | |
29301f40 | 705 | config &= ~CORE_DLL_RST; |
bc99266b SL |
706 | writel_relaxed(config, host->ioaddr + |
707 | msm_offset->core_dll_config); | |
415b5a75 | 708 | |
bc99266b SL |
709 | config = readl_relaxed(host->ioaddr + |
710 | msm_offset->core_dll_config); | |
29301f40 | 711 | config &= ~CORE_DLL_PDN; |
bc99266b SL |
712 | writel_relaxed(config, host->ioaddr + |
713 | msm_offset->core_dll_config); | |
415b5a75 | 714 | |
83736352 | 715 | if (msm_host->use_14lpp_dll_reset) { |
03591160 SG |
716 | if (!msm_host->dll_config) |
717 | msm_cm_dll_set_freq(host); | |
bc99266b SL |
718 | config = readl_relaxed(host->ioaddr + |
719 | msm_offset->core_dll_config_2); | |
83736352 | 720 | config &= ~CORE_DLL_CLOCK_DISABLE; |
bc99266b SL |
721 | writel_relaxed(config, host->ioaddr + |
722 | msm_offset->core_dll_config_2); | |
83736352 VG |
723 | } |
724 | ||
5c30f340 VB |
725 | /* |
726 | * Configure DLL user control register to enable DLL status. | |
727 | * This setting is applicable to SDCC v5.1 onwards only. | |
728 | */ | |
729 | if (msm_host->uses_tassadar_dll) { | |
730 | config = DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN | | |
731 | ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL; | |
732 | writel_relaxed(config, host->ioaddr + | |
733 | msm_offset->core_dll_usr_ctl); | |
04816e67 SG |
734 | |
735 | config = readl_relaxed(host->ioaddr + | |
736 | msm_offset->core_dll_config_3); | |
737 | config &= ~0xFF; | |
738 | if (msm_host->clk_rate < 150000000) | |
739 | config |= DLL_CONFIG_3_LOW_FREQ_VAL; | |
740 | else | |
741 | config |= DLL_CONFIG_3_HIGH_FREQ_VAL; | |
742 | writel_relaxed(config, host->ioaddr + | |
743 | msm_offset->core_dll_config_3); | |
5c30f340 VB |
744 | } |
745 | ||
bc99266b SL |
746 | config = readl_relaxed(host->ioaddr + |
747 | msm_offset->core_dll_config); | |
29301f40 | 748 | config |= CORE_DLL_EN; |
bc99266b SL |
749 | writel_relaxed(config, host->ioaddr + |
750 | msm_offset->core_dll_config); | |
415b5a75 | 751 | |
bc99266b SL |
752 | config = readl_relaxed(host->ioaddr + |
753 | msm_offset->core_dll_config); | |
29301f40 | 754 | config |= CORE_CK_OUT_EN; |
bc99266b SL |
755 | writel_relaxed(config, host->ioaddr + |
756 | msm_offset->core_dll_config); | |
415b5a75 GD |
757 | |
758 | /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ | |
bc99266b | 759 | while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) & |
415b5a75 GD |
760 | CORE_DLL_LOCK)) { |
761 | /* max. wait for 50us sec for LOCK bit to be set */ | |
762 | if (--wait_cnt == 0) { | |
763 | dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", | |
764 | mmc_hostname(mmc)); | |
765 | spin_unlock_irqrestore(&host->lock, flags); | |
766 | return -ETIMEDOUT; | |
767 | } | |
768 | udelay(1); | |
769 | } | |
770 | ||
771 | spin_unlock_irqrestore(&host->lock, flags); | |
0eb0d9f4 GD |
772 | return 0; |
773 | } | |
774 | ||
b54aaa8a RH |
775 | static void msm_hc_select_default(struct sdhci_host *host) |
776 | { | |
777 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
778 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
779 | u32 config; | |
bc99266b SL |
780 | const struct sdhci_msm_offset *msm_offset = |
781 | msm_host->offset; | |
b54aaa8a RH |
782 | |
783 | if (!msm_host->use_cdclp533) { | |
784 | config = readl_relaxed(host->ioaddr + | |
bc99266b | 785 | msm_offset->core_vendor_spec3); |
b54aaa8a RH |
786 | config &= ~CORE_PWRSAVE_DLL; |
787 | writel_relaxed(config, host->ioaddr + | |
bc99266b | 788 | msm_offset->core_vendor_spec3); |
b54aaa8a RH |
789 | } |
790 | ||
bc99266b | 791 | config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
792 | config &= ~CORE_HC_MCLK_SEL_MASK; |
793 | config |= CORE_HC_MCLK_SEL_DFLT; | |
bc99266b | 794 | writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
795 | |
796 | /* | |
797 | * Disable HC_SELECT_IN to be able to use the UHS mode select | |
798 | * configuration from Host Control2 register for all other | |
799 | * modes. | |
800 | * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field | |
801 | * in VENDOR_SPEC_FUNC | |
802 | */ | |
bc99266b | 803 | config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
804 | config &= ~CORE_HC_SELECT_IN_EN; |
805 | config &= ~CORE_HC_SELECT_IN_MASK; | |
bc99266b | 806 | writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
807 | |
808 | /* | |
809 | * Make sure above writes impacting free running MCLK are completed | |
810 | * before changing the clk_rate at GCC. | |
811 | */ | |
812 | wmb(); | |
813 | } | |
814 | ||
815 | static void msm_hc_select_hs400(struct sdhci_host *host) | |
816 | { | |
817 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
818 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
44bf2312 | 819 | struct mmc_ios ios = host->mmc->ios; |
b54aaa8a RH |
820 | u32 config, dll_lock; |
821 | int rc; | |
bc99266b SL |
822 | const struct sdhci_msm_offset *msm_offset = |
823 | msm_host->offset; | |
b54aaa8a RH |
824 | |
825 | /* Select the divided clock (free running MCLK/2) */ | |
bc99266b | 826 | config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
827 | config &= ~CORE_HC_MCLK_SEL_MASK; |
828 | config |= CORE_HC_MCLK_SEL_HS400; | |
829 | ||
bc99266b | 830 | writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
831 | /* |
832 | * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC | |
833 | * register | |
834 | */ | |
44bf2312 RH |
835 | if ((msm_host->tuning_done || ios.enhanced_strobe) && |
836 | !msm_host->calibration_done) { | |
bc99266b SL |
837 | config = readl_relaxed(host->ioaddr + |
838 | msm_offset->core_vendor_spec); | |
b54aaa8a RH |
839 | config |= CORE_HC_SELECT_IN_HS400; |
840 | config |= CORE_HC_SELECT_IN_EN; | |
bc99266b SL |
841 | writel_relaxed(config, host->ioaddr + |
842 | msm_offset->core_vendor_spec); | |
b54aaa8a RH |
843 | } |
844 | if (!msm_host->clk_rate && !msm_host->use_cdclp533) { | |
845 | /* | |
846 | * Poll on DLL_LOCK or DDR_DLL_LOCK bits in | |
bc99266b | 847 | * core_dll_status to be set. This should get set |
b54aaa8a RH |
848 | * within 15 us at 200 MHz. |
849 | */ | |
850 | rc = readl_relaxed_poll_timeout(host->ioaddr + | |
bc99266b | 851 | msm_offset->core_dll_status, |
b54aaa8a RH |
852 | dll_lock, |
853 | (dll_lock & | |
854 | (CORE_DLL_LOCK | | |
855 | CORE_DDR_DLL_LOCK)), 10, | |
856 | 1000); | |
857 | if (rc == -ETIMEDOUT) | |
858 | pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n", | |
859 | mmc_hostname(host->mmc), dll_lock); | |
860 | } | |
861 | /* | |
862 | * Make sure above writes impacting free running MCLK are completed | |
863 | * before changing the clk_rate at GCC. | |
864 | */ | |
865 | wmb(); | |
866 | } | |
867 | ||
868 | /* | |
869 | * sdhci_msm_hc_select_mode :- In general all timing modes are | |
870 | * controlled via UHS mode select in Host Control2 register. | |
871 | * eMMC specific HS200/HS400 doesn't have their respective modes | |
872 | * defined here, hence we use these values. | |
873 | * | |
874 | * HS200 - SDR104 (Since they both are equivalent in functionality) | |
875 | * HS400 - This involves multiple configurations | |
876 | * Initially SDR104 - when tuning is required as HS200 | |
877 | * Then when switching to DDR @ 400MHz (HS400) we use | |
878 | * the vendor specific HC_SELECT_IN to control the mode. | |
879 | * | |
880 | * In addition to controlling the modes we also need to select the | |
881 | * correct input clock for DLL depending on the mode. | |
882 | * | |
883 | * HS400 - divided clock (free running MCLK/2) | |
884 | * All other modes - default (free running MCLK) | |
885 | */ | |
30de038d | 886 | static void sdhci_msm_hc_select_mode(struct sdhci_host *host) |
b54aaa8a RH |
887 | { |
888 | struct mmc_ios ios = host->mmc->ios; | |
889 | ||
d7507aa1 RH |
890 | if (ios.timing == MMC_TIMING_MMC_HS400 || |
891 | host->flags & SDHCI_HS400_TUNING) | |
b54aaa8a RH |
892 | msm_hc_select_hs400(host); |
893 | else | |
894 | msm_hc_select_default(host); | |
895 | } | |
896 | ||
cc392c58 RH |
897 | static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) |
898 | { | |
899 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
900 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
901 | u32 config, calib_done; | |
902 | int ret; | |
bc99266b SL |
903 | const struct sdhci_msm_offset *msm_offset = |
904 | msm_host->offset; | |
cc392c58 RH |
905 | |
906 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
907 | ||
908 | /* | |
909 | * Retuning in HS400 (DDR mode) will fail, just reset the | |
910 | * tuning block and restore the saved tuning phase. | |
911 | */ | |
912 | ret = msm_init_cm_dll(host); | |
913 | if (ret) | |
914 | goto out; | |
915 | ||
916 | /* Set the selected phase in delay line hw block */ | |
917 | ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); | |
918 | if (ret) | |
919 | goto out; | |
920 | ||
bc99266b | 921 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
cc392c58 | 922 | config |= CORE_CMD_DAT_TRACK_SEL; |
bc99266b | 923 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
cc392c58 | 924 | |
bc99266b | 925 | config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 | 926 | config &= ~CORE_CDC_T4_DLY_SEL; |
bc99266b | 927 | writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 RH |
928 | |
929 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
930 | config &= ~CORE_CDC_SWITCH_BYPASS_OFF; | |
931 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
932 | ||
933 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
934 | config |= CORE_CDC_SWITCH_RC_EN; | |
935 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
936 | ||
bc99266b | 937 | config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 | 938 | config &= ~CORE_START_CDC_TRAFFIC; |
bc99266b | 939 | writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 | 940 | |
543c576d | 941 | /* Perform CDC Register Initialization Sequence */ |
cc392c58 RH |
942 | |
943 | writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
944 | writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); | |
945 | writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
946 | writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); | |
947 | writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); | |
948 | writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); | |
083c9aa0 | 949 | writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); |
cc392c58 RH |
950 | writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); |
951 | writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); | |
952 | ||
953 | /* CDC HW Calibration */ | |
954 | ||
955 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
956 | config |= CORE_SW_TRIG_FULL_CALIB; | |
957 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
958 | ||
959 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
960 | config &= ~CORE_SW_TRIG_FULL_CALIB; | |
961 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
962 | ||
963 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
964 | config |= CORE_HW_AUTOCAL_ENA; | |
965 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
966 | ||
967 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
968 | config |= CORE_TIMER_ENA; | |
969 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
970 | ||
971 | ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, | |
972 | calib_done, | |
973 | (calib_done & CORE_CALIBRATION_DONE), | |
974 | 1, 50); | |
975 | ||
976 | if (ret == -ETIMEDOUT) { | |
977 | pr_err("%s: %s: CDC calibration was not completed\n", | |
978 | mmc_hostname(host->mmc), __func__); | |
979 | goto out; | |
980 | } | |
981 | ||
982 | ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) | |
983 | & CORE_CDC_ERROR_CODE_MASK; | |
984 | if (ret) { | |
985 | pr_err("%s: %s: CDC error code %d\n", | |
986 | mmc_hostname(host->mmc), __func__, ret); | |
987 | ret = -EINVAL; | |
988 | goto out; | |
989 | } | |
990 | ||
bc99266b | 991 | config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 | 992 | config |= CORE_START_CDC_TRAFFIC; |
bc99266b | 993 | writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 RH |
994 | out: |
995 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
996 | __func__, ret); | |
997 | return ret; | |
998 | } | |
999 | ||
02e4293d RH |
1000 | static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) |
1001 | { | |
44bf2312 | 1002 | struct mmc_host *mmc = host->mmc; |
fa56ac97 | 1003 | u32 dll_status, config, ddr_cfg_offset; |
02e4293d | 1004 | int ret; |
fa56ac97 VB |
1005 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
1006 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
bc99266b SL |
1007 | const struct sdhci_msm_offset *msm_offset = |
1008 | sdhci_priv_msm_offset(host); | |
02e4293d RH |
1009 | |
1010 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
1011 | ||
1012 | /* | |
bc99266b | 1013 | * Currently the core_ddr_config register defaults to desired |
02e4293d RH |
1014 | * configuration on reset. Currently reprogramming the power on |
1015 | * reset (POR) value in case it might have been modified by | |
1016 | * bootloaders. In the future, if this changes, then the desired | |
1017 | * values will need to be programmed appropriately. | |
1018 | */ | |
fa56ac97 VB |
1019 | if (msm_host->updated_ddr_cfg) |
1020 | ddr_cfg_offset = msm_offset->core_ddr_config; | |
1021 | else | |
1022 | ddr_cfg_offset = msm_offset->core_ddr_config_old; | |
1dfbe3ff | 1023 | writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); |
02e4293d | 1024 | |
44bf2312 | 1025 | if (mmc->ios.enhanced_strobe) { |
bc99266b SL |
1026 | config = readl_relaxed(host->ioaddr + |
1027 | msm_offset->core_ddr_200_cfg); | |
44bf2312 | 1028 | config |= CORE_CMDIN_RCLK_EN; |
bc99266b SL |
1029 | writel_relaxed(config, host->ioaddr + |
1030 | msm_offset->core_ddr_200_cfg); | |
44bf2312 RH |
1031 | } |
1032 | ||
bc99266b | 1033 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2); |
02e4293d | 1034 | config |= CORE_DDR_CAL_EN; |
bc99266b | 1035 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2); |
02e4293d | 1036 | |
bc99266b SL |
1037 | ret = readl_relaxed_poll_timeout(host->ioaddr + |
1038 | msm_offset->core_dll_status, | |
1039 | dll_status, | |
1040 | (dll_status & CORE_DDR_DLL_LOCK), | |
1041 | 10, 1000); | |
02e4293d RH |
1042 | |
1043 | if (ret == -ETIMEDOUT) { | |
1044 | pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n", | |
1045 | mmc_hostname(host->mmc), __func__); | |
1046 | goto out; | |
1047 | } | |
1048 | ||
219c02ca RH |
1049 | /* |
1050 | * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3. | |
1051 | * When MCLK is gated OFF, it is not gated for less than 0.5us | |
1052 | * and MCLK must be switched on for at-least 1us before DATA | |
1053 | * starts coming. Controllers with 14lpp and later tech DLL cannot | |
1054 | * guarantee above requirement. So PWRSAVE_DLL should not be | |
1055 | * turned on for host controllers using this DLL. | |
1056 | */ | |
1057 | if (!msm_host->use_14lpp_dll_reset) { | |
1058 | config = readl_relaxed(host->ioaddr + | |
1059 | msm_offset->core_vendor_spec3); | |
1060 | config |= CORE_PWRSAVE_DLL; | |
1061 | writel_relaxed(config, host->ioaddr + | |
1062 | msm_offset->core_vendor_spec3); | |
1063 | } | |
02e4293d RH |
1064 | |
1065 | /* | |
1066 | * Drain writebuffer to ensure above DLL calibration | |
1067 | * and PWRSAVE DLL is enabled. | |
1068 | */ | |
1069 | wmb(); | |
1070 | out: | |
1071 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
1072 | __func__, ret); | |
1073 | return ret; | |
1074 | } | |
1075 | ||
1076 | static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) | |
1077 | { | |
1078 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1079 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
44bf2312 | 1080 | struct mmc_host *mmc = host->mmc; |
02e4293d RH |
1081 | int ret; |
1082 | u32 config; | |
bc99266b SL |
1083 | const struct sdhci_msm_offset *msm_offset = |
1084 | msm_host->offset; | |
02e4293d RH |
1085 | |
1086 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
1087 | ||
1088 | /* | |
1089 | * Retuning in HS400 (DDR mode) will fail, just reset the | |
1090 | * tuning block and restore the saved tuning phase. | |
1091 | */ | |
1092 | ret = msm_init_cm_dll(host); | |
1093 | if (ret) | |
1094 | goto out; | |
1095 | ||
44bf2312 RH |
1096 | if (!mmc->ios.enhanced_strobe) { |
1097 | /* Set the selected phase in delay line hw block */ | |
1098 | ret = msm_config_cm_dll_phase(host, | |
1099 | msm_host->saved_tuning_phase); | |
1100 | if (ret) | |
1101 | goto out; | |
bc99266b SL |
1102 | config = readl_relaxed(host->ioaddr + |
1103 | msm_offset->core_dll_config); | |
44bf2312 | 1104 | config |= CORE_CMD_DAT_TRACK_SEL; |
bc99266b SL |
1105 | writel_relaxed(config, host->ioaddr + |
1106 | msm_offset->core_dll_config); | |
44bf2312 | 1107 | } |
02e4293d | 1108 | |
02e4293d RH |
1109 | if (msm_host->use_cdclp533) |
1110 | ret = sdhci_msm_cdclp533_calibration(host); | |
1111 | else | |
1112 | ret = sdhci_msm_cm_dll_sdc4_calibration(host); | |
1113 | out: | |
1114 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
1115 | __func__, ret); | |
1116 | return ret; | |
1117 | } | |
1118 | ||
21f1e2d4 VB |
1119 | static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host) |
1120 | { | |
1121 | struct mmc_ios *ios = &host->mmc->ios; | |
1122 | ||
1123 | /* | |
1124 | * Tuning is required for SDR104, HS200 and HS400 cards and | |
1125 | * if clock frequency is greater than 100MHz in these modes. | |
1126 | */ | |
1127 | if (host->clock <= CORE_FREQ_100MHZ || | |
1128 | !(ios->timing == MMC_TIMING_MMC_HS400 || | |
1129 | ios->timing == MMC_TIMING_MMC_HS200 || | |
1130 | ios->timing == MMC_TIMING_UHS_SDR104) || | |
1131 | ios->enhanced_strobe) | |
1132 | return false; | |
1133 | ||
1134 | return true; | |
1135 | } | |
1136 | ||
1137 | static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host) | |
1138 | { | |
1139 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1140 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1141 | int ret; | |
1142 | ||
1143 | /* | |
1144 | * SDR DLL comes into picture only for timing modes which needs | |
1145 | * tuning. | |
1146 | */ | |
1147 | if (!sdhci_msm_is_tuning_needed(host)) | |
1148 | return 0; | |
1149 | ||
1150 | /* Reset the tuning block */ | |
1151 | ret = msm_init_cm_dll(host); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | ||
1155 | /* Restore the tuning block */ | |
1156 | ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); | |
1157 | ||
1158 | return ret; | |
1159 | } | |
1160 | ||
a89e7bcb LP |
1161 | static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable) |
1162 | { | |
1163 | const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host); | |
1164 | u32 config, oldconfig = readl_relaxed(host->ioaddr + | |
1165 | msm_offset->core_dll_config); | |
1166 | ||
1167 | config = oldconfig; | |
1168 | if (enable) { | |
1169 | config |= CORE_CDR_EN; | |
1170 | config &= ~CORE_CDR_EXT_EN; | |
1171 | } else { | |
1172 | config &= ~CORE_CDR_EN; | |
1173 | config |= CORE_CDR_EXT_EN; | |
1174 | } | |
1175 | ||
1176 | if (config != oldconfig) { | |
1177 | writel_relaxed(config, host->ioaddr + | |
1178 | msm_offset->core_dll_config); | |
1179 | } | |
1180 | } | |
1181 | ||
4436c535 | 1182 | static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) |
415b5a75 | 1183 | { |
4436c535 | 1184 | struct sdhci_host *host = mmc_priv(mmc); |
9d5dcefb | 1185 | int tuning_seq_cnt = 10; |
33d73935 | 1186 | u8 phase, tuned_phases[16], tuned_phase_cnt = 0; |
415b5a75 | 1187 | int rc; |
415b5a75 | 1188 | struct mmc_ios ios = host->mmc->ios; |
abf270e5 RH |
1189 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
1190 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
415b5a75 | 1191 | |
a89e7bcb LP |
1192 | if (!sdhci_msm_is_tuning_needed(host)) { |
1193 | msm_host->use_cdr = false; | |
1194 | sdhci_msm_set_cdr(host, false); | |
415b5a75 | 1195 | return 0; |
a89e7bcb LP |
1196 | } |
1197 | ||
1198 | /* Clock-Data-Recovery used to dynamically adjust RX sampling point */ | |
1199 | msm_host->use_cdr = true; | |
415b5a75 | 1200 | |
9253d710 VB |
1201 | /* |
1202 | * Clear tuning_done flag before tuning to ensure proper | |
1203 | * HS400 settings. | |
1204 | */ | |
1205 | msm_host->tuning_done = 0; | |
1206 | ||
d7507aa1 RH |
1207 | /* |
1208 | * For HS400 tuning in HS200 timing requires: | |
1209 | * - select MCLK/2 in VENDOR_SPEC | |
1210 | * - program MCLK to 400MHz (or nearest supported) in GCC | |
1211 | */ | |
1212 | if (host->flags & SDHCI_HS400_TUNING) { | |
1213 | sdhci_msm_hc_select_mode(host); | |
1214 | msm_set_clock_rate_for_bus_mode(host, ios.clock); | |
4436c535 | 1215 | host->flags &= ~SDHCI_HS400_TUNING; |
d7507aa1 RH |
1216 | } |
1217 | ||
415b5a75 GD |
1218 | retry: |
1219 | /* First of all reset the tuning block */ | |
1220 | rc = msm_init_cm_dll(host); | |
1221 | if (rc) | |
33d73935 | 1222 | return rc; |
415b5a75 GD |
1223 | |
1224 | phase = 0; | |
1225 | do { | |
415b5a75 GD |
1226 | /* Set the phase in delay line hw block */ |
1227 | rc = msm_config_cm_dll_phase(host, phase); | |
1228 | if (rc) | |
33d73935 | 1229 | return rc; |
415b5a75 | 1230 | |
9979dbe5 | 1231 | rc = mmc_send_tuning(mmc, opcode, NULL); |
33d73935 | 1232 | if (!rc) { |
415b5a75 GD |
1233 | /* Tuning is successful at this tuning point */ |
1234 | tuned_phases[tuned_phase_cnt++] = phase; | |
1235 | dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", | |
1236 | mmc_hostname(mmc), phase); | |
1237 | } | |
1238 | } while (++phase < ARRAY_SIZE(tuned_phases)); | |
1239 | ||
1240 | if (tuned_phase_cnt) { | |
9d5dcefb DA |
1241 | if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) { |
1242 | /* | |
1243 | * All phases valid is _almost_ as bad as no phases | |
1244 | * valid. Probably all phases are not really reliable | |
1245 | * but we didn't detect where the unreliable place is. | |
1246 | * That means we'll essentially be guessing and hoping | |
1247 | * we get a good phase. Better to try a few times. | |
1248 | */ | |
1249 | dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n", | |
1250 | mmc_hostname(mmc)); | |
1251 | if (--tuning_seq_cnt) { | |
1252 | tuned_phase_cnt = 0; | |
1253 | goto retry; | |
1254 | } | |
1255 | } | |
1256 | ||
415b5a75 GD |
1257 | rc = msm_find_most_appropriate_phase(host, tuned_phases, |
1258 | tuned_phase_cnt); | |
1259 | if (rc < 0) | |
33d73935 | 1260 | return rc; |
415b5a75 GD |
1261 | else |
1262 | phase = rc; | |
1263 | ||
1264 | /* | |
1265 | * Finally set the selected phase in delay | |
1266 | * line hw block. | |
1267 | */ | |
1268 | rc = msm_config_cm_dll_phase(host, phase); | |
1269 | if (rc) | |
33d73935 | 1270 | return rc; |
21f1e2d4 | 1271 | msm_host->saved_tuning_phase = phase; |
415b5a75 GD |
1272 | dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", |
1273 | mmc_hostname(mmc), phase); | |
1274 | } else { | |
1275 | if (--tuning_seq_cnt) | |
1276 | goto retry; | |
1277 | /* Tuning failed */ | |
1278 | dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", | |
1279 | mmc_hostname(mmc)); | |
1280 | rc = -EIO; | |
1281 | } | |
1282 | ||
ff06ce41 VG |
1283 | if (!rc) |
1284 | msm_host->tuning_done = true; | |
415b5a75 GD |
1285 | return rc; |
1286 | } | |
1287 | ||
db9bd163 RH |
1288 | /* |
1289 | * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation. | |
44bf2312 | 1290 | * This needs to be done for both tuning and enhanced_strobe mode. |
db9bd163 RH |
1291 | * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz |
1292 | * fixed feedback clock is used. | |
1293 | */ | |
1294 | static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios) | |
1295 | { | |
1296 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1297 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1298 | int ret; | |
1299 | ||
1300 | if (host->clock > CORE_FREQ_100MHZ && | |
44bf2312 RH |
1301 | (msm_host->tuning_done || ios->enhanced_strobe) && |
1302 | !msm_host->calibration_done) { | |
db9bd163 RH |
1303 | ret = sdhci_msm_hs400_dll_calibration(host); |
1304 | if (!ret) | |
1305 | msm_host->calibration_done = true; | |
1306 | else | |
1307 | pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n", | |
1308 | mmc_hostname(host->mmc), ret); | |
1309 | } | |
1310 | } | |
1311 | ||
ee320674 RH |
1312 | static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, |
1313 | unsigned int uhs) | |
1314 | { | |
1315 | struct mmc_host *mmc = host->mmc; | |
ff06ce41 VG |
1316 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
1317 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
ee320674 | 1318 | u16 ctrl_2; |
ff06ce41 | 1319 | u32 config; |
bc99266b SL |
1320 | const struct sdhci_msm_offset *msm_offset = |
1321 | msm_host->offset; | |
ee320674 RH |
1322 | |
1323 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1324 | /* Select Bus Speed Mode for host */ | |
1325 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
1326 | switch (uhs) { | |
1327 | case MMC_TIMING_UHS_SDR12: | |
1328 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
1329 | break; | |
1330 | case MMC_TIMING_UHS_SDR25: | |
1331 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
1332 | break; | |
1333 | case MMC_TIMING_UHS_SDR50: | |
1334 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
1335 | break; | |
ff06ce41 | 1336 | case MMC_TIMING_MMC_HS400: |
ee320674 RH |
1337 | case MMC_TIMING_MMC_HS200: |
1338 | case MMC_TIMING_UHS_SDR104: | |
1339 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
1340 | break; | |
1341 | case MMC_TIMING_UHS_DDR50: | |
1342 | case MMC_TIMING_MMC_DDR52: | |
1343 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
1344 | break; | |
1345 | } | |
1346 | ||
1347 | /* | |
1348 | * When clock frequency is less than 100MHz, the feedback clock must be | |
1349 | * provided and DLL must not be used so that tuning can be skipped. To | |
1350 | * provide feedback clock, the mode selection can be any value less | |
1351 | * than 3'b011 in bits [2:0] of HOST CONTROL2 register. | |
1352 | */ | |
ff06ce41 VG |
1353 | if (host->clock <= CORE_FREQ_100MHZ) { |
1354 | if (uhs == MMC_TIMING_MMC_HS400 || | |
1355 | uhs == MMC_TIMING_MMC_HS200 || | |
1356 | uhs == MMC_TIMING_UHS_SDR104) | |
1357 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
1358 | /* | |
1359 | * DLL is not required for clock <= 100MHz | |
1360 | * Thus, make sure DLL it is disabled when not required | |
1361 | */ | |
bc99266b SL |
1362 | config = readl_relaxed(host->ioaddr + |
1363 | msm_offset->core_dll_config); | |
ff06ce41 | 1364 | config |= CORE_DLL_RST; |
bc99266b SL |
1365 | writel_relaxed(config, host->ioaddr + |
1366 | msm_offset->core_dll_config); | |
ff06ce41 | 1367 | |
bc99266b SL |
1368 | config = readl_relaxed(host->ioaddr + |
1369 | msm_offset->core_dll_config); | |
ff06ce41 | 1370 | config |= CORE_DLL_PDN; |
bc99266b SL |
1371 | writel_relaxed(config, host->ioaddr + |
1372 | msm_offset->core_dll_config); | |
ff06ce41 VG |
1373 | |
1374 | /* | |
1375 | * The DLL needs to be restored and CDCLP533 recalibrated | |
1376 | * when the clock frequency is set back to 400MHz. | |
1377 | */ | |
1378 | msm_host->calibration_done = false; | |
1379 | } | |
ee320674 RH |
1380 | |
1381 | dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", | |
1382 | mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); | |
1383 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
cc392c58 | 1384 | |
db9bd163 RH |
1385 | if (mmc->ios.timing == MMC_TIMING_MMC_HS400) |
1386 | sdhci_msm_hs400(host, &mmc->ios); | |
ee320674 RH |
1387 | } |
1388 | ||
b5c833b7 VB |
1389 | static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level) |
1390 | { | |
1391 | struct platform_device *pdev = msm_host->pdev; | |
1392 | int ret; | |
1393 | ||
1394 | if (level) | |
1395 | ret = pinctrl_pm_select_default_state(&pdev->dev); | |
1396 | else | |
1397 | ret = pinctrl_pm_select_sleep_state(&pdev->dev); | |
1398 | ||
1399 | return ret; | |
1400 | } | |
1401 | ||
92a21738 VB |
1402 | static int sdhci_msm_set_vmmc(struct mmc_host *mmc) |
1403 | { | |
1404 | if (IS_ERR(mmc->supply.vmmc)) | |
1405 | return 0; | |
1406 | ||
1407 | return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd); | |
1408 | } | |
1409 | ||
1410 | static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host, | |
1411 | struct mmc_host *mmc, bool level) | |
1412 | { | |
1413 | int ret; | |
1414 | struct mmc_ios ios; | |
1415 | ||
1416 | if (msm_host->vqmmc_enabled == level) | |
1417 | return 0; | |
1418 | ||
1419 | if (level) { | |
1420 | /* Set the IO voltage regulator to default voltage level */ | |
1421 | if (msm_host->caps_0 & CORE_3_0V_SUPPORT) | |
1422 | ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330; | |
1423 | else if (msm_host->caps_0 & CORE_1_8V_SUPPORT) | |
1424 | ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180; | |
1425 | ||
1426 | if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { | |
1427 | ret = mmc_regulator_set_vqmmc(mmc, &ios); | |
1428 | if (ret < 0) { | |
1429 | dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n", | |
1430 | mmc_hostname(mmc), ret); | |
1431 | goto out; | |
1432 | } | |
1433 | } | |
1434 | ret = regulator_enable(mmc->supply.vqmmc); | |
1435 | } else { | |
1436 | ret = regulator_disable(mmc->supply.vqmmc); | |
1437 | } | |
1438 | ||
1439 | if (ret) | |
1440 | dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n", | |
1441 | mmc_hostname(mmc), level ? "en":"dis", ret); | |
1442 | else | |
1443 | msm_host->vqmmc_enabled = level; | |
1444 | out: | |
1445 | return ret; | |
1446 | } | |
1447 | ||
1448 | static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host, | |
1449 | struct mmc_host *mmc, bool hpm) | |
1450 | { | |
1451 | int load, ret; | |
1452 | ||
1453 | load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0; | |
1454 | ret = regulator_set_load(mmc->supply.vqmmc, load); | |
1455 | if (ret) | |
1456 | dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n", | |
1457 | mmc_hostname(mmc), ret); | |
1458 | return ret; | |
1459 | } | |
1460 | ||
1461 | static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host, | |
1462 | struct mmc_host *mmc, bool level) | |
1463 | { | |
1464 | int ret; | |
1465 | bool always_on; | |
1466 | ||
1467 | if (IS_ERR(mmc->supply.vqmmc) || | |
1468 | (mmc->ios.power_mode == MMC_POWER_UNDEFINED)) | |
1469 | return 0; | |
1470 | /* | |
1471 | * For eMMC don't turn off Vqmmc, Instead just configure it in LPM | |
1472 | * and HPM modes by setting the corresponding load. | |
1473 | * | |
1474 | * Till eMMC is initialized (i.e. always_on == 0), just turn on/off | |
1475 | * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off | |
1476 | * gets invoked. Once eMMC is initialized (i.e. always_on == 1), | |
1477 | * Vqmmc should remain ON, So just set the load instead of turning it | |
1478 | * off/on. | |
1479 | */ | |
1480 | always_on = !mmc_card_is_removable(mmc) && | |
1481 | mmc->card && mmc_card_mmc(mmc->card); | |
1482 | ||
1483 | if (always_on) | |
1484 | ret = msm_config_vqmmc_mode(msm_host, mmc, level); | |
1485 | else | |
1486 | ret = msm_toggle_vqmmc(msm_host, mmc, level); | |
1487 | ||
1488 | return ret; | |
1489 | } | |
1490 | ||
c0309b38 VV |
1491 | static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host) |
1492 | { | |
1493 | init_waitqueue_head(&msm_host->pwr_irq_wait); | |
1494 | } | |
1495 | ||
1496 | static inline void sdhci_msm_complete_pwr_irq_wait( | |
1497 | struct sdhci_msm_host *msm_host) | |
1498 | { | |
1499 | wake_up(&msm_host->pwr_irq_wait); | |
1500 | } | |
1501 | ||
1502 | /* | |
1503 | * sdhci_msm_check_power_status API should be called when registers writes | |
1504 | * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens. | |
1505 | * To what state the register writes will change the IO lines should be passed | |
1506 | * as the argument req_type. This API will check whether the IO line's state | |
1507 | * is already the expected state and will wait for power irq only if | |
27d8a86a | 1508 | * power irq is expected to be triggered based on the current IO line state |
c0309b38 VV |
1509 | * and expected IO line state. |
1510 | */ | |
1511 | static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type) | |
1512 | { | |
1513 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1514 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1515 | bool done = false; | |
bc99266b SL |
1516 | u32 val = SWITCHABLE_SIGNALING_VOLTAGE; |
1517 | const struct sdhci_msm_offset *msm_offset = | |
1518 | msm_host->offset; | |
c0309b38 VV |
1519 | |
1520 | pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n", | |
1521 | mmc_hostname(host->mmc), __func__, req_type, | |
1522 | msm_host->curr_pwr_state, msm_host->curr_io_level); | |
1523 | ||
52884f8f BA |
1524 | /* |
1525 | * The power interrupt will not be generated for signal voltage | |
1526 | * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set. | |
bc99266b SL |
1527 | * Since sdhci-msm-v5, this bit has been removed and SW must consider |
1528 | * it as always set. | |
52884f8f | 1529 | */ |
bc99266b SL |
1530 | if (!msm_host->mci_removed) |
1531 | val = msm_host_readl(msm_host, host, | |
1532 | msm_offset->core_generics); | |
52884f8f BA |
1533 | if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) && |
1534 | !(val & SWITCHABLE_SIGNALING_VOLTAGE)) { | |
1535 | return; | |
1536 | } | |
1537 | ||
c0309b38 VV |
1538 | /* |
1539 | * The IRQ for request type IO High/LOW will be generated when - | |
1540 | * there is a state change in 1.8V enable bit (bit 3) of | |
1541 | * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0 | |
1542 | * which indicates 3.3V IO voltage. So, when MMC core layer tries | |
1543 | * to set it to 3.3V before card detection happens, the | |
1544 | * IRQ doesn't get triggered as there is no state change in this bit. | |
1545 | * The driver already handles this case by changing the IO voltage | |
1546 | * level to high as part of controller power up sequence. Hence, check | |
1547 | * for host->pwr to handle a case where IO voltage high request is | |
1548 | * issued even before controller power up. | |
1549 | */ | |
1550 | if ((req_type & REQ_IO_HIGH) && !host->pwr) { | |
1551 | pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n", | |
1552 | mmc_hostname(host->mmc), req_type); | |
1553 | return; | |
1554 | } | |
1555 | if ((req_type & msm_host->curr_pwr_state) || | |
1556 | (req_type & msm_host->curr_io_level)) | |
1557 | done = true; | |
1558 | /* | |
1559 | * This is needed here to handle cases where register writes will | |
1560 | * not change the current bus state or io level of the controller. | |
1561 | * In this case, no power irq will be triggerred and we should | |
1562 | * not wait. | |
1563 | */ | |
1564 | if (!done) { | |
1565 | if (!wait_event_timeout(msm_host->pwr_irq_wait, | |
1566 | msm_host->pwr_irq_flag, | |
1567 | msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS))) | |
9ccfa817 AB |
1568 | dev_warn(&msm_host->pdev->dev, |
1569 | "%s: pwr_irq for req: (%d) timed out\n", | |
1570 | mmc_hostname(host->mmc), req_type); | |
c0309b38 VV |
1571 | } |
1572 | pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), | |
1573 | __func__, req_type); | |
1574 | } | |
1575 | ||
401b2d06 ST |
1576 | static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host) |
1577 | { | |
1578 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1579 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
bc99266b SL |
1580 | const struct sdhci_msm_offset *msm_offset = |
1581 | msm_host->offset; | |
401b2d06 ST |
1582 | |
1583 | pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n", | |
bc99266b SL |
1584 | mmc_hostname(host->mmc), |
1585 | msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status), | |
1586 | msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask), | |
1587 | msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl)); | |
401b2d06 ST |
1588 | } |
1589 | ||
1590 | static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) | |
ad81d387 GD |
1591 | { |
1592 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1593 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
92a21738 | 1594 | struct mmc_host *mmc = host->mmc; |
ad81d387 | 1595 | u32 irq_status, irq_ack = 0; |
92a21738 | 1596 | int retry = 10, ret; |
ac06fba1 | 1597 | u32 pwr_state = 0, io_level = 0; |
5c132323 | 1598 | u32 config; |
bc99266b | 1599 | const struct sdhci_msm_offset *msm_offset = msm_host->offset; |
ad81d387 | 1600 | |
bc99266b SL |
1601 | irq_status = msm_host_readl(msm_host, host, |
1602 | msm_offset->core_pwrctl_status); | |
ad81d387 GD |
1603 | irq_status &= INT_MASK; |
1604 | ||
bc99266b SL |
1605 | msm_host_writel(msm_host, irq_status, host, |
1606 | msm_offset->core_pwrctl_clear); | |
ad81d387 | 1607 | |
401b2d06 ST |
1608 | /* |
1609 | * There is a rare HW scenario where the first clear pulse could be | |
1610 | * lost when actual reset and clear/read of status register is | |
1611 | * happening at a time. Hence, retry for at least 10 times to make | |
1612 | * sure status register is cleared. Otherwise, this will result in | |
1613 | * a spurious power IRQ resulting in system instability. | |
1614 | */ | |
bc99266b SL |
1615 | while (irq_status & msm_host_readl(msm_host, host, |
1616 | msm_offset->core_pwrctl_status)) { | |
401b2d06 ST |
1617 | if (retry == 0) { |
1618 | pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n", | |
1619 | mmc_hostname(host->mmc), irq_status); | |
1620 | sdhci_msm_dump_pwr_ctrl_regs(host); | |
1621 | WARN_ON(1); | |
1622 | break; | |
1623 | } | |
bc99266b SL |
1624 | msm_host_writel(msm_host, irq_status, host, |
1625 | msm_offset->core_pwrctl_clear); | |
401b2d06 ST |
1626 | retry--; |
1627 | udelay(10); | |
1628 | } | |
1629 | ||
c0309b38 VV |
1630 | /* Handle BUS ON/OFF*/ |
1631 | if (irq_status & CORE_PWRCTL_BUS_ON) { | |
1632 | pwr_state = REQ_BUS_ON; | |
1633 | io_level = REQ_IO_HIGH; | |
c0309b38 VV |
1634 | } |
1635 | if (irq_status & CORE_PWRCTL_BUS_OFF) { | |
1636 | pwr_state = REQ_BUS_OFF; | |
1637 | io_level = REQ_IO_LOW; | |
c0309b38 | 1638 | } |
92a21738 VB |
1639 | |
1640 | if (pwr_state) { | |
1641 | ret = sdhci_msm_set_vmmc(mmc); | |
1642 | if (!ret) | |
1643 | ret = sdhci_msm_set_vqmmc(msm_host, mmc, | |
1644 | pwr_state & REQ_BUS_ON); | |
b5c833b7 VB |
1645 | if (!ret) |
1646 | ret = sdhci_msm_set_pincfg(msm_host, | |
1647 | pwr_state & REQ_BUS_ON); | |
92a21738 VB |
1648 | if (!ret) |
1649 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; | |
1650 | else | |
1651 | irq_ack |= CORE_PWRCTL_BUS_FAIL; | |
1652 | } | |
1653 | ||
c0309b38 | 1654 | /* Handle IO LOW/HIGH */ |
92a21738 | 1655 | if (irq_status & CORE_PWRCTL_IO_LOW) |
c0309b38 | 1656 | io_level = REQ_IO_LOW; |
92a21738 VB |
1657 | |
1658 | if (irq_status & CORE_PWRCTL_IO_HIGH) | |
c0309b38 | 1659 | io_level = REQ_IO_HIGH; |
92a21738 VB |
1660 | |
1661 | if (io_level) | |
c0309b38 | 1662 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
92a21738 VB |
1663 | |
1664 | if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) { | |
1665 | ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios); | |
1666 | if (ret < 0) { | |
1667 | dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n", | |
1668 | mmc_hostname(mmc), ret, | |
1669 | mmc->ios.signal_voltage, mmc->ios.vdd, | |
1670 | irq_status); | |
1671 | irq_ack |= CORE_PWRCTL_IO_FAIL; | |
1672 | } | |
c0309b38 | 1673 | } |
ad81d387 GD |
1674 | |
1675 | /* | |
1676 | * The driver has to acknowledge the interrupt, switch voltages and | |
1677 | * report back if it succeded or not to this register. The voltage | |
1678 | * switches are handled by the sdhci core, so just report success. | |
1679 | */ | |
bc99266b SL |
1680 | msm_host_writel(msm_host, irq_ack, host, |
1681 | msm_offset->core_pwrctl_ctl); | |
401b2d06 | 1682 | |
5c132323 VV |
1683 | /* |
1684 | * If we don't have info regarding the voltage levels supported by | |
1685 | * regulators, don't change the IO PAD PWR SWITCH. | |
1686 | */ | |
1687 | if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { | |
1688 | u32 new_config; | |
1689 | /* | |
1690 | * We should unset IO PAD PWR switch only if the register write | |
1691 | * can set IO lines high and the regulator also switches to 3 V. | |
1692 | * Else, we should keep the IO PAD PWR switch set. | |
1693 | * This is applicable to certain targets where eMMC vccq supply | |
1694 | * is only 1.8V. In such targets, even during REQ_IO_HIGH, the | |
1695 | * IO PAD PWR switch must be kept set to reflect actual | |
1696 | * regulator voltage. This way, during initialization of | |
1697 | * controllers with only 1.8V, we will set the IO PAD bit | |
1698 | * without waiting for a REQ_IO_LOW. | |
1699 | */ | |
bc99266b SL |
1700 | config = readl_relaxed(host->ioaddr + |
1701 | msm_offset->core_vendor_spec); | |
5c132323 VV |
1702 | new_config = config; |
1703 | ||
1704 | if ((io_level & REQ_IO_HIGH) && | |
1705 | (msm_host->caps_0 & CORE_3_0V_SUPPORT)) | |
1706 | new_config &= ~CORE_IO_PAD_PWR_SWITCH; | |
1707 | else if ((io_level & REQ_IO_LOW) || | |
1708 | (msm_host->caps_0 & CORE_1_8V_SUPPORT)) | |
1709 | new_config |= CORE_IO_PAD_PWR_SWITCH; | |
1710 | ||
1711 | if (config ^ new_config) | |
bc99266b SL |
1712 | writel_relaxed(new_config, host->ioaddr + |
1713 | msm_offset->core_vendor_spec); | |
5c132323 VV |
1714 | } |
1715 | ||
c0309b38 VV |
1716 | if (pwr_state) |
1717 | msm_host->curr_pwr_state = pwr_state; | |
1718 | if (io_level) | |
1719 | msm_host->curr_io_level = io_level; | |
1720 | ||
92a21738 | 1721 | dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n", |
401b2d06 ST |
1722 | mmc_hostname(msm_host->mmc), __func__, irq, irq_status, |
1723 | irq_ack); | |
ad81d387 GD |
1724 | } |
1725 | ||
1726 | static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) | |
1727 | { | |
1728 | struct sdhci_host *host = (struct sdhci_host *)data; | |
c0309b38 VV |
1729 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
1730 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
ad81d387 | 1731 | |
401b2d06 | 1732 | sdhci_msm_handle_pwr_irq(host, irq); |
c0309b38 VV |
1733 | msm_host->pwr_irq_flag = 1; |
1734 | sdhci_msm_complete_pwr_irq_wait(msm_host); | |
1735 | ||
ad81d387 GD |
1736 | |
1737 | return IRQ_HANDLED; | |
1738 | } | |
1739 | ||
80031bde RH |
1740 | static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) |
1741 | { | |
1742 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1743 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
e4bf91f6 | 1744 | struct clk *core_clk = msm_host->bulk_clks[0].clk; |
80031bde | 1745 | |
e4bf91f6 | 1746 | return clk_round_rate(core_clk, ULONG_MAX); |
80031bde RH |
1747 | } |
1748 | ||
1749 | static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) | |
1750 | { | |
1751 | return SDHCI_MSM_MIN_CLOCK; | |
1752 | } | |
1753 | ||
abf4633a | 1754 | /* |
edc609fd RH |
1755 | * __sdhci_msm_set_clock - sdhci_msm clock control. |
1756 | * | |
1757 | * Description: | |
1758 | * MSM controller does not use internal divider and | |
1759 | * instead directly control the GCC clock as per | |
1760 | * HW recommendation. | |
1761 | **/ | |
30de038d | 1762 | static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) |
edc609fd RH |
1763 | { |
1764 | u16 clk; | |
edc609fd RH |
1765 | |
1766 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
1767 | ||
1768 | if (clock == 0) | |
1769 | return; | |
1770 | ||
1771 | /* | |
1772 | * MSM controller do not use clock divider. | |
1773 | * Thus read SDHCI_CLOCK_CONTROL and only enable | |
1774 | * clock with no divider value programmed. | |
1775 | */ | |
1776 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1777 | sdhci_enable_clk(host, clk); | |
1778 | } | |
1779 | ||
1780 | /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */ | |
1781 | static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) | |
1782 | { | |
1783 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1784 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
edc609fd RH |
1785 | |
1786 | if (!clock) { | |
f16c8fd4 | 1787 | host->mmc->actual_clock = msm_host->clk_rate = 0; |
edc609fd RH |
1788 | goto out; |
1789 | } | |
1790 | ||
b54aaa8a | 1791 | sdhci_msm_hc_select_mode(host); |
edc609fd | 1792 | |
0fb8a3d4 | 1793 | msm_set_clock_rate_for_bus_mode(host, clock); |
edc609fd RH |
1794 | out: |
1795 | __sdhci_msm_set_clock(host, clock); | |
1796 | } | |
1797 | ||
c93767cf EB |
1798 | /*****************************************************************************\ |
1799 | * * | |
1800 | * Inline Crypto Engine (ICE) support * | |
1801 | * * | |
1802 | \*****************************************************************************/ | |
1803 | ||
1804 | #ifdef CONFIG_MMC_CRYPTO | |
1805 | ||
1806 | #define AES_256_XTS_KEY_SIZE 64 | |
1807 | ||
1808 | /* QCOM ICE registers */ | |
1809 | ||
1810 | #define QCOM_ICE_REG_VERSION 0x0008 | |
1811 | ||
1812 | #define QCOM_ICE_REG_FUSE_SETTING 0x0010 | |
1813 | #define QCOM_ICE_FUSE_SETTING_MASK 0x1 | |
1814 | #define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2 | |
1815 | #define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4 | |
1816 | ||
1817 | #define QCOM_ICE_REG_BIST_STATUS 0x0070 | |
1818 | #define QCOM_ICE_BIST_STATUS_MASK 0xF0000000 | |
1819 | ||
1820 | #define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000 | |
1821 | ||
1822 | #define sdhci_msm_ice_writel(host, val, reg) \ | |
1823 | writel((val), (host)->ice_mem + (reg)) | |
1824 | #define sdhci_msm_ice_readl(host, reg) \ | |
1825 | readl((host)->ice_mem + (reg)) | |
1826 | ||
1827 | static bool sdhci_msm_ice_supported(struct sdhci_msm_host *msm_host) | |
1828 | { | |
1829 | struct device *dev = mmc_dev(msm_host->mmc); | |
1830 | u32 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_VERSION); | |
1831 | int major = regval >> 24; | |
1832 | int minor = (regval >> 16) & 0xFF; | |
1833 | int step = regval & 0xFFFF; | |
1834 | ||
1835 | /* For now this driver only supports ICE version 3. */ | |
1836 | if (major != 3) { | |
1837 | dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n", | |
1838 | major, minor, step); | |
1839 | return false; | |
1840 | } | |
1841 | ||
1842 | dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", | |
1843 | major, minor, step); | |
1844 | ||
1845 | /* If fuses are blown, ICE might not work in the standard way. */ | |
1846 | regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_FUSE_SETTING); | |
1847 | if (regval & (QCOM_ICE_FUSE_SETTING_MASK | | |
1848 | QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK | | |
1849 | QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) { | |
1850 | dev_warn(dev, "Fuses are blown; ICE is unusable!\n"); | |
1851 | return false; | |
1852 | } | |
1853 | return true; | |
1854 | } | |
1855 | ||
1856 | static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev) | |
1857 | { | |
1858 | return devm_clk_get(dev, "ice"); | |
1859 | } | |
1860 | ||
1861 | static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, | |
1862 | struct cqhci_host *cq_host) | |
1863 | { | |
1864 | struct mmc_host *mmc = msm_host->mmc; | |
1865 | struct device *dev = mmc_dev(mmc); | |
1866 | struct resource *res; | |
c93767cf EB |
1867 | |
1868 | if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS)) | |
1869 | return 0; | |
1870 | ||
1871 | res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM, | |
1872 | "ice"); | |
1873 | if (!res) { | |
1874 | dev_warn(dev, "ICE registers not found\n"); | |
1875 | goto disable; | |
1876 | } | |
1877 | ||
1878 | if (!qcom_scm_ice_available()) { | |
1879 | dev_warn(dev, "ICE SCM interface not found\n"); | |
1880 | goto disable; | |
1881 | } | |
1882 | ||
1883 | msm_host->ice_mem = devm_ioremap_resource(dev, res); | |
ffa4877c JY |
1884 | if (IS_ERR(msm_host->ice_mem)) |
1885 | return PTR_ERR(msm_host->ice_mem); | |
c93767cf EB |
1886 | |
1887 | if (!sdhci_msm_ice_supported(msm_host)) | |
1888 | goto disable; | |
1889 | ||
1890 | mmc->caps2 |= MMC_CAP2_CRYPTO; | |
1891 | return 0; | |
1892 | ||
1893 | disable: | |
1894 | dev_warn(dev, "Disabling inline encryption support\n"); | |
1895 | return 0; | |
1896 | } | |
1897 | ||
1898 | static void sdhci_msm_ice_low_power_mode_enable(struct sdhci_msm_host *msm_host) | |
1899 | { | |
1900 | u32 regval; | |
1901 | ||
1902 | regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL); | |
1903 | /* | |
1904 | * Enable low power mode sequence | |
1905 | * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0 | |
1906 | */ | |
1907 | regval |= 0x7000; | |
1908 | sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); | |
1909 | } | |
1910 | ||
1911 | static void sdhci_msm_ice_optimization_enable(struct sdhci_msm_host *msm_host) | |
1912 | { | |
1913 | u32 regval; | |
1914 | ||
1915 | /* ICE Optimizations Enable Sequence */ | |
1916 | regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL); | |
1917 | regval |= 0xD807100; | |
1918 | /* ICE HPG requires delay before writing */ | |
1919 | udelay(5); | |
1920 | sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); | |
1921 | udelay(5); | |
1922 | } | |
1923 | ||
1924 | /* | |
1925 | * Wait until the ICE BIST (built-in self-test) has completed. | |
1926 | * | |
1927 | * This may be necessary before ICE can be used. | |
1928 | * | |
1929 | * Note that we don't really care whether the BIST passed or failed; we really | |
1930 | * just want to make sure that it isn't still running. This is because (a) the | |
1931 | * BIST is a FIPS compliance thing that never fails in practice, (b) ICE is | |
1932 | * documented to reject crypto requests if the BIST fails, so we needn't do it | |
1933 | * in software too, and (c) properly testing storage encryption requires testing | |
1934 | * the full storage stack anyway, and not relying on hardware-level self-tests. | |
1935 | */ | |
1936 | static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host) | |
1937 | { | |
1938 | u32 regval; | |
1939 | int err; | |
1940 | ||
1941 | err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS, | |
1942 | regval, !(regval & QCOM_ICE_BIST_STATUS_MASK), | |
1943 | 50, 5000); | |
1944 | if (err) | |
1945 | dev_err(mmc_dev(msm_host->mmc), | |
1946 | "Timed out waiting for ICE self-test to complete\n"); | |
1947 | return err; | |
1948 | } | |
1949 | ||
1950 | static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) | |
1951 | { | |
1952 | if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) | |
1953 | return; | |
1954 | sdhci_msm_ice_low_power_mode_enable(msm_host); | |
1955 | sdhci_msm_ice_optimization_enable(msm_host); | |
1956 | sdhci_msm_ice_wait_bist_status(msm_host); | |
1957 | } | |
1958 | ||
1959 | static int __maybe_unused sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) | |
1960 | { | |
1961 | if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) | |
1962 | return 0; | |
1963 | return sdhci_msm_ice_wait_bist_status(msm_host); | |
1964 | } | |
1965 | ||
1966 | /* | |
1967 | * Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires | |
1968 | * vendor-specific SCM calls for this; it doesn't support the standard way. | |
1969 | */ | |
1970 | static int sdhci_msm_program_key(struct cqhci_host *cq_host, | |
1971 | const union cqhci_crypto_cfg_entry *cfg, | |
1972 | int slot) | |
1973 | { | |
1974 | struct device *dev = mmc_dev(cq_host->mmc); | |
1975 | union cqhci_crypto_cap_entry cap; | |
1976 | union { | |
1977 | u8 bytes[AES_256_XTS_KEY_SIZE]; | |
1978 | u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)]; | |
1979 | } key; | |
1980 | int i; | |
1981 | int err; | |
1982 | ||
1983 | if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE)) | |
1984 | return qcom_scm_ice_invalidate_key(slot); | |
1985 | ||
1986 | /* Only AES-256-XTS has been tested so far. */ | |
1987 | cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx]; | |
1988 | if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS || | |
1989 | cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) { | |
1990 | dev_err_ratelimited(dev, | |
1991 | "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n", | |
1992 | cap.algorithm_id, cap.key_size); | |
1993 | return -EINVAL; | |
1994 | } | |
1995 | ||
1996 | memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE); | |
1997 | ||
1998 | /* | |
1999 | * The SCM call byte-swaps the 32-bit words of the key. So we have to | |
2000 | * do the same, in order for the final key be correct. | |
2001 | */ | |
2002 | for (i = 0; i < ARRAY_SIZE(key.words); i++) | |
2003 | __cpu_to_be32s(&key.words[i]); | |
2004 | ||
2005 | err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE, | |
2006 | QCOM_SCM_ICE_CIPHER_AES_256_XTS, | |
2007 | cfg->data_unit_size); | |
2008 | memzero_explicit(&key, sizeof(key)); | |
2009 | return err; | |
2010 | } | |
2011 | #else /* CONFIG_MMC_CRYPTO */ | |
2012 | static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev) | |
2013 | { | |
2014 | return NULL; | |
2015 | } | |
2016 | ||
2017 | static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, | |
2018 | struct cqhci_host *cq_host) | |
2019 | { | |
2020 | return 0; | |
2021 | } | |
2022 | ||
2023 | static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) | |
2024 | { | |
2025 | } | |
2026 | ||
2027 | static inline int __maybe_unused | |
2028 | sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) | |
2029 | { | |
2030 | return 0; | |
2031 | } | |
2032 | #endif /* !CONFIG_MMC_CRYPTO */ | |
2033 | ||
87a8df0d RH |
2034 | /*****************************************************************************\ |
2035 | * * | |
2036 | * MSM Command Queue Engine (CQE) * | |
2037 | * * | |
2038 | \*****************************************************************************/ | |
2039 | ||
2040 | static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask) | |
2041 | { | |
2042 | int cmd_error = 0; | |
2043 | int data_error = 0; | |
2044 | ||
2045 | if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) | |
2046 | return intmask; | |
2047 | ||
2048 | cqhci_irq(host->mmc, intmask, cmd_error, data_error); | |
2049 | return 0; | |
2050 | } | |
2051 | ||
c93767cf EB |
2052 | static void sdhci_msm_cqe_enable(struct mmc_host *mmc) |
2053 | { | |
2054 | struct sdhci_host *host = mmc_priv(mmc); | |
2055 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
2056 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
2057 | ||
2058 | sdhci_cqe_enable(mmc); | |
2059 | sdhci_msm_ice_enable(msm_host); | |
2060 | } | |
2061 | ||
9051db38 | 2062 | static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery) |
87a8df0d RH |
2063 | { |
2064 | struct sdhci_host *host = mmc_priv(mmc); | |
2065 | unsigned long flags; | |
2066 | u32 ctrl; | |
2067 | ||
2068 | /* | |
2069 | * When CQE is halted, the legacy SDHCI path operates only | |
2070 | * on 16-byte descriptors in 64bit mode. | |
2071 | */ | |
2072 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
2073 | host->desc_sz = 16; | |
2074 | ||
2075 | spin_lock_irqsave(&host->lock, flags); | |
2076 | ||
2077 | /* | |
2078 | * During CQE command transfers, command complete bit gets latched. | |
2079 | * So s/w should clear command complete interrupt status when CQE is | |
2080 | * either halted or disabled. Otherwise unexpected SDCHI legacy | |
2081 | * interrupt gets triggered when CQE is halted/disabled. | |
2082 | */ | |
2083 | ctrl = sdhci_readl(host, SDHCI_INT_ENABLE); | |
2084 | ctrl |= SDHCI_INT_RESPONSE; | |
2085 | sdhci_writel(host, ctrl, SDHCI_INT_ENABLE); | |
2086 | sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS); | |
2087 | ||
2088 | spin_unlock_irqrestore(&host->lock, flags); | |
2089 | ||
2090 | sdhci_cqe_disable(mmc, recovery); | |
2091 | } | |
2092 | ||
67b13f3e SSB |
2093 | static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
2094 | { | |
2095 | u32 count, start = 15; | |
2096 | ||
2097 | __sdhci_set_timeout(host, cmd); | |
2098 | count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL); | |
2099 | /* | |
2100 | * Update software timeout value if its value is less than hardware data | |
2101 | * timeout value. Qcom SoC hardware data timeout value was calculated | |
2102 | * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock. | |
2103 | */ | |
2104 | if (cmd && cmd->data && host->clock > 400000 && | |
2105 | host->clock <= 50000000 && | |
2106 | ((1 << (count + start)) > (10 * host->clock))) | |
2107 | host->data_timeout = 22LL * NSEC_PER_SEC; | |
2108 | } | |
2109 | ||
87a8df0d | 2110 | static const struct cqhci_host_ops sdhci_msm_cqhci_ops = { |
c93767cf | 2111 | .enable = sdhci_msm_cqe_enable, |
87a8df0d | 2112 | .disable = sdhci_msm_cqe_disable, |
c93767cf EB |
2113 | #ifdef CONFIG_MMC_CRYPTO |
2114 | .program_key = sdhci_msm_program_key, | |
2115 | #endif | |
87a8df0d RH |
2116 | }; |
2117 | ||
2118 | static int sdhci_msm_cqe_add_host(struct sdhci_host *host, | |
2119 | struct platform_device *pdev) | |
2120 | { | |
2121 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
2122 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
2123 | struct cqhci_host *cq_host; | |
2124 | bool dma64; | |
2125 | u32 cqcfg; | |
2126 | int ret; | |
2127 | ||
2128 | /* | |
2129 | * When CQE is halted, SDHC operates only on 16byte ADMA descriptors. | |
2130 | * So ensure ADMA table is allocated for 16byte descriptors. | |
2131 | */ | |
2132 | if (host->caps & SDHCI_CAN_64BIT) | |
2133 | host->alloc_desc_sz = 16; | |
2134 | ||
2135 | ret = sdhci_setup_host(host); | |
2136 | if (ret) | |
2137 | return ret; | |
2138 | ||
2139 | cq_host = cqhci_pltfm_init(pdev); | |
2140 | if (IS_ERR(cq_host)) { | |
2141 | ret = PTR_ERR(cq_host); | |
2142 | dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret); | |
2143 | goto cleanup; | |
2144 | } | |
2145 | ||
2146 | msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; | |
2147 | cq_host->ops = &sdhci_msm_cqhci_ops; | |
2148 | ||
2149 | dma64 = host->flags & SDHCI_USE_64_BIT_DMA; | |
2150 | ||
c93767cf EB |
2151 | ret = sdhci_msm_ice_init(msm_host, cq_host); |
2152 | if (ret) | |
2153 | goto cleanup; | |
2154 | ||
87a8df0d RH |
2155 | ret = cqhci_init(cq_host, host->mmc, dma64); |
2156 | if (ret) { | |
2157 | dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n", | |
2158 | mmc_hostname(host->mmc), ret); | |
2159 | goto cleanup; | |
2160 | } | |
2161 | ||
2162 | /* Disable cqe reset due to cqe enable signal */ | |
2163 | cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1); | |
2164 | cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN; | |
2165 | cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1); | |
2166 | ||
2167 | /* | |
2168 | * SDHC expects 12byte ADMA descriptors till CQE is enabled. | |
2169 | * So limit desc_sz to 12 so that the data commands that are sent | |
2170 | * during card initialization (before CQE gets enabled) would | |
2171 | * get executed without any issues. | |
2172 | */ | |
2173 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
2174 | host->desc_sz = 12; | |
2175 | ||
2176 | ret = __sdhci_add_host(host); | |
2177 | if (ret) | |
2178 | goto cleanup; | |
2179 | ||
2180 | dev_info(&pdev->dev, "%s: CQE init: success\n", | |
2181 | mmc_hostname(host->mmc)); | |
2182 | return ret; | |
2183 | ||
2184 | cleanup: | |
2185 | sdhci_cleanup_host(host); | |
2186 | return ret; | |
2187 | } | |
2188 | ||
c0309b38 VV |
2189 | /* |
2190 | * Platform specific register write functions. This is so that, if any | |
2191 | * register write needs to be followed up by platform specific actions, | |
2192 | * they can be added here. These functions can go to sleep when writes | |
2193 | * to certain registers are done. | |
2194 | * These functions are relying on sdhci_set_ios not using spinlock. | |
2195 | */ | |
2196 | static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg) | |
2197 | { | |
2198 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
2199 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
2200 | u32 req_type = 0; | |
2201 | ||
2202 | switch (reg) { | |
2203 | case SDHCI_HOST_CONTROL2: | |
2204 | req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW : | |
2205 | REQ_IO_HIGH; | |
2206 | break; | |
2207 | case SDHCI_SOFTWARE_RESET: | |
2208 | if (host->pwr && (val & SDHCI_RESET_ALL)) | |
2209 | req_type = REQ_BUS_OFF; | |
2210 | break; | |
2211 | case SDHCI_POWER_CONTROL: | |
2212 | req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON; | |
2213 | break; | |
a89e7bcb LP |
2214 | case SDHCI_TRANSFER_MODE: |
2215 | msm_host->transfer_mode = val; | |
2216 | break; | |
2217 | case SDHCI_COMMAND: | |
2218 | if (!msm_host->use_cdr) | |
2219 | break; | |
2220 | if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && | |
2221 | SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 && | |
2222 | SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK) | |
2223 | sdhci_msm_set_cdr(host, true); | |
2224 | else | |
2225 | sdhci_msm_set_cdr(host, false); | |
2226 | break; | |
c0309b38 VV |
2227 | } |
2228 | ||
2229 | if (req_type) { | |
2230 | msm_host->pwr_irq_flag = 0; | |
2231 | /* | |
2232 | * Since this register write may trigger a power irq, ensure | |
2233 | * all previous register writes are complete by this point. | |
2234 | */ | |
2235 | mb(); | |
2236 | } | |
2237 | return req_type; | |
2238 | } | |
2239 | ||
2240 | /* This function may sleep*/ | |
2241 | static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg) | |
2242 | { | |
2243 | u32 req_type = 0; | |
2244 | ||
2245 | req_type = __sdhci_msm_check_write(host, val, reg); | |
2246 | writew_relaxed(val, host->ioaddr + reg); | |
2247 | ||
2248 | if (req_type) | |
2249 | sdhci_msm_check_power_status(host, req_type); | |
2250 | } | |
2251 | ||
2252 | /* This function may sleep*/ | |
2253 | static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg) | |
2254 | { | |
2255 | u32 req_type = 0; | |
2256 | ||
2257 | req_type = __sdhci_msm_check_write(host, val, reg); | |
2258 | ||
2259 | writeb_relaxed(val, host->ioaddr + reg); | |
2260 | ||
2261 | if (req_type) | |
2262 | sdhci_msm_check_power_status(host, req_type); | |
2263 | } | |
2264 | ||
ac06fba1 VV |
2265 | static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host) |
2266 | { | |
2267 | struct mmc_host *mmc = msm_host->mmc; | |
2268 | struct regulator *supply = mmc->supply.vqmmc; | |
5c132323 VV |
2269 | u32 caps = 0, config; |
2270 | struct sdhci_host *host = mmc_priv(mmc); | |
bc99266b | 2271 | const struct sdhci_msm_offset *msm_offset = msm_host->offset; |
ac06fba1 VV |
2272 | |
2273 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
2274 | if (regulator_is_supported_voltage(supply, 1700000, 1950000)) | |
2275 | caps |= CORE_1_8V_SUPPORT; | |
2276 | if (regulator_is_supported_voltage(supply, 2700000, 3600000)) | |
2277 | caps |= CORE_3_0V_SUPPORT; | |
2278 | ||
2279 | if (!caps) | |
2280 | pr_warn("%s: 1.8/3V not supported for vqmmc\n", | |
2281 | mmc_hostname(mmc)); | |
2282 | } | |
2283 | ||
5c132323 VV |
2284 | if (caps) { |
2285 | /* | |
2286 | * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH | |
2287 | * bit can be used as required later on. | |
2288 | */ | |
2289 | u32 io_level = msm_host->curr_io_level; | |
2290 | ||
bc99266b SL |
2291 | config = readl_relaxed(host->ioaddr + |
2292 | msm_offset->core_vendor_spec); | |
5c132323 VV |
2293 | config |= CORE_IO_PAD_PWR_SWITCH_EN; |
2294 | ||
2295 | if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT)) | |
2296 | config &= ~CORE_IO_PAD_PWR_SWITCH; | |
2297 | else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT)) | |
2298 | config |= CORE_IO_PAD_PWR_SWITCH; | |
2299 | ||
bc99266b SL |
2300 | writel_relaxed(config, |
2301 | host->ioaddr + msm_offset->core_vendor_spec); | |
5c132323 | 2302 | } |
ac06fba1 VV |
2303 | msm_host->caps_0 |= caps; |
2304 | pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps); | |
2305 | } | |
2306 | ||
5cf583f1 VB |
2307 | static void sdhci_msm_reset(struct sdhci_host *host, u8 mask) |
2308 | { | |
2309 | if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) | |
2310 | cqhci_deactivate(host->mmc); | |
2311 | sdhci_reset(host, mask); | |
2312 | } | |
2313 | ||
92a21738 VB |
2314 | static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host) |
2315 | { | |
2316 | int ret; | |
2317 | ||
2318 | ret = mmc_regulator_get_supply(msm_host->mmc); | |
2319 | if (ret) | |
2320 | return ret; | |
2321 | ||
2322 | sdhci_msm_set_regulator_caps(msm_host); | |
2323 | ||
2324 | return 0; | |
2325 | } | |
2326 | ||
2327 | static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc, | |
2328 | struct mmc_ios *ios) | |
2329 | { | |
2330 | struct sdhci_host *host = mmc_priv(mmc); | |
2331 | u16 ctrl, status; | |
2332 | ||
2333 | /* | |
2334 | * Signal Voltage Switching is only applicable for Host Controllers | |
2335 | * v3.00 and above. | |
2336 | */ | |
2337 | if (host->version < SDHCI_SPEC_300) | |
2338 | return 0; | |
2339 | ||
2340 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
2341 | ||
2342 | switch (ios->signal_voltage) { | |
2343 | case MMC_SIGNAL_VOLTAGE_330: | |
2344 | if (!(host->flags & SDHCI_SIGNALING_330)) | |
2345 | return -EINVAL; | |
2346 | ||
2347 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ | |
2348 | ctrl &= ~SDHCI_CTRL_VDD_180; | |
2349 | break; | |
2350 | case MMC_SIGNAL_VOLTAGE_180: | |
2351 | if (!(host->flags & SDHCI_SIGNALING_180)) | |
2352 | return -EINVAL; | |
2353 | ||
2354 | /* Enable 1.8V Signal Enable in the Host Control2 register */ | |
2355 | ctrl |= SDHCI_CTRL_VDD_180; | |
2356 | break; | |
2357 | ||
2358 | default: | |
2359 | return -EINVAL; | |
2360 | } | |
2361 | ||
2362 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
2363 | ||
2364 | /* Wait for 5ms */ | |
2365 | usleep_range(5000, 5500); | |
2366 | ||
2367 | /* regulator output should be stable within 5 ms */ | |
2368 | status = ctrl & SDHCI_CTRL_VDD_180; | |
2369 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
2370 | if ((ctrl & SDHCI_CTRL_VDD_180) == status) | |
2371 | return 0; | |
2372 | ||
2373 | dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n", | |
2374 | mmc_hostname(mmc)); | |
2375 | ||
2376 | return -EAGAIN; | |
2377 | } | |
2378 | ||
16d18d89 SG |
2379 | #define DRIVER_NAME "sdhci_msm" |
2380 | #define SDHCI_MSM_DUMP(f, x...) \ | |
2381 | pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) | |
2382 | ||
53e888d1 | 2383 | static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host) |
16d18d89 SG |
2384 | { |
2385 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
2386 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
2387 | const struct sdhci_msm_offset *msm_offset = msm_host->offset; | |
2388 | ||
2389 | SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n"); | |
2390 | ||
2391 | SDHCI_MSM_DUMP( | |
2392 | "DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n", | |
2393 | readl_relaxed(host->ioaddr + msm_offset->core_dll_status), | |
2394 | readl_relaxed(host->ioaddr + msm_offset->core_dll_config), | |
2395 | readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2)); | |
2396 | SDHCI_MSM_DUMP( | |
2397 | "DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n", | |
2398 | readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3), | |
2399 | readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl), | |
2400 | readl_relaxed(host->ioaddr + msm_offset->core_ddr_config)); | |
2401 | SDHCI_MSM_DUMP( | |
2402 | "Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n", | |
2403 | readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec), | |
2404 | readl_relaxed(host->ioaddr + | |
2405 | msm_offset->core_vendor_spec_func2), | |
2406 | readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3)); | |
2407 | } | |
2408 | ||
6ed4bb43 VV |
2409 | static const struct sdhci_msm_variant_ops mci_var_ops = { |
2410 | .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed, | |
2411 | .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed, | |
2412 | }; | |
2413 | ||
2414 | static const struct sdhci_msm_variant_ops v5_var_ops = { | |
2415 | .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed, | |
2416 | .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed, | |
2417 | }; | |
2418 | ||
2419 | static const struct sdhci_msm_variant_info sdhci_msm_mci_var = { | |
6ed4bb43 VV |
2420 | .var_ops = &mci_var_ops, |
2421 | .offset = &sdhci_msm_mci_offset, | |
2422 | }; | |
2423 | ||
2424 | static const struct sdhci_msm_variant_info sdhci_msm_v5_var = { | |
2425 | .mci_removed = true, | |
2426 | .var_ops = &v5_var_ops, | |
2427 | .offset = &sdhci_msm_v5_offset, | |
2428 | }; | |
2429 | ||
21f1e2d4 VB |
2430 | static const struct sdhci_msm_variant_info sdm845_sdhci_var = { |
2431 | .mci_removed = true, | |
2432 | .restore_dll_config = true, | |
2433 | .var_ops = &v5_var_ops, | |
2434 | .offset = &sdhci_msm_v5_offset, | |
2435 | }; | |
2436 | ||
0eb0d9f4 | 2437 | static const struct of_device_id sdhci_msm_dt_match[] = { |
bc99266b SL |
2438 | {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var}, |
2439 | {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var}, | |
21f1e2d4 | 2440 | {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var}, |
4dac686b | 2441 | {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var}, |
0eb0d9f4 GD |
2442 | {}, |
2443 | }; | |
2444 | ||
2445 | MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); | |
2446 | ||
a50396a4 | 2447 | static const struct sdhci_ops sdhci_msm_ops = { |
5cf583f1 | 2448 | .reset = sdhci_msm_reset, |
edc609fd | 2449 | .set_clock = sdhci_msm_set_clock, |
80031bde RH |
2450 | .get_min_clock = sdhci_msm_get_min_clock, |
2451 | .get_max_clock = sdhci_msm_get_max_clock, | |
ed1761d7 | 2452 | .set_bus_width = sdhci_set_bus_width, |
ee320674 | 2453 | .set_uhs_signaling = sdhci_msm_set_uhs_signaling, |
c0309b38 VV |
2454 | .write_w = sdhci_msm_writew, |
2455 | .write_b = sdhci_msm_writeb, | |
87a8df0d | 2456 | .irq = sdhci_msm_cqe_irq, |
16d18d89 | 2457 | .dump_vendor_regs = sdhci_msm_dump_vendor_regs, |
92a21738 | 2458 | .set_power = sdhci_set_power_noreg, |
67b13f3e | 2459 | .set_timeout = sdhci_msm_set_timeout, |
0eb0d9f4 GD |
2460 | }; |
2461 | ||
a50396a4 JZ |
2462 | static const struct sdhci_pltfm_data sdhci_msm_pdata = { |
2463 | .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | | |
a0e31428 | 2464 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
d863cb03 VB |
2465 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | |
2466 | SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, | |
2467 | ||
a0e31428 | 2468 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, |
a50396a4 JZ |
2469 | .ops = &sdhci_msm_ops, |
2470 | }; | |
2471 | ||
1dfbe3ff SG |
2472 | static inline void sdhci_msm_get_of_property(struct platform_device *pdev, |
2473 | struct sdhci_host *host) | |
2474 | { | |
2475 | struct device_node *node = pdev->dev.of_node; | |
2476 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
2477 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
2478 | ||
2479 | if (of_property_read_u32(node, "qcom,ddr-config", | |
2480 | &msm_host->ddr_config)) | |
2481 | msm_host->ddr_config = DDR_CONFIG_POR_VAL; | |
03591160 SG |
2482 | |
2483 | of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config); | |
1dfbe3ff SG |
2484 | } |
2485 | ||
3e5a8e84 SSB |
2486 | static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host) |
2487 | { | |
2488 | struct reset_control *reset; | |
2489 | int ret = 0; | |
2490 | ||
2491 | reset = reset_control_get_optional_exclusive(dev, NULL); | |
2492 | if (IS_ERR(reset)) | |
2493 | return dev_err_probe(dev, PTR_ERR(reset), | |
2494 | "unable to acquire core_reset\n"); | |
2495 | ||
2496 | if (!reset) | |
2497 | return ret; | |
2498 | ||
2499 | ret = reset_control_assert(reset); | |
2500 | if (ret) { | |
2501 | reset_control_put(reset); | |
2502 | return dev_err_probe(dev, ret, "core_reset assert failed\n"); | |
2503 | } | |
2504 | ||
2505 | /* | |
2506 | * The hardware requirement for delay between assert/deassert | |
2507 | * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to | |
2508 | * ~125us (4/32768). To be on the safe side add 200us delay. | |
2509 | */ | |
2510 | usleep_range(200, 210); | |
2511 | ||
2512 | ret = reset_control_deassert(reset); | |
2513 | if (ret) { | |
2514 | reset_control_put(reset); | |
2515 | return dev_err_probe(dev, ret, "core_reset deassert failed\n"); | |
2516 | } | |
2517 | ||
2518 | usleep_range(200, 210); | |
2519 | reset_control_put(reset); | |
2520 | ||
2521 | return ret; | |
2522 | } | |
1dfbe3ff | 2523 | |
0eb0d9f4 GD |
2524 | static int sdhci_msm_probe(struct platform_device *pdev) |
2525 | { | |
2526 | struct sdhci_host *host; | |
2527 | struct sdhci_pltfm_host *pltfm_host; | |
2528 | struct sdhci_msm_host *msm_host; | |
e4bf91f6 | 2529 | struct clk *clk; |
0eb0d9f4 | 2530 | int ret; |
3a3ad3e9 | 2531 | u16 host_version, core_minor; |
29301f40 | 2532 | u32 core_version, config; |
3a3ad3e9 | 2533 | u8 core_major; |
bc99266b SL |
2534 | const struct sdhci_msm_offset *msm_offset; |
2535 | const struct sdhci_msm_variant_info *var_info; | |
87a8df0d | 2536 | struct device_node *node = pdev->dev.of_node; |
0eb0d9f4 | 2537 | |
6f699531 | 2538 | host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); |
0eb0d9f4 GD |
2539 | if (IS_ERR(host)) |
2540 | return PTR_ERR(host); | |
2541 | ||
2a641e53 | 2542 | host->sdma_boundary = 0; |
0eb0d9f4 | 2543 | pltfm_host = sdhci_priv(host); |
6f699531 | 2544 | msm_host = sdhci_pltfm_priv(pltfm_host); |
0eb0d9f4 GD |
2545 | msm_host->mmc = host->mmc; |
2546 | msm_host->pdev = pdev; | |
2547 | ||
2548 | ret = mmc_of_parse(host->mmc); | |
2549 | if (ret) | |
2550 | goto pltfm_free; | |
2551 | ||
bc99266b SL |
2552 | /* |
2553 | * Based on the compatible string, load the required msm host info from | |
2554 | * the data associated with the version info. | |
2555 | */ | |
2556 | var_info = of_device_get_match_data(&pdev->dev); | |
2557 | ||
2558 | msm_host->mci_removed = var_info->mci_removed; | |
21f1e2d4 | 2559 | msm_host->restore_dll_config = var_info->restore_dll_config; |
bc99266b SL |
2560 | msm_host->var_ops = var_info->var_ops; |
2561 | msm_host->offset = var_info->offset; | |
2562 | ||
2563 | msm_offset = msm_host->offset; | |
2564 | ||
0eb0d9f4 | 2565 | sdhci_get_of_property(pdev); |
1dfbe3ff | 2566 | sdhci_msm_get_of_property(pdev, host); |
0eb0d9f4 | 2567 | |
abf270e5 RH |
2568 | msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; |
2569 | ||
3e5a8e84 SSB |
2570 | ret = sdhci_msm_gcc_reset(&pdev->dev, host); |
2571 | if (ret) | |
2572 | goto pltfm_free; | |
2573 | ||
0eb0d9f4 GD |
2574 | /* Setup SDCC bus voter clock. */ |
2575 | msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); | |
2576 | if (!IS_ERR(msm_host->bus_clk)) { | |
2577 | /* Vote for max. clk rate for max. performance */ | |
2578 | ret = clk_set_rate(msm_host->bus_clk, INT_MAX); | |
2579 | if (ret) | |
2580 | goto pltfm_free; | |
2581 | ret = clk_prepare_enable(msm_host->bus_clk); | |
2582 | if (ret) | |
2583 | goto pltfm_free; | |
2584 | } | |
2585 | ||
2586 | /* Setup main peripheral bus clock */ | |
e4bf91f6 BA |
2587 | clk = devm_clk_get(&pdev->dev, "iface"); |
2588 | if (IS_ERR(clk)) { | |
2589 | ret = PTR_ERR(clk); | |
2801b95e | 2590 | dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); |
0eb0d9f4 GD |
2591 | goto bus_clk_disable; |
2592 | } | |
e4bf91f6 | 2593 | msm_host->bulk_clks[1].clk = clk; |
0eb0d9f4 GD |
2594 | |
2595 | /* Setup SDC MMC clock */ | |
e4bf91f6 BA |
2596 | clk = devm_clk_get(&pdev->dev, "core"); |
2597 | if (IS_ERR(clk)) { | |
2598 | ret = PTR_ERR(clk); | |
0eb0d9f4 | 2599 | dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); |
e4bf91f6 | 2600 | goto bus_clk_disable; |
0eb0d9f4 | 2601 | } |
e4bf91f6 BA |
2602 | msm_host->bulk_clks[0].clk = clk; |
2603 | ||
b4fc8278 P |
2604 | /* Check for optional interconnect paths */ |
2605 | ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL); | |
2606 | if (ret) | |
2607 | goto bus_clk_disable; | |
2608 | ||
411281d2 YL |
2609 | ret = devm_pm_opp_set_clkname(&pdev->dev, "core"); |
2610 | if (ret) | |
0472f8d3 | 2611 | goto bus_clk_disable; |
0472f8d3 RN |
2612 | |
2613 | /* OPP table is optional */ | |
411281d2 | 2614 | ret = devm_pm_opp_of_add_table(&pdev->dev); |
91ca244b | 2615 | if (ret && ret != -ENODEV) { |
c2b613d0 | 2616 | dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); |
411281d2 | 2617 | goto bus_clk_disable; |
c2b613d0 | 2618 | } |
0472f8d3 | 2619 | |
e4bf91f6 | 2620 | /* Vote for maximum clock rate for maximum performance */ |
0472f8d3 | 2621 | ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX); |
e4bf91f6 BA |
2622 | if (ret) |
2623 | dev_warn(&pdev->dev, "core clock boost failed\n"); | |
2624 | ||
4946b3af BA |
2625 | clk = devm_clk_get(&pdev->dev, "cal"); |
2626 | if (IS_ERR(clk)) | |
2627 | clk = NULL; | |
2628 | msm_host->bulk_clks[2].clk = clk; | |
2629 | ||
2630 | clk = devm_clk_get(&pdev->dev, "sleep"); | |
2631 | if (IS_ERR(clk)) | |
2632 | clk = NULL; | |
2633 | msm_host->bulk_clks[3].clk = clk; | |
2634 | ||
c93767cf EB |
2635 | clk = sdhci_msm_ice_get_clk(&pdev->dev); |
2636 | if (IS_ERR(clk)) | |
2637 | clk = NULL; | |
2638 | msm_host->bulk_clks[4].clk = clk; | |
2639 | ||
e4bf91f6 BA |
2640 | ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), |
2641 | msm_host->bulk_clks); | |
2642 | if (ret) | |
411281d2 | 2643 | goto bus_clk_disable; |
0eb0d9f4 | 2644 | |
83736352 VG |
2645 | /* |
2646 | * xo clock is needed for FLL feature of cm_dll. | |
2647 | * In case if xo clock is not mentioned in DT, warn and proceed. | |
2648 | */ | |
2649 | msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); | |
2650 | if (IS_ERR(msm_host->xo_clk)) { | |
2651 | ret = PTR_ERR(msm_host->xo_clk); | |
2652 | dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); | |
2653 | } | |
2654 | ||
bc99266b | 2655 | if (!msm_host->mci_removed) { |
cb064b50 | 2656 | msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1); |
bc99266b | 2657 | if (IS_ERR(msm_host->core_mem)) { |
bc99266b SL |
2658 | ret = PTR_ERR(msm_host->core_mem); |
2659 | goto clk_disable; | |
2660 | } | |
0eb0d9f4 GD |
2661 | } |
2662 | ||
5574ddcc VG |
2663 | /* Reset the vendor spec register to power on reset state */ |
2664 | writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, | |
bc99266b SL |
2665 | host->ioaddr + msm_offset->core_vendor_spec); |
2666 | ||
2667 | if (!msm_host->mci_removed) { | |
2668 | /* Set HC_MODE_EN bit in HC_MODE register */ | |
2669 | msm_host_writel(msm_host, HC_MODE_EN, host, | |
2670 | msm_offset->core_hc_mode); | |
2671 | config = msm_host_readl(msm_host, host, | |
2672 | msm_offset->core_hc_mode); | |
2673 | config |= FF_CLK_SW_RST_DIS; | |
2674 | msm_host_writel(msm_host, config, host, | |
2675 | msm_offset->core_hc_mode); | |
2676 | } | |
ff06ce41 | 2677 | |
0eb0d9f4 GD |
2678 | host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); |
2679 | dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", | |
2680 | host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> | |
2681 | SDHCI_VENDOR_VER_SHIFT)); | |
2682 | ||
bc99266b SL |
2683 | core_version = msm_host_readl(msm_host, host, |
2684 | msm_offset->core_mci_version); | |
3a3ad3e9 GD |
2685 | core_major = (core_version & CORE_VERSION_MAJOR_MASK) >> |
2686 | CORE_VERSION_MAJOR_SHIFT; | |
2687 | core_minor = core_version & CORE_VERSION_MINOR_MASK; | |
2688 | dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", | |
2689 | core_version, core_major, core_minor); | |
2690 | ||
83736352 VG |
2691 | if (core_major == 1 && core_minor >= 0x42) |
2692 | msm_host->use_14lpp_dll_reset = true; | |
2693 | ||
02e4293d RH |
2694 | /* |
2695 | * SDCC 5 controller with major version 1, minor version 0x34 and later | |
2696 | * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL. | |
2697 | */ | |
2698 | if (core_major == 1 && core_minor < 0x34) | |
2699 | msm_host->use_cdclp533 = true; | |
2700 | ||
3a3ad3e9 GD |
2701 | /* |
2702 | * Support for some capabilities is not advertised by newer | |
2703 | * controller versions and must be explicitly enabled. | |
2704 | */ | |
2705 | if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { | |
29301f40 RH |
2706 | config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); |
2707 | config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; | |
2708 | writel_relaxed(config, host->ioaddr + | |
bc99266b | 2709 | msm_offset->core_vendor_spec_capabilities0); |
3a3ad3e9 GD |
2710 | } |
2711 | ||
fa56ac97 VB |
2712 | if (core_major == 1 && core_minor >= 0x49) |
2713 | msm_host->updated_ddr_cfg = true; | |
2714 | ||
8ffbfe43 DB |
2715 | if (core_major == 1 && core_minor >= 0x71) |
2716 | msm_host->uses_tassadar_dll = true; | |
2717 | ||
92a21738 VB |
2718 | ret = sdhci_msm_register_vreg(msm_host); |
2719 | if (ret) | |
2720 | goto clk_disable; | |
2721 | ||
c7ccee22 SJ |
2722 | /* |
2723 | * Power on reset state may trigger power irq if previous status of | |
2724 | * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq | |
2725 | * interrupt in GIC, any pending power irq interrupt should be | |
2726 | * acknowledged. Otherwise power irq interrupt handler would be | |
2727 | * fired prematurely. | |
2728 | */ | |
401b2d06 | 2729 | sdhci_msm_handle_pwr_irq(host, 0); |
c7ccee22 SJ |
2730 | |
2731 | /* | |
2732 | * Ensure that above writes are propogated before interrupt enablement | |
2733 | * in GIC. | |
2734 | */ | |
2735 | mb(); | |
2736 | ||
ad81d387 GD |
2737 | /* Setup IRQ for handling power/voltage tasks with PMIC */ |
2738 | msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); | |
2739 | if (msm_host->pwr_irq < 0) { | |
d1f63f0c | 2740 | ret = msm_host->pwr_irq; |
ad81d387 GD |
2741 | goto clk_disable; |
2742 | } | |
2743 | ||
c0309b38 | 2744 | sdhci_msm_init_pwr_irq_wait(msm_host); |
c7ccee22 | 2745 | /* Enable pwr irq interrupts */ |
bc99266b SL |
2746 | msm_host_writel(msm_host, INT_MASK, host, |
2747 | msm_offset->core_pwrctl_mask); | |
c7ccee22 | 2748 | |
ad81d387 GD |
2749 | ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, |
2750 | sdhci_msm_pwr_irq, IRQF_ONESHOT, | |
2751 | dev_name(&pdev->dev), host); | |
2752 | if (ret) { | |
2753 | dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); | |
2754 | goto clk_disable; | |
2755 | } | |
2756 | ||
9d8cb586 VB |
2757 | msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; |
2758 | ||
ed78a03d ST |
2759 | /* Set the timeout value to max possible */ |
2760 | host->max_timeout_count = 0xF; | |
2761 | ||
67e6db11 PG |
2762 | pm_runtime_get_noresume(&pdev->dev); |
2763 | pm_runtime_set_active(&pdev->dev); | |
2764 | pm_runtime_enable(&pdev->dev); | |
2765 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
2766 | MSM_MMC_AUTOSUSPEND_DELAY_MS); | |
2767 | pm_runtime_use_autosuspend(&pdev->dev); | |
2768 | ||
92a21738 VB |
2769 | host->mmc_host_ops.start_signal_voltage_switch = |
2770 | sdhci_msm_start_signal_voltage_switch; | |
4436c535 | 2771 | host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; |
87a8df0d RH |
2772 | if (of_property_read_bool(node, "supports-cqe")) |
2773 | ret = sdhci_msm_cqe_add_host(host, pdev); | |
2774 | else | |
2775 | ret = sdhci_add_host(host); | |
0eb0d9f4 | 2776 | if (ret) |
67e6db11 PG |
2777 | goto pm_runtime_disable; |
2778 | ||
2779 | pm_runtime_mark_last_busy(&pdev->dev); | |
2780 | pm_runtime_put_autosuspend(&pdev->dev); | |
0eb0d9f4 GD |
2781 | |
2782 | return 0; | |
2783 | ||
67e6db11 PG |
2784 | pm_runtime_disable: |
2785 | pm_runtime_disable(&pdev->dev); | |
2786 | pm_runtime_set_suspended(&pdev->dev); | |
2787 | pm_runtime_put_noidle(&pdev->dev); | |
0eb0d9f4 | 2788 | clk_disable: |
e4bf91f6 BA |
2789 | clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), |
2790 | msm_host->bulk_clks); | |
0eb0d9f4 GD |
2791 | bus_clk_disable: |
2792 | if (!IS_ERR(msm_host->bus_clk)) | |
2793 | clk_disable_unprepare(msm_host->bus_clk); | |
2794 | pltfm_free: | |
2795 | sdhci_pltfm_free(pdev); | |
2796 | return ret; | |
2797 | } | |
2798 | ||
2799 | static int sdhci_msm_remove(struct platform_device *pdev) | |
2800 | { | |
2801 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
2802 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
6f699531 | 2803 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); |
0eb0d9f4 GD |
2804 | int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == |
2805 | 0xffffffff); | |
2806 | ||
2807 | sdhci_remove_host(host, dead); | |
67e6db11 PG |
2808 | |
2809 | pm_runtime_get_sync(&pdev->dev); | |
2810 | pm_runtime_disable(&pdev->dev); | |
2811 | pm_runtime_put_noidle(&pdev->dev); | |
2812 | ||
e4bf91f6 BA |
2813 | clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), |
2814 | msm_host->bulk_clks); | |
0eb0d9f4 GD |
2815 | if (!IS_ERR(msm_host->bus_clk)) |
2816 | clk_disable_unprepare(msm_host->bus_clk); | |
6f699531 | 2817 | sdhci_pltfm_free(pdev); |
0eb0d9f4 GD |
2818 | return 0; |
2819 | } | |
2820 | ||
6809a5f7 | 2821 | static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev) |
67e6db11 PG |
2822 | { |
2823 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2824 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
2825 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
2826 | ||
0472f8d3 RN |
2827 | /* Drop the performance vote */ |
2828 | dev_pm_opp_set_rate(dev, 0); | |
e4bf91f6 BA |
2829 | clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), |
2830 | msm_host->bulk_clks); | |
67e6db11 PG |
2831 | |
2832 | return 0; | |
2833 | } | |
2834 | ||
6809a5f7 | 2835 | static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev) |
67e6db11 PG |
2836 | { |
2837 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2838 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
2839 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
21f1e2d4 | 2840 | int ret; |
67e6db11 | 2841 | |
21f1e2d4 | 2842 | ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), |
e4bf91f6 | 2843 | msm_host->bulk_clks); |
21f1e2d4 VB |
2844 | if (ret) |
2845 | return ret; | |
2846 | /* | |
2847 | * Whenever core-clock is gated dynamically, it's needed to | |
2848 | * restore the SDR DLL settings when the clock is ungated. | |
2849 | */ | |
c93767cf | 2850 | if (msm_host->restore_dll_config && msm_host->clk_rate) { |
0472f8d3 | 2851 | ret = sdhci_msm_restore_sdr_dll_config(host); |
c93767cf EB |
2852 | if (ret) |
2853 | return ret; | |
2854 | } | |
21f1e2d4 | 2855 | |
0472f8d3 RN |
2856 | dev_pm_opp_set_rate(dev, msm_host->clk_rate); |
2857 | ||
c93767cf | 2858 | return sdhci_msm_ice_resume(msm_host); |
67e6db11 | 2859 | } |
67e6db11 PG |
2860 | |
2861 | static const struct dev_pm_ops sdhci_msm_pm_ops = { | |
2862 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
2863 | pm_runtime_force_resume) | |
2864 | SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, | |
2865 | sdhci_msm_runtime_resume, | |
2866 | NULL) | |
2867 | }; | |
2868 | ||
0eb0d9f4 GD |
2869 | static struct platform_driver sdhci_msm_driver = { |
2870 | .probe = sdhci_msm_probe, | |
2871 | .remove = sdhci_msm_remove, | |
2872 | .driver = { | |
2873 | .name = "sdhci_msm", | |
0eb0d9f4 | 2874 | .of_match_table = sdhci_msm_dt_match, |
67e6db11 | 2875 | .pm = &sdhci_msm_pm_ops, |
8c98644b | 2876 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
0eb0d9f4 GD |
2877 | }, |
2878 | }; | |
2879 | ||
2880 | module_platform_driver(sdhci_msm_driver); | |
2881 | ||
2882 | MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver"); | |
2883 | MODULE_LICENSE("GPL v2"); |