Commit | Line | Data |
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0eb0d9f4 GD |
1 | /* |
2 | * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver | |
3 | * | |
4 | * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 and | |
8 | * only version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/of_device.h> | |
0eb0d9f4 | 19 | #include <linux/delay.h> |
415b5a75 | 20 | #include <linux/mmc/mmc.h> |
67e6db11 | 21 | #include <linux/pm_runtime.h> |
415b5a75 | 22 | #include <linux/slab.h> |
cc392c58 | 23 | #include <linux/iopoll.h> |
ac06fba1 | 24 | #include <linux/regulator/consumer.h> |
0eb0d9f4 GD |
25 | |
26 | #include "sdhci-pltfm.h" | |
27 | ||
3a3ad3e9 GD |
28 | #define CORE_MCI_VERSION 0x50 |
29 | #define CORE_VERSION_MAJOR_SHIFT 28 | |
30 | #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) | |
31 | #define CORE_VERSION_MINOR_MASK 0xff | |
32 | ||
52884f8f BA |
33 | #define CORE_MCI_GENERICS 0x70 |
34 | #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29) | |
35 | ||
0eb0d9f4 GD |
36 | #define CORE_HC_MODE 0x78 |
37 | #define HC_MODE_EN 0x1 | |
38 | #define CORE_POWER 0x0 | |
39 | #define CORE_SW_RST BIT(7) | |
ff06ce41 | 40 | #define FF_CLK_SW_RST_DIS BIT(13) |
0eb0d9f4 | 41 | |
ad81d387 GD |
42 | #define CORE_PWRCTL_STATUS 0xdc |
43 | #define CORE_PWRCTL_MASK 0xe0 | |
44 | #define CORE_PWRCTL_CLEAR 0xe4 | |
45 | #define CORE_PWRCTL_CTL 0xe8 | |
46 | #define CORE_PWRCTL_BUS_OFF BIT(0) | |
47 | #define CORE_PWRCTL_BUS_ON BIT(1) | |
48 | #define CORE_PWRCTL_IO_LOW BIT(2) | |
49 | #define CORE_PWRCTL_IO_HIGH BIT(3) | |
50 | #define CORE_PWRCTL_BUS_SUCCESS BIT(0) | |
51 | #define CORE_PWRCTL_IO_SUCCESS BIT(2) | |
52 | #define REQ_BUS_OFF BIT(0) | |
53 | #define REQ_BUS_ON BIT(1) | |
54 | #define REQ_IO_LOW BIT(2) | |
55 | #define REQ_IO_HIGH BIT(3) | |
56 | #define INT_MASK 0xf | |
415b5a75 GD |
57 | #define MAX_PHASES 16 |
58 | #define CORE_DLL_LOCK BIT(7) | |
02e4293d | 59 | #define CORE_DDR_DLL_LOCK BIT(11) |
415b5a75 GD |
60 | #define CORE_DLL_EN BIT(16) |
61 | #define CORE_CDR_EN BIT(17) | |
62 | #define CORE_CK_OUT_EN BIT(18) | |
63 | #define CORE_CDR_EXT_EN BIT(19) | |
64 | #define CORE_DLL_PDN BIT(29) | |
65 | #define CORE_DLL_RST BIT(30) | |
66 | #define CORE_DLL_CONFIG 0x100 | |
cc392c58 | 67 | #define CORE_CMD_DAT_TRACK_SEL BIT(0) |
415b5a75 GD |
68 | #define CORE_DLL_STATUS 0x108 |
69 | ||
83736352 | 70 | #define CORE_DLL_CONFIG_2 0x1b4 |
02e4293d | 71 | #define CORE_DDR_CAL_EN BIT(0) |
83736352 VG |
72 | #define CORE_FLL_CYCLE_CNT BIT(18) |
73 | #define CORE_DLL_CLOCK_DISABLE BIT(21) | |
74 | ||
415b5a75 | 75 | #define CORE_VENDOR_SPEC 0x10c |
5574ddcc | 76 | #define CORE_VENDOR_SPEC_POR_VAL 0xa1c |
415b5a75 | 77 | #define CORE_CLK_PWRSAVE BIT(1) |
ff06ce41 VG |
78 | #define CORE_HC_MCLK_SEL_DFLT (2 << 8) |
79 | #define CORE_HC_MCLK_SEL_HS400 (3 << 8) | |
80 | #define CORE_HC_MCLK_SEL_MASK (3 << 8) | |
5c132323 VV |
81 | #define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15) |
82 | #define CORE_IO_PAD_PWR_SWITCH (1 << 16) | |
ff06ce41 VG |
83 | #define CORE_HC_SELECT_IN_EN BIT(18) |
84 | #define CORE_HC_SELECT_IN_HS400 (6 << 19) | |
85 | #define CORE_HC_SELECT_IN_MASK (7 << 19) | |
415b5a75 | 86 | |
ac06fba1 VV |
87 | #define CORE_3_0V_SUPPORT (1 << 25) |
88 | #define CORE_1_8V_SUPPORT (1 << 26) | |
5c132323 | 89 | #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT) |
ac06fba1 | 90 | |
cc392c58 RH |
91 | #define CORE_CSR_CDC_CTLR_CFG0 0x130 |
92 | #define CORE_SW_TRIG_FULL_CALIB BIT(16) | |
93 | #define CORE_HW_AUTOCAL_ENA BIT(17) | |
94 | ||
95 | #define CORE_CSR_CDC_CTLR_CFG1 0x134 | |
96 | #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138 | |
97 | #define CORE_TIMER_ENA BIT(16) | |
98 | ||
99 | #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C | |
100 | #define CORE_CSR_CDC_REFCOUNT_CFG 0x140 | |
101 | #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144 | |
102 | #define CORE_CDC_OFFSET_CFG 0x14C | |
103 | #define CORE_CSR_CDC_DELAY_CFG 0x150 | |
104 | #define CORE_CDC_SLAVE_DDA_CFG 0x160 | |
105 | #define CORE_CSR_CDC_STATUS0 0x164 | |
106 | #define CORE_CALIBRATION_DONE BIT(0) | |
107 | ||
108 | #define CORE_CDC_ERROR_CODE_MASK 0x7000000 | |
109 | ||
110 | #define CORE_CSR_CDC_GEN_CFG 0x178 | |
111 | #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0) | |
112 | #define CORE_CDC_SWITCH_RC_EN BIT(1) | |
113 | ||
114 | #define CORE_DDR_200_CFG 0x184 | |
115 | #define CORE_CDC_T4_DLY_SEL BIT(0) | |
44bf2312 | 116 | #define CORE_CMDIN_RCLK_EN BIT(1) |
cc392c58 | 117 | #define CORE_START_CDC_TRAFFIC BIT(6) |
02e4293d RH |
118 | #define CORE_VENDOR_SPEC3 0x1b0 |
119 | #define CORE_PWRSAVE_DLL BIT(3) | |
120 | ||
121 | #define CORE_DDR_CONFIG 0x1b8 | |
122 | #define DDR_CONFIG_POR_VAL 0x80040853 | |
cc392c58 | 123 | |
3a3ad3e9 GD |
124 | #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c |
125 | ||
abf270e5 | 126 | #define INVALID_TUNING_PHASE -1 |
80031bde | 127 | #define SDHCI_MSM_MIN_CLOCK 400000 |
ff06ce41 | 128 | #define CORE_FREQ_100MHZ (100 * 1000 * 1000) |
80031bde | 129 | |
415b5a75 GD |
130 | #define CDR_SELEXT_SHIFT 20 |
131 | #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) | |
132 | #define CMUX_SHIFT_PHASE_SHIFT 24 | |
133 | #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) | |
134 | ||
67e6db11 | 135 | #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50 |
c0309b38 VV |
136 | |
137 | /* Timeout value to avoid infinite waiting for pwr_irq */ | |
138 | #define MSM_PWR_IRQ_TIMEOUT_MS 5000 | |
139 | ||
0eb0d9f4 GD |
140 | struct sdhci_msm_host { |
141 | struct platform_device *pdev; | |
142 | void __iomem *core_mem; /* MSM SDCC mapped address */ | |
ad81d387 | 143 | int pwr_irq; /* power irq */ |
0eb0d9f4 | 144 | struct clk *bus_clk; /* SDHC bus voter clock */ |
83736352 | 145 | struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ |
4946b3af | 146 | struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */ |
edc609fd | 147 | unsigned long clk_rate; |
0eb0d9f4 | 148 | struct mmc_host *mmc; |
83736352 | 149 | bool use_14lpp_dll_reset; |
ff06ce41 VG |
150 | bool tuning_done; |
151 | bool calibration_done; | |
abf270e5 | 152 | u8 saved_tuning_phase; |
02e4293d | 153 | bool use_cdclp533; |
c0309b38 VV |
154 | u32 curr_pwr_state; |
155 | u32 curr_io_level; | |
156 | wait_queue_head_t pwr_irq_wait; | |
157 | bool pwr_irq_flag; | |
ac06fba1 | 158 | u32 caps_0; |
0eb0d9f4 GD |
159 | }; |
160 | ||
0fb8a3d4 RH |
161 | static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host, |
162 | unsigned int clock) | |
163 | { | |
164 | struct mmc_ios ios = host->mmc->ios; | |
165 | /* | |
166 | * The SDHC requires internal clock frequency to be double the | |
167 | * actual clock that will be set for DDR mode. The controller | |
168 | * uses the faster clock(100/400MHz) for some of its parts and | |
169 | * send the actual required clock (50/200MHz) to the card. | |
170 | */ | |
171 | if (ios.timing == MMC_TIMING_UHS_DDR50 || | |
172 | ios.timing == MMC_TIMING_MMC_DDR52 || | |
d7507aa1 RH |
173 | ios.timing == MMC_TIMING_MMC_HS400 || |
174 | host->flags & SDHCI_HS400_TUNING) | |
0fb8a3d4 RH |
175 | clock *= 2; |
176 | return clock; | |
177 | } | |
178 | ||
179 | static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host, | |
180 | unsigned int clock) | |
181 | { | |
182 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
183 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
184 | struct mmc_ios curr_ios = host->mmc->ios; | |
e4bf91f6 | 185 | struct clk *core_clk = msm_host->bulk_clks[0].clk; |
0fb8a3d4 RH |
186 | int rc; |
187 | ||
188 | clock = msm_get_clock_rate_for_bus_mode(host, clock); | |
e4bf91f6 | 189 | rc = clk_set_rate(core_clk, clock); |
0fb8a3d4 RH |
190 | if (rc) { |
191 | pr_err("%s: Failed to set clock at rate %u at timing %d\n", | |
192 | mmc_hostname(host->mmc), clock, | |
193 | curr_ios.timing); | |
194 | return; | |
195 | } | |
196 | msm_host->clk_rate = clock; | |
197 | pr_debug("%s: Setting clock at rate %lu at timing %d\n", | |
e4bf91f6 | 198 | mmc_hostname(host->mmc), clk_get_rate(core_clk), |
0fb8a3d4 RH |
199 | curr_ios.timing); |
200 | } | |
201 | ||
0eb0d9f4 | 202 | /* Platform specific tuning */ |
415b5a75 GD |
203 | static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) |
204 | { | |
205 | u32 wait_cnt = 50; | |
206 | u8 ck_out_en; | |
207 | struct mmc_host *mmc = host->mmc; | |
208 | ||
209 | /* Poll for CK_OUT_EN bit. max. poll time = 50us */ | |
210 | ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & | |
211 | CORE_CK_OUT_EN); | |
212 | ||
213 | while (ck_out_en != poll) { | |
214 | if (--wait_cnt == 0) { | |
215 | dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", | |
216 | mmc_hostname(mmc), poll); | |
217 | return -ETIMEDOUT; | |
218 | } | |
219 | udelay(1); | |
220 | ||
221 | ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & | |
222 | CORE_CK_OUT_EN); | |
223 | } | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) | |
229 | { | |
230 | int rc; | |
231 | static const u8 grey_coded_phase_table[] = { | |
232 | 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, | |
233 | 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8 | |
234 | }; | |
235 | unsigned long flags; | |
236 | u32 config; | |
237 | struct mmc_host *mmc = host->mmc; | |
238 | ||
abf270e5 RH |
239 | if (phase > 0xf) |
240 | return -EINVAL; | |
241 | ||
415b5a75 GD |
242 | spin_lock_irqsave(&host->lock, flags); |
243 | ||
244 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
245 | config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); | |
246 | config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); | |
247 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
248 | ||
249 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ | |
250 | rc = msm_dll_poll_ck_out_en(host, 0); | |
251 | if (rc) | |
252 | goto err_out; | |
253 | ||
254 | /* | |
255 | * Write the selected DLL clock output phase (0 ... 15) | |
256 | * to CDR_SELEXT bit field of DLL_CONFIG register. | |
257 | */ | |
258 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
259 | config &= ~CDR_SELEXT_MASK; | |
260 | config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; | |
261 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
262 | ||
29301f40 RH |
263 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
264 | config |= CORE_CK_OUT_EN; | |
265 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 GD |
266 | |
267 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ | |
268 | rc = msm_dll_poll_ck_out_en(host, 1); | |
269 | if (rc) | |
270 | goto err_out; | |
271 | ||
272 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
273 | config |= CORE_CDR_EN; | |
274 | config &= ~CORE_CDR_EXT_EN; | |
275 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
276 | goto out; | |
277 | ||
278 | err_out: | |
279 | dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", | |
280 | mmc_hostname(mmc), phase); | |
281 | out: | |
282 | spin_unlock_irqrestore(&host->lock, flags); | |
283 | return rc; | |
284 | } | |
285 | ||
286 | /* | |
287 | * Find out the greatest range of consecuitive selected | |
288 | * DLL clock output phases that can be used as sampling | |
289 | * setting for SD3.0 UHS-I card read operation (in SDR104 | |
ff06ce41 VG |
290 | * timing mode) or for eMMC4.5 card read operation (in |
291 | * HS400/HS200 timing mode). | |
415b5a75 GD |
292 | * Select the 3/4 of the range and configure the DLL with the |
293 | * selected DLL clock output phase. | |
294 | */ | |
295 | ||
296 | static int msm_find_most_appropriate_phase(struct sdhci_host *host, | |
297 | u8 *phase_table, u8 total_phases) | |
298 | { | |
299 | int ret; | |
300 | u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; | |
301 | u8 phases_per_row[MAX_PHASES] = { 0 }; | |
302 | int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; | |
303 | int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; | |
304 | bool phase_0_found = false, phase_15_found = false; | |
305 | struct mmc_host *mmc = host->mmc; | |
306 | ||
307 | if (!total_phases || (total_phases > MAX_PHASES)) { | |
308 | dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", | |
309 | mmc_hostname(mmc), total_phases); | |
310 | return -EINVAL; | |
311 | } | |
312 | ||
313 | for (cnt = 0; cnt < total_phases; cnt++) { | |
314 | ranges[row_index][col_index] = phase_table[cnt]; | |
315 | phases_per_row[row_index] += 1; | |
316 | col_index++; | |
317 | ||
318 | if ((cnt + 1) == total_phases) { | |
319 | continue; | |
320 | /* check if next phase in phase_table is consecutive or not */ | |
321 | } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { | |
322 | row_index++; | |
323 | col_index = 0; | |
324 | } | |
325 | } | |
326 | ||
327 | if (row_index >= MAX_PHASES) | |
328 | return -EINVAL; | |
329 | ||
330 | /* Check if phase-0 is present in first valid window? */ | |
331 | if (!ranges[0][0]) { | |
332 | phase_0_found = true; | |
333 | phase_0_raw_index = 0; | |
334 | /* Check if cycle exist between 2 valid windows */ | |
335 | for (cnt = 1; cnt <= row_index; cnt++) { | |
336 | if (phases_per_row[cnt]) { | |
337 | for (i = 0; i < phases_per_row[cnt]; i++) { | |
338 | if (ranges[cnt][i] == 15) { | |
339 | phase_15_found = true; | |
340 | phase_15_raw_index = cnt; | |
341 | break; | |
342 | } | |
343 | } | |
344 | } | |
345 | } | |
346 | } | |
347 | ||
348 | /* If 2 valid windows form cycle then merge them as single window */ | |
349 | if (phase_0_found && phase_15_found) { | |
350 | /* number of phases in raw where phase 0 is present */ | |
351 | u8 phases_0 = phases_per_row[phase_0_raw_index]; | |
352 | /* number of phases in raw where phase 15 is present */ | |
353 | u8 phases_15 = phases_per_row[phase_15_raw_index]; | |
354 | ||
355 | if (phases_0 + phases_15 >= MAX_PHASES) | |
356 | /* | |
357 | * If there are more than 1 phase windows then total | |
358 | * number of phases in both the windows should not be | |
359 | * more than or equal to MAX_PHASES. | |
360 | */ | |
361 | return -EINVAL; | |
362 | ||
363 | /* Merge 2 cyclic windows */ | |
364 | i = phases_15; | |
365 | for (cnt = 0; cnt < phases_0; cnt++) { | |
366 | ranges[phase_15_raw_index][i] = | |
367 | ranges[phase_0_raw_index][cnt]; | |
368 | if (++i >= MAX_PHASES) | |
369 | break; | |
370 | } | |
371 | ||
372 | phases_per_row[phase_0_raw_index] = 0; | |
373 | phases_per_row[phase_15_raw_index] = phases_15 + phases_0; | |
374 | } | |
375 | ||
376 | for (cnt = 0; cnt <= row_index; cnt++) { | |
377 | if (phases_per_row[cnt] > curr_max) { | |
378 | curr_max = phases_per_row[cnt]; | |
379 | selected_row_index = cnt; | |
380 | } | |
381 | } | |
382 | ||
383 | i = (curr_max * 3) / 4; | |
384 | if (i) | |
385 | i--; | |
386 | ||
387 | ret = ranges[selected_row_index][i]; | |
388 | ||
389 | if (ret >= MAX_PHASES) { | |
390 | ret = -EINVAL; | |
391 | dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", | |
392 | mmc_hostname(mmc), ret); | |
393 | } | |
394 | ||
395 | return ret; | |
396 | } | |
397 | ||
398 | static inline void msm_cm_dll_set_freq(struct sdhci_host *host) | |
0eb0d9f4 | 399 | { |
415b5a75 GD |
400 | u32 mclk_freq = 0, config; |
401 | ||
402 | /* Program the MCLK value to MCLK_FREQ bit field */ | |
403 | if (host->clock <= 112000000) | |
404 | mclk_freq = 0; | |
405 | else if (host->clock <= 125000000) | |
406 | mclk_freq = 1; | |
407 | else if (host->clock <= 137000000) | |
408 | mclk_freq = 2; | |
409 | else if (host->clock <= 150000000) | |
410 | mclk_freq = 3; | |
411 | else if (host->clock <= 162000000) | |
412 | mclk_freq = 4; | |
413 | else if (host->clock <= 175000000) | |
414 | mclk_freq = 5; | |
415 | else if (host->clock <= 187000000) | |
416 | mclk_freq = 6; | |
417 | else if (host->clock <= 200000000) | |
418 | mclk_freq = 7; | |
419 | ||
420 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
421 | config &= ~CMUX_SHIFT_PHASE_MASK; | |
422 | config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT; | |
423 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
424 | } | |
425 | ||
426 | /* Initialize the DLL (Programmable Delay Line) */ | |
427 | static int msm_init_cm_dll(struct sdhci_host *host) | |
428 | { | |
429 | struct mmc_host *mmc = host->mmc; | |
83736352 VG |
430 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
431 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
415b5a75 GD |
432 | int wait_cnt = 50; |
433 | unsigned long flags; | |
29301f40 | 434 | u32 config; |
415b5a75 GD |
435 | |
436 | spin_lock_irqsave(&host->lock, flags); | |
437 | ||
0eb0d9f4 | 438 | /* |
415b5a75 GD |
439 | * Make sure that clock is always enabled when DLL |
440 | * tuning is in progress. Keeping PWRSAVE ON may | |
441 | * turn off the clock. | |
0eb0d9f4 | 442 | */ |
29301f40 RH |
443 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); |
444 | config &= ~CORE_CLK_PWRSAVE; | |
445 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
415b5a75 | 446 | |
83736352 VG |
447 | if (msm_host->use_14lpp_dll_reset) { |
448 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
449 | config &= ~CORE_CK_OUT_EN; | |
450 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
451 | ||
452 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); | |
453 | config |= CORE_DLL_CLOCK_DISABLE; | |
454 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); | |
455 | } | |
456 | ||
29301f40 RH |
457 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
458 | config |= CORE_DLL_RST; | |
459 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 | 460 | |
29301f40 RH |
461 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
462 | config |= CORE_DLL_PDN; | |
463 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 GD |
464 | msm_cm_dll_set_freq(host); |
465 | ||
83736352 VG |
466 | if (msm_host->use_14lpp_dll_reset && |
467 | !IS_ERR_OR_NULL(msm_host->xo_clk)) { | |
468 | u32 mclk_freq = 0; | |
469 | ||
470 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); | |
471 | config &= CORE_FLL_CYCLE_CNT; | |
472 | if (config) | |
473 | mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), | |
474 | clk_get_rate(msm_host->xo_clk)); | |
475 | else | |
476 | mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), | |
477 | clk_get_rate(msm_host->xo_clk)); | |
478 | ||
479 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); | |
480 | config &= ~(0xFF << 10); | |
481 | config |= mclk_freq << 10; | |
482 | ||
483 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); | |
484 | /* wait for 5us before enabling DLL clock */ | |
485 | udelay(5); | |
486 | } | |
487 | ||
29301f40 RH |
488 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
489 | config &= ~CORE_DLL_RST; | |
490 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 | 491 | |
29301f40 RH |
492 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
493 | config &= ~CORE_DLL_PDN; | |
494 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 | 495 | |
83736352 VG |
496 | if (msm_host->use_14lpp_dll_reset) { |
497 | msm_cm_dll_set_freq(host); | |
498 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); | |
499 | config &= ~CORE_DLL_CLOCK_DISABLE; | |
500 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); | |
501 | } | |
502 | ||
29301f40 RH |
503 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
504 | config |= CORE_DLL_EN; | |
505 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 | 506 | |
29301f40 RH |
507 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
508 | config |= CORE_CK_OUT_EN; | |
509 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 GD |
510 | |
511 | /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ | |
512 | while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & | |
513 | CORE_DLL_LOCK)) { | |
514 | /* max. wait for 50us sec for LOCK bit to be set */ | |
515 | if (--wait_cnt == 0) { | |
516 | dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", | |
517 | mmc_hostname(mmc)); | |
518 | spin_unlock_irqrestore(&host->lock, flags); | |
519 | return -ETIMEDOUT; | |
520 | } | |
521 | udelay(1); | |
522 | } | |
523 | ||
524 | spin_unlock_irqrestore(&host->lock, flags); | |
0eb0d9f4 GD |
525 | return 0; |
526 | } | |
527 | ||
b54aaa8a RH |
528 | static void msm_hc_select_default(struct sdhci_host *host) |
529 | { | |
530 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
531 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
532 | u32 config; | |
533 | ||
534 | if (!msm_host->use_cdclp533) { | |
535 | config = readl_relaxed(host->ioaddr + | |
536 | CORE_VENDOR_SPEC3); | |
537 | config &= ~CORE_PWRSAVE_DLL; | |
538 | writel_relaxed(config, host->ioaddr + | |
539 | CORE_VENDOR_SPEC3); | |
540 | } | |
541 | ||
542 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); | |
543 | config &= ~CORE_HC_MCLK_SEL_MASK; | |
544 | config |= CORE_HC_MCLK_SEL_DFLT; | |
545 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
546 | ||
547 | /* | |
548 | * Disable HC_SELECT_IN to be able to use the UHS mode select | |
549 | * configuration from Host Control2 register for all other | |
550 | * modes. | |
551 | * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field | |
552 | * in VENDOR_SPEC_FUNC | |
553 | */ | |
554 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); | |
555 | config &= ~CORE_HC_SELECT_IN_EN; | |
556 | config &= ~CORE_HC_SELECT_IN_MASK; | |
557 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
558 | ||
559 | /* | |
560 | * Make sure above writes impacting free running MCLK are completed | |
561 | * before changing the clk_rate at GCC. | |
562 | */ | |
563 | wmb(); | |
564 | } | |
565 | ||
566 | static void msm_hc_select_hs400(struct sdhci_host *host) | |
567 | { | |
568 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
569 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
44bf2312 | 570 | struct mmc_ios ios = host->mmc->ios; |
b54aaa8a RH |
571 | u32 config, dll_lock; |
572 | int rc; | |
573 | ||
574 | /* Select the divided clock (free running MCLK/2) */ | |
575 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); | |
576 | config &= ~CORE_HC_MCLK_SEL_MASK; | |
577 | config |= CORE_HC_MCLK_SEL_HS400; | |
578 | ||
579 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
580 | /* | |
581 | * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC | |
582 | * register | |
583 | */ | |
44bf2312 RH |
584 | if ((msm_host->tuning_done || ios.enhanced_strobe) && |
585 | !msm_host->calibration_done) { | |
b54aaa8a RH |
586 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); |
587 | config |= CORE_HC_SELECT_IN_HS400; | |
588 | config |= CORE_HC_SELECT_IN_EN; | |
589 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
590 | } | |
591 | if (!msm_host->clk_rate && !msm_host->use_cdclp533) { | |
592 | /* | |
593 | * Poll on DLL_LOCK or DDR_DLL_LOCK bits in | |
594 | * CORE_DLL_STATUS to be set. This should get set | |
595 | * within 15 us at 200 MHz. | |
596 | */ | |
597 | rc = readl_relaxed_poll_timeout(host->ioaddr + | |
598 | CORE_DLL_STATUS, | |
599 | dll_lock, | |
600 | (dll_lock & | |
601 | (CORE_DLL_LOCK | | |
602 | CORE_DDR_DLL_LOCK)), 10, | |
603 | 1000); | |
604 | if (rc == -ETIMEDOUT) | |
605 | pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n", | |
606 | mmc_hostname(host->mmc), dll_lock); | |
607 | } | |
608 | /* | |
609 | * Make sure above writes impacting free running MCLK are completed | |
610 | * before changing the clk_rate at GCC. | |
611 | */ | |
612 | wmb(); | |
613 | } | |
614 | ||
615 | /* | |
616 | * sdhci_msm_hc_select_mode :- In general all timing modes are | |
617 | * controlled via UHS mode select in Host Control2 register. | |
618 | * eMMC specific HS200/HS400 doesn't have their respective modes | |
619 | * defined here, hence we use these values. | |
620 | * | |
621 | * HS200 - SDR104 (Since they both are equivalent in functionality) | |
622 | * HS400 - This involves multiple configurations | |
623 | * Initially SDR104 - when tuning is required as HS200 | |
624 | * Then when switching to DDR @ 400MHz (HS400) we use | |
625 | * the vendor specific HC_SELECT_IN to control the mode. | |
626 | * | |
627 | * In addition to controlling the modes we also need to select the | |
628 | * correct input clock for DLL depending on the mode. | |
629 | * | |
630 | * HS400 - divided clock (free running MCLK/2) | |
631 | * All other modes - default (free running MCLK) | |
632 | */ | |
30de038d | 633 | static void sdhci_msm_hc_select_mode(struct sdhci_host *host) |
b54aaa8a RH |
634 | { |
635 | struct mmc_ios ios = host->mmc->ios; | |
636 | ||
d7507aa1 RH |
637 | if (ios.timing == MMC_TIMING_MMC_HS400 || |
638 | host->flags & SDHCI_HS400_TUNING) | |
b54aaa8a RH |
639 | msm_hc_select_hs400(host); |
640 | else | |
641 | msm_hc_select_default(host); | |
642 | } | |
643 | ||
cc392c58 RH |
644 | static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) |
645 | { | |
646 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
647 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
648 | u32 config, calib_done; | |
649 | int ret; | |
650 | ||
651 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
652 | ||
653 | /* | |
654 | * Retuning in HS400 (DDR mode) will fail, just reset the | |
655 | * tuning block and restore the saved tuning phase. | |
656 | */ | |
657 | ret = msm_init_cm_dll(host); | |
658 | if (ret) | |
659 | goto out; | |
660 | ||
661 | /* Set the selected phase in delay line hw block */ | |
662 | ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); | |
663 | if (ret) | |
664 | goto out; | |
665 | ||
666 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
667 | config |= CORE_CMD_DAT_TRACK_SEL; | |
668 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
669 | ||
670 | config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG); | |
671 | config &= ~CORE_CDC_T4_DLY_SEL; | |
672 | writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG); | |
673 | ||
674 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
675 | config &= ~CORE_CDC_SWITCH_BYPASS_OFF; | |
676 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
677 | ||
678 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
679 | config |= CORE_CDC_SWITCH_RC_EN; | |
680 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
681 | ||
682 | config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG); | |
683 | config &= ~CORE_START_CDC_TRAFFIC; | |
684 | writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG); | |
685 | ||
543c576d | 686 | /* Perform CDC Register Initialization Sequence */ |
cc392c58 RH |
687 | |
688 | writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
689 | writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); | |
690 | writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
691 | writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); | |
692 | writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); | |
693 | writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); | |
083c9aa0 | 694 | writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); |
cc392c58 RH |
695 | writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); |
696 | writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); | |
697 | ||
698 | /* CDC HW Calibration */ | |
699 | ||
700 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
701 | config |= CORE_SW_TRIG_FULL_CALIB; | |
702 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
703 | ||
704 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
705 | config &= ~CORE_SW_TRIG_FULL_CALIB; | |
706 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
707 | ||
708 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
709 | config |= CORE_HW_AUTOCAL_ENA; | |
710 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
711 | ||
712 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
713 | config |= CORE_TIMER_ENA; | |
714 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
715 | ||
716 | ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, | |
717 | calib_done, | |
718 | (calib_done & CORE_CALIBRATION_DONE), | |
719 | 1, 50); | |
720 | ||
721 | if (ret == -ETIMEDOUT) { | |
722 | pr_err("%s: %s: CDC calibration was not completed\n", | |
723 | mmc_hostname(host->mmc), __func__); | |
724 | goto out; | |
725 | } | |
726 | ||
727 | ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) | |
728 | & CORE_CDC_ERROR_CODE_MASK; | |
729 | if (ret) { | |
730 | pr_err("%s: %s: CDC error code %d\n", | |
731 | mmc_hostname(host->mmc), __func__, ret); | |
732 | ret = -EINVAL; | |
733 | goto out; | |
734 | } | |
735 | ||
736 | config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG); | |
737 | config |= CORE_START_CDC_TRAFFIC; | |
738 | writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG); | |
739 | out: | |
740 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
741 | __func__, ret); | |
742 | return ret; | |
743 | } | |
744 | ||
02e4293d RH |
745 | static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) |
746 | { | |
44bf2312 | 747 | struct mmc_host *mmc = host->mmc; |
02e4293d RH |
748 | u32 dll_status, config; |
749 | int ret; | |
750 | ||
751 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
752 | ||
753 | /* | |
754 | * Currently the CORE_DDR_CONFIG register defaults to desired | |
755 | * configuration on reset. Currently reprogramming the power on | |
756 | * reset (POR) value in case it might have been modified by | |
757 | * bootloaders. In the future, if this changes, then the desired | |
758 | * values will need to be programmed appropriately. | |
759 | */ | |
760 | writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG); | |
761 | ||
44bf2312 RH |
762 | if (mmc->ios.enhanced_strobe) { |
763 | config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG); | |
764 | config |= CORE_CMDIN_RCLK_EN; | |
765 | writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG); | |
766 | } | |
767 | ||
02e4293d RH |
768 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); |
769 | config |= CORE_DDR_CAL_EN; | |
770 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); | |
771 | ||
772 | ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS, | |
773 | dll_status, | |
774 | (dll_status & CORE_DDR_DLL_LOCK), | |
775 | 10, 1000); | |
776 | ||
777 | if (ret == -ETIMEDOUT) { | |
778 | pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n", | |
779 | mmc_hostname(host->mmc), __func__); | |
780 | goto out; | |
781 | } | |
782 | ||
783 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3); | |
784 | config |= CORE_PWRSAVE_DLL; | |
785 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3); | |
786 | ||
787 | /* | |
788 | * Drain writebuffer to ensure above DLL calibration | |
789 | * and PWRSAVE DLL is enabled. | |
790 | */ | |
791 | wmb(); | |
792 | out: | |
793 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
794 | __func__, ret); | |
795 | return ret; | |
796 | } | |
797 | ||
798 | static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) | |
799 | { | |
800 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
801 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
44bf2312 | 802 | struct mmc_host *mmc = host->mmc; |
02e4293d RH |
803 | int ret; |
804 | u32 config; | |
805 | ||
806 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
807 | ||
808 | /* | |
809 | * Retuning in HS400 (DDR mode) will fail, just reset the | |
810 | * tuning block and restore the saved tuning phase. | |
811 | */ | |
812 | ret = msm_init_cm_dll(host); | |
813 | if (ret) | |
814 | goto out; | |
815 | ||
44bf2312 RH |
816 | if (!mmc->ios.enhanced_strobe) { |
817 | /* Set the selected phase in delay line hw block */ | |
818 | ret = msm_config_cm_dll_phase(host, | |
819 | msm_host->saved_tuning_phase); | |
820 | if (ret) | |
821 | goto out; | |
822 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
823 | config |= CORE_CMD_DAT_TRACK_SEL; | |
824 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
825 | } | |
02e4293d | 826 | |
02e4293d RH |
827 | if (msm_host->use_cdclp533) |
828 | ret = sdhci_msm_cdclp533_calibration(host); | |
829 | else | |
830 | ret = sdhci_msm_cm_dll_sdc4_calibration(host); | |
831 | out: | |
832 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
833 | __func__, ret); | |
834 | return ret; | |
835 | } | |
836 | ||
4436c535 | 837 | static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) |
415b5a75 | 838 | { |
4436c535 | 839 | struct sdhci_host *host = mmc_priv(mmc); |
415b5a75 | 840 | int tuning_seq_cnt = 3; |
33d73935 | 841 | u8 phase, tuned_phases[16], tuned_phase_cnt = 0; |
415b5a75 | 842 | int rc; |
415b5a75 | 843 | struct mmc_ios ios = host->mmc->ios; |
abf270e5 RH |
844 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
845 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
415b5a75 GD |
846 | |
847 | /* | |
848 | * Tuning is required for SDR104, HS200 and HS400 cards and | |
849 | * if clock frequency is greater than 100MHz in these modes. | |
850 | */ | |
ff06ce41 VG |
851 | if (host->clock <= CORE_FREQ_100MHZ || |
852 | !(ios.timing == MMC_TIMING_MMC_HS400 || | |
853 | ios.timing == MMC_TIMING_MMC_HS200 || | |
854 | ios.timing == MMC_TIMING_UHS_SDR104)) | |
415b5a75 GD |
855 | return 0; |
856 | ||
d7507aa1 RH |
857 | /* |
858 | * For HS400 tuning in HS200 timing requires: | |
859 | * - select MCLK/2 in VENDOR_SPEC | |
860 | * - program MCLK to 400MHz (or nearest supported) in GCC | |
861 | */ | |
862 | if (host->flags & SDHCI_HS400_TUNING) { | |
863 | sdhci_msm_hc_select_mode(host); | |
864 | msm_set_clock_rate_for_bus_mode(host, ios.clock); | |
4436c535 | 865 | host->flags &= ~SDHCI_HS400_TUNING; |
d7507aa1 RH |
866 | } |
867 | ||
415b5a75 GD |
868 | retry: |
869 | /* First of all reset the tuning block */ | |
870 | rc = msm_init_cm_dll(host); | |
871 | if (rc) | |
33d73935 | 872 | return rc; |
415b5a75 GD |
873 | |
874 | phase = 0; | |
875 | do { | |
415b5a75 GD |
876 | /* Set the phase in delay line hw block */ |
877 | rc = msm_config_cm_dll_phase(host, phase); | |
878 | if (rc) | |
33d73935 | 879 | return rc; |
415b5a75 | 880 | |
abf270e5 | 881 | msm_host->saved_tuning_phase = phase; |
9979dbe5 | 882 | rc = mmc_send_tuning(mmc, opcode, NULL); |
33d73935 | 883 | if (!rc) { |
415b5a75 GD |
884 | /* Tuning is successful at this tuning point */ |
885 | tuned_phases[tuned_phase_cnt++] = phase; | |
886 | dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", | |
887 | mmc_hostname(mmc), phase); | |
888 | } | |
889 | } while (++phase < ARRAY_SIZE(tuned_phases)); | |
890 | ||
891 | if (tuned_phase_cnt) { | |
892 | rc = msm_find_most_appropriate_phase(host, tuned_phases, | |
893 | tuned_phase_cnt); | |
894 | if (rc < 0) | |
33d73935 | 895 | return rc; |
415b5a75 GD |
896 | else |
897 | phase = rc; | |
898 | ||
899 | /* | |
900 | * Finally set the selected phase in delay | |
901 | * line hw block. | |
902 | */ | |
903 | rc = msm_config_cm_dll_phase(host, phase); | |
904 | if (rc) | |
33d73935 | 905 | return rc; |
415b5a75 GD |
906 | dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", |
907 | mmc_hostname(mmc), phase); | |
908 | } else { | |
909 | if (--tuning_seq_cnt) | |
910 | goto retry; | |
911 | /* Tuning failed */ | |
912 | dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", | |
913 | mmc_hostname(mmc)); | |
914 | rc = -EIO; | |
915 | } | |
916 | ||
ff06ce41 VG |
917 | if (!rc) |
918 | msm_host->tuning_done = true; | |
415b5a75 GD |
919 | return rc; |
920 | } | |
921 | ||
db9bd163 RH |
922 | /* |
923 | * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation. | |
44bf2312 | 924 | * This needs to be done for both tuning and enhanced_strobe mode. |
db9bd163 RH |
925 | * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz |
926 | * fixed feedback clock is used. | |
927 | */ | |
928 | static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios) | |
929 | { | |
930 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
931 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
932 | int ret; | |
933 | ||
934 | if (host->clock > CORE_FREQ_100MHZ && | |
44bf2312 RH |
935 | (msm_host->tuning_done || ios->enhanced_strobe) && |
936 | !msm_host->calibration_done) { | |
db9bd163 RH |
937 | ret = sdhci_msm_hs400_dll_calibration(host); |
938 | if (!ret) | |
939 | msm_host->calibration_done = true; | |
940 | else | |
941 | pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n", | |
942 | mmc_hostname(host->mmc), ret); | |
943 | } | |
944 | } | |
945 | ||
ee320674 RH |
946 | static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, |
947 | unsigned int uhs) | |
948 | { | |
949 | struct mmc_host *mmc = host->mmc; | |
ff06ce41 VG |
950 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
951 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
ee320674 | 952 | u16 ctrl_2; |
ff06ce41 | 953 | u32 config; |
ee320674 RH |
954 | |
955 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
956 | /* Select Bus Speed Mode for host */ | |
957 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
958 | switch (uhs) { | |
959 | case MMC_TIMING_UHS_SDR12: | |
960 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
961 | break; | |
962 | case MMC_TIMING_UHS_SDR25: | |
963 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
964 | break; | |
965 | case MMC_TIMING_UHS_SDR50: | |
966 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
967 | break; | |
ff06ce41 | 968 | case MMC_TIMING_MMC_HS400: |
ee320674 RH |
969 | case MMC_TIMING_MMC_HS200: |
970 | case MMC_TIMING_UHS_SDR104: | |
971 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
972 | break; | |
973 | case MMC_TIMING_UHS_DDR50: | |
974 | case MMC_TIMING_MMC_DDR52: | |
975 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
976 | break; | |
977 | } | |
978 | ||
979 | /* | |
980 | * When clock frequency is less than 100MHz, the feedback clock must be | |
981 | * provided and DLL must not be used so that tuning can be skipped. To | |
982 | * provide feedback clock, the mode selection can be any value less | |
983 | * than 3'b011 in bits [2:0] of HOST CONTROL2 register. | |
984 | */ | |
ff06ce41 VG |
985 | if (host->clock <= CORE_FREQ_100MHZ) { |
986 | if (uhs == MMC_TIMING_MMC_HS400 || | |
987 | uhs == MMC_TIMING_MMC_HS200 || | |
988 | uhs == MMC_TIMING_UHS_SDR104) | |
989 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
990 | /* | |
991 | * DLL is not required for clock <= 100MHz | |
992 | * Thus, make sure DLL it is disabled when not required | |
993 | */ | |
994 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
995 | config |= CORE_DLL_RST; | |
996 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
997 | ||
998 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
999 | config |= CORE_DLL_PDN; | |
1000 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
1001 | ||
1002 | /* | |
1003 | * The DLL needs to be restored and CDCLP533 recalibrated | |
1004 | * when the clock frequency is set back to 400MHz. | |
1005 | */ | |
1006 | msm_host->calibration_done = false; | |
1007 | } | |
ee320674 RH |
1008 | |
1009 | dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", | |
1010 | mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); | |
1011 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
cc392c58 | 1012 | |
db9bd163 RH |
1013 | if (mmc->ios.timing == MMC_TIMING_MMC_HS400) |
1014 | sdhci_msm_hs400(host, &mmc->ios); | |
ee320674 RH |
1015 | } |
1016 | ||
c0309b38 VV |
1017 | static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host) |
1018 | { | |
1019 | init_waitqueue_head(&msm_host->pwr_irq_wait); | |
1020 | } | |
1021 | ||
1022 | static inline void sdhci_msm_complete_pwr_irq_wait( | |
1023 | struct sdhci_msm_host *msm_host) | |
1024 | { | |
1025 | wake_up(&msm_host->pwr_irq_wait); | |
1026 | } | |
1027 | ||
1028 | /* | |
1029 | * sdhci_msm_check_power_status API should be called when registers writes | |
1030 | * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens. | |
1031 | * To what state the register writes will change the IO lines should be passed | |
1032 | * as the argument req_type. This API will check whether the IO line's state | |
1033 | * is already the expected state and will wait for power irq only if | |
1034 | * power irq is expected to be trigerred based on the current IO line state | |
1035 | * and expected IO line state. | |
1036 | */ | |
1037 | static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type) | |
1038 | { | |
1039 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1040 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1041 | bool done = false; | |
52884f8f | 1042 | u32 val; |
c0309b38 VV |
1043 | |
1044 | pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n", | |
1045 | mmc_hostname(host->mmc), __func__, req_type, | |
1046 | msm_host->curr_pwr_state, msm_host->curr_io_level); | |
1047 | ||
52884f8f BA |
1048 | /* |
1049 | * The power interrupt will not be generated for signal voltage | |
1050 | * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set. | |
1051 | */ | |
1052 | val = readl(msm_host->core_mem + CORE_MCI_GENERICS); | |
1053 | if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) && | |
1054 | !(val & SWITCHABLE_SIGNALING_VOLTAGE)) { | |
1055 | return; | |
1056 | } | |
1057 | ||
c0309b38 VV |
1058 | /* |
1059 | * The IRQ for request type IO High/LOW will be generated when - | |
1060 | * there is a state change in 1.8V enable bit (bit 3) of | |
1061 | * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0 | |
1062 | * which indicates 3.3V IO voltage. So, when MMC core layer tries | |
1063 | * to set it to 3.3V before card detection happens, the | |
1064 | * IRQ doesn't get triggered as there is no state change in this bit. | |
1065 | * The driver already handles this case by changing the IO voltage | |
1066 | * level to high as part of controller power up sequence. Hence, check | |
1067 | * for host->pwr to handle a case where IO voltage high request is | |
1068 | * issued even before controller power up. | |
1069 | */ | |
1070 | if ((req_type & REQ_IO_HIGH) && !host->pwr) { | |
1071 | pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n", | |
1072 | mmc_hostname(host->mmc), req_type); | |
1073 | return; | |
1074 | } | |
1075 | if ((req_type & msm_host->curr_pwr_state) || | |
1076 | (req_type & msm_host->curr_io_level)) | |
1077 | done = true; | |
1078 | /* | |
1079 | * This is needed here to handle cases where register writes will | |
1080 | * not change the current bus state or io level of the controller. | |
1081 | * In this case, no power irq will be triggerred and we should | |
1082 | * not wait. | |
1083 | */ | |
1084 | if (!done) { | |
1085 | if (!wait_event_timeout(msm_host->pwr_irq_wait, | |
1086 | msm_host->pwr_irq_flag, | |
1087 | msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS))) | |
9ccfa817 AB |
1088 | dev_warn(&msm_host->pdev->dev, |
1089 | "%s: pwr_irq for req: (%d) timed out\n", | |
1090 | mmc_hostname(host->mmc), req_type); | |
c0309b38 VV |
1091 | } |
1092 | pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), | |
1093 | __func__, req_type); | |
1094 | } | |
1095 | ||
401b2d06 ST |
1096 | static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host) |
1097 | { | |
1098 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1099 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1100 | ||
1101 | pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n", | |
1102 | mmc_hostname(host->mmc), | |
1103 | readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS), | |
1104 | readl_relaxed(msm_host->core_mem + CORE_PWRCTL_MASK), | |
1105 | readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL)); | |
1106 | } | |
1107 | ||
1108 | static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) | |
ad81d387 GD |
1109 | { |
1110 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1111 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1112 | u32 irq_status, irq_ack = 0; | |
401b2d06 | 1113 | int retry = 10; |
ac06fba1 | 1114 | u32 pwr_state = 0, io_level = 0; |
5c132323 | 1115 | u32 config; |
ad81d387 GD |
1116 | |
1117 | irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); | |
1118 | irq_status &= INT_MASK; | |
1119 | ||
1120 | writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR); | |
1121 | ||
401b2d06 ST |
1122 | /* |
1123 | * There is a rare HW scenario where the first clear pulse could be | |
1124 | * lost when actual reset and clear/read of status register is | |
1125 | * happening at a time. Hence, retry for at least 10 times to make | |
1126 | * sure status register is cleared. Otherwise, this will result in | |
1127 | * a spurious power IRQ resulting in system instability. | |
1128 | */ | |
1129 | while (irq_status & readl_relaxed(msm_host->core_mem + | |
1130 | CORE_PWRCTL_STATUS)) { | |
1131 | if (retry == 0) { | |
1132 | pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n", | |
1133 | mmc_hostname(host->mmc), irq_status); | |
1134 | sdhci_msm_dump_pwr_ctrl_regs(host); | |
1135 | WARN_ON(1); | |
1136 | break; | |
1137 | } | |
1138 | writel_relaxed(irq_status, | |
1139 | msm_host->core_mem + CORE_PWRCTL_CLEAR); | |
1140 | retry--; | |
1141 | udelay(10); | |
1142 | } | |
1143 | ||
c0309b38 VV |
1144 | /* Handle BUS ON/OFF*/ |
1145 | if (irq_status & CORE_PWRCTL_BUS_ON) { | |
1146 | pwr_state = REQ_BUS_ON; | |
1147 | io_level = REQ_IO_HIGH; | |
1148 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; | |
1149 | } | |
1150 | if (irq_status & CORE_PWRCTL_BUS_OFF) { | |
1151 | pwr_state = REQ_BUS_OFF; | |
1152 | io_level = REQ_IO_LOW; | |
ad81d387 | 1153 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
c0309b38 VV |
1154 | } |
1155 | /* Handle IO LOW/HIGH */ | |
1156 | if (irq_status & CORE_PWRCTL_IO_LOW) { | |
1157 | io_level = REQ_IO_LOW; | |
ad81d387 | 1158 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
c0309b38 VV |
1159 | } |
1160 | if (irq_status & CORE_PWRCTL_IO_HIGH) { | |
1161 | io_level = REQ_IO_HIGH; | |
1162 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; | |
1163 | } | |
ad81d387 GD |
1164 | |
1165 | /* | |
1166 | * The driver has to acknowledge the interrupt, switch voltages and | |
1167 | * report back if it succeded or not to this register. The voltage | |
1168 | * switches are handled by the sdhci core, so just report success. | |
1169 | */ | |
1170 | writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL); | |
401b2d06 | 1171 | |
5c132323 VV |
1172 | /* |
1173 | * If we don't have info regarding the voltage levels supported by | |
1174 | * regulators, don't change the IO PAD PWR SWITCH. | |
1175 | */ | |
1176 | if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { | |
1177 | u32 new_config; | |
1178 | /* | |
1179 | * We should unset IO PAD PWR switch only if the register write | |
1180 | * can set IO lines high and the regulator also switches to 3 V. | |
1181 | * Else, we should keep the IO PAD PWR switch set. | |
1182 | * This is applicable to certain targets where eMMC vccq supply | |
1183 | * is only 1.8V. In such targets, even during REQ_IO_HIGH, the | |
1184 | * IO PAD PWR switch must be kept set to reflect actual | |
1185 | * regulator voltage. This way, during initialization of | |
1186 | * controllers with only 1.8V, we will set the IO PAD bit | |
1187 | * without waiting for a REQ_IO_LOW. | |
1188 | */ | |
1189 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); | |
1190 | new_config = config; | |
1191 | ||
1192 | if ((io_level & REQ_IO_HIGH) && | |
1193 | (msm_host->caps_0 & CORE_3_0V_SUPPORT)) | |
1194 | new_config &= ~CORE_IO_PAD_PWR_SWITCH; | |
1195 | else if ((io_level & REQ_IO_LOW) || | |
1196 | (msm_host->caps_0 & CORE_1_8V_SUPPORT)) | |
1197 | new_config |= CORE_IO_PAD_PWR_SWITCH; | |
1198 | ||
1199 | if (config ^ new_config) | |
1200 | writel_relaxed(new_config, | |
1201 | host->ioaddr + CORE_VENDOR_SPEC); | |
1202 | } | |
1203 | ||
c0309b38 VV |
1204 | if (pwr_state) |
1205 | msm_host->curr_pwr_state = pwr_state; | |
1206 | if (io_level) | |
1207 | msm_host->curr_io_level = io_level; | |
1208 | ||
401b2d06 ST |
1209 | pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n", |
1210 | mmc_hostname(msm_host->mmc), __func__, irq, irq_status, | |
1211 | irq_ack); | |
ad81d387 GD |
1212 | } |
1213 | ||
1214 | static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) | |
1215 | { | |
1216 | struct sdhci_host *host = (struct sdhci_host *)data; | |
c0309b38 VV |
1217 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
1218 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
ad81d387 | 1219 | |
401b2d06 | 1220 | sdhci_msm_handle_pwr_irq(host, irq); |
c0309b38 VV |
1221 | msm_host->pwr_irq_flag = 1; |
1222 | sdhci_msm_complete_pwr_irq_wait(msm_host); | |
1223 | ||
ad81d387 GD |
1224 | |
1225 | return IRQ_HANDLED; | |
1226 | } | |
1227 | ||
80031bde RH |
1228 | static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) |
1229 | { | |
1230 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1231 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
e4bf91f6 | 1232 | struct clk *core_clk = msm_host->bulk_clks[0].clk; |
80031bde | 1233 | |
e4bf91f6 | 1234 | return clk_round_rate(core_clk, ULONG_MAX); |
80031bde RH |
1235 | } |
1236 | ||
1237 | static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) | |
1238 | { | |
1239 | return SDHCI_MSM_MIN_CLOCK; | |
1240 | } | |
1241 | ||
edc609fd RH |
1242 | /** |
1243 | * __sdhci_msm_set_clock - sdhci_msm clock control. | |
1244 | * | |
1245 | * Description: | |
1246 | * MSM controller does not use internal divider and | |
1247 | * instead directly control the GCC clock as per | |
1248 | * HW recommendation. | |
1249 | **/ | |
30de038d | 1250 | static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) |
edc609fd RH |
1251 | { |
1252 | u16 clk; | |
1253 | /* | |
1254 | * Keep actual_clock as zero - | |
1255 | * - since there is no divider used so no need of having actual_clock. | |
1256 | * - MSM controller uses SDCLK for data timeout calculation. If | |
1257 | * actual_clock is zero, host->clock is taken for calculation. | |
1258 | */ | |
1259 | host->mmc->actual_clock = 0; | |
1260 | ||
1261 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
1262 | ||
1263 | if (clock == 0) | |
1264 | return; | |
1265 | ||
1266 | /* | |
1267 | * MSM controller do not use clock divider. | |
1268 | * Thus read SDHCI_CLOCK_CONTROL and only enable | |
1269 | * clock with no divider value programmed. | |
1270 | */ | |
1271 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1272 | sdhci_enable_clk(host, clk); | |
1273 | } | |
1274 | ||
1275 | /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */ | |
1276 | static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) | |
1277 | { | |
1278 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1279 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
edc609fd RH |
1280 | |
1281 | if (!clock) { | |
1282 | msm_host->clk_rate = clock; | |
1283 | goto out; | |
1284 | } | |
1285 | ||
b54aaa8a | 1286 | sdhci_msm_hc_select_mode(host); |
edc609fd | 1287 | |
0fb8a3d4 | 1288 | msm_set_clock_rate_for_bus_mode(host, clock); |
edc609fd RH |
1289 | out: |
1290 | __sdhci_msm_set_clock(host, clock); | |
1291 | } | |
1292 | ||
c0309b38 VV |
1293 | /* |
1294 | * Platform specific register write functions. This is so that, if any | |
1295 | * register write needs to be followed up by platform specific actions, | |
1296 | * they can be added here. These functions can go to sleep when writes | |
1297 | * to certain registers are done. | |
1298 | * These functions are relying on sdhci_set_ios not using spinlock. | |
1299 | */ | |
1300 | static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg) | |
1301 | { | |
1302 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1303 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1304 | u32 req_type = 0; | |
1305 | ||
1306 | switch (reg) { | |
1307 | case SDHCI_HOST_CONTROL2: | |
1308 | req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW : | |
1309 | REQ_IO_HIGH; | |
1310 | break; | |
1311 | case SDHCI_SOFTWARE_RESET: | |
1312 | if (host->pwr && (val & SDHCI_RESET_ALL)) | |
1313 | req_type = REQ_BUS_OFF; | |
1314 | break; | |
1315 | case SDHCI_POWER_CONTROL: | |
1316 | req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON; | |
1317 | break; | |
1318 | } | |
1319 | ||
1320 | if (req_type) { | |
1321 | msm_host->pwr_irq_flag = 0; | |
1322 | /* | |
1323 | * Since this register write may trigger a power irq, ensure | |
1324 | * all previous register writes are complete by this point. | |
1325 | */ | |
1326 | mb(); | |
1327 | } | |
1328 | return req_type; | |
1329 | } | |
1330 | ||
1331 | /* This function may sleep*/ | |
1332 | static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg) | |
1333 | { | |
1334 | u32 req_type = 0; | |
1335 | ||
1336 | req_type = __sdhci_msm_check_write(host, val, reg); | |
1337 | writew_relaxed(val, host->ioaddr + reg); | |
1338 | ||
1339 | if (req_type) | |
1340 | sdhci_msm_check_power_status(host, req_type); | |
1341 | } | |
1342 | ||
1343 | /* This function may sleep*/ | |
1344 | static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg) | |
1345 | { | |
1346 | u32 req_type = 0; | |
1347 | ||
1348 | req_type = __sdhci_msm_check_write(host, val, reg); | |
1349 | ||
1350 | writeb_relaxed(val, host->ioaddr + reg); | |
1351 | ||
1352 | if (req_type) | |
1353 | sdhci_msm_check_power_status(host, req_type); | |
1354 | } | |
1355 | ||
ac06fba1 VV |
1356 | static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host) |
1357 | { | |
1358 | struct mmc_host *mmc = msm_host->mmc; | |
1359 | struct regulator *supply = mmc->supply.vqmmc; | |
5c132323 VV |
1360 | u32 caps = 0, config; |
1361 | struct sdhci_host *host = mmc_priv(mmc); | |
ac06fba1 VV |
1362 | |
1363 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
1364 | if (regulator_is_supported_voltage(supply, 1700000, 1950000)) | |
1365 | caps |= CORE_1_8V_SUPPORT; | |
1366 | if (regulator_is_supported_voltage(supply, 2700000, 3600000)) | |
1367 | caps |= CORE_3_0V_SUPPORT; | |
1368 | ||
1369 | if (!caps) | |
1370 | pr_warn("%s: 1.8/3V not supported for vqmmc\n", | |
1371 | mmc_hostname(mmc)); | |
1372 | } | |
1373 | ||
5c132323 VV |
1374 | if (caps) { |
1375 | /* | |
1376 | * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH | |
1377 | * bit can be used as required later on. | |
1378 | */ | |
1379 | u32 io_level = msm_host->curr_io_level; | |
1380 | ||
1381 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); | |
1382 | config |= CORE_IO_PAD_PWR_SWITCH_EN; | |
1383 | ||
1384 | if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT)) | |
1385 | config &= ~CORE_IO_PAD_PWR_SWITCH; | |
1386 | else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT)) | |
1387 | config |= CORE_IO_PAD_PWR_SWITCH; | |
1388 | ||
1389 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
1390 | } | |
ac06fba1 VV |
1391 | msm_host->caps_0 |= caps; |
1392 | pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps); | |
1393 | } | |
1394 | ||
0eb0d9f4 GD |
1395 | static const struct of_device_id sdhci_msm_dt_match[] = { |
1396 | { .compatible = "qcom,sdhci-msm-v4" }, | |
1397 | {}, | |
1398 | }; | |
1399 | ||
1400 | MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); | |
1401 | ||
a50396a4 | 1402 | static const struct sdhci_ops sdhci_msm_ops = { |
ed1761d7 | 1403 | .reset = sdhci_reset, |
edc609fd | 1404 | .set_clock = sdhci_msm_set_clock, |
80031bde RH |
1405 | .get_min_clock = sdhci_msm_get_min_clock, |
1406 | .get_max_clock = sdhci_msm_get_max_clock, | |
ed1761d7 | 1407 | .set_bus_width = sdhci_set_bus_width, |
ee320674 | 1408 | .set_uhs_signaling = sdhci_msm_set_uhs_signaling, |
c0309b38 VV |
1409 | .write_w = sdhci_msm_writew, |
1410 | .write_b = sdhci_msm_writeb, | |
0eb0d9f4 GD |
1411 | }; |
1412 | ||
a50396a4 JZ |
1413 | static const struct sdhci_pltfm_data sdhci_msm_pdata = { |
1414 | .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | | |
a0e31428 RH |
1415 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
1416 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
1417 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
a50396a4 JZ |
1418 | .ops = &sdhci_msm_ops, |
1419 | }; | |
1420 | ||
0eb0d9f4 GD |
1421 | static int sdhci_msm_probe(struct platform_device *pdev) |
1422 | { | |
1423 | struct sdhci_host *host; | |
1424 | struct sdhci_pltfm_host *pltfm_host; | |
1425 | struct sdhci_msm_host *msm_host; | |
1426 | struct resource *core_memres; | |
e4bf91f6 | 1427 | struct clk *clk; |
0eb0d9f4 | 1428 | int ret; |
3a3ad3e9 | 1429 | u16 host_version, core_minor; |
29301f40 | 1430 | u32 core_version, config; |
3a3ad3e9 | 1431 | u8 core_major; |
0eb0d9f4 | 1432 | |
6f699531 | 1433 | host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); |
0eb0d9f4 GD |
1434 | if (IS_ERR(host)) |
1435 | return PTR_ERR(host); | |
1436 | ||
2a641e53 | 1437 | host->sdma_boundary = 0; |
0eb0d9f4 | 1438 | pltfm_host = sdhci_priv(host); |
6f699531 | 1439 | msm_host = sdhci_pltfm_priv(pltfm_host); |
0eb0d9f4 GD |
1440 | msm_host->mmc = host->mmc; |
1441 | msm_host->pdev = pdev; | |
1442 | ||
1443 | ret = mmc_of_parse(host->mmc); | |
1444 | if (ret) | |
1445 | goto pltfm_free; | |
1446 | ||
1447 | sdhci_get_of_property(pdev); | |
1448 | ||
abf270e5 RH |
1449 | msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; |
1450 | ||
0eb0d9f4 GD |
1451 | /* Setup SDCC bus voter clock. */ |
1452 | msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); | |
1453 | if (!IS_ERR(msm_host->bus_clk)) { | |
1454 | /* Vote for max. clk rate for max. performance */ | |
1455 | ret = clk_set_rate(msm_host->bus_clk, INT_MAX); | |
1456 | if (ret) | |
1457 | goto pltfm_free; | |
1458 | ret = clk_prepare_enable(msm_host->bus_clk); | |
1459 | if (ret) | |
1460 | goto pltfm_free; | |
1461 | } | |
1462 | ||
1463 | /* Setup main peripheral bus clock */ | |
e4bf91f6 BA |
1464 | clk = devm_clk_get(&pdev->dev, "iface"); |
1465 | if (IS_ERR(clk)) { | |
1466 | ret = PTR_ERR(clk); | |
2801b95e | 1467 | dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); |
0eb0d9f4 GD |
1468 | goto bus_clk_disable; |
1469 | } | |
e4bf91f6 | 1470 | msm_host->bulk_clks[1].clk = clk; |
0eb0d9f4 GD |
1471 | |
1472 | /* Setup SDC MMC clock */ | |
e4bf91f6 BA |
1473 | clk = devm_clk_get(&pdev->dev, "core"); |
1474 | if (IS_ERR(clk)) { | |
1475 | ret = PTR_ERR(clk); | |
0eb0d9f4 | 1476 | dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); |
e4bf91f6 | 1477 | goto bus_clk_disable; |
0eb0d9f4 | 1478 | } |
e4bf91f6 BA |
1479 | msm_host->bulk_clks[0].clk = clk; |
1480 | ||
1481 | /* Vote for maximum clock rate for maximum performance */ | |
1482 | ret = clk_set_rate(clk, INT_MAX); | |
1483 | if (ret) | |
1484 | dev_warn(&pdev->dev, "core clock boost failed\n"); | |
1485 | ||
4946b3af BA |
1486 | clk = devm_clk_get(&pdev->dev, "cal"); |
1487 | if (IS_ERR(clk)) | |
1488 | clk = NULL; | |
1489 | msm_host->bulk_clks[2].clk = clk; | |
1490 | ||
1491 | clk = devm_clk_get(&pdev->dev, "sleep"); | |
1492 | if (IS_ERR(clk)) | |
1493 | clk = NULL; | |
1494 | msm_host->bulk_clks[3].clk = clk; | |
1495 | ||
e4bf91f6 BA |
1496 | ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), |
1497 | msm_host->bulk_clks); | |
1498 | if (ret) | |
1499 | goto bus_clk_disable; | |
0eb0d9f4 | 1500 | |
83736352 VG |
1501 | /* |
1502 | * xo clock is needed for FLL feature of cm_dll. | |
1503 | * In case if xo clock is not mentioned in DT, warn and proceed. | |
1504 | */ | |
1505 | msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); | |
1506 | if (IS_ERR(msm_host->xo_clk)) { | |
1507 | ret = PTR_ERR(msm_host->xo_clk); | |
1508 | dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); | |
1509 | } | |
1510 | ||
0eb0d9f4 GD |
1511 | core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1512 | msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres); | |
1513 | ||
1514 | if (IS_ERR(msm_host->core_mem)) { | |
1515 | dev_err(&pdev->dev, "Failed to remap registers\n"); | |
1516 | ret = PTR_ERR(msm_host->core_mem); | |
1517 | goto clk_disable; | |
1518 | } | |
1519 | ||
5574ddcc VG |
1520 | /* Reset the vendor spec register to power on reset state */ |
1521 | writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, | |
1522 | host->ioaddr + CORE_VENDOR_SPEC); | |
0eb0d9f4 GD |
1523 | |
1524 | /* Set HC_MODE_EN bit in HC_MODE register */ | |
1525 | writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); | |
1526 | ||
ff06ce41 VG |
1527 | config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE); |
1528 | config |= FF_CLK_SW_RST_DIS; | |
1529 | writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE); | |
1530 | ||
0eb0d9f4 GD |
1531 | host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); |
1532 | dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", | |
1533 | host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> | |
1534 | SDHCI_VENDOR_VER_SHIFT)); | |
1535 | ||
3a3ad3e9 GD |
1536 | core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); |
1537 | core_major = (core_version & CORE_VERSION_MAJOR_MASK) >> | |
1538 | CORE_VERSION_MAJOR_SHIFT; | |
1539 | core_minor = core_version & CORE_VERSION_MINOR_MASK; | |
1540 | dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", | |
1541 | core_version, core_major, core_minor); | |
1542 | ||
83736352 VG |
1543 | if (core_major == 1 && core_minor >= 0x42) |
1544 | msm_host->use_14lpp_dll_reset = true; | |
1545 | ||
02e4293d RH |
1546 | /* |
1547 | * SDCC 5 controller with major version 1, minor version 0x34 and later | |
1548 | * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL. | |
1549 | */ | |
1550 | if (core_major == 1 && core_minor < 0x34) | |
1551 | msm_host->use_cdclp533 = true; | |
1552 | ||
3a3ad3e9 GD |
1553 | /* |
1554 | * Support for some capabilities is not advertised by newer | |
1555 | * controller versions and must be explicitly enabled. | |
1556 | */ | |
1557 | if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { | |
29301f40 RH |
1558 | config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); |
1559 | config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; | |
1560 | writel_relaxed(config, host->ioaddr + | |
3a3ad3e9 GD |
1561 | CORE_VENDOR_SPEC_CAPABILITIES0); |
1562 | } | |
1563 | ||
c7ccee22 SJ |
1564 | /* |
1565 | * Power on reset state may trigger power irq if previous status of | |
1566 | * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq | |
1567 | * interrupt in GIC, any pending power irq interrupt should be | |
1568 | * acknowledged. Otherwise power irq interrupt handler would be | |
1569 | * fired prematurely. | |
1570 | */ | |
401b2d06 | 1571 | sdhci_msm_handle_pwr_irq(host, 0); |
c7ccee22 SJ |
1572 | |
1573 | /* | |
1574 | * Ensure that above writes are propogated before interrupt enablement | |
1575 | * in GIC. | |
1576 | */ | |
1577 | mb(); | |
1578 | ||
ad81d387 GD |
1579 | /* Setup IRQ for handling power/voltage tasks with PMIC */ |
1580 | msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); | |
1581 | if (msm_host->pwr_irq < 0) { | |
1582 | dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", | |
1583 | msm_host->pwr_irq); | |
d1f63f0c | 1584 | ret = msm_host->pwr_irq; |
ad81d387 GD |
1585 | goto clk_disable; |
1586 | } | |
1587 | ||
c0309b38 | 1588 | sdhci_msm_init_pwr_irq_wait(msm_host); |
c7ccee22 SJ |
1589 | /* Enable pwr irq interrupts */ |
1590 | writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK); | |
1591 | ||
ad81d387 GD |
1592 | ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, |
1593 | sdhci_msm_pwr_irq, IRQF_ONESHOT, | |
1594 | dev_name(&pdev->dev), host); | |
1595 | if (ret) { | |
1596 | dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); | |
1597 | goto clk_disable; | |
1598 | } | |
1599 | ||
67e6db11 PG |
1600 | pm_runtime_get_noresume(&pdev->dev); |
1601 | pm_runtime_set_active(&pdev->dev); | |
1602 | pm_runtime_enable(&pdev->dev); | |
1603 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
1604 | MSM_MMC_AUTOSUSPEND_DELAY_MS); | |
1605 | pm_runtime_use_autosuspend(&pdev->dev); | |
1606 | ||
4436c535 | 1607 | host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; |
0eb0d9f4 GD |
1608 | ret = sdhci_add_host(host); |
1609 | if (ret) | |
67e6db11 | 1610 | goto pm_runtime_disable; |
ac06fba1 | 1611 | sdhci_msm_set_regulator_caps(msm_host); |
67e6db11 PG |
1612 | |
1613 | pm_runtime_mark_last_busy(&pdev->dev); | |
1614 | pm_runtime_put_autosuspend(&pdev->dev); | |
0eb0d9f4 GD |
1615 | |
1616 | return 0; | |
1617 | ||
67e6db11 PG |
1618 | pm_runtime_disable: |
1619 | pm_runtime_disable(&pdev->dev); | |
1620 | pm_runtime_set_suspended(&pdev->dev); | |
1621 | pm_runtime_put_noidle(&pdev->dev); | |
0eb0d9f4 | 1622 | clk_disable: |
e4bf91f6 BA |
1623 | clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), |
1624 | msm_host->bulk_clks); | |
0eb0d9f4 GD |
1625 | bus_clk_disable: |
1626 | if (!IS_ERR(msm_host->bus_clk)) | |
1627 | clk_disable_unprepare(msm_host->bus_clk); | |
1628 | pltfm_free: | |
1629 | sdhci_pltfm_free(pdev); | |
1630 | return ret; | |
1631 | } | |
1632 | ||
1633 | static int sdhci_msm_remove(struct platform_device *pdev) | |
1634 | { | |
1635 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
1636 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
6f699531 | 1637 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); |
0eb0d9f4 GD |
1638 | int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == |
1639 | 0xffffffff); | |
1640 | ||
1641 | sdhci_remove_host(host, dead); | |
67e6db11 PG |
1642 | |
1643 | pm_runtime_get_sync(&pdev->dev); | |
1644 | pm_runtime_disable(&pdev->dev); | |
1645 | pm_runtime_put_noidle(&pdev->dev); | |
1646 | ||
e4bf91f6 BA |
1647 | clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), |
1648 | msm_host->bulk_clks); | |
0eb0d9f4 GD |
1649 | if (!IS_ERR(msm_host->bus_clk)) |
1650 | clk_disable_unprepare(msm_host->bus_clk); | |
6f699531 | 1651 | sdhci_pltfm_free(pdev); |
0eb0d9f4 GD |
1652 | return 0; |
1653 | } | |
1654 | ||
67e6db11 PG |
1655 | #ifdef CONFIG_PM |
1656 | static int sdhci_msm_runtime_suspend(struct device *dev) | |
1657 | { | |
1658 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1659 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1660 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1661 | ||
e4bf91f6 BA |
1662 | clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), |
1663 | msm_host->bulk_clks); | |
67e6db11 PG |
1664 | |
1665 | return 0; | |
1666 | } | |
1667 | ||
1668 | static int sdhci_msm_runtime_resume(struct device *dev) | |
1669 | { | |
1670 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1671 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1672 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
67e6db11 | 1673 | |
e4bf91f6 BA |
1674 | return clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), |
1675 | msm_host->bulk_clks); | |
67e6db11 PG |
1676 | } |
1677 | #endif | |
1678 | ||
1679 | static const struct dev_pm_ops sdhci_msm_pm_ops = { | |
1680 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
1681 | pm_runtime_force_resume) | |
1682 | SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, | |
1683 | sdhci_msm_runtime_resume, | |
1684 | NULL) | |
1685 | }; | |
1686 | ||
0eb0d9f4 GD |
1687 | static struct platform_driver sdhci_msm_driver = { |
1688 | .probe = sdhci_msm_probe, | |
1689 | .remove = sdhci_msm_remove, | |
1690 | .driver = { | |
1691 | .name = "sdhci_msm", | |
0eb0d9f4 | 1692 | .of_match_table = sdhci_msm_dt_match, |
67e6db11 | 1693 | .pm = &sdhci_msm_pm_ops, |
0eb0d9f4 GD |
1694 | }, |
1695 | }; | |
1696 | ||
1697 | module_platform_driver(sdhci_msm_driver); | |
1698 | ||
1699 | MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver"); | |
1700 | MODULE_LICENSE("GPL v2"); |