[linux-2.6-block.git] / drivers / mmc / host / sdhci-esdhc.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Freescale eSDHC controller driver generics for OF and pltfm.
 *
 * Copyright (c) 2007 Freescale Semiconductor, Inc.
 * Copyright (c) 2009 MontaVista Software, Inc.
 * Copyright (c) 2010 Pengutronix e.K.
 * Copyright 2020 NXP
 *   Author: Wolfram Sang <kernel@pengutronix.de>
 */

#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
#define _DRIVERS_MMC_SDHCI_ESDHC_H

/*
 * Ops and quirks for the Freescale eSDHC controller.
 */

#define ESDHC_DEFAULT_QUIRKS	(SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
				SDHCI_QUIRK_32BIT_DMA_ADDR | \
				SDHCI_QUIRK_NO_BUSY_IRQ | \
				SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
				SDHCI_QUIRK_PIO_NEEDS_DELAY | \
				SDHCI_QUIRK_NO_HISPD_BIT)

/* pltfm-specific */
#define ESDHC_HOST_CONTROL_LE	0x20

/*
 * eSDHC register definition
 */

/* Present State Register */
#define ESDHC_PRSSTAT			0x24
#define ESDHC_CLOCK_GATE_OFF		0x00000080
#define ESDHC_CLOCK_STABLE		0x00000008

/* Protocol Control Register */
#define ESDHC_PROCTL			0x28
#define ESDHC_VOLT_SEL			0x00000400
#define ESDHC_CTRL_4BITBUS		(0x1 << 1)
#define ESDHC_CTRL_8BITBUS		(0x2 << 1)
#define ESDHC_CTRL_BUSWIDTH_MASK	(0x3 << 1)
#define ESDHC_HOST_CONTROL_RES		0x01

/* System Control Register */
#define ESDHC_SYSTEM_CONTROL		0x2c
#define ESDHC_CLOCK_MASK		0x0000fff0
#define ESDHC_PREDIV_SHIFT		8
#define ESDHC_DIVIDER_SHIFT		4
#define ESDHC_CLOCK_SDCLKEN		0x00000008
#define ESDHC_CLOCK_PEREN		0x00000004
#define ESDHC_CLOCK_HCKEN		0x00000002
#define ESDHC_CLOCK_IPGEN		0x00000001

/* System Control 2 Register */
#define ESDHC_SYSTEM_CONTROL_2		0x3c
#define ESDHC_SMPCLKSEL			0x00800000
#define ESDHC_EXTN			0x00400000

/* Host Controller Capabilities Register 2 */
#define ESDHC_CAPABILITIES_1		0x114

/* Tuning Block Control Register */
#define ESDHC_TBCTL			0x120
#define ESDHC_HS400_WNDW_ADJUST		0x00000040
#define ESDHC_HS400_MODE		0x00000010
#define ESDHC_TB_EN			0x00000004
#define ESDHC_TB_MODE_MASK		0x00000003
#define ESDHC_TB_MODE_SW		0x00000003
#define ESDHC_TB_MODE_3			0x00000002

#define ESDHC_TBSTAT			0x124

#define ESDHC_TBPTR			0x128
#define ESDHC_WNDW_STRT_PTR_SHIFT	8
#define ESDHC_WNDW_STRT_PTR_MASK	(0x7f << 8)
#define ESDHC_WNDW_END_PTR_MASK		0x7f

/* SD Clock Control Register */
#define ESDHC_SDCLKCTL			0x144
#define ESDHC_LPBK_CLK_SEL		0x80000000
#define ESDHC_CMD_CLK_CTL		0x00008000

/* SD Timing Control Register */
#define ESDHC_SDTIMNGCTL		0x148
#define ESDHC_FLW_CTL_BG		0x00008000

/* DLL Config 0 Register */
#define ESDHC_DLLCFG0			0x160
#define ESDHC_DLL_ENABLE		0x80000000
#define ESDHC_DLL_RESET			0x40000000
#define ESDHC_DLL_FREQ_SEL		0x08000000

/* DLL Config 1 Register */
#define ESDHC_DLLCFG1			0x164
#define ESDHC_DLL_PD_PULSE_STRETCH_SEL	0x80000000

/* DLL Status 0 Register */
#define ESDHC_DLLSTAT0			0x170
#define ESDHC_DLL_STS_SLV_LOCK		0x08000000

/* Control Register for DMA transfer */
#define ESDHC_DMA_SYSCTL		0x40c
#define ESDHC_PERIPHERAL_CLK_SEL	0x00080000
#define ESDHC_FLUSH_ASYNC_FIFO		0x00040000
#define ESDHC_DMA_SNOOP			0x00000040

#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
Commit	Line	Data
84a14ae8	1	/* SPDX-License-Identifier: GPL-2.0-only */
80872e21 WS	2	/*
	3	* Freescale eSDHC controller driver generics for OF and pltfm.
	4	*
	5	* Copyright (c) 2007 Freescale Semiconductor, Inc.
	6	* Copyright (c) 2009 MontaVista Software, Inc.
	7	* Copyright (c) 2010 Pengutronix e.K.
011fde48	8	* Copyright 2020 NXP
30e1028d	9	* Author: Wolfram Sang <kernel@pengutronix.de>
80872e21 WS	10	*/
	11
	12	#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
	13	#define _DRIVERS_MMC_SDHCI_ESDHC_H
	14
	15	/*
	16	* Ops and quirks for the Freescale eSDHC controller.
	17	*/
	18
	19	#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 \| \
cbb45093	20	SDHCI_QUIRK_32BIT_DMA_ADDR \| \
80872e21	21	SDHCI_QUIRK_NO_BUSY_IRQ \| \
80872e21	22	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \| \
67b589a2 YL	23	SDHCI_QUIRK_PIO_NEEDS_DELAY \| \
67b589a2 YL	24	SDHCI_QUIRK_NO_HISPD_BIT)
80872e21	25
80872e21 WS	26	/* pltfm-specific */
	27	#define ESDHC_HOST_CONTROL_LE 0x20
	28
66b50a00	29	/*
a6b44888	30	* eSDHC register definition
66b50a00	31	*/
80872e21	32
e87d2db2	33	/* Present State Register */
e87d2db2	34	#define ESDHC_PRSSTAT 0x24
f581e909	35	#define ESDHC_CLOCK_GATE_OFF 0x00000080
e87d2db2	36	#define ESDHC_CLOCK_STABLE 0x00000008
e87d2db2	37
a6b44888	38	/* Protocol Control Register */
a6b44888	39	#define ESDHC_PROCTL 0x28
ea35645a	40	#define ESDHC_VOLT_SEL 0x00000400
a6b44888	41	#define ESDHC_CTRL_4BITBUS (0x1 << 1)
	42	#define ESDHC_CTRL_8BITBUS (0x2 << 1)
	43	#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
	44	#define ESDHC_HOST_CONTROL_RES 0x01
	45
	46	/* System Control Register */
	47	#define ESDHC_SYSTEM_CONTROL 0x2c
	48	#define ESDHC_CLOCK_MASK 0x0000fff0
	49	#define ESDHC_PREDIV_SHIFT 8
	50	#define ESDHC_DIVIDER_SHIFT 4
e87d2db2	51	#define ESDHC_CLOCK_SDCLKEN 0x00000008
a6b44888	52	#define ESDHC_CLOCK_PEREN 0x00000004
	53	#define ESDHC_CLOCK_HCKEN 0x00000002
	54	#define ESDHC_CLOCK_IPGEN 0x00000001
	55
22dc132d YL	56	/* System Control 2 Register */
	57	#define ESDHC_SYSTEM_CONTROL_2 0x3c
	58	#define ESDHC_SMPCLKSEL 0x00800000
	59	#define ESDHC_EXTN 0x00400000
	60
2f3110cc	61	/* Host Controller Capabilities Register 2 */
	62	#define ESDHC_CAPABILITIES_1 0x114
	63
ba49cbd0	64	/* Tuning Block Control Register */
ba49cbd0	65	#define ESDHC_TBCTL 0x120
54e08d9a YL	66	#define ESDHC_HS400_WNDW_ADJUST 0x00000040
54e08d9a YL	67	#define ESDHC_HS400_MODE 0x00000010
ba49cbd0	68	#define ESDHC_TB_EN 0x00000004
22dc132d YL	69	#define ESDHC_TB_MODE_MASK 0x00000003
	70	#define ESDHC_TB_MODE_SW 0x00000003
	71	#define ESDHC_TB_MODE_3 0x00000002
	72
	73	#define ESDHC_TBSTAT 0x124
	74
b1f378ab	75	#define ESDHC_TBPTR 0x128
22dc132d YL	76	#define ESDHC_WNDW_STRT_PTR_SHIFT 8
	77	#define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8)
	78	#define ESDHC_WNDW_END_PTR_MASK 0x7f
ba49cbd0	79
54e08d9a YL	80	/* SD Clock Control Register */
	81	#define ESDHC_SDCLKCTL 0x144
	82	#define ESDHC_LPBK_CLK_SEL 0x80000000
	83	#define ESDHC_CMD_CLK_CTL 0x00008000
	84
	85	/* SD Timing Control Register */
	86	#define ESDHC_SDTIMNGCTL 0x148
	87	#define ESDHC_FLW_CTL_BG 0x00008000
	88
	89	/* DLL Config 0 Register */
	90	#define ESDHC_DLLCFG0 0x160
	91	#define ESDHC_DLL_ENABLE 0x80000000
011fde48	92	#define ESDHC_DLL_RESET 0x40000000
54e08d9a YL	93	#define ESDHC_DLL_FREQ_SEL 0x08000000
54e08d9a YL	94
48e304cc YL	95	/* DLL Config 1 Register */
	96	#define ESDHC_DLLCFG1 0x164
	97	#define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000
	98
54e08d9a YL	99	/* DLL Status 0 Register */
	100	#define ESDHC_DLLSTAT0 0x170
	101	#define ESDHC_DLL_STS_SLV_LOCK 0x08000000
	102
a6b44888	103	/* Control Register for DMA transfer */
a6b44888	104	#define ESDHC_DMA_SYSCTL 0x40c
19c3a0ef	105	#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
ba49cbd0	106	#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
a6b44888	107	#define ESDHC_DMA_SNOOP 0x00000040
80872e21	108
80872e21	109	#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */