[linux-block.git] / drivers / mmc / host / sdhci-cadence.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 */

#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include "sdhci-pltfm.h"

/* HRS - Host Register Set (specific to Cadence) */
#define SDHCI_CDNS_HRS04		0x10		/* PHY access port */
#define   SDHCI_CDNS_HRS04_ACK			BIT(26)
#define   SDHCI_CDNS_HRS04_RD			BIT(25)
#define   SDHCI_CDNS_HRS04_WR			BIT(24)
#define   SDHCI_CDNS_HRS04_RDATA		GENMASK(23, 16)
#define   SDHCI_CDNS_HRS04_WDATA		GENMASK(15, 8)
#define   SDHCI_CDNS_HRS04_ADDR			GENMASK(5, 0)

#define SDHCI_CDNS_HRS06		0x18		/* eMMC control */
#define   SDHCI_CDNS_HRS06_TUNE_UP		BIT(15)
#define   SDHCI_CDNS_HRS06_TUNE			GENMASK(13, 8)
#define   SDHCI_CDNS_HRS06_MODE			GENMASK(2, 0)
#define   SDHCI_CDNS_HRS06_MODE_SD		0x0
#define   SDHCI_CDNS_HRS06_MODE_MMC_SDR		0x2
#define   SDHCI_CDNS_HRS06_MODE_MMC_DDR		0x3
#define   SDHCI_CDNS_HRS06_MODE_MMC_HS200	0x4
#define   SDHCI_CDNS_HRS06_MODE_MMC_HS400	0x5
#define   SDHCI_CDNS_HRS06_MODE_MMC_HS400ES	0x6

/* SRS - Slot Register Set (SDHCI-compatible) */
#define SDHCI_CDNS_SRS_BASE		0x200

/* PHY */
#define SDHCI_CDNS_PHY_DLY_SD_HS	0x00
#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT	0x01
#define SDHCI_CDNS_PHY_DLY_UHS_SDR12	0x02
#define SDHCI_CDNS_PHY_DLY_UHS_SDR25	0x03
#define SDHCI_CDNS_PHY_DLY_UHS_SDR50	0x04
#define SDHCI_CDNS_PHY_DLY_UHS_DDR50	0x05
#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY	0x06
#define SDHCI_CDNS_PHY_DLY_EMMC_SDR	0x07
#define SDHCI_CDNS_PHY_DLY_EMMC_DDR	0x08
#define SDHCI_CDNS_PHY_DLY_SDCLK	0x0b
#define SDHCI_CDNS_PHY_DLY_HSMMC	0x0c
#define SDHCI_CDNS_PHY_DLY_STROBE	0x0d

/*
 * The tuned val register is 6 bit-wide, but not the whole of the range is
 * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
 * but I am not quite sure if it is official.  Use only 0 to 39 for safety.
 */
#define SDHCI_CDNS_MAX_TUNING_LOOP	40

struct sdhci_cdns_phy_param {
	u8 addr;
	u8 data;
};

struct sdhci_cdns_priv {
	void __iomem *hrs_addr;
	bool enhanced_strobe;
	unsigned int nr_phy_params;
	struct sdhci_cdns_phy_param phy_params[0];
};

struct sdhci_cdns_phy_cfg {
	const char *property;
	u8 addr;
};

static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
};

static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
				    u8 addr, u8 data)
{
	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
	u32 tmp;
	int ret;

	tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
	      FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
	writel(tmp, reg);

	tmp |= SDHCI_CDNS_HRS04_WR;
	writel(tmp, reg);

	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
	if (ret)
		return ret;

	tmp &= ~SDHCI_CDNS_HRS04_WR;
	writel(tmp, reg);

	return 0;
}

static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
{
	unsigned int count = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
		if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
			count++;

	return count;
}

static void sdhci_cdns_phy_param_parse(struct device_node *np,
				       struct sdhci_cdns_priv *priv)
{
	struct sdhci_cdns_phy_param *p = priv->phy_params;
	u32 val;
	int ret, i;

	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
		ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
					   &val);
		if (ret)
			continue;

		p->addr = sdhci_cdns_phy_cfgs[i].addr;
		p->data = val;
		p++;
	}
}

static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
{
	int ret, i;

	for (i = 0; i < priv->nr_phy_params; i++) {
		ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
					       priv->phy_params[i].data);
		if (ret)
			return ret;
	}

	return 0;
}

static void *sdhci_cdns_priv(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	return sdhci_pltfm_priv(pltfm_host);
}

static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
{
	/*
	 * Cadence's spec says the Timeout Clock Frequency is the same as the
	 * Base Clock Frequency.
	 */
	return host->max_clk;
}

static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
{
	u32 tmp;

	/* The speed mode for eMMC is selected by HRS06 register */
	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
	tmp &= ~SDHCI_CDNS_HRS06_MODE;
	tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
	writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
}

static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
{
	u32 tmp;

	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
	return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
}

static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
					 unsigned int timing)
{
	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
	u32 mode;

	switch (timing) {
	case MMC_TIMING_MMC_HS:
		mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
		break;
	case MMC_TIMING_MMC_DDR52:
		mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
		break;
	case MMC_TIMING_MMC_HS200:
		mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
		break;
	case MMC_TIMING_MMC_HS400:
		if (priv->enhanced_strobe)
			mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
		else
			mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
		break;
	default:
		mode = SDHCI_CDNS_HRS06_MODE_SD;
		break;
	}

	sdhci_cdns_set_emmc_mode(priv, mode);

	/* For SD, fall back to the default handler */
	if (mode == SDHCI_CDNS_HRS06_MODE_SD)
		sdhci_set_uhs_signaling(host, timing);
}

static const struct sdhci_ops sdhci_cdns_ops = {
	.set_clock = sdhci_set_clock,
	.get_timeout_clock = sdhci_cdns_get_timeout_clock,
	.set_bus_width = sdhci_set_bus_width,
	.reset = sdhci_reset,
	.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
};

static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = {
	.ops = &sdhci_cdns_ops,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
};

static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
	.ops = &sdhci_cdns_ops,
};

static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
{
	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
	u32 tmp;
	int i, ret;

	if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
		return -EINVAL;

	tmp = readl(reg);
	tmp &= ~SDHCI_CDNS_HRS06_TUNE;
	tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);

	/*
	 * Workaround for IP errata:
	 * The IP6116 SD/eMMC PHY design has a timing issue on receive data
	 * path. Send tune request twice.
	 */
	for (i = 0; i < 2; i++) {
		tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
		writel(tmp, reg);

		ret = readl_poll_timeout(reg, tmp,
					 !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
					 0, 1);
		if (ret)
			return ret;
	}

	return 0;
}

static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
	struct sdhci_host *host = mmc_priv(mmc);
	int cur_streak = 0;
	int max_streak = 0;
	int end_of_streak = 0;
	int i;

	/*
	 * This handler only implements the eMMC tuning that is specific to
	 * this controller.  Fall back to the standard method for SD timing.
	 */
	if (host->timing != MMC_TIMING_MMC_HS200)
		return sdhci_execute_tuning(mmc, opcode);

	if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
		return -EINVAL;

	for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
		if (sdhci_cdns_set_tune_val(host, i) ||
		    mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
			cur_streak = 0;
		} else { /* good */
			cur_streak++;
			if (cur_streak > max_streak) {
				max_streak = cur_streak;
				end_of_streak = i;
			}
		}
	}

	if (!max_streak) {
		dev_err(mmc_dev(host->mmc), "no tuning point found\n");
		return -EIO;
	}

	return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
}

static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
					     struct mmc_ios *ios)
{
	struct sdhci_host *host = mmc_priv(mmc);
	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
	u32 mode;

	priv->enhanced_strobe = ios->enhanced_strobe;

	mode = sdhci_cdns_get_emmc_mode(priv);

	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)
		sdhci_cdns_set_emmc_mode(priv,
					 SDHCI_CDNS_HRS06_MODE_MMC_HS400ES);

	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)
		sdhci_cdns_set_emmc_mode(priv,
					 SDHCI_CDNS_HRS06_MODE_MMC_HS400);
}

static int sdhci_cdns_probe(struct platform_device *pdev)
{
	struct sdhci_host *host;
	const struct sdhci_pltfm_data *data;
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_cdns_priv *priv;
	struct clk *clk;
	unsigned int nr_phy_params;
	int ret;
	struct device *dev = &pdev->dev;
	static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;

	clk = devm_clk_get(dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	data = of_device_get_match_data(dev);
	if (!data)
		data = &sdhci_cdns_pltfm_data;

	nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
	host = sdhci_pltfm_init(pdev, data,
				struct_size(priv, phy_params, nr_phy_params));
	if (IS_ERR(host)) {
		ret = PTR_ERR(host);
		goto disable_clk;
	}

	pltfm_host = sdhci_priv(host);
	pltfm_host->clk = clk;

	priv = sdhci_pltfm_priv(pltfm_host);
	priv->nr_phy_params = nr_phy_params;
	priv->hrs_addr = host->ioaddr;
	priv->enhanced_strobe = false;
	host->ioaddr += SDHCI_CDNS_SRS_BASE;
	host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
	host->mmc_host_ops.hs400_enhanced_strobe =
				sdhci_cdns_hs400_enhanced_strobe;
	sdhci_enable_v4_mode(host);
	__sdhci_read_caps(host, &version, NULL, NULL);

	sdhci_get_of_property(pdev);

	ret = mmc_of_parse(host->mmc);
	if (ret)
		goto free;

	sdhci_cdns_phy_param_parse(dev->of_node, priv);

	ret = sdhci_cdns_phy_init(priv);
	if (ret)
		goto free;

	ret = sdhci_add_host(host);
	if (ret)
		goto free;

	return 0;
free:
	sdhci_pltfm_free(pdev);
disable_clk:
	clk_disable_unprepare(clk);

	return ret;
}

#ifdef CONFIG_PM_SLEEP
static int sdhci_cdns_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host);
	int ret;

	ret = clk_prepare_enable(pltfm_host->clk);
	if (ret)
		return ret;

	ret = sdhci_cdns_phy_init(priv);
	if (ret)
		goto disable_clk;

	ret = sdhci_resume_host(host);
	if (ret)
		goto disable_clk;

	return 0;

disable_clk:
	clk_disable_unprepare(pltfm_host->clk);

	return ret;
}
#endif

static const struct dev_pm_ops sdhci_cdns_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_cdns_resume)
};

static const struct of_device_id sdhci_cdns_match[] = {
	{
		.compatible = "socionext,uniphier-sd4hc",
		.data = &sdhci_cdns_uniphier_pltfm_data,
	},
	{ .compatible = "cdns,sd4hc" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sdhci_cdns_match);

static struct platform_driver sdhci_cdns_driver = {
	.driver = {
		.name = "sdhci-cdns",
		.pm = &sdhci_cdns_pm_ops,
		.of_match_table = sdhci_cdns_match,
	},
	.probe = sdhci_cdns_probe,
	.remove = sdhci_pltfm_unregister,
};
module_platform_driver(sdhci_cdns_driver);

MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
ff6af28f MY	2	/*
	3	* Copyright (C) 2016 Socionext Inc.
	4	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
ff6af28f MY	5	*/
ff6af28f MY	6
f02cebdf	7	#include <linux/bitfield.h>
cd7a0d21	8	#include <linux/bits.h>
ff6af28f MY	9	#include <linux/iopoll.h>
	10	#include <linux/module.h>
	11	#include <linux/mmc/host.h>
963836ad	12	#include <linux/mmc/mmc.h>
a89c472d	13	#include <linux/of.h>
18b587b4	14	#include <linux/of_device.h>
ff6af28f MY	15
	16	#include "sdhci-pltfm.h"
	17
	18	/* HRS - Host Register Set (specific to Cadence) */
	19	#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
	20	#define SDHCI_CDNS_HRS04_ACK BIT(26)
	21	#define SDHCI_CDNS_HRS04_RD BIT(25)
	22	#define SDHCI_CDNS_HRS04_WR BIT(24)
f02cebdf MY	23	#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
	24	#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
	25	#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
ff6af28f MY	26
	27	#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
	28	#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
f02cebdf MY	29	#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
f02cebdf MY	30	#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
ff6af28f MY	31	#define SDHCI_CDNS_HRS06_MODE_SD 0x0
	32	#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
	33	#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
	34	#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
	35	#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
d12990f9	36	#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
ff6af28f MY	37
	38	/* SRS - Slot Register Set (SDHCI-compatible) */
	39	#define SDHCI_CDNS_SRS_BASE 0x200
	40
	41	/* PHY */
	42	#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
	43	#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
	44	#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
	45	#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
	46	#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
	47	#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
	48	#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
	49	#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
	50	#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
a89c472d PS	51	#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
	52	#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
	53	#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
ff6af28f MY	54
	55	/*
	56	* The tuned val register is 6 bit-wide, but not the whole of the range is
	57	* available. The range 0-42 seems to be available (then 43 wraps around to 0)
	58	* but I am not quite sure if it is official. Use only 0 to 39 for safety.
	59	*/
	60	#define SDHCI_CDNS_MAX_TUNING_LOOP 40
	61
a232a8f2 MY	62	struct sdhci_cdns_phy_param {
	63	u8 addr;
	64	u8 data;
	65	};
	66
ff6af28f MY	67	struct sdhci_cdns_priv {
ff6af28f MY	68	void __iomem *hrs_addr;
d12990f9	69	bool enhanced_strobe;
a232a8f2 MY	70	unsigned int nr_phy_params;
a232a8f2 MY	71	struct sdhci_cdns_phy_param phy_params[0];
ff6af28f MY	72	};
ff6af28f MY	73
a89c472d PS	74	struct sdhci_cdns_phy_cfg {
	75	const char *property;
	76	u8 addr;
	77	};
	78
	79	static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
	80	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
	81	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
	82	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
	83	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
	84	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
	85	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
	86	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
	87	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
	88	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
	89	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
	90	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
	91	};
	92
a0f82432 PS	93	static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
a0f82432 PS	94	u8 addr, u8 data)
ff6af28f MY	95	{
	96	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
	97	u32 tmp;
a0f82432	98	int ret;
ff6af28f	99
f02cebdf MY	100	tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) \|
f02cebdf MY	101	FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
ff6af28f MY	102	writel(tmp, reg);
	103
	104	tmp \|= SDHCI_CDNS_HRS04_WR;
	105	writel(tmp, reg);
	106
a0f82432 PS	107	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
	108	if (ret)
	109	return ret;
	110
ff6af28f MY	111	tmp &= ~SDHCI_CDNS_HRS04_WR;
ff6af28f MY	112	writel(tmp, reg);
a0f82432 PS	113
a0f82432 PS	114	return 0;
ff6af28f MY	115	}
ff6af28f MY	116
a232a8f2	117	static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
ff6af28f	118	{
a232a8f2 MY	119	unsigned int count = 0;
	120	int i;
	121
	122	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
	123	if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
	124	count++;
	125
	126	return count;
	127	}
	128
	129	static void sdhci_cdns_phy_param_parse(struct device_node *np,
	130	struct sdhci_cdns_priv *priv)
	131	{
	132	struct sdhci_cdns_phy_param *p = priv->phy_params;
a89c472d PS	133	u32 val;
	134	int ret, i;
	135
	136	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
	137	ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
	138	&val);
	139	if (ret)
	140	continue;
	141
a232a8f2 MY	142	p->addr = sdhci_cdns_phy_cfgs[i].addr;
	143	p->data = val;
	144	p++;
	145	}
	146	}
	147
	148	static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
	149	{
	150	int ret, i;
	151
	152	for (i = 0; i < priv->nr_phy_params; i++) {
	153	ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
	154	priv->phy_params[i].data);
a89c472d PS	155	if (ret)
	156	return ret;
	157	}
	158
	159	return 0;
ff6af28f MY	160	}
ff6af28f MY	161
1d45a3f4	162	static void sdhci_cdns_priv(struct sdhci_host host)
ff6af28f MY	163	{
	164	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	165
	166	return sdhci_pltfm_priv(pltfm_host);
	167	}
	168
	169	static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
	170	{
	171	/*
	172	* Cadence's spec says the Timeout Clock Frequency is the same as the
8cc35289	173	* Base Clock Frequency.
ff6af28f	174	*/
8cc35289	175	return host->max_clk;
ff6af28f MY	176	}
ff6af28f MY	177
d12990f9 PS	178	static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
	179	{
	180	u32 tmp;
	181
	182	/* The speed mode for eMMC is selected by HRS06 register */
	183	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
f02cebdf MY	184	tmp &= ~SDHCI_CDNS_HRS06_MODE;
f02cebdf MY	185	tmp \|= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
d12990f9 PS	186	writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
	187	}
	188
	189	static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
	190	{
	191	u32 tmp;
	192
	193	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
f02cebdf	194	return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
d12990f9 PS	195	}
d12990f9 PS	196
ff6af28f MY	197	static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
	198	unsigned int timing)
	199	{
	200	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
d12990f9	201	u32 mode;
ff6af28f MY	202
	203	switch (timing) {
	204	case MMC_TIMING_MMC_HS:
	205	mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
	206	break;
	207	case MMC_TIMING_MMC_DDR52:
	208	mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
	209	break;
	210	case MMC_TIMING_MMC_HS200:
	211	mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
	212	break;
	213	case MMC_TIMING_MMC_HS400:
d12990f9 PS	214	if (priv->enhanced_strobe)
	215	mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
	216	else
	217	mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
ff6af28f MY	218	break;
	219	default:
	220	mode = SDHCI_CDNS_HRS06_MODE_SD;
	221	break;
	222	}
	223
d12990f9	224	sdhci_cdns_set_emmc_mode(priv, mode);
ff6af28f MY	225
	226	/* For SD, fall back to the default handler */
	227	if (mode == SDHCI_CDNS_HRS06_MODE_SD)
	228	sdhci_set_uhs_signaling(host, timing);
	229	}
	230
	231	static const struct sdhci_ops sdhci_cdns_ops = {
	232	.set_clock = sdhci_set_clock,
	233	.get_timeout_clock = sdhci_cdns_get_timeout_clock,
	234	.set_bus_width = sdhci_set_bus_width,
	235	.reset = sdhci_reset,
	236	.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
	237	};
	238
18b587b4 MY	239	static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = {
	240	.ops = &sdhci_cdns_ops,
	241	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	242	};
	243
ff6af28f MY	244	static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
	245	.ops = &sdhci_cdns_ops,
	246	};
	247
	248	static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
	249	{
	250	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
	251	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
	252	u32 tmp;
ef6b7567	253	int i, ret;
ff6af28f	254
f02cebdf	255	if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
ff6af28f MY	256	return -EINVAL;
	257
	258	tmp = readl(reg);
f02cebdf MY	259	tmp &= ~SDHCI_CDNS_HRS06_TUNE;
f02cebdf MY	260	tmp \|= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
ff6af28f	261
ef6b7567 MY	262	/*
	263	* Workaround for IP errata:
	264	* The IP6116 SD/eMMC PHY design has a timing issue on receive data
	265	* path. Send tune request twice.
	266	*/
	267	for (i = 0; i < 2; i++) {
	268	tmp \|= SDHCI_CDNS_HRS06_TUNE_UP;
	269	writel(tmp, reg);
	270
	271	ret = readl_poll_timeout(reg, tmp,
	272	!(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
	273	0, 1);
3f1109d1 GS	274	if (ret)
3f1109d1 GS	275	return ret;
ef6b7567 MY	276	}
	277
	278	return 0;
ff6af28f MY	279	}
	280
	281	static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode)
	282	{
	283	struct sdhci_host *host = mmc_priv(mmc);
	284	int cur_streak = 0;
	285	int max_streak = 0;
	286	int end_of_streak = 0;
	287	int i;
	288
	289	/*
	290	* This handler only implements the eMMC tuning that is specific to
	291	* this controller. Fall back to the standard method for SD timing.
	292	*/
	293	if (host->timing != MMC_TIMING_MMC_HS200)
	294	return sdhci_execute_tuning(mmc, opcode);
	295
	296	if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
	297	return -EINVAL;
	298
	299	for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
	300	if (sdhci_cdns_set_tune_val(host, i) \|\|
	301	mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
	302	cur_streak = 0;
	303	} else { /* good */
	304	cur_streak++;
	305	if (cur_streak > max_streak) {
	306	max_streak = cur_streak;
	307	end_of_streak = i;
	308	}
	309	}
	310	}
	311
	312	if (!max_streak) {
	313	dev_err(mmc_dev(host->mmc), "no tuning point found\n");
	314	return -EIO;
	315	}
	316
	317	return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
	318	}
	319
d12990f9 PS	320	static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
	321	struct mmc_ios *ios)
	322	{
	323	struct sdhci_host *host = mmc_priv(mmc);
	324	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
	325	u32 mode;
	326
	327	priv->enhanced_strobe = ios->enhanced_strobe;
	328
	329	mode = sdhci_cdns_get_emmc_mode(priv);
	330
	331	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)
	332	sdhci_cdns_set_emmc_mode(priv,
	333	SDHCI_CDNS_HRS06_MODE_MMC_HS400ES);
	334
	335	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)
	336	sdhci_cdns_set_emmc_mode(priv,
	337	SDHCI_CDNS_HRS06_MODE_MMC_HS400);
	338	}
	339
ff6af28f MY	340	static int sdhci_cdns_probe(struct platform_device *pdev)
	341	{
	342	struct sdhci_host *host;
18b587b4	343	const struct sdhci_pltfm_data *data;
ff6af28f MY	344	struct sdhci_pltfm_host *pltfm_host;
	345	struct sdhci_cdns_priv *priv;
	346	struct clk *clk;
a232a8f2	347	unsigned int nr_phy_params;
ff6af28f	348	int ret;
a89c472d	349	struct device *dev = &pdev->dev;
12a632e6	350	static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
ff6af28f	351
edf98579	352	clk = devm_clk_get(dev, NULL);
ff6af28f MY	353	if (IS_ERR(clk))
	354	return PTR_ERR(clk);
	355
	356	ret = clk_prepare_enable(clk);
	357	if (ret)
	358	return ret;
	359
18b587b4 MY	360	data = of_device_get_match_data(dev);
	361	if (!data)
	362	data = &sdhci_cdns_pltfm_data;
	363
a232a8f2	364	nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
18b587b4	365	host = sdhci_pltfm_init(pdev, data,
159a8b46	366	struct_size(priv, phy_params, nr_phy_params));
ff6af28f MY	367	if (IS_ERR(host)) {
	368	ret = PTR_ERR(host);
	369	goto disable_clk;
	370	}
	371
	372	pltfm_host = sdhci_priv(host);
	373	pltfm_host->clk = clk;
	374
a232a8f2 MY	375	priv = sdhci_pltfm_priv(pltfm_host);
a232a8f2 MY	376	priv->nr_phy_params = nr_phy_params;
ff6af28f	377	priv->hrs_addr = host->ioaddr;
d12990f9	378	priv->enhanced_strobe = false;
ff6af28f MY	379	host->ioaddr += SDHCI_CDNS_SRS_BASE;
ff6af28f MY	380	host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
d12990f9 PS	381	host->mmc_host_ops.hs400_enhanced_strobe =
d12990f9 PS	382	sdhci_cdns_hs400_enhanced_strobe;
e73a3896	383	sdhci_enable_v4_mode(host);
12a632e6	384	__sdhci_read_caps(host, &version, NULL, NULL);
ff6af28f	385
861183f1 PS	386	sdhci_get_of_property(pdev);
861183f1 PS	387
ff6af28f MY	388	ret = mmc_of_parse(host->mmc);
	389	if (ret)
	390	goto free;
	391
a232a8f2 MY	392	sdhci_cdns_phy_param_parse(dev->of_node, priv);
	393
	394	ret = sdhci_cdns_phy_init(priv);
a89c472d PS	395	if (ret)
a89c472d PS	396	goto free;
ff6af28f MY	397
	398	ret = sdhci_add_host(host);
	399	if (ret)
	400	goto free;
	401
	402	return 0;
	403	free:
	404	sdhci_pltfm_free(pdev);
	405	disable_clk:
	406	clk_disable_unprepare(clk);
	407
	408	return ret;
	409	}
	410
a232a8f2	411	#ifdef CONFIG_PM_SLEEP
a232a8f2 MY	412	static int sdhci_cdns_resume(struct device *dev)
	413	{
	414	struct sdhci_host *host = dev_get_drvdata(dev);
	415	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	416	struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host);
	417	int ret;
	418
	419	ret = clk_prepare_enable(pltfm_host->clk);
	420	if (ret)
	421	return ret;
	422
	423	ret = sdhci_cdns_phy_init(priv);
	424	if (ret)
	425	goto disable_clk;
	426
	427	ret = sdhci_resume_host(host);
	428	if (ret)
	429	goto disable_clk;
	430
	431	return 0;
	432
	433	disable_clk:
	434	clk_disable_unprepare(pltfm_host->clk);
	435
	436	return ret;
	437	}
	438	#endif
	439
	440	static const struct dev_pm_ops sdhci_cdns_pm_ops = {
83a7b32a	441	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_cdns_resume)
a232a8f2 MY	442	};
a232a8f2 MY	443
ff6af28f	444	static const struct of_device_id sdhci_cdns_match[] = {
18b587b4 MY	445	{
	446	.compatible = "socionext,uniphier-sd4hc",
	447	.data = &sdhci_cdns_uniphier_pltfm_data,
	448	},
ff6af28f MY	449	{ .compatible = "cdns,sd4hc" },
	450	{ /* sentinel */ }
	451	};
	452	MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
	453
	454	static struct platform_driver sdhci_cdns_driver = {
	455	.driver = {
	456	.name = "sdhci-cdns",
a232a8f2	457	.pm = &sdhci_cdns_pm_ops,
ff6af28f MY	458	.of_match_table = sdhci_cdns_match,
	459	},
	460	.probe = sdhci_cdns_probe,
	461	.remove = sdhci_pltfm_unregister,
	462	};
	463	module_platform_driver(sdhci_cdns_driver);
	464
	465	MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
	466	MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
	467	MODULE_LICENSE("GPL");