Commit | Line | Data |
---|---|---|
a61127c2 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c4e05037 AH |
2 | /* |
3 | * Secure Digital Host Controller Interface ACPI driver. | |
4 | * | |
5 | * Copyright (c) 2012, Intel Corporation. | |
c4e05037 AH |
6 | */ |
7 | ||
8 | #include <linux/init.h> | |
9 | #include <linux/export.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/device.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/ioport.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/compiler.h> | |
17 | #include <linux/stddef.h> | |
18 | #include <linux/bitops.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/acpi.h> | |
23 | #include <linux/pm.h> | |
24 | #include <linux/pm_runtime.h> | |
b04fa064 | 25 | #include <linux/delay.h> |
c4e05037 AH |
26 | |
27 | #include <linux/mmc/host.h> | |
28 | #include <linux/mmc/pm.h> | |
4fd4409c | 29 | #include <linux/mmc/slot-gpio.h> |
c4e05037 | 30 | |
6e1c7d61 AH |
31 | #ifdef CONFIG_X86 |
32 | #include <asm/cpu_device_id.h> | |
8ba4cb53 | 33 | #include <asm/intel-family.h> |
6e1c7d61 | 34 | #include <asm/iosf_mbi.h> |
17753d16 | 35 | #include <linux/pci.h> |
6e1c7d61 AH |
36 | #endif |
37 | ||
c4e05037 AH |
38 | #include "sdhci.h" |
39 | ||
40 | enum { | |
4fd4409c AH |
41 | SDHCI_ACPI_SD_CD = BIT(0), |
42 | SDHCI_ACPI_RUNTIME_PM = BIT(1), | |
43 | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2), | |
c4e05037 AH |
44 | }; |
45 | ||
46 | struct sdhci_acpi_chip { | |
47 | const struct sdhci_ops *ops; | |
48 | unsigned int quirks; | |
49 | unsigned int quirks2; | |
50 | unsigned long caps; | |
51 | unsigned int caps2; | |
52 | mmc_pm_flag_t pm_caps; | |
53 | }; | |
54 | ||
55 | struct sdhci_acpi_slot { | |
56 | const struct sdhci_acpi_chip *chip; | |
57 | unsigned int quirks; | |
58 | unsigned int quirks2; | |
59 | unsigned long caps; | |
60 | unsigned int caps2; | |
61 | mmc_pm_flag_t pm_caps; | |
62 | unsigned int flags; | |
f07b7952 | 63 | size_t priv_size; |
7dafca83 | 64 | int (*probe_slot)(struct platform_device *, const char *, const char *); |
578b36b6 | 65 | int (*remove_slot)(struct platform_device *); |
c7eabbee | 66 | int (*free_slot)(struct platform_device *pdev); |
0cc1a0f4 | 67 | int (*setup_host)(struct platform_device *pdev); |
c4e05037 AH |
68 | }; |
69 | ||
70 | struct sdhci_acpi_host { | |
71 | struct sdhci_host *host; | |
72 | const struct sdhci_acpi_slot *slot; | |
73 | struct platform_device *pdev; | |
74 | bool use_runtime_pm; | |
f07b7952 | 75 | unsigned long private[0] ____cacheline_aligned; |
c4e05037 AH |
76 | }; |
77 | ||
f07b7952 AH |
78 | static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c) |
79 | { | |
80 | return (void *)c->private; | |
81 | } | |
82 | ||
c4e05037 AH |
83 | static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag) |
84 | { | |
85 | return c->slot && (c->slot->flags & flag); | |
86 | } | |
87 | ||
0acccf41 AH |
88 | #define INTEL_DSM_HS_CAPS_SDR25 BIT(0) |
89 | #define INTEL_DSM_HS_CAPS_DDR50 BIT(1) | |
90 | #define INTEL_DSM_HS_CAPS_SDR50 BIT(2) | |
91 | #define INTEL_DSM_HS_CAPS_SDR104 BIT(3) | |
92 | ||
1c451c13 AH |
93 | enum { |
94 | INTEL_DSM_FNS = 0, | |
95 | INTEL_DSM_V18_SWITCH = 3, | |
96 | INTEL_DSM_V33_SWITCH = 4, | |
0acccf41 | 97 | INTEL_DSM_HS_CAPS = 8, |
1c451c13 AH |
98 | }; |
99 | ||
100 | struct intel_host { | |
101 | u32 dsm_fns; | |
0acccf41 | 102 | u32 hs_caps; |
1c451c13 AH |
103 | }; |
104 | ||
105 | static const guid_t intel_dsm_guid = | |
106 | GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, | |
107 | 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); | |
108 | ||
109 | static int __intel_dsm(struct intel_host *intel_host, struct device *dev, | |
110 | unsigned int fn, u32 *result) | |
111 | { | |
112 | union acpi_object *obj; | |
113 | int err = 0; | |
114 | ||
115 | obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); | |
116 | if (!obj) | |
117 | return -EOPNOTSUPP; | |
118 | ||
119 | if (obj->type == ACPI_TYPE_INTEGER) { | |
120 | *result = obj->integer.value; | |
121 | } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) { | |
122 | size_t len = min_t(size_t, obj->buffer.length, 4); | |
123 | ||
124 | *result = 0; | |
125 | memcpy(result, obj->buffer.pointer, len); | |
126 | } else { | |
127 | dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n", | |
128 | __func__, fn, obj->type, obj->buffer.length); | |
129 | err = -EINVAL; | |
130 | } | |
131 | ||
132 | ACPI_FREE(obj); | |
133 | ||
134 | return err; | |
135 | } | |
136 | ||
137 | static int intel_dsm(struct intel_host *intel_host, struct device *dev, | |
138 | unsigned int fn, u32 *result) | |
139 | { | |
140 | if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) | |
141 | return -EOPNOTSUPP; | |
142 | ||
143 | return __intel_dsm(intel_host, dev, fn, result); | |
144 | } | |
145 | ||
146 | static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, | |
147 | struct mmc_host *mmc) | |
148 | { | |
149 | int err; | |
150 | ||
0acccf41 AH |
151 | intel_host->hs_caps = ~0; |
152 | ||
1c451c13 AH |
153 | err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); |
154 | if (err) { | |
155 | pr_debug("%s: DSM not supported, error %d\n", | |
156 | mmc_hostname(mmc), err); | |
157 | return; | |
158 | } | |
159 | ||
160 | pr_debug("%s: DSM function mask %#x\n", | |
161 | mmc_hostname(mmc), intel_host->dsm_fns); | |
0acccf41 AH |
162 | |
163 | intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps); | |
1c451c13 AH |
164 | } |
165 | ||
166 | static int intel_start_signal_voltage_switch(struct mmc_host *mmc, | |
167 | struct mmc_ios *ios) | |
168 | { | |
169 | struct device *dev = mmc_dev(mmc); | |
170 | struct sdhci_acpi_host *c = dev_get_drvdata(dev); | |
171 | struct intel_host *intel_host = sdhci_acpi_priv(c); | |
172 | unsigned int fn; | |
173 | u32 result = 0; | |
174 | int err; | |
175 | ||
176 | err = sdhci_start_signal_voltage_switch(mmc, ios); | |
177 | if (err) | |
178 | return err; | |
179 | ||
180 | switch (ios->signal_voltage) { | |
181 | case MMC_SIGNAL_VOLTAGE_330: | |
182 | fn = INTEL_DSM_V33_SWITCH; | |
183 | break; | |
184 | case MMC_SIGNAL_VOLTAGE_180: | |
185 | fn = INTEL_DSM_V18_SWITCH; | |
186 | break; | |
187 | default: | |
188 | return 0; | |
189 | } | |
190 | ||
191 | err = intel_dsm(intel_host, dev, fn, &result); | |
192 | pr_debug("%s: %s DSM fn %u error %d result %u\n", | |
193 | mmc_hostname(mmc), __func__, fn, err, result); | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
b04fa064 AH |
198 | static void sdhci_acpi_int_hw_reset(struct sdhci_host *host) |
199 | { | |
200 | u8 reg; | |
201 | ||
202 | reg = sdhci_readb(host, SDHCI_POWER_CONTROL); | |
203 | reg |= 0x10; | |
204 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
205 | /* For eMMC, minimum is 1us but give it 9us for good measure */ | |
206 | udelay(9); | |
207 | reg &= ~0x10; | |
208 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
209 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
210 | usleep_range(300, 1000); | |
211 | } | |
212 | ||
c4e05037 | 213 | static const struct sdhci_ops sdhci_acpi_ops_dflt = { |
1771059c | 214 | .set_clock = sdhci_set_clock, |
2317f56c | 215 | .set_bus_width = sdhci_set_bus_width, |
03231f9b | 216 | .reset = sdhci_reset, |
96d7b78c | 217 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
c4e05037 AH |
218 | }; |
219 | ||
b04fa064 | 220 | static const struct sdhci_ops sdhci_acpi_ops_int = { |
1771059c | 221 | .set_clock = sdhci_set_clock, |
2317f56c | 222 | .set_bus_width = sdhci_set_bus_width, |
03231f9b | 223 | .reset = sdhci_reset, |
96d7b78c | 224 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
b04fa064 AH |
225 | .hw_reset = sdhci_acpi_int_hw_reset, |
226 | }; | |
227 | ||
228 | static const struct sdhci_acpi_chip sdhci_acpi_chip_int = { | |
229 | .ops = &sdhci_acpi_ops_int, | |
230 | }; | |
231 | ||
6e1c7d61 AH |
232 | #ifdef CONFIG_X86 |
233 | ||
234 | static bool sdhci_acpi_byt(void) | |
235 | { | |
236 | static const struct x86_cpu_id byt[] = { | |
f2c4db1b | 237 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT }, |
6e1c7d61 AH |
238 | {} |
239 | }; | |
240 | ||
241 | return x86_match_cpu(byt); | |
242 | } | |
243 | ||
17753d16 AH |
244 | static bool sdhci_acpi_cht(void) |
245 | { | |
246 | static const struct x86_cpu_id cht[] = { | |
247 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, | |
248 | {} | |
249 | }; | |
250 | ||
251 | return x86_match_cpu(cht); | |
252 | } | |
253 | ||
6e1c7d61 AH |
254 | #define BYT_IOSF_SCCEP 0x63 |
255 | #define BYT_IOSF_OCP_NETCTRL0 0x1078 | |
256 | #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) | |
257 | ||
258 | static void sdhci_acpi_byt_setting(struct device *dev) | |
259 | { | |
260 | u32 val = 0; | |
261 | ||
262 | if (!sdhci_acpi_byt()) | |
263 | return; | |
264 | ||
265 | if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, | |
266 | &val)) { | |
267 | dev_err(dev, "%s read error\n", __func__); | |
268 | return; | |
269 | } | |
270 | ||
271 | if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) | |
272 | return; | |
273 | ||
274 | val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; | |
275 | ||
276 | if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, | |
277 | val)) { | |
278 | dev_err(dev, "%s write error\n", __func__); | |
279 | return; | |
280 | } | |
281 | ||
282 | dev_dbg(dev, "%s completed\n", __func__); | |
283 | } | |
284 | ||
285 | static bool sdhci_acpi_byt_defer(struct device *dev) | |
286 | { | |
287 | if (!sdhci_acpi_byt()) | |
288 | return false; | |
289 | ||
290 | if (!iosf_mbi_available()) | |
291 | return true; | |
292 | ||
293 | sdhci_acpi_byt_setting(dev); | |
294 | ||
295 | return false; | |
296 | } | |
297 | ||
17753d16 AH |
298 | static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device, |
299 | unsigned int slot, unsigned int parent_slot) | |
300 | { | |
301 | struct pci_dev *dev, *parent, *from = NULL; | |
302 | ||
303 | while (1) { | |
304 | dev = pci_get_device(vendor, device, from); | |
305 | pci_dev_put(from); | |
306 | if (!dev) | |
307 | break; | |
308 | parent = pci_upstream_bridge(dev); | |
309 | if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot && | |
310 | parent && PCI_SLOT(parent->devfn) == parent_slot && | |
311 | !pci_upstream_bridge(parent)) { | |
312 | pci_dev_put(dev); | |
313 | return true; | |
314 | } | |
315 | from = dev; | |
316 | } | |
317 | ||
318 | return false; | |
319 | } | |
320 | ||
321 | /* | |
322 | * GPDwin uses PCI wifi which conflicts with SDIO's use of | |
323 | * acpi_device_fix_up_power() on child device nodes. Identifying GPDwin is | |
324 | * problematic, but since SDIO is only used for wifi, the presence of the PCI | |
325 | * wifi card in the expected slot with an ACPI companion node, is used to | |
326 | * indicate that acpi_device_fix_up_power() should be avoided. | |
327 | */ | |
328 | static inline bool sdhci_acpi_no_fixup_child_power(const char *hid, | |
329 | const char *uid) | |
330 | { | |
331 | return sdhci_acpi_cht() && | |
332 | !strcmp(hid, "80860F14") && | |
333 | !strcmp(uid, "2") && | |
334 | sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28); | |
335 | } | |
336 | ||
6e1c7d61 AH |
337 | #else |
338 | ||
339 | static inline void sdhci_acpi_byt_setting(struct device *dev) | |
340 | { | |
341 | } | |
342 | ||
343 | static inline bool sdhci_acpi_byt_defer(struct device *dev) | |
344 | { | |
345 | return false; | |
346 | } | |
347 | ||
17753d16 AH |
348 | static inline bool sdhci_acpi_no_fixup_child_power(const char *hid, |
349 | const char *uid) | |
350 | { | |
351 | return false; | |
352 | } | |
353 | ||
6e1c7d61 AH |
354 | #endif |
355 | ||
6a645dd8 AH |
356 | static int bxt_get_cd(struct mmc_host *mmc) |
357 | { | |
358 | int gpio_cd = mmc_gpio_get_cd(mmc); | |
359 | struct sdhci_host *host = mmc_priv(mmc); | |
360 | unsigned long flags; | |
361 | int ret = 0; | |
362 | ||
363 | if (!gpio_cd) | |
364 | return 0; | |
365 | ||
6a645dd8 AH |
366 | spin_lock_irqsave(&host->lock, flags); |
367 | ||
368 | if (host->flags & SDHCI_DEVICE_DEAD) | |
369 | goto out; | |
370 | ||
371 | ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); | |
372 | out: | |
373 | spin_unlock_irqrestore(&host->lock, flags); | |
374 | ||
6a645dd8 AH |
375 | return ret; |
376 | } | |
377 | ||
159cd328 AH |
378 | static int intel_probe_slot(struct platform_device *pdev, const char *hid, |
379 | const char *uid) | |
578b36b6 GY |
380 | { |
381 | struct sdhci_acpi_host *c = platform_get_drvdata(pdev); | |
1c451c13 | 382 | struct intel_host *intel_host = sdhci_acpi_priv(c); |
159cd328 | 383 | struct sdhci_host *host = c->host; |
578b36b6 | 384 | |
8024379e AH |
385 | if (hid && uid && !strcmp(hid, "80860F14") && !strcmp(uid, "1") && |
386 | sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && | |
387 | sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) | |
388 | host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ | |
389 | ||
d3e97407 | 390 | if (hid && !strcmp(hid, "80865ACA")) |
6a645dd8 AH |
391 | host->mmc_host_ops.get_cd = bxt_get_cd; |
392 | ||
1c451c13 AH |
393 | intel_dsm_init(intel_host, &pdev->dev, host->mmc); |
394 | ||
395 | host->mmc_host_ops.start_signal_voltage_switch = | |
396 | intel_start_signal_voltage_switch; | |
397 | ||
578b36b6 GY |
398 | return 0; |
399 | } | |
400 | ||
0acccf41 AH |
401 | static int intel_setup_host(struct platform_device *pdev) |
402 | { | |
403 | struct sdhci_acpi_host *c = platform_get_drvdata(pdev); | |
404 | struct intel_host *intel_host = sdhci_acpi_priv(c); | |
405 | ||
406 | if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25)) | |
407 | c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25; | |
408 | ||
409 | if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50)) | |
410 | c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50; | |
411 | ||
412 | if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50)) | |
413 | c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50; | |
414 | ||
415 | if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104)) | |
416 | c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104; | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
07a58883 | 421 | static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = { |
b04fa064 | 422 | .chip = &sdhci_acpi_chip_int, |
f25c3372 | 423 | .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | |
9d65cb88 | 424 | MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | |
c80f275f | 425 | MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY, |
07a58883 | 426 | .flags = SDHCI_ACPI_RUNTIME_PM, |
197ce1a5 AH |
427 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
428 | SDHCI_QUIRK_NO_LED, | |
e839b134 AH |
429 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
430 | SDHCI_QUIRK2_STOP_WITH_TC | | |
431 | SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400, | |
159cd328 | 432 | .probe_slot = intel_probe_slot, |
0acccf41 | 433 | .setup_host = intel_setup_host, |
1c451c13 | 434 | .priv_size = sizeof(struct intel_host), |
07a58883 AH |
435 | }; |
436 | ||
e5571397 | 437 | static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = { |
e1f5633a | 438 | .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
197ce1a5 | 439 | SDHCI_QUIRK_NO_LED | |
e1f5633a | 440 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
e5571397 | 441 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, |
9d65cb88 | 442 | .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD | |
265984b3 | 443 | MMC_CAP_WAIT_WHILE_BUSY, |
e5571397 AH |
444 | .flags = SDHCI_ACPI_RUNTIME_PM, |
445 | .pm_caps = MMC_PM_KEEP_POWER, | |
159cd328 | 446 | .probe_slot = intel_probe_slot, |
0acccf41 | 447 | .setup_host = intel_setup_host, |
1c451c13 | 448 | .priv_size = sizeof(struct intel_host), |
e5571397 AH |
449 | }; |
450 | ||
07a58883 | 451 | static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = { |
4fd4409c AH |
452 | .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL | |
453 | SDHCI_ACPI_RUNTIME_PM, | |
197ce1a5 AH |
454 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
455 | SDHCI_QUIRK_NO_LED, | |
934e31b9 AH |
456 | .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | |
457 | SDHCI_QUIRK2_STOP_WITH_TC, | |
d3e97407 | 458 | .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM, |
159cd328 | 459 | .probe_slot = intel_probe_slot, |
0acccf41 | 460 | .setup_host = intel_setup_host, |
1c451c13 | 461 | .priv_size = sizeof(struct intel_host), |
07a58883 AH |
462 | }; |
463 | ||
96ccb858 WD |
464 | #define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG 0x1a8 |
465 | #define VENDOR_SPECIFIC_PWRCTL_CTL_REG 0x1ac | |
466 | static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr) | |
467 | { | |
468 | struct sdhci_host *host = ptr; | |
469 | ||
470 | sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG); | |
471 | sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG); | |
472 | ||
473 | return IRQ_HANDLED; | |
474 | } | |
475 | ||
476 | static int qcom_probe_slot(struct platform_device *pdev, const char *hid, | |
477 | const char *uid) | |
478 | { | |
479 | struct sdhci_acpi_host *c = platform_get_drvdata(pdev); | |
480 | struct sdhci_host *host = c->host; | |
481 | int *irq = sdhci_acpi_priv(c); | |
482 | ||
483 | *irq = -EINVAL; | |
484 | ||
485 | if (strcmp(hid, "QCOM8051")) | |
486 | return 0; | |
487 | ||
488 | *irq = platform_get_irq(pdev, 1); | |
489 | if (*irq < 0) | |
490 | return 0; | |
491 | ||
492 | return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler, | |
493 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
494 | "sdhci_qcom", host); | |
495 | } | |
496 | ||
497 | static int qcom_free_slot(struct platform_device *pdev) | |
498 | { | |
499 | struct device *dev = &pdev->dev; | |
500 | struct sdhci_acpi_host *c = platform_get_drvdata(pdev); | |
501 | struct sdhci_host *host = c->host; | |
502 | struct acpi_device *adev; | |
503 | int *irq = sdhci_acpi_priv(c); | |
504 | const char *hid; | |
505 | ||
506 | adev = ACPI_COMPANION(dev); | |
507 | if (!adev) | |
508 | return -ENODEV; | |
509 | ||
510 | hid = acpi_device_hid(adev); | |
511 | if (strcmp(hid, "QCOM8051")) | |
512 | return 0; | |
513 | ||
514 | if (*irq < 0) | |
515 | return 0; | |
516 | ||
517 | free_irq(*irq, host); | |
518 | return 0; | |
519 | } | |
520 | ||
70cce2af PE |
521 | static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = { |
522 | .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION, | |
523 | .quirks2 = SDHCI_QUIRK2_NO_1_8_V, | |
524 | .caps = MMC_CAP_NONREMOVABLE, | |
96ccb858 WD |
525 | .priv_size = sizeof(int), |
526 | .probe_slot = qcom_probe_slot, | |
527 | .free_slot = qcom_free_slot, | |
70cce2af PE |
528 | }; |
529 | ||
530 | static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = { | |
531 | .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION, | |
532 | .caps = MMC_CAP_NONREMOVABLE, | |
533 | }; | |
534 | ||
34597a3f SNB |
535 | /* AMD sdhci reset dll register. */ |
536 | #define SDHCI_AMD_RESET_DLL_REGISTER 0x908 | |
537 | ||
538 | static int amd_select_drive_strength(struct mmc_card *card, | |
539 | unsigned int max_dtr, int host_drv, | |
540 | int card_drv, int *drv_type) | |
541 | { | |
542 | return MMC_SET_DRIVER_TYPE_A; | |
543 | } | |
544 | ||
545 | static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host) | |
546 | { | |
547 | /* AMD Platform requires dll setting */ | |
548 | sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER); | |
549 | usleep_range(10, 20); | |
550 | sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER); | |
551 | } | |
552 | ||
553 | /* | |
554 | * For AMD Platform it is required to disable the tuning | |
555 | * bit first controller to bring to HS Mode from HS200 | |
556 | * mode, later enable to tune to HS400 mode. | |
557 | */ | |
558 | static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
559 | { | |
560 | struct sdhci_host *host = mmc_priv(mmc); | |
561 | unsigned int old_timing = host->timing; | |
562 | ||
563 | sdhci_set_ios(mmc, ios); | |
564 | if (old_timing == MMC_TIMING_MMC_HS200 && | |
565 | ios->timing == MMC_TIMING_MMC_HS) | |
566 | sdhci_writew(host, 0x9, SDHCI_HOST_CONTROL2); | |
567 | if (old_timing != MMC_TIMING_MMC_HS400 && | |
568 | ios->timing == MMC_TIMING_MMC_HS400) { | |
569 | sdhci_writew(host, 0x80, SDHCI_HOST_CONTROL2); | |
570 | sdhci_acpi_amd_hs400_dll(host); | |
571 | } | |
572 | } | |
573 | ||
574 | static const struct sdhci_ops sdhci_acpi_ops_amd = { | |
575 | .set_clock = sdhci_set_clock, | |
576 | .set_bus_width = sdhci_set_bus_width, | |
577 | .reset = sdhci_reset, | |
578 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
579 | }; | |
580 | ||
581 | static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = { | |
582 | .ops = &sdhci_acpi_ops_amd, | |
583 | }; | |
584 | ||
585 | static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev, | |
586 | const char *hid, const char *uid) | |
587 | { | |
588 | struct sdhci_acpi_host *c = platform_get_drvdata(pdev); | |
589 | struct sdhci_host *host = c->host; | |
590 | ||
591 | sdhci_read_caps(host); | |
592 | if (host->caps1 & SDHCI_SUPPORT_DDR50) | |
593 | host->mmc->caps = MMC_CAP_1_8V_DDR; | |
594 | ||
595 | if ((host->caps1 & SDHCI_SUPPORT_SDR104) && | |
596 | (host->mmc->caps & MMC_CAP_1_8V_DDR)) | |
597 | host->mmc->caps2 = MMC_CAP2_HS400_1_8V; | |
598 | ||
599 | host->mmc_host_ops.select_drive_strength = amd_select_drive_strength; | |
600 | host->mmc_host_ops.set_ios = amd_set_ios; | |
601 | return 0; | |
602 | } | |
603 | ||
604 | static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = { | |
605 | .chip = &sdhci_acpi_chip_amd, | |
606 | .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, | |
607 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
608 | SDHCI_QUIRK_32BIT_ADMA_SIZE, | |
609 | .probe_slot = sdhci_acpi_emmc_amd_probe_slot, | |
610 | }; | |
611 | ||
07a58883 AH |
612 | struct sdhci_acpi_uid_slot { |
613 | const char *hid; | |
614 | const char *uid; | |
615 | const struct sdhci_acpi_slot *slot; | |
616 | }; | |
617 | ||
618 | static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = { | |
e839b134 AH |
619 | { "80865ACA", NULL, &sdhci_acpi_slot_int_sd }, |
620 | { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc }, | |
621 | { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio }, | |
07a58883 | 622 | { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc }, |
db52d4f8 | 623 | { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio }, |
07a58883 | 624 | { "80860F14" , "3" , &sdhci_acpi_slot_int_sd }, |
aad95dc4 | 625 | { "80860F16" , NULL, &sdhci_acpi_slot_int_sd }, |
07a58883 | 626 | { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio }, |
7147eaf3 | 627 | { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd }, |
07a58883 | 628 | { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio }, |
07c001c1 | 629 | { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio }, |
d0ed8e6b | 630 | { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio }, |
0cd2f044 | 631 | { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd }, |
07a58883 | 632 | { "PNP0D40" }, |
70cce2af PE |
633 | { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v }, |
634 | { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd }, | |
34597a3f | 635 | { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc }, |
07a58883 AH |
636 | { }, |
637 | }; | |
638 | ||
c4e05037 | 639 | static const struct acpi_device_id sdhci_acpi_ids[] = { |
e839b134 AH |
640 | { "80865ACA" }, |
641 | { "80865ACC" }, | |
642 | { "80865AD0" }, | |
07a58883 | 643 | { "80860F14" }, |
aad95dc4 | 644 | { "80860F16" }, |
07a58883 AH |
645 | { "INT33BB" }, |
646 | { "INT33C6" }, | |
07c001c1 | 647 | { "INT3436" }, |
d0ed8e6b | 648 | { "INT344D" }, |
07a58883 | 649 | { "PNP0D40" }, |
70cce2af PE |
650 | { "QCOM8051" }, |
651 | { "QCOM8052" }, | |
34597a3f | 652 | { "AMDI0040" }, |
c4e05037 AH |
653 | { }, |
654 | }; | |
655 | MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids); | |
656 | ||
3db35251 AH |
657 | static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(const char *hid, |
658 | const char *uid) | |
c4e05037 | 659 | { |
07a58883 AH |
660 | const struct sdhci_acpi_uid_slot *u; |
661 | ||
662 | for (u = sdhci_acpi_uids; u->hid; u++) { | |
663 | if (strcmp(u->hid, hid)) | |
664 | continue; | |
665 | if (!u->uid) | |
666 | return u->slot; | |
667 | if (uid && !strcmp(u->uid, uid)) | |
668 | return u->slot; | |
669 | } | |
c4e05037 AH |
670 | return NULL; |
671 | } | |
672 | ||
4e608e4e | 673 | static int sdhci_acpi_probe(struct platform_device *pdev) |
c4e05037 AH |
674 | { |
675 | struct device *dev = &pdev->dev; | |
f07b7952 | 676 | const struct sdhci_acpi_slot *slot; |
e5bbf307 | 677 | struct acpi_device *device, *child; |
c4e05037 AH |
678 | struct sdhci_acpi_host *c; |
679 | struct sdhci_host *host; | |
680 | struct resource *iomem; | |
681 | resource_size_t len; | |
f07b7952 | 682 | size_t priv_size; |
c4e05037 | 683 | const char *hid; |
3db35251 | 684 | const char *uid; |
87875655 | 685 | int err; |
c4e05037 | 686 | |
cd25c7be AS |
687 | device = ACPI_COMPANION(dev); |
688 | if (!device) | |
c4e05037 AH |
689 | return -ENODEV; |
690 | ||
17753d16 | 691 | hid = acpi_device_hid(device); |
a2038497 | 692 | uid = acpi_device_uid(device); |
17753d16 | 693 | |
f07b7952 AH |
694 | slot = sdhci_acpi_get_slot(hid, uid); |
695 | ||
e5bbf307 AH |
696 | /* Power on the SDHCI controller and its children */ |
697 | acpi_device_fix_up_power(device); | |
17753d16 AH |
698 | if (!sdhci_acpi_no_fixup_child_power(hid, uid)) { |
699 | list_for_each_entry(child, &device->children, node) | |
700 | if (child->status.present && child->status.enabled) | |
701 | acpi_device_fix_up_power(child); | |
702 | } | |
e5bbf307 | 703 | |
6e1c7d61 AH |
704 | if (sdhci_acpi_byt_defer(dev)) |
705 | return -EPROBE_DEFER; | |
706 | ||
c4e05037 AH |
707 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
708 | if (!iomem) | |
709 | return -ENOMEM; | |
710 | ||
711 | len = resource_size(iomem); | |
712 | if (len < 0x100) | |
713 | dev_err(dev, "Invalid iomem size!\n"); | |
714 | ||
715 | if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev))) | |
716 | return -ENOMEM; | |
717 | ||
f07b7952 AH |
718 | priv_size = slot ? slot->priv_size : 0; |
719 | host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size); | |
c4e05037 AH |
720 | if (IS_ERR(host)) |
721 | return PTR_ERR(host); | |
722 | ||
723 | c = sdhci_priv(host); | |
724 | c->host = host; | |
f07b7952 | 725 | c->slot = slot; |
c4e05037 AH |
726 | c->pdev = pdev; |
727 | c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM); | |
728 | ||
729 | platform_set_drvdata(pdev, c); | |
730 | ||
731 | host->hw_name = "ACPI"; | |
732 | host->ops = &sdhci_acpi_ops_dflt; | |
733 | host->irq = platform_get_irq(pdev, 0); | |
d58ac803 | 734 | if (host->irq < 0) { |
1b7ba57e AY |
735 | err = -EINVAL; |
736 | goto err_free; | |
737 | } | |
c4e05037 AH |
738 | |
739 | host->ioaddr = devm_ioremap_nocache(dev, iomem->start, | |
740 | resource_size(iomem)); | |
741 | if (host->ioaddr == NULL) { | |
742 | err = -ENOMEM; | |
743 | goto err_free; | |
744 | } | |
745 | ||
c4e05037 | 746 | if (c->slot) { |
578b36b6 | 747 | if (c->slot->probe_slot) { |
7dafca83 | 748 | err = c->slot->probe_slot(pdev, hid, uid); |
578b36b6 GY |
749 | if (err) |
750 | goto err_free; | |
751 | } | |
c4e05037 AH |
752 | if (c->slot->chip) { |
753 | host->ops = c->slot->chip->ops; | |
754 | host->quirks |= c->slot->chip->quirks; | |
755 | host->quirks2 |= c->slot->chip->quirks2; | |
756 | host->mmc->caps |= c->slot->chip->caps; | |
757 | host->mmc->caps2 |= c->slot->chip->caps2; | |
758 | host->mmc->pm_caps |= c->slot->chip->pm_caps; | |
759 | } | |
760 | host->quirks |= c->slot->quirks; | |
761 | host->quirks2 |= c->slot->quirks2; | |
762 | host->mmc->caps |= c->slot->caps; | |
763 | host->mmc->caps2 |= c->slot->caps2; | |
764 | host->mmc->pm_caps |= c->slot->pm_caps; | |
765 | } | |
766 | ||
0d3e3350 AH |
767 | host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; |
768 | ||
a61abe6e | 769 | if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) { |
4fd4409c AH |
770 | bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL); |
771 | ||
e28d6f04 ZR |
772 | err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0, NULL); |
773 | if (err) { | |
774 | if (err == -EPROBE_DEFER) | |
775 | goto err_free; | |
4fd4409c | 776 | dev_warn(dev, "failed to setup card detect gpio\n"); |
a61abe6e | 777 | c->use_runtime_pm = false; |
4fd4409c | 778 | } |
a61abe6e AH |
779 | } |
780 | ||
0cc1a0f4 | 781 | err = sdhci_setup_host(host); |
4fd4409c AH |
782 | if (err) |
783 | goto err_free; | |
784 | ||
0cc1a0f4 AH |
785 | if (c->slot && c->slot->setup_host) { |
786 | err = c->slot->setup_host(pdev); | |
787 | if (err) | |
788 | goto err_cleanup; | |
789 | } | |
790 | ||
791 | err = __sdhci_add_host(host); | |
792 | if (err) | |
793 | goto err_cleanup; | |
794 | ||
c4e05037 | 795 | if (c->use_runtime_pm) { |
1d1ff458 | 796 | pm_runtime_set_active(dev); |
c4e05037 AH |
797 | pm_suspend_ignore_children(dev, 1); |
798 | pm_runtime_set_autosuspend_delay(dev, 50); | |
799 | pm_runtime_use_autosuspend(dev); | |
800 | pm_runtime_enable(dev); | |
801 | } | |
802 | ||
4e6a2ef9 FZ |
803 | device_enable_async_suspend(dev); |
804 | ||
c4e05037 AH |
805 | return 0; |
806 | ||
0cc1a0f4 AH |
807 | err_cleanup: |
808 | sdhci_cleanup_host(c->host); | |
c4e05037 | 809 | err_free: |
c7eabbee WD |
810 | if (c->slot && c->slot->free_slot) |
811 | c->slot->free_slot(pdev); | |
812 | ||
c4e05037 AH |
813 | sdhci_free_host(c->host); |
814 | return err; | |
815 | } | |
816 | ||
4e608e4e | 817 | static int sdhci_acpi_remove(struct platform_device *pdev) |
c4e05037 AH |
818 | { |
819 | struct sdhci_acpi_host *c = platform_get_drvdata(pdev); | |
820 | struct device *dev = &pdev->dev; | |
821 | int dead; | |
822 | ||
823 | if (c->use_runtime_pm) { | |
824 | pm_runtime_get_sync(dev); | |
825 | pm_runtime_disable(dev); | |
826 | pm_runtime_put_noidle(dev); | |
827 | } | |
828 | ||
578b36b6 GY |
829 | if (c->slot && c->slot->remove_slot) |
830 | c->slot->remove_slot(pdev); | |
831 | ||
c4e05037 AH |
832 | dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); |
833 | sdhci_remove_host(c->host, dead); | |
c7eabbee WD |
834 | |
835 | if (c->slot && c->slot->free_slot) | |
836 | c->slot->free_slot(pdev); | |
837 | ||
c4e05037 AH |
838 | sdhci_free_host(c->host); |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
843 | #ifdef CONFIG_PM_SLEEP | |
844 | ||
845 | static int sdhci_acpi_suspend(struct device *dev) | |
846 | { | |
847 | struct sdhci_acpi_host *c = dev_get_drvdata(dev); | |
d38dcad4 | 848 | struct sdhci_host *host = c->host; |
c4e05037 | 849 | |
d38dcad4 AH |
850 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
851 | mmc_retune_needed(host->mmc); | |
852 | ||
853 | return sdhci_suspend_host(host); | |
c4e05037 AH |
854 | } |
855 | ||
856 | static int sdhci_acpi_resume(struct device *dev) | |
857 | { | |
858 | struct sdhci_acpi_host *c = dev_get_drvdata(dev); | |
859 | ||
6e1c7d61 AH |
860 | sdhci_acpi_byt_setting(&c->pdev->dev); |
861 | ||
c4e05037 AH |
862 | return sdhci_resume_host(c->host); |
863 | } | |
864 | ||
c4e05037 AH |
865 | #endif |
866 | ||
162d6f98 | 867 | #ifdef CONFIG_PM |
c4e05037 AH |
868 | |
869 | static int sdhci_acpi_runtime_suspend(struct device *dev) | |
870 | { | |
871 | struct sdhci_acpi_host *c = dev_get_drvdata(dev); | |
d38dcad4 AH |
872 | struct sdhci_host *host = c->host; |
873 | ||
874 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) | |
875 | mmc_retune_needed(host->mmc); | |
c4e05037 | 876 | |
d38dcad4 | 877 | return sdhci_runtime_suspend_host(host); |
c4e05037 AH |
878 | } |
879 | ||
880 | static int sdhci_acpi_runtime_resume(struct device *dev) | |
881 | { | |
882 | struct sdhci_acpi_host *c = dev_get_drvdata(dev); | |
883 | ||
6e1c7d61 AH |
884 | sdhci_acpi_byt_setting(&c->pdev->dev); |
885 | ||
c4e05037 AH |
886 | return sdhci_runtime_resume_host(c->host); |
887 | } | |
888 | ||
c4e05037 AH |
889 | #endif |
890 | ||
891 | static const struct dev_pm_ops sdhci_acpi_pm_ops = { | |
dafed447 | 892 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume) |
1d75f74b | 893 | SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend, |
9b449e99 | 894 | sdhci_acpi_runtime_resume, NULL) |
c4e05037 AH |
895 | }; |
896 | ||
897 | static struct platform_driver sdhci_acpi_driver = { | |
898 | .driver = { | |
899 | .name = "sdhci-acpi", | |
c4e05037 AH |
900 | .acpi_match_table = sdhci_acpi_ids, |
901 | .pm = &sdhci_acpi_pm_ops, | |
902 | }, | |
903 | .probe = sdhci_acpi_probe, | |
4e608e4e | 904 | .remove = sdhci_acpi_remove, |
c4e05037 AH |
905 | }; |
906 | ||
907 | module_platform_driver(sdhci_acpi_driver); | |
908 | ||
909 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver"); | |
910 | MODULE_AUTHOR("Adrian Hunter"); | |
911 | MODULE_LICENSE("GPL v2"); |