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MMC: DMA free fix for S3C24XX SD/MMC driver
[linux-2.6-block.git] / drivers / mmc / host / s3cmci.c
CommitLineData
be518018
TK		 1/*
2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
3 *
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/dma-mapping.h>
13#include <linux/clk.h>
14#include <linux/mmc/host.h>
15#include <linux/platform_device.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18
19#include <asm/dma.h>
20
21#include <asm/arch/regs-sdi.h>
22#include <asm/arch/regs-gpio.h>
23
24#include "s3cmci.h"
25
26#define DRIVER_NAME "s3c-mci"
27
28enum dbg_channels {
29 dbg_err = (1 << 0),
30 dbg_debug = (1 << 1),
31 dbg_info = (1 << 2),
32 dbg_irq = (1 << 3),
33 dbg_sg = (1 << 4),
34 dbg_dma = (1 << 5),
35 dbg_pio = (1 << 6),
36 dbg_fail = (1 << 7),
37 dbg_conf = (1 << 8),
38};
39
40static const int dbgmap_err = dbg_err | dbg_fail;
41static const int dbgmap_info = dbg_info | dbg_conf;
42static const int dbgmap_debug = dbg_debug;
43
44#define dbg(host, channels, args...) \
45 do { \
46 if (dbgmap_err & channels) \
47 dev_err(&host->pdev->dev, args); \
48 else if (dbgmap_info & channels) \
49 dev_info(&host->pdev->dev, args); \
50 else if (dbgmap_debug & channels) \
51 dev_dbg(&host->pdev->dev, args); \
52 } while (0)
53
54#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
55
56static struct s3c2410_dma_client s3cmci_dma_client = {
57 .name = "s3c-mci",
58};
59
60static void finalize_request(struct s3cmci_host *host);
61static void s3cmci_send_request(struct mmc_host *mmc);
62static void s3cmci_reset(struct s3cmci_host *host);
63
64#ifdef CONFIG_MMC_DEBUG
65
66static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
67{
68 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
69 u32 datcon, datcnt, datsta, fsta, imask;
70
71 con = readl(host->base + S3C2410_SDICON);
72 pre = readl(host->base + S3C2410_SDIPRE);
73 cmdarg = readl(host->base + S3C2410_SDICMDARG);
74 cmdcon = readl(host->base + S3C2410_SDICMDCON);
75 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
76 r0 = readl(host->base + S3C2410_SDIRSP0);
77 r1 = readl(host->base + S3C2410_SDIRSP1);
78 r2 = readl(host->base + S3C2410_SDIRSP2);
79 r3 = readl(host->base + S3C2410_SDIRSP3);
80 timer = readl(host->base + S3C2410_SDITIMER);
81 bsize = readl(host->base + S3C2410_SDIBSIZE);
82 datcon = readl(host->base + S3C2410_SDIDCON);
83 datcnt = readl(host->base + S3C2410_SDIDCNT);
84 datsta = readl(host->base + S3C2410_SDIDSTA);
85 fsta = readl(host->base + S3C2410_SDIFSTA);
86 imask = readl(host->base + host->sdiimsk);
87
88 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
89 prefix, con, pre, timer);
90
91 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
92 prefix, cmdcon, cmdarg, cmdsta);
93
94 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
95 " DSTA:[%08x] DCNT:[%08x]\n",
96 prefix, datcon, fsta, datsta, datcnt);
97
98 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
99 " R2:[%08x] R3:[%08x]\n",
100 prefix, r0, r1, r2, r3);
101}
102
103static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
104 int stop)
105{
106 snprintf(host->dbgmsg_cmd, 300,
107 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
108 host->ccnt, (stop ? " (STOP)" : ""),
109 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
110
111 if (cmd->data) {
112 snprintf(host->dbgmsg_dat, 300,
113 "#%u bsize:%u blocks:%u bytes:%u",
114 host->dcnt, cmd->data->blksz,
115 cmd->data->blocks,
116 cmd->data->blocks * cmd->data->blksz);
117 } else {
118 host->dbgmsg_dat[0] = '\0';
119 }
120}
121
122static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
123 int fail)
124{
125 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
126
127 if (!cmd)
128 return;
129
130 if (cmd->error == 0) {
131 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
132 host->dbgmsg_cmd, cmd->resp[0]);
133 } else {
134 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
135 cmd->error, host->dbgmsg_cmd, host->status);
136 }
137
138 if (!cmd->data)
139 return;
140
141 if (cmd->data->error == 0) {
142 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
143 } else {
144 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
145 cmd->data->error, host->dbgmsg_dat,
146 readl(host->base + S3C2410_SDIDCNT));
147 }
148}
149#else
150static void dbg_dumpcmd(struct s3cmci_host *host,
151 struct mmc_command *cmd, int fail) { }
152
153static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
154 int stop) { }
155
156static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
157
158#endif /* CONFIG_MMC_DEBUG */
159
160static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
161{
162 u32 newmask;
163
164 newmask = readl(host->base + host->sdiimsk);
165 newmask |= imask;
166
167 writel(newmask, host->base + host->sdiimsk);
168
169 return newmask;
170}
171
172static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
173{
174 u32 newmask;
175
176 newmask = readl(host->base + host->sdiimsk);
177 newmask &= ~imask;
178
179 writel(newmask, host->base + host->sdiimsk);
180
181 return newmask;
182}
183
184static inline void clear_imask(struct s3cmci_host *host)
185{
186 writel(0, host->base + host->sdiimsk);
187}
188
189static inline int get_data_buffer(struct s3cmci_host *host,
190 u32 *words, u32 **pointer)
191{
192 struct scatterlist *sg;
193
194 if (host->pio_active == XFER_NONE)
195 return -EINVAL;
196
197 if ((!host->mrq) || (!host->mrq->data))
198 return -EINVAL;
199
200 if (host->pio_sgptr >= host->mrq->data->sg_len) {
201 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
202 host->pio_sgptr, host->mrq->data->sg_len);
203 return -EBUSY;
204 }
205 sg = &host->mrq->data->sg[host->pio_sgptr];
206
207 *words = sg->length >> 2;
208 *pointer = sg_virt(sg);
209
210 host->pio_sgptr++;
211
212 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
213 host->pio_sgptr, host->mrq->data->sg_len);
214
215 return 0;
216}
217
218static inline u32 fifo_count(struct s3cmci_host *host)
219{
220 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
221
222 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
223 return fifostat >> 2;
224}
225
226static inline u32 fifo_free(struct s3cmci_host *host)
227{
228 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
229
230 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
231 return (63 - fifostat) >> 2;
232}
233
234static void do_pio_read(struct s3cmci_host *host)
235{
236 int res;
237 u32 fifo;
238 void __iomem *from_ptr;
239
240 /* write real prescaler to host, it might be set slow to fix */
241 writel(host->prescaler, host->base + S3C2410_SDIPRE);
242
243 from_ptr = host->base + host->sdidata;
244
245 while ((fifo = fifo_count(host))) {
246 if (!host->pio_words) {
247 res = get_data_buffer(host, &host->pio_words,
248 &host->pio_ptr);
249 if (res) {
250 host->pio_active = XFER_NONE;
251 host->complete_what = COMPLETION_FINALIZE;
252
253 dbg(host, dbg_pio, "pio_read(): "
254 "complete (no more data).\n");
255 return;
256 }
257
258 dbg(host, dbg_pio,
259 "pio_read(): new target: [%i]@[%p]\n",
260 host->pio_words, host->pio_ptr);
261 }
262
263 dbg(host, dbg_pio,
264 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
265 fifo, host->pio_words,
266 readl(host->base + S3C2410_SDIDCNT));
267
268 if (fifo > host->pio_words)
269 fifo = host->pio_words;
270
271 host->pio_words -= fifo;
272 host->pio_count += fifo;
273
274 while (fifo--)
275 *(host->pio_ptr++) = readl(from_ptr);
276 }
277
278 if (!host->pio_words) {
279 res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
280 if (res) {
281 dbg(host, dbg_pio,
282 "pio_read(): complete (no more buffers).\n");
283 host->pio_active = XFER_NONE;
284 host->complete_what = COMPLETION_FINALIZE;
285
286 return;
287 }
288 }
289
290 enable_imask(host,
291 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
292}
293
294static void do_pio_write(struct s3cmci_host *host)
295{
296 void __iomem *to_ptr;
297 int res;
298 u32 fifo;
299
300 to_ptr = host->base + host->sdidata;
301
302 while ((fifo = fifo_free(host))) {
303 if (!host->pio_words) {
304 res = get_data_buffer(host, &host->pio_words,
305 &host->pio_ptr);
306 if (res) {
307 dbg(host, dbg_pio,
308 "pio_write(): complete (no more data).\n");
309 host->pio_active = XFER_NONE;
310
311 return;
312 }
313
314 dbg(host, dbg_pio,
315 "pio_write(): new source: [%i]@[%p]\n",
316 host->pio_words, host->pio_ptr);
317
318 }
319
320 if (fifo > host->pio_words)
321 fifo = host->pio_words;
322
323 host->pio_words -= fifo;
324 host->pio_count += fifo;
325
326 while (fifo--)
327 writel(*(host->pio_ptr++), to_ptr);
328 }
329
330 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
331}
332
333static void pio_tasklet(unsigned long data)
334{
335 struct s3cmci_host *host = (struct s3cmci_host *) data;
336
337
338 if (host->pio_active == XFER_WRITE)
339 do_pio_write(host);
340
341 if (host->pio_active == XFER_READ)
342 do_pio_read(host);
343
344 if (host->complete_what == COMPLETION_FINALIZE) {
345 clear_imask(host);
346 if (host->pio_active != XFER_NONE) {
347 dbg(host, dbg_err, "unfinished %s "
348 "- pio_count:[%u] pio_words:[%u]\n",
349 (host->pio_active == XFER_READ) ? "read" : "write",
350 host->pio_count, host->pio_words);
351
352 host->mrq->data->error = -EINVAL;
353 }
354
355 disable_irq(host->irq);
356 finalize_request(host);
357 }
358}
359
360/*
361 * ISR for SDI Interface IRQ
362 * Communication between driver and ISR works as follows:
363 * host->mrq points to current request
364 * host->complete_what Indicates when the request is considered done
365 * COMPLETION_CMDSENT when the command was sent
366 * COMPLETION_RSPFIN when a response was received
367 * COMPLETION_XFERFINISH when the data transfer is finished
368 * COMPLETION_XFERFINISH_RSPFIN both of the above.
369 * host->complete_request is the completion-object the driver waits for
370 *
371 * 1) Driver sets up host->mrq and host->complete_what
372 * 2) Driver prepares the transfer
373 * 3) Driver enables interrupts
374 * 4) Driver starts transfer
375 * 5) Driver waits for host->complete_rquest
376 * 6) ISR checks for request status (errors and success)
377 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
378 * 7) ISR completes host->complete_request
379 * 8) ISR disables interrupts
380 * 9) Driver wakes up and takes care of the request
381 *
382 * Note: "->error"-fields are expected to be set to 0 before the request
383 * was issued by mmc.c - therefore they are only set, when an error
384 * contition comes up
385 */
386
387static irqreturn_t s3cmci_irq(int irq, void *dev_id)
388{
389 struct s3cmci_host *host = dev_id;
390 struct mmc_command *cmd;
391 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
392 u32 mci_cclear, mci_dclear;
393 unsigned long iflags;
394
395 spin_lock_irqsave(&host->complete_lock, iflags);
396
397 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
398 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
399 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
400 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
401 mci_imsk = readl(host->base + host->sdiimsk);
402 mci_cclear = 0;
403 mci_dclear = 0;
404
405 if ((host->complete_what == COMPLETION_NONE) ||
406 (host->complete_what == COMPLETION_FINALIZE)) {
407 host->status = "nothing to complete";
408 clear_imask(host);
409 goto irq_out;
410 }
411
412 if (!host->mrq) {
413 host->status = "no active mrq";
414 clear_imask(host);
415 goto irq_out;
416 }
417
418 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
419
420 if (!cmd) {
421 host->status = "no active cmd";
422 clear_imask(host);
423 goto irq_out;
424 }
425
426 if (!host->dodma) {
427 if ((host->pio_active == XFER_WRITE) &&
428 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
429
430 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
431 tasklet_schedule(&host->pio_tasklet);
432 host->status = "pio tx";
433 }
434
435 if ((host->pio_active == XFER_READ) &&
436 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
437
438 disable_imask(host,
439 S3C2410_SDIIMSK_RXFIFOHALF |
440 S3C2410_SDIIMSK_RXFIFOLAST);
441
442 tasklet_schedule(&host->pio_tasklet);
443 host->status = "pio rx";
444 }
445 }
446
447 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
448 cmd->error = -ETIMEDOUT;
449 host->status = "error: command timeout";
450 goto fail_transfer;
451 }
452
453 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
454 if (host->complete_what == COMPLETION_CMDSENT) {
455 host->status = "ok: command sent";
456 goto close_transfer;
457 }
458
459 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
460 }
461
462 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
463 if (cmd->flags & MMC_RSP_CRC) {
679f0f8a
HW		 464 if (host->mrq->cmd->flags & MMC_RSP_136) {
465 dbg(host, dbg_irq,
466 "fixup: ignore CRC fail with long rsp\n");
467 } else {
468 /* note, we used to fail the transfer
469 * here, but it seems that this is just
470 * the hardware getting it wrong.
471 *
472 * cmd->error = -EILSEQ;
473 * host->status = "error: bad command crc";
474 * goto fail_transfer;
475 */
476 }
be518018
TK		 477 }
478
479 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
480 }
481
482 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
483 if (host->complete_what == COMPLETION_RSPFIN) {
484 host->status = "ok: command response received";
485 goto close_transfer;
486 }
487
488 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
489 host->complete_what = COMPLETION_XFERFINISH;
490
491 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
492 }
493
494 /* errors handled after this point are only relevant
495 when a data transfer is in progress */
496
497 if (!cmd->data)
498 goto clear_status_bits;
499
500 /* Check for FIFO failure */
501 if (host->is2440) {
502 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
503 host->mrq->data->error = -EILSEQ;
504 host->status = "error: 2440 fifo failure";
505 goto fail_transfer;
506 }
507 } else {
508 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
509 cmd->data->error = -EILSEQ;
510 host->status = "error: fifo failure";
511 goto fail_transfer;
512 }
513 }
514
515 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
516 cmd->data->error = -EILSEQ;
517 host->status = "error: bad data crc (outgoing)";
518 goto fail_transfer;
519 }
520
521 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
522 cmd->data->error = -EILSEQ;
523 host->status = "error: bad data crc (incoming)";
524 goto fail_transfer;
525 }
526
527 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
528 cmd->data->error = -ETIMEDOUT;
529 host->status = "error: data timeout";
530 goto fail_transfer;
531 }
532
533 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
534 if (host->complete_what == COMPLETION_XFERFINISH) {
535 host->status = "ok: data transfer completed";
536 goto close_transfer;
537 }
538
539 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
540 host->complete_what = COMPLETION_RSPFIN;
541
542 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
543 }
544
545clear_status_bits:
546 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
547 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
548
549 goto irq_out;
550
551fail_transfer:
552 host->pio_active = XFER_NONE;
553
554close_transfer:
555 host->complete_what = COMPLETION_FINALIZE;
556
557 clear_imask(host);
558 tasklet_schedule(&host->pio_tasklet);
559
560 goto irq_out;
561
562irq_out:
563 dbg(host, dbg_irq,
564 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
565 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
566
567 spin_unlock_irqrestore(&host->complete_lock, iflags);
568 return IRQ_HANDLED;
569
570}
571
572/*
573 * ISR for the CardDetect Pin
574*/
575
576static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
577{
578 struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
579
580 dbg(host, dbg_irq, "card detect\n");
581
582 mmc_detect_change(host->mmc, 500);
583
584 return IRQ_HANDLED;
585}
586
587void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch, void *buf_id,
588 int size, enum s3c2410_dma_buffresult result)
589{
590 struct s3cmci_host *host = buf_id;
591 unsigned long iflags;
592 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
593
594 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
595 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
596 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
597 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
598
599 BUG_ON(!host->mrq);
600 BUG_ON(!host->mrq->data);
601 BUG_ON(!host->dmatogo);
602
603 spin_lock_irqsave(&host->complete_lock, iflags);
604
605 if (result != S3C2410_RES_OK) {
606 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
607 "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
608 mci_csta, mci_dsta, mci_fsta,
609 mci_dcnt, result, host->dmatogo);
610
611 goto fail_request;
612 }
613
614 host->dmatogo--;
615 if (host->dmatogo) {
616 dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] "
617 "DCNT:[%08x] toGo:%u\n",
618 size, mci_dsta, mci_dcnt, host->dmatogo);
619
620 goto out;
621 }
622
623 dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
624 size, mci_dsta, mci_dcnt);
625
626 host->complete_what = COMPLETION_FINALIZE;
627
628out:
629 tasklet_schedule(&host->pio_tasklet);
630 spin_unlock_irqrestore(&host->complete_lock, iflags);
631 return;
632
633
634fail_request:
635 host->mrq->data->error = -EINVAL;
636 host->complete_what = COMPLETION_FINALIZE;
637 writel(0, host->base + host->sdiimsk);
638 goto out;
639
640}
641
642static void finalize_request(struct s3cmci_host *host)
643{
644 struct mmc_request *mrq = host->mrq;
645 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
646 int debug_as_failure = 0;
647
648 if (host->complete_what != COMPLETION_FINALIZE)
649 return;
650
651 if (!mrq)
652 return;
653
654 if (cmd->data && (cmd->error == 0) &&
655 (cmd->data->error == 0)) {
656 if (host->dodma && (!host->dma_complete)) {
657 dbg(host, dbg_dma, "DMA Missing!\n");
658 return;
659 }
660 }
661
662 /* Read response from controller. */
663 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
664 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
665 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
666 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
667
668 writel(host->prescaler, host->base + S3C2410_SDIPRE);
669
670 if (cmd->error)
671 debug_as_failure = 1;
672
673 if (cmd->data && cmd->data->error)
674 debug_as_failure = 1;
675
676 dbg_dumpcmd(host, cmd, debug_as_failure);
677
678 /* Cleanup controller */
679 writel(0, host->base + S3C2410_SDICMDARG);
680 writel(0, host->base + S3C2410_SDIDCON);
681 writel(0, host->base + S3C2410_SDICMDCON);
682 writel(0, host->base + host->sdiimsk);
683
684 if (cmd->data && cmd->error)
685 cmd->data->error = cmd->error;
686
687 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
688 host->cmd_is_stop = 1;
689 s3cmci_send_request(host->mmc);
690 return;
691 }
692
693 /* If we have no data transfer we are finished here */
694 if (!mrq->data)
695 goto request_done;
696
697 /* Calulate the amout of bytes transfer if there was no error */
698 if (mrq->data->error == 0) {
699 mrq->data->bytes_xfered =
700 (mrq->data->blocks * mrq->data->blksz);
701 } else {
702 mrq->data->bytes_xfered = 0;
703 }
704
705 /* If we had an error while transfering data we flush the
706 * DMA channel and the fifo to clear out any garbage. */
707 if (mrq->data->error != 0) {
708 if (host->dodma)
709 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
710
711 if (host->is2440) {
712 /* Clear failure register and reset fifo. */
713 writel(S3C2440_SDIFSTA_FIFORESET |
714 S3C2440_SDIFSTA_FIFOFAIL,
715 host->base + S3C2410_SDIFSTA);
716 } else {
717 u32 mci_con;
718
719 /* reset fifo */
720 mci_con = readl(host->base + S3C2410_SDICON);
721 mci_con |= S3C2410_SDICON_FIFORESET;
722
723 writel(mci_con, host->base + S3C2410_SDICON);
724 }
725 }
726
727request_done:
728 host->complete_what = COMPLETION_NONE;
729 host->mrq = NULL;
730 mmc_request_done(host->mmc, mrq);
731}
732
733
734void s3cmci_dma_setup(struct s3cmci_host *host, enum s3c2410_dmasrc source)
735{
736 static enum s3c2410_dmasrc last_source = -1;
737 static int setup_ok;
738
739 if (last_source == source)
740 return;
741
742 last_source = source;
743
744 s3c2410_dma_devconfig(host->dma, source, 3,
745 host->mem->start + host->sdidata);
746
747 if (!setup_ok) {
748 s3c2410_dma_config(host->dma, 4,
749 (S3C2410_DCON_HWTRIG | S3C2410_DCON_CH0_SDI));
750 s3c2410_dma_set_buffdone_fn(host->dma,
751 s3cmci_dma_done_callback);
752 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
753 setup_ok = 1;
754 }
755}
756
757static void s3cmci_send_command(struct s3cmci_host *host,
758 struct mmc_command *cmd)
759{
760 u32 ccon, imsk;
761
762 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
763 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
764 S3C2410_SDIIMSK_RESPONSECRC;
765
766 enable_imask(host, imsk);
767
768 if (cmd->data)
769 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
770 else if (cmd->flags & MMC_RSP_PRESENT)
771 host->complete_what = COMPLETION_RSPFIN;
772 else
773 host->complete_what = COMPLETION_CMDSENT;
774
775 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
776
777 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
778 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
779
780 if (cmd->flags & MMC_RSP_PRESENT)
781 ccon |= S3C2410_SDICMDCON_WAITRSP;
782
783 if (cmd->flags & MMC_RSP_136)
784 ccon |= S3C2410_SDICMDCON_LONGRSP;
785
786 writel(ccon, host->base + S3C2410_SDICMDCON);
787}
788
789static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
790{
791 u32 dcon, imsk, stoptries = 3;
792
793 /* write DCON register */
794
795 if (!data) {
796 writel(0, host->base + S3C2410_SDIDCON);
797 return 0;
798 }
799
800 while (readl(host->base + S3C2410_SDIDSTA) &
801 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
802
803 dbg(host, dbg_err,
804 "mci_setup_data() transfer stillin progress.\n");
805
806 writel(0, host->base + S3C2410_SDIDCON);
807 s3cmci_reset(host);
808
809 if ((stoptries--) == 0) {
810 dbg_dumpregs(host, "DRF");
811 return -EINVAL;
812 }
813 }
814
815 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
816
817 if (host->dodma)
818 dcon |= S3C2410_SDIDCON_DMAEN;
819
820 if (host->bus_width == MMC_BUS_WIDTH_4)
821 dcon |= S3C2410_SDIDCON_WIDEBUS;
822
823 if (!(data->flags & MMC_DATA_STREAM))
824 dcon |= S3C2410_SDIDCON_BLOCKMODE;
825
826 if (data->flags & MMC_DATA_WRITE) {
827 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
828 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
829 }
830
831 if (data->flags & MMC_DATA_READ) {
832 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
833 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
834 }
835
836 if (host->is2440) {
837 dcon |= S3C2440_SDIDCON_DS_WORD;
838 dcon |= S3C2440_SDIDCON_DATSTART;
839 }
840
841 writel(dcon, host->base + S3C2410_SDIDCON);
842
843 /* write BSIZE register */
844
845 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
846
847 /* add to IMASK register */
848 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
849 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
850
851 enable_imask(host, imsk);
852
853 /* write TIMER register */
854
855 if (host->is2440) {
856 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
857 } else {
858 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
859
860 /* FIX: set slow clock to prevent timeouts on read */
861 if (data->flags & MMC_DATA_READ)
862 writel(0xFF, host->base + S3C2410_SDIPRE);
863 }
864
865 return 0;
866}
867
868#define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
869
870static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
871{
872 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
873
874 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
875
876 host->pio_sgptr = 0;
877 host->pio_words = 0;
878 host->pio_count = 0;
879 host->pio_active = rw ? XFER_WRITE : XFER_READ;
880
881 if (rw) {
882 do_pio_write(host);
883 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
884 } else {
885 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
886 | S3C2410_SDIIMSK_RXFIFOLAST);
887 }
888
889 return 0;
890}
891
892static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
893{
894 int dma_len, i;
895 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
896
897 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
898
899 s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW);
900 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
901
902 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
903 (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
904
905 if (dma_len == 0)
906 return -ENOMEM;
907
908 host->dma_complete = 0;
909 host->dmatogo = dma_len;
910
911 for (i = 0; i < dma_len; i++) {
912 int res;
913
914 dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i,
915 sg_dma_address(&data->sg[i]),
916 sg_dma_len(&data->sg[i]));
917
918 res = s3c2410_dma_enqueue(host->dma, (void *) host,
919 sg_dma_address(&data->sg[i]),
920 sg_dma_len(&data->sg[i]));
921
922 if (res) {
923 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
924 return -EBUSY;
925 }
926 }
927
928 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
929
930 return 0;
931}
932
933static void s3cmci_send_request(struct mmc_host *mmc)
934{
935 struct s3cmci_host *host = mmc_priv(mmc);
936 struct mmc_request *mrq = host->mrq;
937 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
938
939 host->ccnt++;
940 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
941
942 /* Clear command, data and fifo status registers
943 Fifo clear only necessary on 2440, but doesn't hurt on 2410
944 */
945 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
946 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
947 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
948
949 if (cmd->data) {
950 int res = s3cmci_setup_data(host, cmd->data);
951
952 host->dcnt++;
953
954 if (res) {
955 cmd->error = -EINVAL;
956 cmd->data->error = -EINVAL;
957
958 mmc_request_done(mmc, mrq);
959 return;
960 }
961
962 if (host->dodma)
963 res = s3cmci_prepare_dma(host, cmd->data);
964 else
965 res = s3cmci_prepare_pio(host, cmd->data);
966
967 if (res) {
968 cmd->error = res;
969 cmd->data->error = res;
970
971 mmc_request_done(mmc, mrq);
972 return;
973 }
974 }
975
976 /* Send command */
977 s3cmci_send_command(host, cmd);
978
979 /* Enable Interrupt */
980 enable_irq(host->irq);
981}
982
983static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
984{
985 struct s3cmci_host *host = mmc_priv(mmc);
986
987 host->status = "mmc request";
988 host->cmd_is_stop = 0;
989 host->mrq = mrq;
990
991 s3cmci_send_request(mmc);
992}
993
994static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
995{
996 struct s3cmci_host *host = mmc_priv(mmc);
997 u32 mci_psc, mci_con;
998
999 /* Set the power state */
1000
1001 mci_con = readl(host->base + S3C2410_SDICON);
1002
1003 switch (ios->power_mode) {
1004 case MMC_POWER_ON:
1005 case MMC_POWER_UP:
1006 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK);
1007 s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD);
1008 s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0);
1009 s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
1010 s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2);
1011 s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3);
1012
1013 if (!host->is2440)
1014 mci_con |= S3C2410_SDICON_FIFORESET;
1015
1016 break;
1017
1018 case MMC_POWER_OFF:
1019 default:
1020 s3c2410_gpio_setpin(S3C2410_GPE5, 0);
1021 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_OUTP);
1022
1023 if (host->is2440)
1024 mci_con |= S3C2440_SDICON_SDRESET;
1025
1026 break;
1027 }
1028
1029 /* Set clock */
1030 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1031 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1032
1033 if (host->real_rate <= ios->clock)
1034 break;
1035 }
1036
1037 if (mci_psc > 255)
1038 mci_psc = 255;
1039
1040 host->prescaler = mci_psc;
1041 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1042
1043 /* If requested clock is 0, real_rate will be 0, too */
1044 if (ios->clock == 0)
1045 host->real_rate = 0;
1046
1047 /* Set CLOCK_ENABLE */
1048 if (ios->clock)
1049 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1050 else
1051 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1052
1053 writel(mci_con, host->base + S3C2410_SDICON);
1054
1055 if ((ios->power_mode == MMC_POWER_ON) ||
1056 (ios->power_mode == MMC_POWER_UP)) {
1057 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1058 host->real_rate/1000, ios->clock/1000);
1059 } else {
1060 dbg(host, dbg_conf, "powered down.\n");
1061 }
1062
1063 host->bus_width = ios->bus_width;
1064}
1065
1066static void s3cmci_reset(struct s3cmci_host *host)
1067{
1068 u32 con = readl(host->base + S3C2410_SDICON);
1069
1070 con |= S3C2440_SDICON_SDRESET;
1071 writel(con, host->base + S3C2410_SDICON);
1072}
1073
1074static struct mmc_host_ops s3cmci_ops = {
1075 .request = s3cmci_request,
1076 .set_ios = s3cmci_set_ios,
1077};
1078
1079static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440)
1080{
1081 struct s3cmci_host *host;
1082 struct mmc_host *mmc;
1083 int ret;
1084
1085 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1086 if (!mmc) {
1087 ret = -ENOMEM;
1088 goto probe_out;
1089 }
1090
1091 host = mmc_priv(mmc);
1092 host->mmc = mmc;
1093 host->pdev = pdev;
1094 host->is2440 = is2440;
1095
1096 spin_lock_init(&host->complete_lock);
1097 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1098
1099 if (is2440) {
1100 host->sdiimsk = S3C2440_SDIIMSK;
1101 host->sdidata = S3C2440_SDIDATA;
1102 host->clk_div = 1;
1103 } else {
1104 host->sdiimsk = S3C2410_SDIIMSK;
1105 host->sdidata = S3C2410_SDIDATA;
1106 host->clk_div = 2;
1107 }
1108
1109 host->dodma = 0;
1110 host->complete_what = COMPLETION_NONE;
1111 host->pio_active = XFER_NONE;
1112
1113 host->dma = S3CMCI_DMA;
1114 host->irq_cd = IRQ_EINT2;
1115
1116 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1117 if (!host->mem) {
1118 dev_err(&pdev->dev,
1119 "failed to get io memory region resouce.\n");
1120
1121 ret = -ENOENT;
1122 goto probe_free_host;
1123 }
1124
1125 host->mem = request_mem_region(host->mem->start,
1126 RESSIZE(host->mem), pdev->name);
1127
1128 if (!host->mem) {
1129 dev_err(&pdev->dev, "failed to request io memory region.\n");
1130 ret = -ENOENT;
1131 goto probe_free_host;
1132 }
1133
1134 host->base = ioremap(host->mem->start, RESSIZE(host->mem));
1135 if (host->base == 0) {
1136 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1137 ret = -EINVAL;
1138 goto probe_free_mem_region;
1139 }
1140
1141 host->irq = platform_get_irq(pdev, 0);
1142 if (host->irq == 0) {
1143 dev_err(&pdev->dev, "failed to get interrupt resouce.\n");
1144 ret = -EINVAL;
1145 goto probe_iounmap;
1146 }
1147
1148 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1149 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1150 ret = -ENOENT;
1151 goto probe_iounmap;
1152 }
1153
1154 /* We get spurious interrupts even when we have set the IMSK
1155 * register to ignore everything, so use disable_irq() to make
1156 * ensure we don't lock the system with un-serviceable requests. */
1157
1158 disable_irq(host->irq);
1159
1160 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_EINT2);
1161 set_irq_type(host->irq_cd, IRQT_BOTHEDGE);
1162
1163 if (request_irq(host->irq_cd, s3cmci_irq_cd, 0, DRIVER_NAME, host)) {
1164 dev_err(&pdev->dev,
1165 "failed to request card detect interrupt.\n");
1166 ret = -ENOENT;
1167 goto probe_free_irq;
1168 }
1169
1170 if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL)) {
1171 dev_err(&pdev->dev, "unable to get DMA channel.\n");
1172 ret = -EBUSY;
1173 goto probe_free_irq_cd;
1174 }
1175
1176 host->clk = clk_get(&pdev->dev, "sdi");
1177 if (IS_ERR(host->clk)) {
1178 dev_err(&pdev->dev, "failed to find clock source.\n");
1179 ret = PTR_ERR(host->clk);
1180 host->clk = NULL;
1181 goto probe_free_host;
1182 }
1183
1184 ret = clk_enable(host->clk);
1185 if (ret) {
1186 dev_err(&pdev->dev, "failed to enable clock source.\n");
1187 goto clk_free;
1188 }
1189
1190 host->clk_rate = clk_get_rate(host->clk);
1191
1192 mmc->ops = &s3cmci_ops;
1193 mmc->ocr_avail = MMC_VDD_32_33;
1194 mmc->caps = MMC_CAP_4_BIT_DATA;
1195 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1196 mmc->f_max = host->clk_rate / host->clk_div;
1197
1198 mmc->max_blk_count = 4095;
1199 mmc->max_blk_size = 4095;
1200 mmc->max_req_size = 4095 * 512;
1201 mmc->max_seg_size = mmc->max_req_size;
1202
1203 mmc->max_phys_segs = 128;
1204 mmc->max_hw_segs = 128;
1205
1206 dbg(host, dbg_debug,
1207 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1208 (host->is2440?"2440":""),
1209 host->base, host->irq, host->irq_cd, host->dma);
1210
1211 ret = mmc_add_host(mmc);
1212 if (ret) {
1213 dev_err(&pdev->dev, "failed to add mmc host.\n");
1214 goto free_dmabuf;
1215 }
1216
1217 platform_set_drvdata(pdev, mmc);
1218 dev_info(&pdev->dev, "initialisation done.\n");
1219
1220 return 0;
1221
1222 free_dmabuf:
1223 clk_disable(host->clk);
1224
1225 clk_free:
1226 clk_put(host->clk);
1227
1228 probe_free_irq_cd:
1229 free_irq(host->irq_cd, host);
1230
1231 probe_free_irq:
1232 free_irq(host->irq, host);
1233
1234 probe_iounmap:
1235 iounmap(host->base);
1236
1237 probe_free_mem_region:
1238 release_mem_region(host->mem->start, RESSIZE(host->mem));
1239
1240 probe_free_host:
1241 mmc_free_host(mmc);
1242 probe_out:
1243 return ret;
1244}
1245
1246static int __devexit s3cmci_remove(struct platform_device *pdev)
1247{
1248 struct mmc_host *mmc = platform_get_drvdata(pdev);
1249 struct s3cmci_host *host = mmc_priv(mmc);
1250
1251 mmc_remove_host(mmc);
1252
1253 clk_disable(host->clk);
1254 clk_put(host->clk);
1255
1256 tasklet_disable(&host->pio_tasklet);
ceb3ac25 1257 s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client);
be518018
TK		 1258
1259 free_irq(host->irq_cd, host);
1260 free_irq(host->irq, host);
1261
1262 iounmap(host->base);
1263 release_mem_region(host->mem->start, RESSIZE(host->mem));
1264
1265 mmc_free_host(mmc);
1266 return 0;
1267}
1268
1269static int __devinit s3cmci_probe_2410(struct platform_device *dev)
1270{
1271 return s3cmci_probe(dev, 0);
1272}
1273
1274static int __devinit s3cmci_probe_2412(struct platform_device *dev)
1275{
1276 return s3cmci_probe(dev, 1);
1277}
1278
1279static int __devinit s3cmci_probe_2440(struct platform_device *dev)
1280{
1281 return s3cmci_probe(dev, 1);
1282}
1283
1284#ifdef CONFIG_PM
1285
1286static int s3cmci_suspend(struct platform_device *dev, pm_message_t state)
1287{
1288 struct mmc_host *mmc = platform_get_drvdata(dev);
1289
1290 return mmc_suspend_host(mmc, state);
1291}
1292
1293static int s3cmci_resume(struct platform_device *dev)
1294{
1295 struct mmc_host *mmc = platform_get_drvdata(dev);
1296
1297 return mmc_resume_host(mmc);
1298}
1299
1300#else /* CONFIG_PM */
1301#define s3cmci_suspend NULL
1302#define s3cmci_resume NULL
1303#endif /* CONFIG_PM */
1304
1305
1306static struct platform_driver s3cmci_driver_2410 = {
1307 .driver.name = "s3c2410-sdi",
1308 .driver.owner = THIS_MODULE,
1309 .probe = s3cmci_probe_2410,
1310 .remove = __devexit_p(s3cmci_remove),
1311 .suspend = s3cmci_suspend,
1312 .resume = s3cmci_resume,
1313};
1314
1315static struct platform_driver s3cmci_driver_2412 = {
1316 .driver.name = "s3c2412-sdi",
1317 .driver.owner = THIS_MODULE,
1318 .probe = s3cmci_probe_2412,
1319 .remove = __devexit_p(s3cmci_remove),
1320 .suspend = s3cmci_suspend,
1321 .resume = s3cmci_resume,
1322};
1323
1324static struct platform_driver s3cmci_driver_2440 = {
1325 .driver.name = "s3c2440-sdi",
1326 .driver.owner = THIS_MODULE,
1327 .probe = s3cmci_probe_2440,
1328 .remove = __devexit_p(s3cmci_remove),
1329 .suspend = s3cmci_suspend,
1330 .resume = s3cmci_resume,
1331};
1332
1333
1334static int __init s3cmci_init(void)
1335{
1336 platform_driver_register(&s3cmci_driver_2410);
1337 platform_driver_register(&s3cmci_driver_2412);
1338 platform_driver_register(&s3cmci_driver_2440);
1339 return 0;
1340}
1341
1342static void __exit s3cmci_exit(void)
1343{
1344 platform_driver_unregister(&s3cmci_driver_2410);
1345 platform_driver_unregister(&s3cmci_driver_2412);
1346 platform_driver_unregister(&s3cmci_driver_2440);
1347}
1348
1349module_init(s3cmci_init);
1350module_exit(s3cmci_exit);
1351
1352MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1353MODULE_LICENSE("GPL v2");
1354MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>");
Linux 6.x block layer and io_uring tree(s)