Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/pxa.c - PXA MMCI driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This hardware is really sick: | |
11 | * - No way to clear interrupts. | |
12 | * - Have to turn off the clock whenever we touch the device. | |
13 | * - Doesn't tell you how many data blocks were transferred. | |
14 | * Yuck! | |
15 | * | |
16 | * 1 and 3 byte data transfers not supported | |
17 | * max block length up to 1023 | |
18 | */ | |
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/ioport.h> | |
d052d1be | 22 | #include <linux/platform_device.h> |
1da177e4 LT |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/dma-mapping.h> | |
ebebd9b0 RK |
26 | #include <linux/clk.h> |
27 | #include <linux/err.h> | |
1da177e4 | 28 | #include <linux/mmc/host.h> |
05678a96 | 29 | #include <linux/io.h> |
1da177e4 | 30 | |
1da177e4 LT |
31 | #include <asm/sizes.h> |
32 | ||
dcea83ad | 33 | #include <mach/dma.h> |
05678a96 | 34 | #include <mach/hardware.h> |
a09e64fb RK |
35 | #include <mach/pxa-regs.h> |
36 | #include <mach/mmc.h> | |
1da177e4 LT |
37 | |
38 | #include "pxamci.h" | |
39 | ||
1da177e4 LT |
40 | #define DRIVER_NAME "pxa2xx-mci" |
41 | ||
42 | #define NR_SG 1 | |
d8cb70d1 | 43 | #define CLKRT_OFF (~0) |
1da177e4 LT |
44 | |
45 | struct pxamci_host { | |
46 | struct mmc_host *mmc; | |
47 | spinlock_t lock; | |
48 | struct resource *res; | |
49 | void __iomem *base; | |
ebebd9b0 RK |
50 | struct clk *clk; |
51 | unsigned long clkrate; | |
1da177e4 LT |
52 | int irq; |
53 | int dma; | |
54 | unsigned int clkrt; | |
55 | unsigned int cmdat; | |
56 | unsigned int imask; | |
57 | unsigned int power_mode; | |
58 | struct pxamci_platform_data *pdata; | |
59 | ||
60 | struct mmc_request *mrq; | |
61 | struct mmc_command *cmd; | |
62 | struct mmc_data *data; | |
63 | ||
64 | dma_addr_t sg_dma; | |
65 | struct pxa_dma_desc *sg_cpu; | |
66 | unsigned int dma_len; | |
67 | ||
68 | unsigned int dma_dir; | |
9a788c6b BW |
69 | unsigned int dma_drcmrrx; |
70 | unsigned int dma_drcmrtx; | |
1da177e4 LT |
71 | }; |
72 | ||
1da177e4 LT |
73 | static void pxamci_stop_clock(struct pxamci_host *host) |
74 | { | |
75 | if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { | |
76 | unsigned long timeout = 10000; | |
77 | unsigned int v; | |
78 | ||
79 | writel(STOP_CLOCK, host->base + MMC_STRPCL); | |
80 | ||
81 | do { | |
82 | v = readl(host->base + MMC_STAT); | |
83 | if (!(v & STAT_CLK_EN)) | |
84 | break; | |
85 | udelay(1); | |
86 | } while (timeout--); | |
87 | ||
88 | if (v & STAT_CLK_EN) | |
89 | dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); | |
90 | } | |
91 | } | |
92 | ||
93 | static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) | |
94 | { | |
95 | unsigned long flags; | |
96 | ||
97 | spin_lock_irqsave(&host->lock, flags); | |
98 | host->imask &= ~mask; | |
99 | writel(host->imask, host->base + MMC_I_MASK); | |
100 | spin_unlock_irqrestore(&host->lock, flags); | |
101 | } | |
102 | ||
103 | static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) | |
104 | { | |
105 | unsigned long flags; | |
106 | ||
107 | spin_lock_irqsave(&host->lock, flags); | |
108 | host->imask |= mask; | |
109 | writel(host->imask, host->base + MMC_I_MASK); | |
110 | spin_unlock_irqrestore(&host->lock, flags); | |
111 | } | |
112 | ||
113 | static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) | |
114 | { | |
115 | unsigned int nob = data->blocks; | |
3d63abe5 | 116 | unsigned long long clks; |
1da177e4 | 117 | unsigned int timeout; |
97f8571e | 118 | bool dalgn = 0; |
1da177e4 LT |
119 | u32 dcmd; |
120 | int i; | |
121 | ||
122 | host->data = data; | |
123 | ||
124 | if (data->flags & MMC_DATA_STREAM) | |
125 | nob = 0xffff; | |
126 | ||
127 | writel(nob, host->base + MMC_NOB); | |
2c171bf1 | 128 | writel(data->blksz, host->base + MMC_BLKLEN); |
1da177e4 | 129 | |
ebebd9b0 | 130 | clks = (unsigned long long)data->timeout_ns * host->clkrate; |
3d63abe5 RK |
131 | do_div(clks, 1000000000UL); |
132 | timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); | |
1da177e4 LT |
133 | writel((timeout + 255) / 256, host->base + MMC_RDTO); |
134 | ||
135 | if (data->flags & MMC_DATA_READ) { | |
136 | host->dma_dir = DMA_FROM_DEVICE; | |
137 | dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG; | |
9a788c6b BW |
138 | DRCMR(host->dma_drcmrtx) = 0; |
139 | DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD; | |
1da177e4 LT |
140 | } else { |
141 | host->dma_dir = DMA_TO_DEVICE; | |
142 | dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC; | |
9a788c6b BW |
143 | DRCMR(host->dma_drcmrrx) = 0; |
144 | DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD; | |
1da177e4 LT |
145 | } |
146 | ||
147 | dcmd |= DCMD_BURST32 | DCMD_WIDTH1; | |
148 | ||
149 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
150 | host->dma_dir); | |
151 | ||
152 | for (i = 0; i < host->dma_len; i++) { | |
c783837b NP |
153 | unsigned int length = sg_dma_len(&data->sg[i]); |
154 | host->sg_cpu[i].dcmd = dcmd | length; | |
155 | if (length & 31 && !(data->flags & MMC_DATA_READ)) | |
156 | host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN; | |
97f8571e PZ |
157 | /* Not aligned to 8-byte boundary? */ |
158 | if (sg_dma_address(&data->sg[i]) & 0x7) | |
159 | dalgn = 1; | |
1da177e4 LT |
160 | if (data->flags & MMC_DATA_READ) { |
161 | host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO; | |
162 | host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]); | |
163 | } else { | |
164 | host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]); | |
165 | host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO; | |
166 | } | |
1da177e4 LT |
167 | host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) * |
168 | sizeof(struct pxa_dma_desc); | |
169 | } | |
170 | host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP; | |
171 | wmb(); | |
172 | ||
97f8571e PZ |
173 | /* |
174 | * The PXA27x DMA controller encounters overhead when working with | |
175 | * unaligned (to 8-byte boundaries) data, so switch on byte alignment | |
176 | * mode only if we have unaligned data. | |
177 | */ | |
178 | if (dalgn) | |
179 | DALGN |= (1 << host->dma); | |
180 | else | |
4fe16897 | 181 | DALGN &= ~(1 << host->dma); |
1da177e4 LT |
182 | DDADR(host->dma) = host->sg_dma; |
183 | DCSR(host->dma) = DCSR_RUN; | |
184 | } | |
185 | ||
186 | static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) | |
187 | { | |
188 | WARN_ON(host->cmd != NULL); | |
189 | host->cmd = cmd; | |
190 | ||
191 | if (cmd->flags & MMC_RSP_BUSY) | |
192 | cmdat |= CMDAT_BUSY; | |
193 | ||
e9225176 RK |
194 | #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) |
195 | switch (RSP_TYPE(mmc_resp_type(cmd))) { | |
6f949909 | 196 | case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */ |
1da177e4 LT |
197 | cmdat |= CMDAT_RESP_SHORT; |
198 | break; | |
e9225176 | 199 | case RSP_TYPE(MMC_RSP_R3): |
1da177e4 LT |
200 | cmdat |= CMDAT_RESP_R3; |
201 | break; | |
e9225176 | 202 | case RSP_TYPE(MMC_RSP_R2): |
1da177e4 LT |
203 | cmdat |= CMDAT_RESP_R2; |
204 | break; | |
205 | default: | |
206 | break; | |
207 | } | |
208 | ||
209 | writel(cmd->opcode, host->base + MMC_CMD); | |
210 | writel(cmd->arg >> 16, host->base + MMC_ARGH); | |
211 | writel(cmd->arg & 0xffff, host->base + MMC_ARGL); | |
212 | writel(cmdat, host->base + MMC_CMDAT); | |
213 | writel(host->clkrt, host->base + MMC_CLKRT); | |
214 | ||
215 | writel(START_CLOCK, host->base + MMC_STRPCL); | |
216 | ||
217 | pxamci_enable_irq(host, END_CMD_RES); | |
218 | } | |
219 | ||
220 | static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) | |
221 | { | |
1da177e4 LT |
222 | host->mrq = NULL; |
223 | host->cmd = NULL; | |
224 | host->data = NULL; | |
225 | mmc_request_done(host->mmc, mrq); | |
226 | } | |
227 | ||
228 | static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) | |
229 | { | |
230 | struct mmc_command *cmd = host->cmd; | |
231 | int i; | |
232 | u32 v; | |
233 | ||
234 | if (!cmd) | |
235 | return 0; | |
236 | ||
237 | host->cmd = NULL; | |
238 | ||
239 | /* | |
240 | * Did I mention this is Sick. We always need to | |
241 | * discard the upper 8 bits of the first 16-bit word. | |
242 | */ | |
243 | v = readl(host->base + MMC_RES) & 0xffff; | |
244 | for (i = 0; i < 4; i++) { | |
245 | u32 w1 = readl(host->base + MMC_RES) & 0xffff; | |
246 | u32 w2 = readl(host->base + MMC_RES) & 0xffff; | |
247 | cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; | |
248 | v = w2; | |
249 | } | |
250 | ||
251 | if (stat & STAT_TIME_OUT_RESPONSE) { | |
17b0429d | 252 | cmd->error = -ETIMEDOUT; |
1da177e4 LT |
253 | } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { |
254 | #ifdef CONFIG_PXA27x | |
255 | /* | |
256 | * workaround for erratum #42: | |
257 | * Intel PXA27x Family Processor Specification Update Rev 001 | |
90e07d9f NP |
258 | * A bogus CRC error can appear if the msb of a 136 bit |
259 | * response is a one. | |
1da177e4 | 260 | */ |
90e07d9f NP |
261 | if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) { |
262 | pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); | |
263 | } else | |
1da177e4 | 264 | #endif |
17b0429d | 265 | cmd->error = -EILSEQ; |
1da177e4 LT |
266 | } |
267 | ||
268 | pxamci_disable_irq(host, END_CMD_RES); | |
17b0429d | 269 | if (host->data && !cmd->error) { |
1da177e4 LT |
270 | pxamci_enable_irq(host, DATA_TRAN_DONE); |
271 | } else { | |
272 | pxamci_finish_request(host, host->mrq); | |
273 | } | |
274 | ||
275 | return 1; | |
276 | } | |
277 | ||
278 | static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) | |
279 | { | |
280 | struct mmc_data *data = host->data; | |
281 | ||
282 | if (!data) | |
283 | return 0; | |
284 | ||
285 | DCSR(host->dma) = 0; | |
286 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, | |
287 | host->dma_dir); | |
288 | ||
289 | if (stat & STAT_READ_TIME_OUT) | |
17b0429d | 290 | data->error = -ETIMEDOUT; |
1da177e4 | 291 | else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) |
17b0429d | 292 | data->error = -EILSEQ; |
1da177e4 LT |
293 | |
294 | /* | |
295 | * There appears to be a hardware design bug here. There seems to | |
296 | * be no way to find out how much data was transferred to the card. | |
297 | * This means that if there was an error on any block, we mark all | |
298 | * data blocks as being in error. | |
299 | */ | |
17b0429d | 300 | if (!data->error) |
2c171bf1 | 301 | data->bytes_xfered = data->blocks * data->blksz; |
1da177e4 LT |
302 | else |
303 | data->bytes_xfered = 0; | |
304 | ||
305 | pxamci_disable_irq(host, DATA_TRAN_DONE); | |
306 | ||
307 | host->data = NULL; | |
58741e8b | 308 | if (host->mrq->stop) { |
1da177e4 | 309 | pxamci_stop_clock(host); |
df456f47 | 310 | pxamci_start_cmd(host, host->mrq->stop, host->cmdat); |
1da177e4 LT |
311 | } else { |
312 | pxamci_finish_request(host, host->mrq); | |
313 | } | |
314 | ||
315 | return 1; | |
316 | } | |
317 | ||
7d12e780 | 318 | static irqreturn_t pxamci_irq(int irq, void *devid) |
1da177e4 LT |
319 | { |
320 | struct pxamci_host *host = devid; | |
321 | unsigned int ireg; | |
322 | int handled = 0; | |
323 | ||
81ab570f | 324 | ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); |
1da177e4 | 325 | |
1da177e4 LT |
326 | if (ireg) { |
327 | unsigned stat = readl(host->base + MMC_STAT); | |
328 | ||
d78e9079 | 329 | pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); |
1da177e4 LT |
330 | |
331 | if (ireg & END_CMD_RES) | |
332 | handled |= pxamci_cmd_done(host, stat); | |
333 | if (ireg & DATA_TRAN_DONE) | |
334 | handled |= pxamci_data_done(host, stat); | |
5d3ad4e8 BW |
335 | if (ireg & SDIO_INT) { |
336 | mmc_signal_sdio_irq(host->mmc); | |
337 | handled = 1; | |
338 | } | |
1da177e4 LT |
339 | } |
340 | ||
341 | return IRQ_RETVAL(handled); | |
342 | } | |
343 | ||
344 | static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
345 | { | |
346 | struct pxamci_host *host = mmc_priv(mmc); | |
347 | unsigned int cmdat; | |
348 | ||
349 | WARN_ON(host->mrq != NULL); | |
350 | ||
351 | host->mrq = mrq; | |
352 | ||
353 | pxamci_stop_clock(host); | |
354 | ||
355 | cmdat = host->cmdat; | |
356 | host->cmdat &= ~CMDAT_INIT; | |
357 | ||
358 | if (mrq->data) { | |
359 | pxamci_setup_data(host, mrq->data); | |
360 | ||
361 | cmdat &= ~CMDAT_BUSY; | |
362 | cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; | |
363 | if (mrq->data->flags & MMC_DATA_WRITE) | |
364 | cmdat |= CMDAT_WRITE; | |
365 | ||
366 | if (mrq->data->flags & MMC_DATA_STREAM) | |
367 | cmdat |= CMDAT_STREAM; | |
368 | } | |
369 | ||
370 | pxamci_start_cmd(host, mrq->cmd, cmdat); | |
371 | } | |
372 | ||
e619524f RP |
373 | static int pxamci_get_ro(struct mmc_host *mmc) |
374 | { | |
375 | struct pxamci_host *host = mmc_priv(mmc); | |
376 | ||
377 | if (host->pdata && host->pdata->get_ro) | |
08f80bb5 AV |
378 | return !!host->pdata->get_ro(mmc_dev(mmc)); |
379 | /* | |
380 | * Board doesn't support read only detection; let the mmc core | |
381 | * decide what to do. | |
382 | */ | |
383 | return -ENOSYS; | |
e619524f RP |
384 | } |
385 | ||
1da177e4 LT |
386 | static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
387 | { | |
388 | struct pxamci_host *host = mmc_priv(mmc); | |
389 | ||
1da177e4 | 390 | if (ios->clock) { |
ebebd9b0 RK |
391 | unsigned long rate = host->clkrate; |
392 | unsigned int clk = rate / ios->clock; | |
393 | ||
d8cb70d1 RK |
394 | if (host->clkrt == CLKRT_OFF) |
395 | clk_enable(host->clk); | |
396 | ||
64eb036a BW |
397 | if (ios->clock == 26000000) { |
398 | /* to support 26MHz on pxa300/pxa310 */ | |
399 | host->clkrt = 7; | |
400 | } else { | |
401 | /* to handle (19.5MHz, 26MHz) */ | |
402 | if (!clk) | |
403 | clk = 1; | |
404 | ||
405 | /* | |
406 | * clk might result in a lower divisor than we | |
407 | * desire. check for that condition and adjust | |
408 | * as appropriate. | |
409 | */ | |
410 | if (rate / clk > ios->clock) | |
411 | clk <<= 1; | |
412 | host->clkrt = fls(clk) - 1; | |
413 | } | |
1da177e4 LT |
414 | |
415 | /* | |
416 | * we write clkrt on the next command | |
417 | */ | |
418 | } else { | |
419 | pxamci_stop_clock(host); | |
d8cb70d1 RK |
420 | if (host->clkrt != CLKRT_OFF) { |
421 | host->clkrt = CLKRT_OFF; | |
422 | clk_disable(host->clk); | |
423 | } | |
1da177e4 LT |
424 | } |
425 | ||
426 | if (host->power_mode != ios->power_mode) { | |
427 | host->power_mode = ios->power_mode; | |
428 | ||
429 | if (host->pdata && host->pdata->setpower) | |
9e86619b | 430 | host->pdata->setpower(mmc_dev(mmc), ios->vdd); |
1da177e4 LT |
431 | |
432 | if (ios->power_mode == MMC_POWER_ON) | |
433 | host->cmdat |= CMDAT_INIT; | |
434 | } | |
435 | ||
df456f47 BW |
436 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
437 | host->cmdat |= CMDAT_SD_4DAT; | |
438 | else | |
439 | host->cmdat &= ~CMDAT_SD_4DAT; | |
440 | ||
d78e9079 | 441 | pr_debug("PXAMCI: clkrt = %x cmdat = %x\n", |
c6563178 | 442 | host->clkrt, host->cmdat); |
1da177e4 LT |
443 | } |
444 | ||
5d3ad4e8 BW |
445 | static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable) |
446 | { | |
447 | struct pxamci_host *pxa_host = mmc_priv(host); | |
448 | ||
449 | if (enable) | |
450 | pxamci_enable_irq(pxa_host, SDIO_INT); | |
451 | else | |
452 | pxamci_disable_irq(pxa_host, SDIO_INT); | |
453 | } | |
454 | ||
ab7aefd0 | 455 | static const struct mmc_host_ops pxamci_ops = { |
5d3ad4e8 BW |
456 | .request = pxamci_request, |
457 | .get_ro = pxamci_get_ro, | |
458 | .set_ios = pxamci_set_ios, | |
459 | .enable_sdio_irq = pxamci_enable_sdio_irq, | |
1da177e4 LT |
460 | }; |
461 | ||
7d12e780 | 462 | static void pxamci_dma_irq(int dma, void *devid) |
1da177e4 | 463 | { |
c783837b NP |
464 | struct pxamci_host *host = devid; |
465 | int dcsr = DCSR(dma); | |
466 | DCSR(dma) = dcsr & ~DCSR_STOPIRQEN; | |
467 | ||
468 | if (dcsr & DCSR_ENDINTR) { | |
469 | writel(BUF_PART_FULL, host->base + MMC_PRTBUF); | |
470 | } else { | |
471 | printk(KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n", | |
472 | mmc_hostname(host->mmc), dma, dcsr); | |
473 | host->data->error = -EIO; | |
474 | pxamci_data_done(host, 0); | |
475 | } | |
1da177e4 LT |
476 | } |
477 | ||
7d12e780 | 478 | static irqreturn_t pxamci_detect_irq(int irq, void *devid) |
1da177e4 | 479 | { |
c26971cb RP |
480 | struct pxamci_host *host = mmc_priv(devid); |
481 | ||
482 | mmc_detect_change(devid, host->pdata->detect_delay); | |
1da177e4 LT |
483 | return IRQ_HANDLED; |
484 | } | |
485 | ||
3ae5eaec | 486 | static int pxamci_probe(struct platform_device *pdev) |
1da177e4 | 487 | { |
1da177e4 LT |
488 | struct mmc_host *mmc; |
489 | struct pxamci_host *host = NULL; | |
9a788c6b | 490 | struct resource *r, *dmarx, *dmatx; |
1da177e4 LT |
491 | int ret, irq; |
492 | ||
493 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
494 | irq = platform_get_irq(pdev, 0); | |
48944738 | 495 | if (!r || irq < 0) |
1da177e4 LT |
496 | return -ENXIO; |
497 | ||
498 | r = request_mem_region(r->start, SZ_4K, DRIVER_NAME); | |
499 | if (!r) | |
500 | return -EBUSY; | |
501 | ||
3ae5eaec | 502 | mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev); |
1da177e4 LT |
503 | if (!mmc) { |
504 | ret = -ENOMEM; | |
505 | goto out; | |
506 | } | |
507 | ||
508 | mmc->ops = &pxamci_ops; | |
1da177e4 LT |
509 | |
510 | /* | |
511 | * We can do SG-DMA, but we don't because we never know how much | |
512 | * data we successfully wrote to the card. | |
513 | */ | |
514 | mmc->max_phys_segs = NR_SG; | |
515 | ||
516 | /* | |
517 | * Our hardware DMA can handle a maximum of one page per SG entry. | |
518 | */ | |
519 | mmc->max_seg_size = PAGE_SIZE; | |
520 | ||
fe4a3c7a | 521 | /* |
fe2dc44e | 522 | * Block length register is only 10 bits before PXA27x. |
fe4a3c7a | 523 | */ |
0ffcbfd5 | 524 | mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048; |
fe4a3c7a | 525 | |
55db890a PO |
526 | /* |
527 | * Block count register is 16 bits. | |
528 | */ | |
529 | mmc->max_blk_count = 65535; | |
530 | ||
1da177e4 LT |
531 | host = mmc_priv(mmc); |
532 | host->mmc = mmc; | |
533 | host->dma = -1; | |
534 | host->pdata = pdev->dev.platform_data; | |
d8cb70d1 | 535 | host->clkrt = CLKRT_OFF; |
ebebd9b0 | 536 | |
e0d8b13a | 537 | host->clk = clk_get(&pdev->dev, NULL); |
ebebd9b0 RK |
538 | if (IS_ERR(host->clk)) { |
539 | ret = PTR_ERR(host->clk); | |
540 | host->clk = NULL; | |
541 | goto out; | |
542 | } | |
543 | ||
544 | host->clkrate = clk_get_rate(host->clk); | |
545 | ||
546 | /* | |
547 | * Calculate minimum clock rate, rounding up. | |
548 | */ | |
549 | mmc->f_min = (host->clkrate + 63) / 64; | |
64eb036a BW |
550 | mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000 |
551 | : host->clkrate; | |
ebebd9b0 | 552 | |
1da177e4 LT |
553 | mmc->ocr_avail = host->pdata ? |
554 | host->pdata->ocr_mask : | |
555 | MMC_VDD_32_33|MMC_VDD_33_34; | |
df456f47 | 556 | mmc->caps = 0; |
5d3ad4e8 | 557 | host->cmdat = 0; |
0ffcbfd5 | 558 | if (!cpu_is_pxa25x()) { |
5d3ad4e8 BW |
559 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; |
560 | host->cmdat |= CMDAT_SDIO_INT_EN; | |
64eb036a BW |
561 | if (cpu_is_pxa300() || cpu_is_pxa310()) |
562 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | | |
563 | MMC_CAP_SD_HIGHSPEED; | |
5d3ad4e8 | 564 | } |
1da177e4 | 565 | |
3ae5eaec | 566 | host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL); |
1da177e4 LT |
567 | if (!host->sg_cpu) { |
568 | ret = -ENOMEM; | |
569 | goto out; | |
570 | } | |
571 | ||
572 | spin_lock_init(&host->lock); | |
573 | host->res = r; | |
574 | host->irq = irq; | |
575 | host->imask = MMC_I_MASK_ALL; | |
576 | ||
577 | host->base = ioremap(r->start, SZ_4K); | |
578 | if (!host->base) { | |
579 | ret = -ENOMEM; | |
580 | goto out; | |
581 | } | |
582 | ||
583 | /* | |
584 | * Ensure that the host controller is shut down, and setup | |
585 | * with our defaults. | |
586 | */ | |
587 | pxamci_stop_clock(host); | |
588 | writel(0, host->base + MMC_SPI); | |
589 | writel(64, host->base + MMC_RESTO); | |
590 | writel(host->imask, host->base + MMC_I_MASK); | |
591 | ||
592 | host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW, | |
593 | pxamci_dma_irq, host); | |
594 | if (host->dma < 0) { | |
595 | ret = -EBUSY; | |
596 | goto out; | |
597 | } | |
598 | ||
599 | ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host); | |
600 | if (ret) | |
601 | goto out; | |
602 | ||
3ae5eaec | 603 | platform_set_drvdata(pdev, mmc); |
1da177e4 | 604 | |
9a788c6b BW |
605 | dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
606 | if (!dmarx) { | |
607 | ret = -ENXIO; | |
608 | goto out; | |
609 | } | |
610 | host->dma_drcmrrx = dmarx->start; | |
611 | ||
612 | dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
613 | if (!dmatx) { | |
614 | ret = -ENXIO; | |
615 | goto out; | |
616 | } | |
617 | host->dma_drcmrtx = dmatx->start; | |
618 | ||
1da177e4 | 619 | if (host->pdata && host->pdata->init) |
3ae5eaec | 620 | host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); |
1da177e4 LT |
621 | |
622 | mmc_add_host(mmc); | |
623 | ||
624 | return 0; | |
625 | ||
626 | out: | |
627 | if (host) { | |
628 | if (host->dma >= 0) | |
629 | pxa_free_dma(host->dma); | |
630 | if (host->base) | |
631 | iounmap(host->base); | |
632 | if (host->sg_cpu) | |
3ae5eaec | 633 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
ebebd9b0 RK |
634 | if (host->clk) |
635 | clk_put(host->clk); | |
1da177e4 LT |
636 | } |
637 | if (mmc) | |
638 | mmc_free_host(mmc); | |
639 | release_resource(r); | |
640 | return ret; | |
641 | } | |
642 | ||
3ae5eaec | 643 | static int pxamci_remove(struct platform_device *pdev) |
1da177e4 | 644 | { |
3ae5eaec | 645 | struct mmc_host *mmc = platform_get_drvdata(pdev); |
1da177e4 | 646 | |
3ae5eaec | 647 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
648 | |
649 | if (mmc) { | |
650 | struct pxamci_host *host = mmc_priv(mmc); | |
651 | ||
652 | if (host->pdata && host->pdata->exit) | |
3ae5eaec | 653 | host->pdata->exit(&pdev->dev, mmc); |
1da177e4 LT |
654 | |
655 | mmc_remove_host(mmc); | |
656 | ||
657 | pxamci_stop_clock(host); | |
658 | writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| | |
659 | END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, | |
660 | host->base + MMC_I_MASK); | |
661 | ||
9a788c6b BW |
662 | DRCMR(host->dma_drcmrrx) = 0; |
663 | DRCMR(host->dma_drcmrtx) = 0; | |
1da177e4 LT |
664 | |
665 | free_irq(host->irq, host); | |
666 | pxa_free_dma(host->dma); | |
667 | iounmap(host->base); | |
3ae5eaec | 668 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
1da177e4 | 669 | |
ebebd9b0 RK |
670 | clk_put(host->clk); |
671 | ||
1da177e4 LT |
672 | release_resource(host->res); |
673 | ||
674 | mmc_free_host(mmc); | |
675 | } | |
676 | return 0; | |
677 | } | |
678 | ||
679 | #ifdef CONFIG_PM | |
3ae5eaec | 680 | static int pxamci_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 681 | { |
3ae5eaec | 682 | struct mmc_host *mmc = platform_get_drvdata(dev); |
1da177e4 LT |
683 | int ret = 0; |
684 | ||
9480e307 | 685 | if (mmc) |
1da177e4 LT |
686 | ret = mmc_suspend_host(mmc, state); |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
3ae5eaec | 691 | static int pxamci_resume(struct platform_device *dev) |
1da177e4 | 692 | { |
3ae5eaec | 693 | struct mmc_host *mmc = platform_get_drvdata(dev); |
1da177e4 LT |
694 | int ret = 0; |
695 | ||
9480e307 | 696 | if (mmc) |
1da177e4 LT |
697 | ret = mmc_resume_host(mmc); |
698 | ||
699 | return ret; | |
700 | } | |
701 | #else | |
702 | #define pxamci_suspend NULL | |
703 | #define pxamci_resume NULL | |
704 | #endif | |
705 | ||
3ae5eaec | 706 | static struct platform_driver pxamci_driver = { |
1da177e4 LT |
707 | .probe = pxamci_probe, |
708 | .remove = pxamci_remove, | |
709 | .suspend = pxamci_suspend, | |
710 | .resume = pxamci_resume, | |
3ae5eaec RK |
711 | .driver = { |
712 | .name = DRIVER_NAME, | |
bc65c724 | 713 | .owner = THIS_MODULE, |
3ae5eaec | 714 | }, |
1da177e4 LT |
715 | }; |
716 | ||
717 | static int __init pxamci_init(void) | |
718 | { | |
3ae5eaec | 719 | return platform_driver_register(&pxamci_driver); |
1da177e4 LT |
720 | } |
721 | ||
722 | static void __exit pxamci_exit(void) | |
723 | { | |
3ae5eaec | 724 | platform_driver_unregister(&pxamci_driver); |
1da177e4 LT |
725 | } |
726 | ||
727 | module_init(pxamci_init); | |
728 | module_exit(pxamci_exit); | |
729 | ||
730 | MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); | |
731 | MODULE_LICENSE("GPL"); | |
bc65c724 | 732 | MODULE_ALIAS("platform:pxa2xx-mci"); |