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mmc: omap_hsmmc: use devm_regulator API
[linux-2.6-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712 21#include <linux/debugfs.h>
c5c98927 22#include <linux/dmaengine.h>
d900f712 23#include <linux/seq_file.h>
031cd037 24#include <linux/sizes.h>
a45c6cb8
MC		 25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
a45c6cb8
MC		 29#include <linux/timer.h>
30#include <linux/clk.h>
46856a68
RN		 31#include <linux/of.h>
32#include <linux/of_gpio.h>
33#include <linux/of_device.h>
3451c067 34#include <linux/omap-dma.h>
a45c6cb8 35#include <linux/mmc/host.h>
13189e78 36#include <linux/mmc/core.h>
93caf8e6 37#include <linux/mmc/mmc.h>
a45c6cb8 38#include <linux/io.h>
db0fefc5
AH		 39#include <linux/gpio.h>
40#include <linux/regulator/consumer.h>
46b76035 41#include <linux/pinctrl/consumer.h>
fa4aa2d4 42#include <linux/pm_runtime.h>
68f39e74 43#include <linux/platform_data/mmc-omap.h>
a45c6cb8
MC		 44
45/* OMAP HSMMC Host Controller Registers */
11dd62a7 46#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 47#define OMAP_HSMMC_CON 0x002C
48#define OMAP_HSMMC_BLK 0x0104
49#define OMAP_HSMMC_ARG 0x0108
50#define OMAP_HSMMC_CMD 0x010C
51#define OMAP_HSMMC_RSP10 0x0110
52#define OMAP_HSMMC_RSP32 0x0114
53#define OMAP_HSMMC_RSP54 0x0118
54#define OMAP_HSMMC_RSP76 0x011C
55#define OMAP_HSMMC_DATA 0x0120
56#define OMAP_HSMMC_HCTL 0x0128
57#define OMAP_HSMMC_SYSCTL 0x012C
58#define OMAP_HSMMC_STAT 0x0130
59#define OMAP_HSMMC_IE 0x0134
60#define OMAP_HSMMC_ISE 0x0138
61#define OMAP_HSMMC_CAPA 0x0140
62
63#define VS18 (1 << 26)
64#define VS30 (1 << 25)
cd587096 65#define HSS (1 << 21)
a45c6cb8
MC		 66#define SDVS18 (0x5 << 9)
67#define SDVS30 (0x6 << 9)
eb250826 68#define SDVS33 (0x7 << 9)
1b331e69 69#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 70#define SDVSCLR 0xFFFFF1FF
71#define SDVSDET 0x00000400
72#define AUTOIDLE 0x1
73#define SDBP (1 << 8)
74#define DTO 0xe
75#define ICE 0x1
76#define ICS 0x2
77#define CEN (1 << 2)
ed164182 78#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
a45c6cb8
MC		 79#define CLKD_MASK 0x0000FFC0
80#define CLKD_SHIFT 6
81#define DTO_MASK 0x000F0000
82#define DTO_SHIFT 16
a45c6cb8
MC		 83#define INIT_STREAM (1 << 1)
84#define DP_SELECT (1 << 21)
85#define DDIR (1 << 4)
a7e96879 86#define DMAE 0x1
a45c6cb8
MC		 87#define MSBS (1 << 5)
88#define BCE (1 << 1)
89#define FOUR_BIT (1 << 1)
cd587096 90#define HSPE (1 << 2)
03b5d924 91#define DDR (1 << 19)
73153010 92#define DW8 (1 << 5)
a45c6cb8 93#define OD 0x1
a45c6cb8
MC		 94#define STAT_CLEAR 0xFFFFFFFF
95#define INIT_STREAM_CMD 0x00000000
96#define DUAL_VOLT_OCR_BIT 7
97#define SRC (1 << 25)
98#define SRD (1 << 26)
11dd62a7
DK		 99#define SOFTRESET (1 << 1)
100#define RESETDONE (1 << 0)
a45c6cb8 101
a7e96879
V		 102/* Interrupt masks for IE and ISE register */
103#define CC_EN (1 << 0)
104#define TC_EN (1 << 1)
105#define BWR_EN (1 << 4)
106#define BRR_EN (1 << 5)
107#define ERR_EN (1 << 15)
108#define CTO_EN (1 << 16)
109#define CCRC_EN (1 << 17)
110#define CEB_EN (1 << 18)
111#define CIE_EN (1 << 19)
112#define DTO_EN (1 << 20)
113#define DCRC_EN (1 << 21)
114#define DEB_EN (1 << 22)
115#define CERR_EN (1 << 28)
116#define BADA_EN (1 << 29)
117
118#define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
119 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
120 BRR_EN | BWR_EN | TC_EN | CC_EN)
121
fa4aa2d4 122#define MMC_AUTOSUSPEND_DELAY 100
1e881786
JM		 123#define MMC_TIMEOUT_MS 20 /* 20 mSec */
124#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
6b206efe
AS		 125#define OMAP_MMC_MIN_CLOCK 400000
126#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 127#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 128
129/*
130 * One controller can have multiple slots, like on some omap boards using
131 * omap.c controller driver. Luckily this is not currently done on any known
132 * omap_hsmmc.c device.
133 */
134#define mmc_slot(host) (host->pdata->slots[host->slot_id])
135
136/*
137 * MMC Host controller read/write API's
138 */
139#define OMAP_HSMMC_READ(base, reg) \
140 __raw_readl((base) + OMAP_HSMMC_##reg)
141
142#define OMAP_HSMMC_WRITE(base, reg, val) \
143 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
144
9782aff8
PF		 145struct omap_hsmmc_next {
146 unsigned int dma_len;
147 s32 cookie;
148};
149
70a3341a 150struct omap_hsmmc_host {
a45c6cb8
MC		 151 struct device *dev;
152 struct mmc_host *mmc;
153 struct mmc_request *mrq;
154 struct mmc_command *cmd;
155 struct mmc_data *data;
156 struct clk *fclk;
a45c6cb8 157 struct clk *dbclk;
db0fefc5
AH		 158 /*
159 * vcc == configured supply
160 * vcc_aux == optional
161 * - MMC1, supply for DAT4..DAT7
162 * - MMC2/MMC2, external level shifter voltage supply, for
163 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
164 */
165 struct regulator *vcc;
166 struct regulator *vcc_aux;
cf5ae40b 167 int pbias_disable;
a45c6cb8
MC		 168 void __iomem *base;
169 resource_size_t mapbase;
4dffd7a2 170 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 171 unsigned int dma_len;
0ccd76d4 172 unsigned int dma_sg_idx;
a45c6cb8 173 unsigned char bus_mode;
a3621465 174 unsigned char power_mode;
a45c6cb8 175 int suspended;
0a82e06e
TL		 176 u32 con;
177 u32 hctl;
178 u32 sysctl;
179 u32 capa;
a45c6cb8 180 int irq;
a45c6cb8 181 int use_dma, dma_ch;
c5c98927
RK		 182 struct dma_chan *tx_chan;
183 struct dma_chan *rx_chan;
a45c6cb8 184 int slot_id;
4a694dc9 185 int response_busy;
11dd62a7 186 int context_loss;
b62f6228
AH		 187 int protect_card;
188 int reqs_blocked;
db0fefc5 189 int use_reg;
b417577d 190 int req_in_progress;
9782aff8 191 struct omap_hsmmc_next next_data;
a45c6cb8
MC		 192 struct omap_mmc_platform_data *pdata;
193};
194
59445b10
NM		 195struct omap_mmc_of_data {
196 u32 reg_offset;
197 u8 controller_flags;
198};
199
db0fefc5
AH		 200static int omap_hsmmc_card_detect(struct device *dev, int slot)
201{
9ea28ecb
B		 202 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
203 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 204
205 /* NOTE: assumes card detect signal is active-low */
206 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
207}
208
209static int omap_hsmmc_get_wp(struct device *dev, int slot)
210{
9ea28ecb
B		 211 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
212 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 213
214 /* NOTE: assumes write protect signal is active-high */
215 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
216}
217
218static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
219{
9ea28ecb
B		 220 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
221 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 222
223 /* NOTE: assumes card detect signal is active-low */
224 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
225}
226
227#ifdef CONFIG_PM
228
229static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
230{
9ea28ecb
B		 231 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
232 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 233
234 disable_irq(mmc->slots[0].card_detect_irq);
235 return 0;
236}
237
238static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
239{
9ea28ecb
B		 240 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
241 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 242
243 enable_irq(mmc->slots[0].card_detect_irq);
244 return 0;
245}
246
247#else
248
249#define omap_hsmmc_suspend_cdirq NULL
250#define omap_hsmmc_resume_cdirq NULL
251
252#endif
253
b702b106
AH		 254#ifdef CONFIG_REGULATOR
255
69b07ece 256static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 257 int vdd)
258{
259 struct omap_hsmmc_host *host =
260 platform_get_drvdata(to_platform_device(dev));
261 int ret = 0;
262
263 /*
264 * If we don't see a Vcc regulator, assume it's a fixed
265 * voltage always-on regulator.
266 */
267 if (!host->vcc)
268 return 0;
1f84b71b 269 /*
cf5ae40b 270 * With DT, never turn OFF the regulator for MMC1. This is because
1f84b71b
RN		 271 * the pbias cell programming support is still missing when
272 * booting with Device tree
273 */
cf5ae40b 274 if (host->pbias_disable && !vdd)
1f84b71b 275 return 0;
db0fefc5
AH		 276
277 if (mmc_slot(host).before_set_reg)
278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
279
280 /*
281 * Assume Vcc regulator is used only to power the card ... OMAP
282 * VDDS is used to power the pins, optionally with a transceiver to
283 * support cards using voltages other than VDDS (1.8V nominal). When a
284 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
285 *
286 * In some cases this regulator won't support enable/disable;
287 * e.g. it's a fixed rail for a WLAN chip.
288 *
289 * In other cases vcc_aux switches interface power. Example, for
290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
291 * chips/cards need an interface voltage rail too.
292 */
293 if (power_on) {
99fc5131 294 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 295 /* Enable interface voltage rail, if needed */
296 if (ret == 0 && host->vcc_aux) {
297 ret = regulator_enable(host->vcc_aux);
298 if (ret < 0)
99fc5131
LW		 299 ret = mmc_regulator_set_ocr(host->mmc,
300 host->vcc, 0);
db0fefc5
AH		 301 }
302 } else {
99fc5131 303 /* Shut down the rail */
6da20c89
AH		 304 if (host->vcc_aux)
305 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 306 if (!ret) {
307 /* Then proceed to shut down the local regulator */
308 ret = mmc_regulator_set_ocr(host->mmc,
309 host->vcc, 0);
310 }
db0fefc5
AH		 311 }
312
313 if (mmc_slot(host).after_set_reg)
314 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
315
316 return ret;
317}
318
db0fefc5
AH		 319static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
320{
321 struct regulator *reg;
64be9782 322 int ocr_value = 0;
db0fefc5 323
f2ddc1da 324 reg = devm_regulator_get(host->dev, "vmmc");
db0fefc5 325 if (IS_ERR(reg)) {
b1e056ae 326 dev_err(host->dev, "vmmc regulator missing\n");
1fdc90fb 327 return PTR_ERR(reg);
db0fefc5 328 } else {
1fdc90fb 329 mmc_slot(host).set_power = omap_hsmmc_set_power;
db0fefc5 330 host->vcc = reg;
64be9782 331 ocr_value = mmc_regulator_get_ocrmask(reg);
332 if (!mmc_slot(host).ocr_mask) {
333 mmc_slot(host).ocr_mask = ocr_value;
334 } else {
335 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
2cecdf00 336 dev_err(host->dev, "ocrmask %x is not supported\n",
e3f1adb6 337 mmc_slot(host).ocr_mask);
64be9782 338 mmc_slot(host).ocr_mask = 0;
339 return -EINVAL;
340 }
341 }
db0fefc5
AH		 342
343 /* Allow an aux regulator */
f2ddc1da 344 reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
db0fefc5
AH		 345 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
346
b1c1df7a
B		 347 /* For eMMC do not power off when not in sleep state */
348 if (mmc_slot(host).no_regulator_off_init)
349 return 0;
db0fefc5
AH		 350 /*
351 * UGLY HACK: workaround regulator framework bugs.
352 * When the bootloader leaves a supply active, it's
353 * initialized with zero usecount ... and we can't
354 * disable it without first enabling it. Until the
355 * framework is fixed, we need a workaround like this
356 * (which is safe for MMC, but not in general).
357 */
e840ce13
AH		 358 if (regulator_is_enabled(host->vcc) > 0 ||
359 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
360 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
361
362 mmc_slot(host).set_power(host->dev, host->slot_id,
363 1, vdd);
364 mmc_slot(host).set_power(host->dev, host->slot_id,
365 0, 0);
db0fefc5
AH		 366 }
367 }
368
369 return 0;
db0fefc5
AH		 370}
371
372static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
373{
db0fefc5 374 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 375}
376
b702b106
AH		 377static inline int omap_hsmmc_have_reg(void)
378{
379 return 1;
380}
381
382#else
383
384static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
385{
386 return -EINVAL;
387}
388
389static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
390{
391}
392
393static inline int omap_hsmmc_have_reg(void)
394{
395 return 0;
396}
397
398#endif
399
400static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
401{
402 int ret;
403
404 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 405 if (pdata->slots[0].cover)
406 pdata->slots[0].get_cover_state =
407 omap_hsmmc_get_cover_state;
408 else
409 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
410 pdata->slots[0].card_detect_irq =
411 gpio_to_irq(pdata->slots[0].switch_pin);
412 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
413 if (ret)
414 return ret;
415 ret = gpio_direction_input(pdata->slots[0].switch_pin);
416 if (ret)
417 goto err_free_sp;
418 } else
419 pdata->slots[0].switch_pin = -EINVAL;
420
421 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
422 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
423 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
424 if (ret)
425 goto err_free_cd;
426 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
427 if (ret)
428 goto err_free_wp;
429 } else
430 pdata->slots[0].gpio_wp = -EINVAL;
431
432 return 0;
433
434err_free_wp:
435 gpio_free(pdata->slots[0].gpio_wp);
436err_free_cd:
437 if (gpio_is_valid(pdata->slots[0].switch_pin))
438err_free_sp:
439 gpio_free(pdata->slots[0].switch_pin);
440 return ret;
441}
442
443static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
444{
445 if (gpio_is_valid(pdata->slots[0].gpio_wp))
446 gpio_free(pdata->slots[0].gpio_wp);
447 if (gpio_is_valid(pdata->slots[0].switch_pin))
448 gpio_free(pdata->slots[0].switch_pin);
449}
450
e0c7f99b
AS		 451/*
452 * Start clock to the card
453 */
454static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
455{
456 OMAP_HSMMC_WRITE(host->base, SYSCTL,
457 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
458}
459
a45c6cb8
MC		 460/*
461 * Stop clock to the card
462 */
70a3341a 463static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 464{
465 OMAP_HSMMC_WRITE(host->base, SYSCTL,
466 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
467 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
7122bbb0 468 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
a45c6cb8
MC		 469}
470
93caf8e6
AH		 471static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
472 struct mmc_command *cmd)
b417577d
AH		 473{
474 unsigned int irq_mask;
475
476 if (host->use_dma)
a7e96879 477 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
b417577d
AH		 478 else
479 irq_mask = INT_EN_MASK;
480
93caf8e6
AH		 481 /* Disable timeout for erases */
482 if (cmd->opcode == MMC_ERASE)
a7e96879 483 irq_mask &= ~DTO_EN;
93caf8e6 484
b417577d
AH		 485 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
486 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
487 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
488}
489
490static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
491{
492 OMAP_HSMMC_WRITE(host->base, ISE, 0);
493 OMAP_HSMMC_WRITE(host->base, IE, 0);
494 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
495}
496
ac330f44 497/* Calculate divisor for the given clock frequency */
d83b6e03 498static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 499{
500 u16 dsor = 0;
501
502 if (ios->clock) {
d83b6e03 503 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ed164182
B		 504 if (dsor > CLKD_MAX)
505 dsor = CLKD_MAX;
ac330f44
AS		 506 }
507
508 return dsor;
509}
510
5934df2f
AS		 511static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
512{
513 struct mmc_ios *ios = &host->mmc->ios;
514 unsigned long regval;
515 unsigned long timeout;
cd587096 516 unsigned long clkdiv;
5934df2f 517
8986d31b 518 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
5934df2f
AS		 519
520 omap_hsmmc_stop_clock(host);
521
522 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
523 regval = regval & ~(CLKD_MASK | DTO_MASK);
cd587096
HG		 524 clkdiv = calc_divisor(host, ios);
525 regval = regval | (clkdiv << 6) | (DTO << 16);
5934df2f
AS		 526 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
527 OMAP_HSMMC_WRITE(host->base, SYSCTL,
528 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
529
530 /* Wait till the ICS bit is set */
531 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
532 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
533 && time_before(jiffies, timeout))
534 cpu_relax();
535
cd587096
HG		 536 /*
537 * Enable High-Speed Support
538 * Pre-Requisites
539 * - Controller should support High-Speed-Enable Bit
540 * - Controller should not be using DDR Mode
541 * - Controller should advertise that it supports High Speed
542 * in capabilities register
543 * - MMC/SD clock coming out of controller > 25MHz
544 */
545 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
546 (ios->timing != MMC_TIMING_UHS_DDR50) &&
547 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
548 regval = OMAP_HSMMC_READ(host->base, HCTL);
549 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
550 regval |= HSPE;
551 else
552 regval &= ~HSPE;
553
554 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
555 }
556
5934df2f
AS		 557 omap_hsmmc_start_clock(host);
558}
559
3796fb8a
AS		 560static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
561{
562 struct mmc_ios *ios = &host->mmc->ios;
563 u32 con;
564
565 con = OMAP_HSMMC_READ(host->base, CON);
03b5d924
B		 566 if (ios->timing == MMC_TIMING_UHS_DDR50)
567 con |= DDR; /* configure in DDR mode */
568 else
569 con &= ~DDR;
3796fb8a
AS		 570 switch (ios->bus_width) {
571 case MMC_BUS_WIDTH_8:
572 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
573 break;
574 case MMC_BUS_WIDTH_4:
575 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
576 OMAP_HSMMC_WRITE(host->base, HCTL,
577 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
578 break;
579 case MMC_BUS_WIDTH_1:
580 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
581 OMAP_HSMMC_WRITE(host->base, HCTL,
582 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
583 break;
584 }
585}
586
587static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
588{
589 struct mmc_ios *ios = &host->mmc->ios;
590 u32 con;
591
592 con = OMAP_HSMMC_READ(host->base, CON);
593 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
594 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
595 else
596 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
597}
598
11dd62a7
DK		 599#ifdef CONFIG_PM
600
601/*
602 * Restore the MMC host context, if it was lost as result of a
603 * power state change.
604 */
70a3341a 605static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 606{
607 struct mmc_ios *ios = &host->mmc->ios;
3796fb8a 608 u32 hctl, capa;
11dd62a7
DK		 609 unsigned long timeout;
610
6c31b215
V		 611 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
612 return 1;
11dd62a7 613
0a82e06e
TL		 614 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
615 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
616 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
617 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
618 return 0;
619
620 host->context_loss++;
621
c2200efb 622 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 623 if (host->power_mode != MMC_POWER_OFF &&
624 (1 << ios->vdd) <= MMC_VDD_23_24)
625 hctl = SDVS18;
626 else
627 hctl = SDVS30;
628 capa = VS30 | VS18;
629 } else {
630 hctl = SDVS18;
631 capa = VS18;
632 }
633
634 OMAP_HSMMC_WRITE(host->base, HCTL,
635 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
636
637 OMAP_HSMMC_WRITE(host->base, CAPA,
638 OMAP_HSMMC_READ(host->base, CAPA) | capa);
639
640 OMAP_HSMMC_WRITE(host->base, HCTL,
641 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
642
643 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
644 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
645 && time_before(jiffies, timeout))
646 ;
647
b417577d 648 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 649
650 /* Do not initialize card-specific things if the power is off */
651 if (host->power_mode == MMC_POWER_OFF)
652 goto out;
653
3796fb8a 654 omap_hsmmc_set_bus_width(host);
11dd62a7 655
5934df2f 656 omap_hsmmc_set_clock(host);
11dd62a7 657
3796fb8a
AS		 658 omap_hsmmc_set_bus_mode(host);
659
11dd62a7 660out:
0a82e06e
TL		 661 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
662 host->context_loss);
11dd62a7
DK		 663 return 0;
664}
665
666/*
667 * Save the MMC host context (store the number of power state changes so far).
668 */
70a3341a 669static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7 670{
0a82e06e
TL		 671 host->con = OMAP_HSMMC_READ(host->base, CON);
672 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
673 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
674 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
11dd62a7
DK		 675}
676
677#else
678
70a3341a 679static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 680{
681 return 0;
682}
683
70a3341a 684static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 685{
686}
687
688#endif
689
a45c6cb8
MC		 690/*
691 * Send init stream sequence to card
692 * before sending IDLE command
693 */
70a3341a 694static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 695{
696 int reg = 0;
697 unsigned long timeout;
698
b62f6228
AH		 699 if (host->protect_card)
700 return;
701
a45c6cb8 702 disable_irq(host->irq);
b417577d
AH		 703
704 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 705 OMAP_HSMMC_WRITE(host->base, CON,
706 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
707 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
708
709 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
a7e96879
V		 710 while ((reg != CC_EN) && time_before(jiffies, timeout))
711 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
a45c6cb8
MC		 712
713 OMAP_HSMMC_WRITE(host->base, CON,
714 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 715
716 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
717 OMAP_HSMMC_READ(host->base, STAT);
718
a45c6cb8
MC		 719 enable_irq(host->irq);
720}
721
722static inline
70a3341a 723int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 724{
725 int r = 1;
726
191d1f1d
DK		 727 if (mmc_slot(host).get_cover_state)
728 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 729 return r;
730}
731
732static ssize_t
70a3341a 733omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 734 char *buf)
735{
736 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 737 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 738
70a3341a
DK		 739 return sprintf(buf, "%s\n",
740 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 741}
742
70a3341a 743static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 744
745static ssize_t
70a3341a 746omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 747 char *buf)
748{
749 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 750 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 751
191d1f1d 752 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 753}
754
70a3341a 755static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 756
757/*
758 * Configure the response type and send the cmd.
759 */
760static void
70a3341a 761omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 762 struct mmc_data *data)
763{
764 int cmdreg = 0, resptype = 0, cmdtype = 0;
765
8986d31b 766 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
a45c6cb8
MC		 767 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
768 host->cmd = cmd;
769
93caf8e6 770 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 771
4a694dc9 772 host->response_busy = 0;
a45c6cb8
MC		 773 if (cmd->flags & MMC_RSP_PRESENT) {
774 if (cmd->flags & MMC_RSP_136)
775 resptype = 1;
4a694dc9
AH		 776 else if (cmd->flags & MMC_RSP_BUSY) {
777 resptype = 3;
778 host->response_busy = 1;
779 } else
a45c6cb8
MC		 780 resptype = 2;
781 }
782
783 /*
784 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
785 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
786 * a val of 0x3, rest 0x0.
787 */
788 if (cmd == host->mrq->stop)
789 cmdtype = 0x3;
790
791 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
792
793 if (data) {
794 cmdreg |= DP_SELECT | MSBS | BCE;
795 if (data->flags & MMC_DATA_READ)
796 cmdreg |= DDIR;
797 else
798 cmdreg &= ~(DDIR);
799 }
800
801 if (host->use_dma)
a7e96879 802 cmdreg |= DMAE;
a45c6cb8 803
b417577d 804 host->req_in_progress = 1;
4dffd7a2 805
a45c6cb8
MC		 806 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
807 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
808}
809
0ccd76d4 810static int
70a3341a 811omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 812{
813 if (data->flags & MMC_DATA_WRITE)
814 return DMA_TO_DEVICE;
815 else
816 return DMA_FROM_DEVICE;
817}
818
c5c98927
RK		 819static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
820 struct mmc_data *data)
821{
822 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
823}
824
b417577d
AH		 825static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
826{
827 int dma_ch;
31463b14 828 unsigned long flags;
b417577d 829
31463b14 830 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 831 host->req_in_progress = 0;
832 dma_ch = host->dma_ch;
31463b14 833 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 834
835 omap_hsmmc_disable_irq(host);
836 /* Do not complete the request if DMA is still in progress */
837 if (mrq->data && host->use_dma && dma_ch != -1)
838 return;
839 host->mrq = NULL;
840 mmc_request_done(host->mmc, mrq);
841}
842
a45c6cb8
MC		 843/*
844 * Notify the transfer complete to MMC core
845 */
846static void
70a3341a 847omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 848{
4a694dc9
AH		 849 if (!data) {
850 struct mmc_request *mrq = host->mrq;
851
23050103
AH		 852 /* TC before CC from CMD6 - don't know why, but it happens */
853 if (host->cmd && host->cmd->opcode == 6 &&
854 host->response_busy) {
855 host->response_busy = 0;
856 return;
857 }
858
b417577d 859 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 860 return;
861 }
862
a45c6cb8
MC		 863 host->data = NULL;
864
a45c6cb8
MC		 865 if (!data->error)
866 data->bytes_xfered += data->blocks * (data->blksz);
867 else
868 data->bytes_xfered = 0;
869
fe852273 870 if (!data->stop) {
b417577d 871 omap_hsmmc_request_done(host, data->mrq);
fe852273 872 return;
a45c6cb8 873 }
fe852273 874 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 875}
876
877/*
878 * Notify the core about command completion
879 */
880static void
70a3341a 881omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 882{
883 host->cmd = NULL;
884
885 if (cmd->flags & MMC_RSP_PRESENT) {
886 if (cmd->flags & MMC_RSP_136) {
887 /* response type 2 */
888 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
889 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
890 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
891 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
892 } else {
893 /* response types 1, 1b, 3, 4, 5, 6 */
894 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
895 }
896 }
b417577d
AH		 897 if ((host->data == NULL && !host->response_busy) || cmd->error)
898 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 899}
900
901/*
902 * DMA clean up for command errors
903 */
70a3341a 904static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 905{
b417577d 906 int dma_ch;
31463b14 907 unsigned long flags;
b417577d 908
82788ff5 909 host->data->error = errno;
a45c6cb8 910
31463b14 911 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 912 dma_ch = host->dma_ch;
913 host->dma_ch = -1;
31463b14 914 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 915
916 if (host->use_dma && dma_ch != -1) {
c5c98927
RK		 917 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
918
919 dmaengine_terminate_all(chan);
920 dma_unmap_sg(chan->device->dev,
921 host->data->sg, host->data->sg_len,
70a3341a 922 omap_hsmmc_get_dma_dir(host, host->data));
c5c98927 923
053bf34f 924 host->data->host_cookie = 0;
a45c6cb8
MC		 925 }
926 host->data = NULL;
a45c6cb8
MC		 927}
928
929/*
930 * Readable error output
931 */
932#ifdef CONFIG_MMC_DEBUG
699b958b 933static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 934{
935 /* --- means reserved bit without definition at documentation */
70a3341a 936 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 937 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
938 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
939 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
940 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 941 };
942 char res[256];
943 char *buf = res;
944 int len, i;
945
946 len = sprintf(buf, "MMC IRQ 0x%x :", status);
947 buf += len;
948
70a3341a 949 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 950 if (status & (1 << i)) {
70a3341a 951 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 952 buf += len;
953 }
954
8986d31b 955 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
a45c6cb8 956}
699b958b
AH		 957#else
958static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
959 u32 status)
960{
961}
a45c6cb8
MC		 962#endif /* CONFIG_MMC_DEBUG */
963
3ebf74b1
JP		 964/*
965 * MMC controller internal state machines reset
966 *
967 * Used to reset command or data internal state machines, using respectively
968 * SRC or SRD bit of SYSCTL register
969 * Can be called from interrupt context
970 */
70a3341a
DK		 971static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
972 unsigned long bit)
3ebf74b1
JP		 973{
974 unsigned long i = 0;
1e881786 975 unsigned long limit = MMC_TIMEOUT_US;
3ebf74b1
JP		 976
977 OMAP_HSMMC_WRITE(host->base, SYSCTL,
978 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
979
07ad64b6
MC		 980 /*
981 * OMAP4 ES2 and greater has an updated reset logic.
982 * Monitor a 0->1 transition first
983 */
984 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 985 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6 986 && (i++ < limit))
1e881786 987 udelay(1);
07ad64b6
MC		 988 }
989 i = 0;
990
3ebf74b1
JP		 991 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
992 (i++ < limit))
1e881786 993 udelay(1);
3ebf74b1
JP		 994
995 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
996 dev_err(mmc_dev(host->mmc),
997 "Timeout waiting on controller reset in %s\n",
998 __func__);
999}
a45c6cb8 1000
25e1897b
B		 1001static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1002 int err, int end_cmd)
ae4bf788 1003{
25e1897b 1004 if (end_cmd) {
94d4f272 1005 omap_hsmmc_reset_controller_fsm(host, SRC);
25e1897b
B		 1006 if (host->cmd)
1007 host->cmd->error = err;
1008 }
ae4bf788
V		 1009
1010 if (host->data) {
1011 omap_hsmmc_reset_controller_fsm(host, SRD);
1012 omap_hsmmc_dma_cleanup(host, err);
dc7745bd
B		 1013 } else if (host->mrq && host->mrq->cmd)
1014 host->mrq->cmd->error = err;
ae4bf788
V		 1015}
1016
b417577d 1017static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1018{
a45c6cb8 1019 struct mmc_data *data;
b417577d
AH		 1020 int end_cmd = 0, end_trans = 0;
1021
a45c6cb8 1022 data = host->data;
8986d31b 1023 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
a45c6cb8 1024
a7e96879 1025 if (status & ERR_EN) {
699b958b 1026 omap_hsmmc_dbg_report_irq(host, status);
25e1897b 1027
a7e96879 1028 if (status & (CTO_EN | CCRC_EN))
25e1897b 1029 end_cmd = 1;
a7e96879 1030 if (status & (CTO_EN | DTO_EN))
25e1897b 1031 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
a7e96879 1032 else if (status & (CCRC_EN | DCRC_EN))
25e1897b 1033 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
ae4bf788 1034
ae4bf788 1035 if (host->data || host->response_busy) {
25e1897b 1036 end_trans = !end_cmd;
ae4bf788 1037 host->response_busy = 0;
a45c6cb8
MC		 1038 }
1039 }
1040
7472bab2 1041 OMAP_HSMMC_WRITE(host->base, STAT, status);
a7e96879 1042 if (end_cmd || ((status & CC_EN) && host->cmd))
70a3341a 1043 omap_hsmmc_cmd_done(host, host->cmd);
a7e96879 1044 if ((end_trans || (status & TC_EN)) && host->mrq)
70a3341a 1045 omap_hsmmc_xfer_done(host, data);
b417577d 1046}
a45c6cb8 1047
b417577d
AH		 1048/*
1049 * MMC controller IRQ handler
1050 */
1051static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1052{
1053 struct omap_hsmmc_host *host = dev_id;
1054 int status;
1055
1056 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1057 while (status & INT_EN_MASK && host->req_in_progress) {
b417577d 1058 omap_hsmmc_do_irq(host, status);
1f6b9fa4 1059
b417577d
AH		 1060 /* Flush posted write */
1061 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1062 }
4dffd7a2 1063
a45c6cb8
MC		 1064 return IRQ_HANDLED;
1065}
1066
70a3341a 1067static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1068{
1069 unsigned long i;
1070
1071 OMAP_HSMMC_WRITE(host->base, HCTL,
1072 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1073 for (i = 0; i < loops_per_jiffy; i++) {
1074 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1075 break;
1076 cpu_relax();
1077 }
1078}
1079
a45c6cb8 1080/*
eb250826
DB		 1081 * Switch MMC interface voltage ... only relevant for MMC1.
1082 *
1083 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1084 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1085 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1086 */
70a3341a 1087static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1088{
1089 u32 reg_val = 0;
1090 int ret;
1091
1092 /* Disable the clocks */
fa4aa2d4 1093 pm_runtime_put_sync(host->dev);
cd03d9a8 1094 if (host->dbclk)
94c18149 1095 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1096
1097 /* Turn the power off */
1098 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1099
1100 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1101 if (!ret)
1102 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1103 vdd);
fa4aa2d4 1104 pm_runtime_get_sync(host->dev);
cd03d9a8 1105 if (host->dbclk)
94c18149 1106 clk_prepare_enable(host->dbclk);
2bec0893 1107
a45c6cb8
MC		 1108 if (ret != 0)
1109 goto err;
1110
a45c6cb8
MC		 1111 OMAP_HSMMC_WRITE(host->base, HCTL,
1112 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1113 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1114
a45c6cb8
MC		 1115 /*
1116 * If a MMC dual voltage card is detected, the set_ios fn calls
1117 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1118 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1119 *
eb250826
DB		 1120 * Cope with a bit of slop in the range ... per data sheets:
1121 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1122 * but recommended values are 1.71V to 1.89V
1123 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1124 * but recommended values are 2.7V to 3.3V
1125 *
1126 * Board setup code shouldn't permit anything very out-of-range.
1127 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1128 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1129 */
eb250826 1130 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1131 reg_val |= SDVS18;
eb250826
DB		 1132 else
1133 reg_val |= SDVS30;
a45c6cb8
MC		 1134
1135 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1136 set_sd_bus_power(host);
a45c6cb8
MC		 1137
1138 return 0;
1139err:
b1e056ae 1140 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
a45c6cb8
MC		 1141 return ret;
1142}
1143
b62f6228
AH		 1144/* Protect the card while the cover is open */
1145static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1146{
1147 if (!mmc_slot(host).get_cover_state)
1148 return;
1149
1150 host->reqs_blocked = 0;
1151 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1152 if (host->protect_card) {
2cecdf00 1153 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1154 "card is now accessible\n",
1155 mmc_hostname(host->mmc));
1156 host->protect_card = 0;
1157 }
1158 } else {
1159 if (!host->protect_card) {
2cecdf00 1160 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1161 "card is now inaccessible\n",
1162 mmc_hostname(host->mmc));
1163 host->protect_card = 1;
1164 }
1165 }
1166}
1167
a45c6cb8 1168/*
7efab4f3 1169 * irq handler to notify the core about card insertion/removal
a45c6cb8 1170 */
7efab4f3 1171static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1172{
7efab4f3 1173 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1174 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1175 int carddetect;
1176
a6b2240d 1177 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1178
191d1f1d 1179 if (slot->card_detect)
db0fefc5 1180 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1181 else {
1182 omap_hsmmc_protect_card(host);
a6b2240d 1183 carddetect = -ENOSYS;
b62f6228 1184 }
a45c6cb8 1185
cdeebadd 1186 if (carddetect)
a45c6cb8 1187 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1188 else
a45c6cb8 1189 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1190 return IRQ_HANDLED;
1191}
1192
c5c98927 1193static void omap_hsmmc_dma_callback(void *param)
a45c6cb8 1194{
c5c98927
RK		 1195 struct omap_hsmmc_host *host = param;
1196 struct dma_chan *chan;
770d7432 1197 struct mmc_data *data;
c5c98927 1198 int req_in_progress;
a45c6cb8 1199
c5c98927 1200 spin_lock_irq(&host->irq_lock);
b417577d 1201 if (host->dma_ch < 0) {
c5c98927 1202 spin_unlock_irq(&host->irq_lock);
a45c6cb8 1203 return;
b417577d 1204 }
a45c6cb8 1205
770d7432 1206 data = host->mrq->data;
c5c98927 1207 chan = omap_hsmmc_get_dma_chan(host, data);
9782aff8 1208 if (!data->host_cookie)
c5c98927
RK		 1209 dma_unmap_sg(chan->device->dev,
1210 data->sg, data->sg_len,
9782aff8 1211 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1212
1213 req_in_progress = host->req_in_progress;
a45c6cb8 1214 host->dma_ch = -1;
c5c98927 1215 spin_unlock_irq(&host->irq_lock);
b417577d
AH		 1216
1217 /* If DMA has finished after TC, complete the request */
1218 if (!req_in_progress) {
1219 struct mmc_request *mrq = host->mrq;
1220
1221 host->mrq = NULL;
1222 mmc_request_done(host->mmc, mrq);
1223 }
a45c6cb8
MC		 1224}
1225
9782aff8
PF		 1226static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1227 struct mmc_data *data,
c5c98927 1228 struct omap_hsmmc_next *next,
26b88520 1229 struct dma_chan *chan)
9782aff8
PF		 1230{
1231 int dma_len;
1232
1233 if (!next && data->host_cookie &&
1234 data->host_cookie != host->next_data.cookie) {
2cecdf00 1235 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1236 " host->next_data.cookie %d\n",
1237 __func__, data->host_cookie, host->next_data.cookie);
1238 data->host_cookie = 0;
1239 }
1240
1241 /* Check if next job is already prepared */
b38313d6 1242 if (next || data->host_cookie != host->next_data.cookie) {
26b88520 1243 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
9782aff8
PF		 1244 omap_hsmmc_get_dma_dir(host, data));
1245
1246 } else {
1247 dma_len = host->next_data.dma_len;
1248 host->next_data.dma_len = 0;
1249 }
1250
1251
1252 if (dma_len == 0)
1253 return -EINVAL;
1254
1255 if (next) {
1256 next->dma_len = dma_len;
1257 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1258 } else
1259 host->dma_len = dma_len;
1260
1261 return 0;
1262}
1263
a45c6cb8
MC		 1264/*
1265 * Routine to configure and start DMA for the MMC card
1266 */
70a3341a
DK		 1267static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1268 struct mmc_request *req)
a45c6cb8 1269{
26b88520
RK		 1270 struct dma_slave_config cfg;
1271 struct dma_async_tx_descriptor *tx;
1272 int ret = 0, i;
a45c6cb8 1273 struct mmc_data *data = req->data;
c5c98927 1274 struct dma_chan *chan;
a45c6cb8 1275
0ccd76d4 1276 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1277 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1278 struct scatterlist *sgl;
1279
1280 sgl = data->sg + i;
1281 if (sgl->length % data->blksz)
1282 return -EINVAL;
1283 }
1284 if ((data->blksz % 4) != 0)
1285 /* REVISIT: The MMC buffer increments only when MSB is written.
1286 * Return error for blksz which is non multiple of four.
1287 */
1288 return -EINVAL;
1289
b417577d 1290 BUG_ON(host->dma_ch != -1);
a45c6cb8 1291
c5c98927 1292 chan = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1293
26b88520
RK		 1294 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1295 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1296 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1297 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1298 cfg.src_maxburst = data->blksz / 4;
1299 cfg.dst_maxburst = data->blksz / 4;
c5c98927 1300
26b88520
RK		 1301 ret = dmaengine_slave_config(chan, &cfg);
1302 if (ret)
a45c6cb8 1303 return ret;
c5c98927 1304
26b88520 1305 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
9782aff8
PF		 1306 if (ret)
1307 return ret;
a45c6cb8 1308
26b88520
RK		 1309 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1310 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1311 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1312 if (!tx) {
1313 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1314 /* FIXME: cleanup */
1315 return -1;
1316 }
a45c6cb8 1317
26b88520
RK		 1318 tx->callback = omap_hsmmc_dma_callback;
1319 tx->callback_param = host;
a45c6cb8 1320
26b88520
RK		 1321 /* Does not fail */
1322 dmaengine_submit(tx);
c5c98927 1323
26b88520 1324 host->dma_ch = 1;
c5c98927 1325
26b88520 1326 dma_async_issue_pending(chan);
a45c6cb8 1327
a45c6cb8
MC		 1328 return 0;
1329}
1330
70a3341a 1331static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1332 unsigned int timeout_ns,
1333 unsigned int timeout_clks)
a45c6cb8
MC		 1334{
1335 unsigned int timeout, cycle_ns;
1336 uint32_t reg, clkd, dto = 0;
1337
1338 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1339 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1340 if (clkd == 0)
1341 clkd = 1;
1342
1343 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1344 timeout = timeout_ns / cycle_ns;
1345 timeout += timeout_clks;
a45c6cb8
MC		 1346 if (timeout) {
1347 while ((timeout & 0x80000000) == 0) {
1348 dto += 1;
1349 timeout <<= 1;
1350 }
1351 dto = 31 - dto;
1352 timeout <<= 1;
1353 if (timeout && dto)
1354 dto += 1;
1355 if (dto >= 13)
1356 dto -= 13;
1357 else
1358 dto = 0;
1359 if (dto > 14)
1360 dto = 14;
1361 }
1362
1363 reg &= ~DTO_MASK;
1364 reg |= dto << DTO_SHIFT;
1365 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1366}
1367
1368/*
1369 * Configure block length for MMC/SD cards and initiate the transfer.
1370 */
1371static int
70a3341a 1372omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1373{
1374 int ret;
1375 host->data = req->data;
1376
1377 if (req->data == NULL) {
a45c6cb8 1378 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1379 /*
1380 * Set an arbitrary 100ms data timeout for commands with
1381 * busy signal.
1382 */
1383 if (req->cmd->flags & MMC_RSP_BUSY)
1384 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1385 return 0;
1386 }
1387
1388 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1389 | (req->data->blocks << 16));
e2bf08d6 1390 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1391
a45c6cb8 1392 if (host->use_dma) {
70a3341a 1393 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8 1394 if (ret != 0) {
b1e056ae 1395 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
a45c6cb8
MC		 1396 return ret;
1397 }
1398 }
1399 return 0;
1400}
1401
9782aff8
PF		 1402static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1403 int err)
1404{
1405 struct omap_hsmmc_host *host = mmc_priv(mmc);
1406 struct mmc_data *data = mrq->data;
1407
26b88520 1408 if (host->use_dma && data->host_cookie) {
c5c98927 1409 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1410
26b88520
RK		 1411 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1412 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1413 data->host_cookie = 0;
1414 }
1415}
1416
1417static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1418 bool is_first_req)
1419{
1420 struct omap_hsmmc_host *host = mmc_priv(mmc);
1421
1422 if (mrq->data->host_cookie) {
1423 mrq->data->host_cookie = 0;
1424 return ;
1425 }
1426
c5c98927
RK		 1427 if (host->use_dma) {
1428 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
c5c98927 1429
9782aff8 1430 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
26b88520 1431 &host->next_data, c))
9782aff8 1432 mrq->data->host_cookie = 0;
c5c98927 1433 }
9782aff8
PF		 1434}
1435
a45c6cb8
MC		 1436/*
1437 * Request function. for read/write operation
1438 */
70a3341a 1439static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1440{
70a3341a 1441 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1442 int err;
a45c6cb8 1443
b417577d
AH		 1444 BUG_ON(host->req_in_progress);
1445 BUG_ON(host->dma_ch != -1);
1446 if (host->protect_card) {
1447 if (host->reqs_blocked < 3) {
1448 /*
1449 * Ensure the controller is left in a consistent
1450 * state by resetting the command and data state
1451 * machines.
1452 */
1453 omap_hsmmc_reset_controller_fsm(host, SRD);
1454 omap_hsmmc_reset_controller_fsm(host, SRC);
1455 host->reqs_blocked += 1;
1456 }
1457 req->cmd->error = -EBADF;
1458 if (req->data)
1459 req->data->error = -EBADF;
1460 req->cmd->retries = 0;
1461 mmc_request_done(mmc, req);
1462 return;
1463 } else if (host->reqs_blocked)
1464 host->reqs_blocked = 0;
a45c6cb8
MC		 1465 WARN_ON(host->mrq != NULL);
1466 host->mrq = req;
70a3341a 1467 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1468 if (err) {
1469 req->cmd->error = err;
1470 if (req->data)
1471 req->data->error = err;
1472 host->mrq = NULL;
1473 mmc_request_done(mmc, req);
1474 return;
1475 }
1476
70a3341a 1477 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1478}
1479
a45c6cb8 1480/* Routine to configure clock values. Exposed API to core */
70a3341a 1481static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1482{
70a3341a 1483 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1484 int do_send_init_stream = 0;
a45c6cb8 1485
fa4aa2d4 1486 pm_runtime_get_sync(host->dev);
5e2ea617 1487
a3621465
AH		 1488 if (ios->power_mode != host->power_mode) {
1489 switch (ios->power_mode) {
1490 case MMC_POWER_OFF:
1491 mmc_slot(host).set_power(host->dev, host->slot_id,
1492 0, 0);
1493 break;
1494 case MMC_POWER_UP:
1495 mmc_slot(host).set_power(host->dev, host->slot_id,
1496 1, ios->vdd);
1497 break;
1498 case MMC_POWER_ON:
1499 do_send_init_stream = 1;
1500 break;
1501 }
1502 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1503 }
1504
dd498eff
DK		 1505 /* FIXME: set registers based only on changes to ios */
1506
3796fb8a 1507 omap_hsmmc_set_bus_width(host);
a45c6cb8 1508
4621d5f8 1509 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1510 /* Only MMC1 can interface at 3V without some flavor
1511 * of external transceiver; but they all handle 1.8V.
1512 */
a45c6cb8 1513 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1f84b71b
RN		 1514 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1515 /*
1516 * With pbias cell programming missing, this
cf5ae40b 1517 * can't be allowed on MMC1 when booting with device
1f84b71b
RN		 1518 * tree.
1519 */
cf5ae40b 1520 !host->pbias_disable) {
a45c6cb8
MC		 1521 /*
1522 * The mmc_select_voltage fn of the core does
1523 * not seem to set the power_mode to
1524 * MMC_POWER_UP upon recalculating the voltage.
1525 * vdd 1.8v.
1526 */
70a3341a
DK		 1527 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1528 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1529 "Switch operation failed\n");
1530 }
1531 }
1532
5934df2f 1533 omap_hsmmc_set_clock(host);
a45c6cb8 1534
a3621465 1535 if (do_send_init_stream)
a45c6cb8
MC		 1536 send_init_stream(host);
1537
3796fb8a 1538 omap_hsmmc_set_bus_mode(host);
5e2ea617 1539
fa4aa2d4 1540 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1541}
1542
1543static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1544{
70a3341a 1545 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1546
191d1f1d 1547 if (!mmc_slot(host).card_detect)
a45c6cb8 1548 return -ENOSYS;
db0fefc5 1549 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1550}
1551
1552static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1553{
70a3341a 1554 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1555
191d1f1d 1556 if (!mmc_slot(host).get_ro)
a45c6cb8 1557 return -ENOSYS;
191d1f1d 1558 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1559}
1560
4816858c
GI		 1561static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1562{
1563 struct omap_hsmmc_host *host = mmc_priv(mmc);
1564
1565 if (mmc_slot(host).init_card)
1566 mmc_slot(host).init_card(card);
1567}
1568
70a3341a 1569static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1570{
1571 u32 hctl, capa, value;
1572
1573 /* Only MMC1 supports 3.0V */
4621d5f8 1574 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1575 hctl = SDVS30;
1576 capa = VS30 | VS18;
1577 } else {
1578 hctl = SDVS18;
1579 capa = VS18;
1580 }
1581
1582 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1583 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1584
1585 value = OMAP_HSMMC_READ(host->base, CAPA);
1586 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1587
1b331e69 1588 /* Set SD bus power bit */
e13bb300 1589 set_sd_bus_power(host);
1b331e69
KK		 1590}
1591
70a3341a 1592static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1593{
70a3341a 1594 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1595
fa4aa2d4
B		 1596 pm_runtime_get_sync(host->dev);
1597
dd498eff
DK		 1598 return 0;
1599}
1600
907d2e7c 1601static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
dd498eff 1602{
70a3341a 1603 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1604
fa4aa2d4
B		 1605 pm_runtime_mark_last_busy(host->dev);
1606 pm_runtime_put_autosuspend(host->dev);
1607
dd498eff
DK		 1608 return 0;
1609}
1610
70a3341a
DK		 1611static const struct mmc_host_ops omap_hsmmc_ops = {
1612 .enable = omap_hsmmc_enable_fclk,
1613 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1614 .post_req = omap_hsmmc_post_req,
1615 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1616 .request = omap_hsmmc_request,
1617 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1618 .get_cd = omap_hsmmc_get_cd,
1619 .get_ro = omap_hsmmc_get_ro,
4816858c 1620 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1621 /* NYET -- enable_sdio_irq */
1622};
1623
d900f712
DK		 1624#ifdef CONFIG_DEBUG_FS
1625
70a3341a 1626static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1627{
1628 struct mmc_host *mmc = s->private;
70a3341a 1629 struct omap_hsmmc_host *host = mmc_priv(mmc);
d900f712 1630
0a82e06e
TL		 1631 seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n",
1632 mmc->index, host->context_loss);
5e2ea617 1633
fa4aa2d4 1634 pm_runtime_get_sync(host->dev);
d900f712 1635
d900f712
DK		 1636 seq_printf(s, "CON:\t\t0x%08x\n",
1637 OMAP_HSMMC_READ(host->base, CON));
1638 seq_printf(s, "HCTL:\t\t0x%08x\n",
1639 OMAP_HSMMC_READ(host->base, HCTL));
1640 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1641 OMAP_HSMMC_READ(host->base, SYSCTL));
1642 seq_printf(s, "IE:\t\t0x%08x\n",
1643 OMAP_HSMMC_READ(host->base, IE));
1644 seq_printf(s, "ISE:\t\t0x%08x\n",
1645 OMAP_HSMMC_READ(host->base, ISE));
1646 seq_printf(s, "CAPA:\t\t0x%08x\n",
1647 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1648
fa4aa2d4
B		 1649 pm_runtime_mark_last_busy(host->dev);
1650 pm_runtime_put_autosuspend(host->dev);
dd498eff 1651
d900f712
DK		 1652 return 0;
1653}
1654
70a3341a 1655static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1656{
70a3341a 1657 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1658}
1659
1660static const struct file_operations mmc_regs_fops = {
70a3341a 1661 .open = omap_hsmmc_regs_open,
d900f712
DK		 1662 .read = seq_read,
1663 .llseek = seq_lseek,
1664 .release = single_release,
1665};
1666
70a3341a 1667static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1668{
1669 if (mmc->debugfs_root)
1670 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1671 mmc, &mmc_regs_fops);
1672}
1673
1674#else
1675
70a3341a 1676static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1677{
1678}
1679
1680#endif
1681
46856a68 1682#ifdef CONFIG_OF
59445b10
NM		 1683static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1684 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1685 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1686};
1687
1688static const struct omap_mmc_of_data omap4_mmc_of_data = {
1689 .reg_offset = 0x100,
1690};
46856a68
RN		 1691
1692static const struct of_device_id omap_mmc_of_match[] = {
1693 {
1694 .compatible = "ti,omap2-hsmmc",
1695 },
59445b10
NM		 1696 {
1697 .compatible = "ti,omap3-pre-es3-hsmmc",
1698 .data = &omap3_pre_es3_mmc_of_data,
1699 },
46856a68
RN		 1700 {
1701 .compatible = "ti,omap3-hsmmc",
1702 },
1703 {
1704 .compatible = "ti,omap4-hsmmc",
59445b10 1705 .data = &omap4_mmc_of_data,
46856a68
RN		 1706 },
1707 {},
b6d085f6 1708};
46856a68
RN		 1709MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1710
1711static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1712{
1713 struct omap_mmc_platform_data *pdata;
1714 struct device_node *np = dev->of_node;
d8714e87 1715 u32 bus_width, max_freq;
dc642c28
JL		 1716 int cd_gpio, wp_gpio;
1717
1718 cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1719 wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1720 if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1721 return ERR_PTR(-EPROBE_DEFER);
46856a68
RN		 1722
1723 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1724 if (!pdata)
1725 return NULL; /* out of memory */
1726
1727 if (of_find_property(np, "ti,dual-volt", NULL))
1728 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1729
1730 /* This driver only supports 1 slot */
1731 pdata->nr_slots = 1;
dc642c28
JL		 1732 pdata->slots[0].switch_pin = cd_gpio;
1733 pdata->slots[0].gpio_wp = wp_gpio;
46856a68
RN		 1734
1735 if (of_find_property(np, "ti,non-removable", NULL)) {
1736 pdata->slots[0].nonremovable = true;
1737 pdata->slots[0].no_regulator_off_init = true;
1738 }
7f217794 1739 of_property_read_u32(np, "bus-width", &bus_width);
46856a68
RN		 1740 if (bus_width == 4)
1741 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1742 else if (bus_width == 8)
1743 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1744
1745 if (of_find_property(np, "ti,needs-special-reset", NULL))
1746 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1747
d8714e87
DM		 1748 if (!of_property_read_u32(np, "max-frequency", &max_freq))
1749 pdata->max_freq = max_freq;
1750
cd587096
HG		 1751 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1752 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1753
c9ae64db
DM		 1754 if (of_find_property(np, "keep-power-in-suspend", NULL))
1755 pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER;
1756
1757 if (of_find_property(np, "enable-sdio-wakeup", NULL))
1758 pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1759
46856a68
RN		 1760 return pdata;
1761}
1762#else
1763static inline struct omap_mmc_platform_data
1764 *of_get_hsmmc_pdata(struct device *dev)
1765{
1766 return NULL;
1767}
1768#endif
1769
c3be1efd 1770static int omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1771{
1772 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1773 struct mmc_host *mmc;
70a3341a 1774 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1775 struct resource *res;
db0fefc5 1776 int ret, irq;
46856a68 1777 const struct of_device_id *match;
26b88520
RK		 1778 dma_cap_mask_t mask;
1779 unsigned tx_req, rx_req;
46b76035 1780 struct pinctrl *pinctrl;
59445b10 1781 const struct omap_mmc_of_data *data;
46856a68
RN		 1782
1783 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1784 if (match) {
1785 pdata = of_get_hsmmc_pdata(&pdev->dev);
dc642c28
JL		 1786
1787 if (IS_ERR(pdata))
1788 return PTR_ERR(pdata);
1789
46856a68 1790 if (match->data) {
59445b10
NM		 1791 data = match->data;
1792 pdata->reg_offset = data->reg_offset;
1793 pdata->controller_flags |= data->controller_flags;
46856a68
RN		 1794 }
1795 }
a45c6cb8
MC		 1796
1797 if (pdata == NULL) {
1798 dev_err(&pdev->dev, "Platform Data is missing\n");
1799 return -ENXIO;
1800 }
1801
1802 if (pdata->nr_slots == 0) {
1803 dev_err(&pdev->dev, "No Slots\n");
1804 return -ENXIO;
1805 }
1806
1807 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1808 irq = platform_get_irq(pdev, 0);
1809 if (res == NULL || irq < 0)
1810 return -ENXIO;
1811
984b203a 1812 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1813 if (res == NULL)
1814 return -EBUSY;
1815
db0fefc5
AH		 1816 ret = omap_hsmmc_gpio_init(pdata);
1817 if (ret)
1818 goto err;
1819
70a3341a 1820 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1821 if (!mmc) {
1822 ret = -ENOMEM;
db0fefc5 1823 goto err_alloc;
a45c6cb8
MC		 1824 }
1825
1826 host = mmc_priv(mmc);
1827 host->mmc = mmc;
1828 host->pdata = pdata;
1829 host->dev = &pdev->dev;
1830 host->use_dma = 1;
a45c6cb8
MC		 1831 host->dma_ch = -1;
1832 host->irq = irq;
a45c6cb8 1833 host->slot_id = 0;
fc307df8 1834 host->mapbase = res->start + pdata->reg_offset;
a45c6cb8 1835 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1836 host->power_mode = MMC_POWER_OFF;
9782aff8 1837 host->next_data.cookie = 1;
a45c6cb8
MC		 1838
1839 platform_set_drvdata(pdev, host);
a45c6cb8 1840
7a8c2cef 1841 mmc->ops = &omap_hsmmc_ops;
dd498eff 1842
d418ed87
DM		 1843 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1844
1845 if (pdata->max_freq > 0)
1846 mmc->f_max = pdata->max_freq;
1847 else
1848 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1849
4dffd7a2 1850 spin_lock_init(&host->irq_lock);
a45c6cb8 1851
6f7607cc 1852 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1853 if (IS_ERR(host->fclk)) {
1854 ret = PTR_ERR(host->fclk);
1855 host->fclk = NULL;
a45c6cb8
MC		 1856 goto err1;
1857 }
1858
9b68256c
PW		 1859 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1860 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1861 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1862 }
dd498eff 1863
fa4aa2d4
B		 1864 pm_runtime_enable(host->dev);
1865 pm_runtime_get_sync(host->dev);
1866 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1867 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1868
92a3aebf
B		 1869 omap_hsmmc_context_save(host);
1870
cf5ae40b 1871 /* This can be removed once we support PBIAS with DT */
e002264f 1872 if (host->dev->of_node && res->start == 0x4809c000)
cf5ae40b
TL		 1873 host->pbias_disable = 1;
1874
cd03d9a8
RN		 1875 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1876 /*
1877 * MMC can still work without debounce clock.
1878 */
1879 if (IS_ERR(host->dbclk)) {
cd03d9a8 1880 host->dbclk = NULL;
94c18149 1881 } else if (clk_prepare_enable(host->dbclk) != 0) {
cd03d9a8
RN		 1882 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1883 clk_put(host->dbclk);
1884 host->dbclk = NULL;
2bec0893 1885 }
a45c6cb8 1886
0ccd76d4
JY		 1887 /* Since we do only SG emulation, we can have as many segs
1888 * as we want. */
a36274e0 1889 mmc->max_segs = 1024;
0ccd76d4 1890
a45c6cb8
MC		 1891 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1892 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1893 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1894 mmc->max_seg_size = mmc->max_req_size;
1895
13189e78 1896 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1897 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1898
3a63833e
SG		 1899 mmc->caps |= mmc_slot(host).caps;
1900 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1901 mmc->caps |= MMC_CAP_4_BIT_DATA;
1902
191d1f1d 1903 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1904 mmc->caps |= MMC_CAP_NONREMOVABLE;
1905
6fdc75de
EP		 1906 mmc->pm_caps = mmc_slot(host).pm_caps;
1907
70a3341a 1908 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1909
4a29b559
SS		 1910 if (!pdev->dev.of_node) {
1911 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1912 if (!res) {
1913 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1914 ret = -ENXIO;
1915 goto err_irq;
1916 }
1917 tx_req = res->start;
b7bf773b 1918
4a29b559
SS		 1919 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1920 if (!res) {
1921 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1922 ret = -ENXIO;
1923 goto err_irq;
1924 }
1925 rx_req = res->start;
f3e2f1dd 1926 }
a45c6cb8 1927
26b88520
RK		 1928 dma_cap_zero(mask);
1929 dma_cap_set(DMA_SLAVE, mask);
1930
d272fbf0
MP		 1931 host->rx_chan =
1932 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1933 &rx_req, &pdev->dev, "rx");
1934
26b88520
RK		 1935 if (!host->rx_chan) {
1936 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
04e8c7bc 1937 ret = -ENXIO;
26b88520
RK		 1938 goto err_irq;
1939 }
1940
d272fbf0
MP		 1941 host->tx_chan =
1942 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1943 &tx_req, &pdev->dev, "tx");
1944
26b88520
RK		 1945 if (!host->tx_chan) {
1946 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
04e8c7bc 1947 ret = -ENXIO;
26b88520 1948 goto err_irq;
c5c98927 1949 }
a45c6cb8
MC		 1950
1951 /* Request IRQ for MMC operations */
d9618e9f 1952 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1953 mmc_hostname(mmc), host);
1954 if (ret) {
b1e056ae 1955 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
a45c6cb8
MC		 1956 goto err_irq;
1957 }
1958
1959 if (pdata->init != NULL) {
1960 if (pdata->init(&pdev->dev) != 0) {
b1e056ae 1961 dev_err(mmc_dev(host->mmc),
70a3341a 1962 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1963 goto err_irq_cd_init;
1964 }
1965 }
db0fefc5 1966
b702b106 1967 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1968 ret = omap_hsmmc_reg_get(host);
1969 if (ret)
1970 goto err_reg;
1971 host->use_reg = 1;
1972 }
1973
b583f26d 1974 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1975
1976 /* Request IRQ for card detect */
e1a55f5e 1977 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1978 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1979 NULL,
1980 omap_hsmmc_detect,
db35f83e 1981 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
7efab4f3 1982 mmc_hostname(mmc), host);
a45c6cb8 1983 if (ret) {
b1e056ae 1984 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1985 "Unable to grab MMC CD IRQ\n");
1986 goto err_irq_cd;
1987 }
72f2e2c7 1988 pdata->suspend = omap_hsmmc_suspend_cdirq;
1989 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 1990 }
1991
b417577d 1992 omap_hsmmc_disable_irq(host);
a45c6cb8 1993
46b76035
DM		 1994 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1995 if (IS_ERR(pinctrl))
1996 dev_warn(&pdev->dev,
1997 "pins are not configured from the driver\n");
1998
b62f6228
AH		 1999 omap_hsmmc_protect_card(host);
2000
a45c6cb8
MC		 2001 mmc_add_host(mmc);
2002
191d1f1d 2003 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2004 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2005 if (ret < 0)
2006 goto err_slot_name;
2007 }
191d1f1d 2008 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2009 ret = device_create_file(&mmc->class_dev,
2010 &dev_attr_cover_switch);
2011 if (ret < 0)
db0fefc5 2012 goto err_slot_name;
a45c6cb8
MC		 2013 }
2014
70a3341a 2015 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2016 pm_runtime_mark_last_busy(host->dev);
2017 pm_runtime_put_autosuspend(host->dev);
d900f712 2018
a45c6cb8
MC		 2019 return 0;
2020
a45c6cb8
MC		 2021err_slot_name:
2022 mmc_remove_host(mmc);
a45c6cb8 2023 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2024err_irq_cd:
2025 if (host->use_reg)
2026 omap_hsmmc_reg_put(host);
2027err_reg:
2028 if (host->pdata->cleanup)
2029 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2030err_irq_cd_init:
2031 free_irq(host->irq, host);
2032err_irq:
c5c98927
RK		 2033 if (host->tx_chan)
2034 dma_release_channel(host->tx_chan);
2035 if (host->rx_chan)
2036 dma_release_channel(host->rx_chan);
d59d77ed 2037 pm_runtime_put_sync(host->dev);
37f6190d 2038 pm_runtime_disable(host->dev);
a45c6cb8 2039 clk_put(host->fclk);
cd03d9a8 2040 if (host->dbclk) {
94c18149 2041 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 2042 clk_put(host->dbclk);
2043 }
a45c6cb8
MC		 2044err1:
2045 iounmap(host->base);
db0fefc5
AH		 2046 mmc_free_host(mmc);
2047err_alloc:
2048 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2049err:
48b332f9
RK		 2050 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2051 if (res)
2052 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2053 return ret;
2054}
2055
6e0ee714 2056static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2057{
70a3341a 2058 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2059 struct resource *res;
2060
927ce944
FB		 2061 pm_runtime_get_sync(host->dev);
2062 mmc_remove_host(host->mmc);
2063 if (host->use_reg)
2064 omap_hsmmc_reg_put(host);
2065 if (host->pdata->cleanup)
2066 host->pdata->cleanup(&pdev->dev);
2067 free_irq(host->irq, host);
2068 if (mmc_slot(host).card_detect_irq)
2069 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 2070
c5c98927
RK		 2071 if (host->tx_chan)
2072 dma_release_channel(host->tx_chan);
2073 if (host->rx_chan)
2074 dma_release_channel(host->rx_chan);
2075
927ce944
FB		 2076 pm_runtime_put_sync(host->dev);
2077 pm_runtime_disable(host->dev);
2078 clk_put(host->fclk);
cd03d9a8 2079 if (host->dbclk) {
94c18149 2080 clk_disable_unprepare(host->dbclk);
927ce944 2081 clk_put(host->dbclk);
a45c6cb8
MC		 2082 }
2083
9ea28ecb 2084 omap_hsmmc_gpio_free(host->pdata);
927ce944 2085 iounmap(host->base);
9d1f0286 2086 mmc_free_host(host->mmc);
927ce944 2087
a45c6cb8
MC		 2088 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2089 if (res)
984b203a 2090 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2091
2092 return 0;
2093}
2094
2095#ifdef CONFIG_PM
a48ce884
FB		 2096static int omap_hsmmc_prepare(struct device *dev)
2097{
2098 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2099
2100 if (host->pdata->suspend)
2101 return host->pdata->suspend(dev, host->slot_id);
2102
2103 return 0;
2104}
2105
2106static void omap_hsmmc_complete(struct device *dev)
2107{
2108 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2109
2110 if (host->pdata->resume)
2111 host->pdata->resume(dev, host->slot_id);
2112
2113}
2114
a791daa1 2115static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8 2116{
927ce944 2117 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2118
927ce944 2119 if (!host)
a45c6cb8
MC		 2120 return 0;
2121
927ce944 2122 pm_runtime_get_sync(host->dev);
31f9d463 2123
927ce944
FB		 2124 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2125 omap_hsmmc_disable_irq(host);
2126 OMAP_HSMMC_WRITE(host->base, HCTL,
2127 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2128 }
927ce944 2129
cd03d9a8 2130 if (host->dbclk)
94c18149 2131 clk_disable_unprepare(host->dbclk);
3932afd5 2132
31f9d463 2133 pm_runtime_put_sync(host->dev);
3932afd5 2134 return 0;
a45c6cb8
MC		 2135}
2136
2137/* Routine to resume the MMC device */
a791daa1 2138static int omap_hsmmc_resume(struct device *dev)
a45c6cb8 2139{
927ce944
FB		 2140 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2141
2142 if (!host)
2143 return 0;
a45c6cb8 2144
927ce944 2145 pm_runtime_get_sync(host->dev);
11dd62a7 2146
cd03d9a8 2147 if (host->dbclk)
94c18149 2148 clk_prepare_enable(host->dbclk);
2bec0893 2149
927ce944
FB		 2150 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2151 omap_hsmmc_conf_bus_power(host);
1b331e69 2152
927ce944 2153 omap_hsmmc_protect_card(host);
b62f6228 2154
927ce944
FB		 2155 pm_runtime_mark_last_busy(host->dev);
2156 pm_runtime_put_autosuspend(host->dev);
3932afd5 2157 return 0;
a45c6cb8
MC		 2158}
2159
2160#else
a48ce884
FB		 2161#define omap_hsmmc_prepare NULL
2162#define omap_hsmmc_complete NULL
70a3341a 2163#define omap_hsmmc_suspend NULL
a48ce884 2164#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2165#endif
2166
fa4aa2d4
B		 2167static int omap_hsmmc_runtime_suspend(struct device *dev)
2168{
2169 struct omap_hsmmc_host *host;
2170
2171 host = platform_get_drvdata(to_platform_device(dev));
2172 omap_hsmmc_context_save(host);
927ce944 2173 dev_dbg(dev, "disabled\n");
fa4aa2d4
B		 2174
2175 return 0;
2176}
2177
2178static int omap_hsmmc_runtime_resume(struct device *dev)
2179{
2180 struct omap_hsmmc_host *host;
2181
2182 host = platform_get_drvdata(to_platform_device(dev));
2183 omap_hsmmc_context_restore(host);
927ce944 2184 dev_dbg(dev, "enabled\n");
fa4aa2d4
B		 2185
2186 return 0;
2187}
2188
a791daa1 2189static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2190 .suspend = omap_hsmmc_suspend,
2191 .resume = omap_hsmmc_resume,
a48ce884
FB		 2192 .prepare = omap_hsmmc_prepare,
2193 .complete = omap_hsmmc_complete,
fa4aa2d4
B		 2194 .runtime_suspend = omap_hsmmc_runtime_suspend,
2195 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2196};
2197
2198static struct platform_driver omap_hsmmc_driver = {
efa25fd3 2199 .probe = omap_hsmmc_probe,
0433c143 2200 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2201 .driver = {
2202 .name = DRIVER_NAME,
2203 .owner = THIS_MODULE,
a791daa1 2204 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2205 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2206 },
2207};
2208
b796450b 2209module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2210MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2211MODULE_LICENSE("GPL");
2212MODULE_ALIAS("platform:" DRIVER_NAME);
2213MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)