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Merge tag 'driver-core-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712 21#include <linux/debugfs.h>
c5c98927 22#include <linux/dmaengine.h>
d900f712 23#include <linux/seq_file.h>
a45c6cb8
MC		 24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
a45c6cb8
MC		 28#include <linux/timer.h>
29#include <linux/clk.h>
46856a68
RN		 30#include <linux/of.h>
31#include <linux/of_gpio.h>
32#include <linux/of_device.h>
3451c067 33#include <linux/omap-dma.h>
a45c6cb8 34#include <linux/mmc/host.h>
13189e78 35#include <linux/mmc/core.h>
93caf8e6 36#include <linux/mmc/mmc.h>
a45c6cb8 37#include <linux/io.h>
db0fefc5
AH		 38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
46b76035 40#include <linux/pinctrl/consumer.h>
fa4aa2d4 41#include <linux/pm_runtime.h>
a45c6cb8 42#include <mach/hardware.h>
ce491cf8
TL		 43#include <plat/mmc.h>
44#include <plat/cpu.h>
a45c6cb8
MC		 45
46/* OMAP HSMMC Host Controller Registers */
11dd62a7 47#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 48#define OMAP_HSMMC_CON 0x002C
49#define OMAP_HSMMC_BLK 0x0104
50#define OMAP_HSMMC_ARG 0x0108
51#define OMAP_HSMMC_CMD 0x010C
52#define OMAP_HSMMC_RSP10 0x0110
53#define OMAP_HSMMC_RSP32 0x0114
54#define OMAP_HSMMC_RSP54 0x0118
55#define OMAP_HSMMC_RSP76 0x011C
56#define OMAP_HSMMC_DATA 0x0120
57#define OMAP_HSMMC_HCTL 0x0128
58#define OMAP_HSMMC_SYSCTL 0x012C
59#define OMAP_HSMMC_STAT 0x0130
60#define OMAP_HSMMC_IE 0x0134
61#define OMAP_HSMMC_ISE 0x0138
62#define OMAP_HSMMC_CAPA 0x0140
63
64#define VS18 (1 << 26)
65#define VS30 (1 << 25)
cd587096 66#define HSS (1 << 21)
a45c6cb8
MC		 67#define SDVS18 (0x5 << 9)
68#define SDVS30 (0x6 << 9)
eb250826 69#define SDVS33 (0x7 << 9)
1b331e69 70#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 71#define SDVSCLR 0xFFFFF1FF
72#define SDVSDET 0x00000400
73#define AUTOIDLE 0x1
74#define SDBP (1 << 8)
75#define DTO 0xe
76#define ICE 0x1
77#define ICS 0x2
78#define CEN (1 << 2)
79#define CLKD_MASK 0x0000FFC0
80#define CLKD_SHIFT 6
81#define DTO_MASK 0x000F0000
82#define DTO_SHIFT 16
a45c6cb8
MC		 83#define INIT_STREAM (1 << 1)
84#define DP_SELECT (1 << 21)
85#define DDIR (1 << 4)
a7e96879 86#define DMAE 0x1
a45c6cb8
MC		 87#define MSBS (1 << 5)
88#define BCE (1 << 1)
89#define FOUR_BIT (1 << 1)
cd587096 90#define HSPE (1 << 2)
03b5d924 91#define DDR (1 << 19)
73153010 92#define DW8 (1 << 5)
a45c6cb8 93#define OD 0x1
a45c6cb8
MC		 94#define STAT_CLEAR 0xFFFFFFFF
95#define INIT_STREAM_CMD 0x00000000
96#define DUAL_VOLT_OCR_BIT 7
97#define SRC (1 << 25)
98#define SRD (1 << 26)
11dd62a7
DK		 99#define SOFTRESET (1 << 1)
100#define RESETDONE (1 << 0)
a45c6cb8 101
a7e96879
V		 102/* Interrupt masks for IE and ISE register */
103#define CC_EN (1 << 0)
104#define TC_EN (1 << 1)
105#define BWR_EN (1 << 4)
106#define BRR_EN (1 << 5)
107#define ERR_EN (1 << 15)
108#define CTO_EN (1 << 16)
109#define CCRC_EN (1 << 17)
110#define CEB_EN (1 << 18)
111#define CIE_EN (1 << 19)
112#define DTO_EN (1 << 20)
113#define DCRC_EN (1 << 21)
114#define DEB_EN (1 << 22)
115#define CERR_EN (1 << 28)
116#define BADA_EN (1 << 29)
117
118#define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
119 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
120 BRR_EN | BWR_EN | TC_EN | CC_EN)
121
fa4aa2d4 122#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8 123#define MMC_TIMEOUT_MS 20
6b206efe
AS		 124#define OMAP_MMC_MIN_CLOCK 400000
125#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 126#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 127
128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
9782aff8
PF		 144struct omap_hsmmc_next {
145 unsigned int dma_len;
146 s32 cookie;
147};
148
70a3341a 149struct omap_hsmmc_host {
a45c6cb8
MC		 150 struct device *dev;
151 struct mmc_host *mmc;
152 struct mmc_request *mrq;
153 struct mmc_command *cmd;
154 struct mmc_data *data;
155 struct clk *fclk;
a45c6cb8 156 struct clk *dbclk;
db0fefc5
AH		 157 /*
158 * vcc == configured supply
159 * vcc_aux == optional
160 * - MMC1, supply for DAT4..DAT7
161 * - MMC2/MMC2, external level shifter voltage supply, for
162 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
163 */
164 struct regulator *vcc;
165 struct regulator *vcc_aux;
a45c6cb8
MC		 166 void __iomem *base;
167 resource_size_t mapbase;
4dffd7a2 168 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 169 unsigned int dma_len;
0ccd76d4 170 unsigned int dma_sg_idx;
a45c6cb8 171 unsigned char bus_mode;
a3621465 172 unsigned char power_mode;
a45c6cb8
MC		 173 int suspended;
174 int irq;
a45c6cb8 175 int use_dma, dma_ch;
c5c98927
RK		 176 struct dma_chan *tx_chan;
177 struct dma_chan *rx_chan;
a45c6cb8 178 int slot_id;
4a694dc9 179 int response_busy;
11dd62a7 180 int context_loss;
b62f6228
AH		 181 int protect_card;
182 int reqs_blocked;
db0fefc5 183 int use_reg;
b417577d 184 int req_in_progress;
9782aff8 185 struct omap_hsmmc_next next_data;
11dd62a7 186
a45c6cb8
MC		 187 struct omap_mmc_platform_data *pdata;
188};
189
db0fefc5
AH		 190static int omap_hsmmc_card_detect(struct device *dev, int slot)
191{
9ea28ecb
B		 192 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
193 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 194
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
197}
198
199static int omap_hsmmc_get_wp(struct device *dev, int slot)
200{
9ea28ecb
B		 201 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
202 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 203
204 /* NOTE: assumes write protect signal is active-high */
205 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
206}
207
208static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
209{
9ea28ecb
B		 210 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
211 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 212
213 /* NOTE: assumes card detect signal is active-low */
214 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
215}
216
217#ifdef CONFIG_PM
218
219static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
220{
9ea28ecb
B		 221 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
222 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 223
224 disable_irq(mmc->slots[0].card_detect_irq);
225 return 0;
226}
227
228static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
229{
9ea28ecb
B		 230 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
231 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 232
233 enable_irq(mmc->slots[0].card_detect_irq);
234 return 0;
235}
236
237#else
238
239#define omap_hsmmc_suspend_cdirq NULL
240#define omap_hsmmc_resume_cdirq NULL
241
242#endif
243
b702b106
AH		 244#ifdef CONFIG_REGULATOR
245
69b07ece 246static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 247 int vdd)
248{
249 struct omap_hsmmc_host *host =
250 platform_get_drvdata(to_platform_device(dev));
251 int ret = 0;
252
253 /*
254 * If we don't see a Vcc regulator, assume it's a fixed
255 * voltage always-on regulator.
256 */
257 if (!host->vcc)
258 return 0;
1f84b71b
RN		 259 /*
260 * With DT, never turn OFF the regulator. This is because
261 * the pbias cell programming support is still missing when
262 * booting with Device tree
263 */
4d048f91 264 if (dev->of_node && !vdd)
1f84b71b 265 return 0;
db0fefc5
AH		 266
267 if (mmc_slot(host).before_set_reg)
268 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
269
270 /*
271 * Assume Vcc regulator is used only to power the card ... OMAP
272 * VDDS is used to power the pins, optionally with a transceiver to
273 * support cards using voltages other than VDDS (1.8V nominal). When a
274 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
275 *
276 * In some cases this regulator won't support enable/disable;
277 * e.g. it's a fixed rail for a WLAN chip.
278 *
279 * In other cases vcc_aux switches interface power. Example, for
280 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
281 * chips/cards need an interface voltage rail too.
282 */
283 if (power_on) {
99fc5131 284 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 285 /* Enable interface voltage rail, if needed */
286 if (ret == 0 && host->vcc_aux) {
287 ret = regulator_enable(host->vcc_aux);
288 if (ret < 0)
99fc5131
LW		 289 ret = mmc_regulator_set_ocr(host->mmc,
290 host->vcc, 0);
db0fefc5
AH		 291 }
292 } else {
99fc5131 293 /* Shut down the rail */
6da20c89
AH		 294 if (host->vcc_aux)
295 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 296 if (!ret) {
297 /* Then proceed to shut down the local regulator */
298 ret = mmc_regulator_set_ocr(host->mmc,
299 host->vcc, 0);
300 }
db0fefc5
AH		 301 }
302
303 if (mmc_slot(host).after_set_reg)
304 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
305
306 return ret;
307}
308
db0fefc5
AH		 309static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
310{
311 struct regulator *reg;
64be9782 312 int ocr_value = 0;
db0fefc5 313
db0fefc5
AH		 314 reg = regulator_get(host->dev, "vmmc");
315 if (IS_ERR(reg)) {
b1e056ae 316 dev_err(host->dev, "vmmc regulator missing\n");
1fdc90fb 317 return PTR_ERR(reg);
db0fefc5 318 } else {
1fdc90fb 319 mmc_slot(host).set_power = omap_hsmmc_set_power;
db0fefc5 320 host->vcc = reg;
64be9782 321 ocr_value = mmc_regulator_get_ocrmask(reg);
322 if (!mmc_slot(host).ocr_mask) {
323 mmc_slot(host).ocr_mask = ocr_value;
324 } else {
325 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
2cecdf00 326 dev_err(host->dev, "ocrmask %x is not supported\n",
e3f1adb6 327 mmc_slot(host).ocr_mask);
64be9782 328 mmc_slot(host).ocr_mask = 0;
329 return -EINVAL;
330 }
331 }
db0fefc5
AH		 332
333 /* Allow an aux regulator */
334 reg = regulator_get(host->dev, "vmmc_aux");
335 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
336
b1c1df7a
B		 337 /* For eMMC do not power off when not in sleep state */
338 if (mmc_slot(host).no_regulator_off_init)
339 return 0;
db0fefc5
AH		 340 /*
341 * UGLY HACK: workaround regulator framework bugs.
342 * When the bootloader leaves a supply active, it's
343 * initialized with zero usecount ... and we can't
344 * disable it without first enabling it. Until the
345 * framework is fixed, we need a workaround like this
346 * (which is safe for MMC, but not in general).
347 */
e840ce13
AH		 348 if (regulator_is_enabled(host->vcc) > 0 ||
349 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
350 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
351
352 mmc_slot(host).set_power(host->dev, host->slot_id,
353 1, vdd);
354 mmc_slot(host).set_power(host->dev, host->slot_id,
355 0, 0);
db0fefc5
AH		 356 }
357 }
358
359 return 0;
db0fefc5
AH		 360}
361
362static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
363{
364 regulator_put(host->vcc);
365 regulator_put(host->vcc_aux);
366 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 367}
368
b702b106
AH		 369static inline int omap_hsmmc_have_reg(void)
370{
371 return 1;
372}
373
374#else
375
376static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
377{
378 return -EINVAL;
379}
380
381static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
382{
383}
384
385static inline int omap_hsmmc_have_reg(void)
386{
387 return 0;
388}
389
390#endif
391
392static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
393{
394 int ret;
395
396 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 397 if (pdata->slots[0].cover)
398 pdata->slots[0].get_cover_state =
399 omap_hsmmc_get_cover_state;
400 else
401 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
402 pdata->slots[0].card_detect_irq =
403 gpio_to_irq(pdata->slots[0].switch_pin);
404 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
405 if (ret)
406 return ret;
407 ret = gpio_direction_input(pdata->slots[0].switch_pin);
408 if (ret)
409 goto err_free_sp;
410 } else
411 pdata->slots[0].switch_pin = -EINVAL;
412
413 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
414 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
415 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
416 if (ret)
417 goto err_free_cd;
418 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
419 if (ret)
420 goto err_free_wp;
421 } else
422 pdata->slots[0].gpio_wp = -EINVAL;
423
424 return 0;
425
426err_free_wp:
427 gpio_free(pdata->slots[0].gpio_wp);
428err_free_cd:
429 if (gpio_is_valid(pdata->slots[0].switch_pin))
430err_free_sp:
431 gpio_free(pdata->slots[0].switch_pin);
432 return ret;
433}
434
435static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
436{
437 if (gpio_is_valid(pdata->slots[0].gpio_wp))
438 gpio_free(pdata->slots[0].gpio_wp);
439 if (gpio_is_valid(pdata->slots[0].switch_pin))
440 gpio_free(pdata->slots[0].switch_pin);
441}
442
e0c7f99b
AS		 443/*
444 * Start clock to the card
445 */
446static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
447{
448 OMAP_HSMMC_WRITE(host->base, SYSCTL,
449 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
450}
451
a45c6cb8
MC		 452/*
453 * Stop clock to the card
454 */
70a3341a 455static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 456{
457 OMAP_HSMMC_WRITE(host->base, SYSCTL,
458 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
459 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
7122bbb0 460 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
a45c6cb8
MC		 461}
462
93caf8e6
AH		 463static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
464 struct mmc_command *cmd)
b417577d
AH		 465{
466 unsigned int irq_mask;
467
468 if (host->use_dma)
a7e96879 469 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
b417577d
AH		 470 else
471 irq_mask = INT_EN_MASK;
472
93caf8e6
AH		 473 /* Disable timeout for erases */
474 if (cmd->opcode == MMC_ERASE)
a7e96879 475 irq_mask &= ~DTO_EN;
93caf8e6 476
b417577d
AH		 477 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
478 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
479 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
480}
481
482static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
483{
484 OMAP_HSMMC_WRITE(host->base, ISE, 0);
485 OMAP_HSMMC_WRITE(host->base, IE, 0);
486 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
487}
488
ac330f44 489/* Calculate divisor for the given clock frequency */
d83b6e03 490static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 491{
492 u16 dsor = 0;
493
494 if (ios->clock) {
d83b6e03 495 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ac330f44
AS		 496 if (dsor > 250)
497 dsor = 250;
498 }
499
500 return dsor;
501}
502
5934df2f
AS		 503static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
504{
505 struct mmc_ios *ios = &host->mmc->ios;
506 unsigned long regval;
507 unsigned long timeout;
cd587096 508 unsigned long clkdiv;
5934df2f 509
8986d31b 510 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
5934df2f
AS		 511
512 omap_hsmmc_stop_clock(host);
513
514 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
515 regval = regval & ~(CLKD_MASK | DTO_MASK);
cd587096
HG		 516 clkdiv = calc_divisor(host, ios);
517 regval = regval | (clkdiv << 6) | (DTO << 16);
5934df2f
AS		 518 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
519 OMAP_HSMMC_WRITE(host->base, SYSCTL,
520 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
521
522 /* Wait till the ICS bit is set */
523 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
524 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
525 && time_before(jiffies, timeout))
526 cpu_relax();
527
cd587096
HG		 528 /*
529 * Enable High-Speed Support
530 * Pre-Requisites
531 * - Controller should support High-Speed-Enable Bit
532 * - Controller should not be using DDR Mode
533 * - Controller should advertise that it supports High Speed
534 * in capabilities register
535 * - MMC/SD clock coming out of controller > 25MHz
536 */
537 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
538 (ios->timing != MMC_TIMING_UHS_DDR50) &&
539 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
540 regval = OMAP_HSMMC_READ(host->base, HCTL);
541 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
542 regval |= HSPE;
543 else
544 regval &= ~HSPE;
545
546 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
547 }
548
5934df2f
AS		 549 omap_hsmmc_start_clock(host);
550}
551
3796fb8a
AS		 552static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
553{
554 struct mmc_ios *ios = &host->mmc->ios;
555 u32 con;
556
557 con = OMAP_HSMMC_READ(host->base, CON);
03b5d924
B		 558 if (ios->timing == MMC_TIMING_UHS_DDR50)
559 con |= DDR; /* configure in DDR mode */
560 else
561 con &= ~DDR;
3796fb8a
AS		 562 switch (ios->bus_width) {
563 case MMC_BUS_WIDTH_8:
564 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
565 break;
566 case MMC_BUS_WIDTH_4:
567 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
568 OMAP_HSMMC_WRITE(host->base, HCTL,
569 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
570 break;
571 case MMC_BUS_WIDTH_1:
572 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
573 OMAP_HSMMC_WRITE(host->base, HCTL,
574 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
575 break;
576 }
577}
578
579static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
580{
581 struct mmc_ios *ios = &host->mmc->ios;
582 u32 con;
583
584 con = OMAP_HSMMC_READ(host->base, CON);
585 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
586 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
587 else
588 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
589}
590
11dd62a7
DK		 591#ifdef CONFIG_PM
592
593/*
594 * Restore the MMC host context, if it was lost as result of a
595 * power state change.
596 */
70a3341a 597static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 598{
599 struct mmc_ios *ios = &host->mmc->ios;
600 struct omap_mmc_platform_data *pdata = host->pdata;
601 int context_loss = 0;
3796fb8a 602 u32 hctl, capa;
11dd62a7
DK		 603 unsigned long timeout;
604
605 if (pdata->get_context_loss_count) {
606 context_loss = pdata->get_context_loss_count(host->dev);
607 if (context_loss < 0)
608 return 1;
609 }
610
611 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
612 context_loss == host->context_loss ? "not " : "");
613 if (host->context_loss == context_loss)
614 return 1;
615
6c31b215
V		 616 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
617 return 1;
11dd62a7 618
c2200efb 619 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 620 if (host->power_mode != MMC_POWER_OFF &&
621 (1 << ios->vdd) <= MMC_VDD_23_24)
622 hctl = SDVS18;
623 else
624 hctl = SDVS30;
625 capa = VS30 | VS18;
626 } else {
627 hctl = SDVS18;
628 capa = VS18;
629 }
630
631 OMAP_HSMMC_WRITE(host->base, HCTL,
632 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
633
634 OMAP_HSMMC_WRITE(host->base, CAPA,
635 OMAP_HSMMC_READ(host->base, CAPA) | capa);
636
637 OMAP_HSMMC_WRITE(host->base, HCTL,
638 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
639
640 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
641 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
642 && time_before(jiffies, timeout))
643 ;
644
b417577d 645 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 646
647 /* Do not initialize card-specific things if the power is off */
648 if (host->power_mode == MMC_POWER_OFF)
649 goto out;
650
3796fb8a 651 omap_hsmmc_set_bus_width(host);
11dd62a7 652
5934df2f 653 omap_hsmmc_set_clock(host);
11dd62a7 654
3796fb8a
AS		 655 omap_hsmmc_set_bus_mode(host);
656
11dd62a7
DK		 657out:
658 host->context_loss = context_loss;
659
660 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
661 return 0;
662}
663
664/*
665 * Save the MMC host context (store the number of power state changes so far).
666 */
70a3341a 667static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 668{
669 struct omap_mmc_platform_data *pdata = host->pdata;
670 int context_loss;
671
672 if (pdata->get_context_loss_count) {
673 context_loss = pdata->get_context_loss_count(host->dev);
674 if (context_loss < 0)
675 return;
676 host->context_loss = context_loss;
677 }
678}
679
680#else
681
70a3341a 682static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 683{
684 return 0;
685}
686
70a3341a 687static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 688{
689}
690
691#endif
692
a45c6cb8
MC		 693/*
694 * Send init stream sequence to card
695 * before sending IDLE command
696 */
70a3341a 697static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 698{
699 int reg = 0;
700 unsigned long timeout;
701
b62f6228
AH		 702 if (host->protect_card)
703 return;
704
a45c6cb8 705 disable_irq(host->irq);
b417577d
AH		 706
707 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 708 OMAP_HSMMC_WRITE(host->base, CON,
709 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
710 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
711
712 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
a7e96879
V		 713 while ((reg != CC_EN) && time_before(jiffies, timeout))
714 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
a45c6cb8
MC		 715
716 OMAP_HSMMC_WRITE(host->base, CON,
717 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 718
719 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
720 OMAP_HSMMC_READ(host->base, STAT);
721
a45c6cb8
MC		 722 enable_irq(host->irq);
723}
724
725static inline
70a3341a 726int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 727{
728 int r = 1;
729
191d1f1d
DK		 730 if (mmc_slot(host).get_cover_state)
731 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 732 return r;
733}
734
735static ssize_t
70a3341a 736omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 737 char *buf)
738{
739 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 740 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 741
70a3341a
DK		 742 return sprintf(buf, "%s\n",
743 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 744}
745
70a3341a 746static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 747
748static ssize_t
70a3341a 749omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 750 char *buf)
751{
752 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 753 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 754
191d1f1d 755 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 756}
757
70a3341a 758static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 759
760/*
761 * Configure the response type and send the cmd.
762 */
763static void
70a3341a 764omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 765 struct mmc_data *data)
766{
767 int cmdreg = 0, resptype = 0, cmdtype = 0;
768
8986d31b 769 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
a45c6cb8
MC		 770 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
771 host->cmd = cmd;
772
93caf8e6 773 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 774
4a694dc9 775 host->response_busy = 0;
a45c6cb8
MC		 776 if (cmd->flags & MMC_RSP_PRESENT) {
777 if (cmd->flags & MMC_RSP_136)
778 resptype = 1;
4a694dc9
AH		 779 else if (cmd->flags & MMC_RSP_BUSY) {
780 resptype = 3;
781 host->response_busy = 1;
782 } else
a45c6cb8
MC		 783 resptype = 2;
784 }
785
786 /*
787 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
788 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
789 * a val of 0x3, rest 0x0.
790 */
791 if (cmd == host->mrq->stop)
792 cmdtype = 0x3;
793
794 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
795
796 if (data) {
797 cmdreg |= DP_SELECT | MSBS | BCE;
798 if (data->flags & MMC_DATA_READ)
799 cmdreg |= DDIR;
800 else
801 cmdreg &= ~(DDIR);
802 }
803
804 if (host->use_dma)
a7e96879 805 cmdreg |= DMAE;
a45c6cb8 806
b417577d 807 host->req_in_progress = 1;
4dffd7a2 808
a45c6cb8
MC		 809 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
810 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
811}
812
0ccd76d4 813static int
70a3341a 814omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 815{
816 if (data->flags & MMC_DATA_WRITE)
817 return DMA_TO_DEVICE;
818 else
819 return DMA_FROM_DEVICE;
820}
821
c5c98927
RK		 822static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
823 struct mmc_data *data)
824{
825 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
826}
827
b417577d
AH		 828static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
829{
830 int dma_ch;
31463b14 831 unsigned long flags;
b417577d 832
31463b14 833 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 834 host->req_in_progress = 0;
835 dma_ch = host->dma_ch;
31463b14 836 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 837
838 omap_hsmmc_disable_irq(host);
839 /* Do not complete the request if DMA is still in progress */
840 if (mrq->data && host->use_dma && dma_ch != -1)
841 return;
842 host->mrq = NULL;
843 mmc_request_done(host->mmc, mrq);
844}
845
a45c6cb8
MC		 846/*
847 * Notify the transfer complete to MMC core
848 */
849static void
70a3341a 850omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 851{
4a694dc9
AH		 852 if (!data) {
853 struct mmc_request *mrq = host->mrq;
854
23050103
AH		 855 /* TC before CC from CMD6 - don't know why, but it happens */
856 if (host->cmd && host->cmd->opcode == 6 &&
857 host->response_busy) {
858 host->response_busy = 0;
859 return;
860 }
861
b417577d 862 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 863 return;
864 }
865
a45c6cb8
MC		 866 host->data = NULL;
867
a45c6cb8
MC		 868 if (!data->error)
869 data->bytes_xfered += data->blocks * (data->blksz);
870 else
871 data->bytes_xfered = 0;
872
fe852273 873 if (!data->stop) {
b417577d 874 omap_hsmmc_request_done(host, data->mrq);
fe852273 875 return;
a45c6cb8 876 }
fe852273 877 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 878}
879
880/*
881 * Notify the core about command completion
882 */
883static void
70a3341a 884omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 885{
886 host->cmd = NULL;
887
888 if (cmd->flags & MMC_RSP_PRESENT) {
889 if (cmd->flags & MMC_RSP_136) {
890 /* response type 2 */
891 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
892 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
893 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
894 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
895 } else {
896 /* response types 1, 1b, 3, 4, 5, 6 */
897 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
898 }
899 }
b417577d
AH		 900 if ((host->data == NULL && !host->response_busy) || cmd->error)
901 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 902}
903
904/*
905 * DMA clean up for command errors
906 */
70a3341a 907static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 908{
b417577d 909 int dma_ch;
31463b14 910 unsigned long flags;
b417577d 911
82788ff5 912 host->data->error = errno;
a45c6cb8 913
31463b14 914 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 915 dma_ch = host->dma_ch;
916 host->dma_ch = -1;
31463b14 917 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 918
919 if (host->use_dma && dma_ch != -1) {
c5c98927
RK		 920 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
921
922 dmaengine_terminate_all(chan);
923 dma_unmap_sg(chan->device->dev,
924 host->data->sg, host->data->sg_len,
70a3341a 925 omap_hsmmc_get_dma_dir(host, host->data));
c5c98927 926
053bf34f 927 host->data->host_cookie = 0;
a45c6cb8
MC		 928 }
929 host->data = NULL;
a45c6cb8
MC		 930}
931
932/*
933 * Readable error output
934 */
935#ifdef CONFIG_MMC_DEBUG
699b958b 936static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 937{
938 /* --- means reserved bit without definition at documentation */
70a3341a 939 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 940 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
941 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
942 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
943 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 944 };
945 char res[256];
946 char *buf = res;
947 int len, i;
948
949 len = sprintf(buf, "MMC IRQ 0x%x :", status);
950 buf += len;
951
70a3341a 952 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 953 if (status & (1 << i)) {
70a3341a 954 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 955 buf += len;
956 }
957
8986d31b 958 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
a45c6cb8 959}
699b958b
AH		 960#else
961static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
962 u32 status)
963{
964}
a45c6cb8
MC		 965#endif /* CONFIG_MMC_DEBUG */
966
3ebf74b1
JP		 967/*
968 * MMC controller internal state machines reset
969 *
970 * Used to reset command or data internal state machines, using respectively
971 * SRC or SRD bit of SYSCTL register
972 * Can be called from interrupt context
973 */
70a3341a
DK		 974static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
975 unsigned long bit)
3ebf74b1
JP		 976{
977 unsigned long i = 0;
978 unsigned long limit = (loops_per_jiffy *
979 msecs_to_jiffies(MMC_TIMEOUT_MS));
980
981 OMAP_HSMMC_WRITE(host->base, SYSCTL,
982 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
983
07ad64b6
MC		 984 /*
985 * OMAP4 ES2 and greater has an updated reset logic.
986 * Monitor a 0->1 transition first
987 */
988 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 989 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 990 && (i++ < limit))
991 cpu_relax();
992 }
993 i = 0;
994
3ebf74b1
JP		 995 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
996 (i++ < limit))
997 cpu_relax();
998
999 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1000 dev_err(mmc_dev(host->mmc),
1001 "Timeout waiting on controller reset in %s\n",
1002 __func__);
1003}
a45c6cb8 1004
25e1897b
B		 1005static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1006 int err, int end_cmd)
ae4bf788 1007{
25e1897b 1008 if (end_cmd) {
94d4f272 1009 omap_hsmmc_reset_controller_fsm(host, SRC);
25e1897b
B		 1010 if (host->cmd)
1011 host->cmd->error = err;
1012 }
ae4bf788
V		 1013
1014 if (host->data) {
1015 omap_hsmmc_reset_controller_fsm(host, SRD);
1016 omap_hsmmc_dma_cleanup(host, err);
dc7745bd
B		 1017 } else if (host->mrq && host->mrq->cmd)
1018 host->mrq->cmd->error = err;
ae4bf788
V		 1019}
1020
b417577d 1021static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1022{
a45c6cb8 1023 struct mmc_data *data;
b417577d
AH		 1024 int end_cmd = 0, end_trans = 0;
1025
a45c6cb8 1026 data = host->data;
8986d31b 1027 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
a45c6cb8 1028
a7e96879 1029 if (status & ERR_EN) {
699b958b 1030 omap_hsmmc_dbg_report_irq(host, status);
25e1897b 1031
a7e96879 1032 if (status & (CTO_EN | CCRC_EN))
25e1897b 1033 end_cmd = 1;
a7e96879 1034 if (status & (CTO_EN | DTO_EN))
25e1897b 1035 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
a7e96879 1036 else if (status & (CCRC_EN | DCRC_EN))
25e1897b 1037 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
ae4bf788 1038
ae4bf788 1039 if (host->data || host->response_busy) {
25e1897b 1040 end_trans = !end_cmd;
ae4bf788 1041 host->response_busy = 0;
a45c6cb8
MC		 1042 }
1043 }
1044
a7e96879 1045 if (end_cmd || ((status & CC_EN) && host->cmd))
70a3341a 1046 omap_hsmmc_cmd_done(host, host->cmd);
a7e96879 1047 if ((end_trans || (status & TC_EN)) && host->mrq)
70a3341a 1048 omap_hsmmc_xfer_done(host, data);
b417577d 1049}
a45c6cb8 1050
b417577d
AH		 1051/*
1052 * MMC controller IRQ handler
1053 */
1054static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1055{
1056 struct omap_hsmmc_host *host = dev_id;
1057 int status;
1058
1059 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1060 while (status & INT_EN_MASK && host->req_in_progress) {
b417577d 1061 omap_hsmmc_do_irq(host, status);
1f6b9fa4 1062
b417577d 1063 /* Flush posted write */
1f6b9fa4 1064 OMAP_HSMMC_WRITE(host->base, STAT, status);
b417577d 1065 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1066 }
4dffd7a2 1067
a45c6cb8
MC		 1068 return IRQ_HANDLED;
1069}
1070
70a3341a 1071static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1072{
1073 unsigned long i;
1074
1075 OMAP_HSMMC_WRITE(host->base, HCTL,
1076 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1077 for (i = 0; i < loops_per_jiffy; i++) {
1078 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1079 break;
1080 cpu_relax();
1081 }
1082}
1083
a45c6cb8 1084/*
eb250826
DB		 1085 * Switch MMC interface voltage ... only relevant for MMC1.
1086 *
1087 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1088 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1089 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1090 */
70a3341a 1091static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1092{
1093 u32 reg_val = 0;
1094 int ret;
1095
1096 /* Disable the clocks */
fa4aa2d4 1097 pm_runtime_put_sync(host->dev);
cd03d9a8 1098 if (host->dbclk)
94c18149 1099 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1100
1101 /* Turn the power off */
1102 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1103
1104 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1105 if (!ret)
1106 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1107 vdd);
fa4aa2d4 1108 pm_runtime_get_sync(host->dev);
cd03d9a8 1109 if (host->dbclk)
94c18149 1110 clk_prepare_enable(host->dbclk);
2bec0893 1111
a45c6cb8
MC		 1112 if (ret != 0)
1113 goto err;
1114
a45c6cb8
MC		 1115 OMAP_HSMMC_WRITE(host->base, HCTL,
1116 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1117 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1118
a45c6cb8
MC		 1119 /*
1120 * If a MMC dual voltage card is detected, the set_ios fn calls
1121 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1122 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1123 *
eb250826
DB		 1124 * Cope with a bit of slop in the range ... per data sheets:
1125 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1126 * but recommended values are 1.71V to 1.89V
1127 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1128 * but recommended values are 2.7V to 3.3V
1129 *
1130 * Board setup code shouldn't permit anything very out-of-range.
1131 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1132 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1133 */
eb250826 1134 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1135 reg_val |= SDVS18;
eb250826
DB		 1136 else
1137 reg_val |= SDVS30;
a45c6cb8
MC		 1138
1139 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1140 set_sd_bus_power(host);
a45c6cb8
MC		 1141
1142 return 0;
1143err:
b1e056ae 1144 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
a45c6cb8
MC		 1145 return ret;
1146}
1147
b62f6228
AH		 1148/* Protect the card while the cover is open */
1149static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1150{
1151 if (!mmc_slot(host).get_cover_state)
1152 return;
1153
1154 host->reqs_blocked = 0;
1155 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1156 if (host->protect_card) {
2cecdf00 1157 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1158 "card is now accessible\n",
1159 mmc_hostname(host->mmc));
1160 host->protect_card = 0;
1161 }
1162 } else {
1163 if (!host->protect_card) {
2cecdf00 1164 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1165 "card is now inaccessible\n",
1166 mmc_hostname(host->mmc));
1167 host->protect_card = 1;
1168 }
1169 }
1170}
1171
a45c6cb8 1172/*
7efab4f3 1173 * irq handler to notify the core about card insertion/removal
a45c6cb8 1174 */
7efab4f3 1175static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1176{
7efab4f3 1177 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1178 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1179 int carddetect;
1180
1181 if (host->suspended)
7efab4f3 1182 return IRQ_HANDLED;
a6b2240d
AH		 1183
1184 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1185
191d1f1d 1186 if (slot->card_detect)
db0fefc5 1187 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1188 else {
1189 omap_hsmmc_protect_card(host);
a6b2240d 1190 carddetect = -ENOSYS;
b62f6228 1191 }
a45c6cb8 1192
cdeebadd 1193 if (carddetect)
a45c6cb8 1194 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1195 else
a45c6cb8 1196 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1197 return IRQ_HANDLED;
1198}
1199
c5c98927 1200static void omap_hsmmc_dma_callback(void *param)
a45c6cb8 1201{
c5c98927
RK		 1202 struct omap_hsmmc_host *host = param;
1203 struct dma_chan *chan;
770d7432 1204 struct mmc_data *data;
c5c98927 1205 int req_in_progress;
a45c6cb8 1206
c5c98927 1207 spin_lock_irq(&host->irq_lock);
b417577d 1208 if (host->dma_ch < 0) {
c5c98927 1209 spin_unlock_irq(&host->irq_lock);
a45c6cb8 1210 return;
b417577d 1211 }
a45c6cb8 1212
770d7432 1213 data = host->mrq->data;
c5c98927 1214 chan = omap_hsmmc_get_dma_chan(host, data);
9782aff8 1215 if (!data->host_cookie)
c5c98927
RK		 1216 dma_unmap_sg(chan->device->dev,
1217 data->sg, data->sg_len,
9782aff8 1218 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1219
1220 req_in_progress = host->req_in_progress;
a45c6cb8 1221 host->dma_ch = -1;
c5c98927 1222 spin_unlock_irq(&host->irq_lock);
b417577d
AH		 1223
1224 /* If DMA has finished after TC, complete the request */
1225 if (!req_in_progress) {
1226 struct mmc_request *mrq = host->mrq;
1227
1228 host->mrq = NULL;
1229 mmc_request_done(host->mmc, mrq);
1230 }
a45c6cb8
MC		 1231}
1232
9782aff8
PF		 1233static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1234 struct mmc_data *data,
c5c98927 1235 struct omap_hsmmc_next *next,
26b88520 1236 struct dma_chan *chan)
9782aff8
PF		 1237{
1238 int dma_len;
1239
1240 if (!next && data->host_cookie &&
1241 data->host_cookie != host->next_data.cookie) {
2cecdf00 1242 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1243 " host->next_data.cookie %d\n",
1244 __func__, data->host_cookie, host->next_data.cookie);
1245 data->host_cookie = 0;
1246 }
1247
1248 /* Check if next job is already prepared */
1249 if (next ||
1250 (!next && data->host_cookie != host->next_data.cookie)) {
26b88520 1251 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
9782aff8
PF		 1252 omap_hsmmc_get_dma_dir(host, data));
1253
1254 } else {
1255 dma_len = host->next_data.dma_len;
1256 host->next_data.dma_len = 0;
1257 }
1258
1259
1260 if (dma_len == 0)
1261 return -EINVAL;
1262
1263 if (next) {
1264 next->dma_len = dma_len;
1265 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1266 } else
1267 host->dma_len = dma_len;
1268
1269 return 0;
1270}
1271
a45c6cb8
MC		 1272/*
1273 * Routine to configure and start DMA for the MMC card
1274 */
70a3341a
DK		 1275static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1276 struct mmc_request *req)
a45c6cb8 1277{
26b88520
RK		 1278 struct dma_slave_config cfg;
1279 struct dma_async_tx_descriptor *tx;
1280 int ret = 0, i;
a45c6cb8 1281 struct mmc_data *data = req->data;
c5c98927 1282 struct dma_chan *chan;
a45c6cb8 1283
0ccd76d4 1284 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1285 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1286 struct scatterlist *sgl;
1287
1288 sgl = data->sg + i;
1289 if (sgl->length % data->blksz)
1290 return -EINVAL;
1291 }
1292 if ((data->blksz % 4) != 0)
1293 /* REVISIT: The MMC buffer increments only when MSB is written.
1294 * Return error for blksz which is non multiple of four.
1295 */
1296 return -EINVAL;
1297
b417577d 1298 BUG_ON(host->dma_ch != -1);
a45c6cb8 1299
c5c98927 1300 chan = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1301
26b88520
RK		 1302 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1303 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1304 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1305 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1306 cfg.src_maxburst = data->blksz / 4;
1307 cfg.dst_maxburst = data->blksz / 4;
c5c98927 1308
26b88520
RK		 1309 ret = dmaengine_slave_config(chan, &cfg);
1310 if (ret)
a45c6cb8 1311 return ret;
c5c98927 1312
26b88520 1313 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
9782aff8
PF		 1314 if (ret)
1315 return ret;
a45c6cb8 1316
26b88520
RK		 1317 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1318 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1319 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1320 if (!tx) {
1321 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1322 /* FIXME: cleanup */
1323 return -1;
1324 }
a45c6cb8 1325
26b88520
RK		 1326 tx->callback = omap_hsmmc_dma_callback;
1327 tx->callback_param = host;
a45c6cb8 1328
26b88520
RK		 1329 /* Does not fail */
1330 dmaengine_submit(tx);
c5c98927 1331
26b88520 1332 host->dma_ch = 1;
c5c98927 1333
26b88520 1334 dma_async_issue_pending(chan);
a45c6cb8 1335
a45c6cb8
MC		 1336 return 0;
1337}
1338
70a3341a 1339static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1340 unsigned int timeout_ns,
1341 unsigned int timeout_clks)
a45c6cb8
MC		 1342{
1343 unsigned int timeout, cycle_ns;
1344 uint32_t reg, clkd, dto = 0;
1345
1346 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1347 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1348 if (clkd == 0)
1349 clkd = 1;
1350
1351 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1352 timeout = timeout_ns / cycle_ns;
1353 timeout += timeout_clks;
a45c6cb8
MC		 1354 if (timeout) {
1355 while ((timeout & 0x80000000) == 0) {
1356 dto += 1;
1357 timeout <<= 1;
1358 }
1359 dto = 31 - dto;
1360 timeout <<= 1;
1361 if (timeout && dto)
1362 dto += 1;
1363 if (dto >= 13)
1364 dto -= 13;
1365 else
1366 dto = 0;
1367 if (dto > 14)
1368 dto = 14;
1369 }
1370
1371 reg &= ~DTO_MASK;
1372 reg |= dto << DTO_SHIFT;
1373 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1374}
1375
1376/*
1377 * Configure block length for MMC/SD cards and initiate the transfer.
1378 */
1379static int
70a3341a 1380omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1381{
1382 int ret;
1383 host->data = req->data;
1384
1385 if (req->data == NULL) {
a45c6cb8 1386 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1387 /*
1388 * Set an arbitrary 100ms data timeout for commands with
1389 * busy signal.
1390 */
1391 if (req->cmd->flags & MMC_RSP_BUSY)
1392 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1393 return 0;
1394 }
1395
1396 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1397 | (req->data->blocks << 16));
e2bf08d6 1398 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1399
a45c6cb8 1400 if (host->use_dma) {
70a3341a 1401 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8 1402 if (ret != 0) {
b1e056ae 1403 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
a45c6cb8
MC		 1404 return ret;
1405 }
1406 }
1407 return 0;
1408}
1409
9782aff8
PF		 1410static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1411 int err)
1412{
1413 struct omap_hsmmc_host *host = mmc_priv(mmc);
1414 struct mmc_data *data = mrq->data;
1415
26b88520 1416 if (host->use_dma && data->host_cookie) {
c5c98927 1417 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1418
26b88520
RK		 1419 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1420 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1421 data->host_cookie = 0;
1422 }
1423}
1424
1425static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1426 bool is_first_req)
1427{
1428 struct omap_hsmmc_host *host = mmc_priv(mmc);
1429
1430 if (mrq->data->host_cookie) {
1431 mrq->data->host_cookie = 0;
1432 return ;
1433 }
1434
c5c98927
RK		 1435 if (host->use_dma) {
1436 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
c5c98927 1437
9782aff8 1438 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
26b88520 1439 &host->next_data, c))
9782aff8 1440 mrq->data->host_cookie = 0;
c5c98927 1441 }
9782aff8
PF		 1442}
1443
a45c6cb8
MC		 1444/*
1445 * Request function. for read/write operation
1446 */
70a3341a 1447static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1448{
70a3341a 1449 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1450 int err;
a45c6cb8 1451
b417577d
AH		 1452 BUG_ON(host->req_in_progress);
1453 BUG_ON(host->dma_ch != -1);
1454 if (host->protect_card) {
1455 if (host->reqs_blocked < 3) {
1456 /*
1457 * Ensure the controller is left in a consistent
1458 * state by resetting the command and data state
1459 * machines.
1460 */
1461 omap_hsmmc_reset_controller_fsm(host, SRD);
1462 omap_hsmmc_reset_controller_fsm(host, SRC);
1463 host->reqs_blocked += 1;
1464 }
1465 req->cmd->error = -EBADF;
1466 if (req->data)
1467 req->data->error = -EBADF;
1468 req->cmd->retries = 0;
1469 mmc_request_done(mmc, req);
1470 return;
1471 } else if (host->reqs_blocked)
1472 host->reqs_blocked = 0;
a45c6cb8
MC		 1473 WARN_ON(host->mrq != NULL);
1474 host->mrq = req;
70a3341a 1475 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1476 if (err) {
1477 req->cmd->error = err;
1478 if (req->data)
1479 req->data->error = err;
1480 host->mrq = NULL;
1481 mmc_request_done(mmc, req);
1482 return;
1483 }
1484
70a3341a 1485 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1486}
1487
a45c6cb8 1488/* Routine to configure clock values. Exposed API to core */
70a3341a 1489static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1490{
70a3341a 1491 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1492 int do_send_init_stream = 0;
a45c6cb8 1493
fa4aa2d4 1494 pm_runtime_get_sync(host->dev);
5e2ea617 1495
a3621465
AH		 1496 if (ios->power_mode != host->power_mode) {
1497 switch (ios->power_mode) {
1498 case MMC_POWER_OFF:
1499 mmc_slot(host).set_power(host->dev, host->slot_id,
1500 0, 0);
1501 break;
1502 case MMC_POWER_UP:
1503 mmc_slot(host).set_power(host->dev, host->slot_id,
1504 1, ios->vdd);
1505 break;
1506 case MMC_POWER_ON:
1507 do_send_init_stream = 1;
1508 break;
1509 }
1510 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1511 }
1512
dd498eff
DK		 1513 /* FIXME: set registers based only on changes to ios */
1514
3796fb8a 1515 omap_hsmmc_set_bus_width(host);
a45c6cb8 1516
4621d5f8 1517 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1518 /* Only MMC1 can interface at 3V without some flavor
1519 * of external transceiver; but they all handle 1.8V.
1520 */
a45c6cb8 1521 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1f84b71b
RN		 1522 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1523 /*
1524 * With pbias cell programming missing, this
1525 * can't be allowed when booting with device
1526 * tree.
1527 */
4d048f91 1528 !host->dev->of_node) {
a45c6cb8
MC		 1529 /*
1530 * The mmc_select_voltage fn of the core does
1531 * not seem to set the power_mode to
1532 * MMC_POWER_UP upon recalculating the voltage.
1533 * vdd 1.8v.
1534 */
70a3341a
DK		 1535 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1536 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1537 "Switch operation failed\n");
1538 }
1539 }
1540
5934df2f 1541 omap_hsmmc_set_clock(host);
a45c6cb8 1542
a3621465 1543 if (do_send_init_stream)
a45c6cb8
MC		 1544 send_init_stream(host);
1545
3796fb8a 1546 omap_hsmmc_set_bus_mode(host);
5e2ea617 1547
fa4aa2d4 1548 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1549}
1550
1551static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1552{
70a3341a 1553 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1554
191d1f1d 1555 if (!mmc_slot(host).card_detect)
a45c6cb8 1556 return -ENOSYS;
db0fefc5 1557 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1558}
1559
1560static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1561{
70a3341a 1562 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1563
191d1f1d 1564 if (!mmc_slot(host).get_ro)
a45c6cb8 1565 return -ENOSYS;
191d1f1d 1566 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1567}
1568
4816858c
GI		 1569static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1570{
1571 struct omap_hsmmc_host *host = mmc_priv(mmc);
1572
1573 if (mmc_slot(host).init_card)
1574 mmc_slot(host).init_card(card);
1575}
1576
70a3341a 1577static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1578{
1579 u32 hctl, capa, value;
1580
1581 /* Only MMC1 supports 3.0V */
4621d5f8 1582 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1583 hctl = SDVS30;
1584 capa = VS30 | VS18;
1585 } else {
1586 hctl = SDVS18;
1587 capa = VS18;
1588 }
1589
1590 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1591 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1592
1593 value = OMAP_HSMMC_READ(host->base, CAPA);
1594 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1595
1b331e69 1596 /* Set SD bus power bit */
e13bb300 1597 set_sd_bus_power(host);
1b331e69
KK		 1598}
1599
70a3341a 1600static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1601{
70a3341a 1602 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1603
fa4aa2d4
B		 1604 pm_runtime_get_sync(host->dev);
1605
dd498eff
DK		 1606 return 0;
1607}
1608
907d2e7c 1609static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
dd498eff 1610{
70a3341a 1611 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1612
fa4aa2d4
B		 1613 pm_runtime_mark_last_busy(host->dev);
1614 pm_runtime_put_autosuspend(host->dev);
1615
dd498eff
DK		 1616 return 0;
1617}
1618
70a3341a
DK		 1619static const struct mmc_host_ops omap_hsmmc_ops = {
1620 .enable = omap_hsmmc_enable_fclk,
1621 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1622 .post_req = omap_hsmmc_post_req,
1623 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1624 .request = omap_hsmmc_request,
1625 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1626 .get_cd = omap_hsmmc_get_cd,
1627 .get_ro = omap_hsmmc_get_ro,
4816858c 1628 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1629 /* NYET -- enable_sdio_irq */
1630};
1631
d900f712
DK		 1632#ifdef CONFIG_DEBUG_FS
1633
70a3341a 1634static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1635{
1636 struct mmc_host *mmc = s->private;
70a3341a 1637 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1638 int context_loss = 0;
1639
70a3341a
DK		 1640 if (host->pdata->get_context_loss_count)
1641 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1642
907d2e7c
AH		 1643 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1644 mmc->index, host->context_loss, context_loss);
5e2ea617 1645
7a8c2cef 1646 if (host->suspended) {
dd498eff
DK		 1647 seq_printf(s, "host suspended, can't read registers\n");
1648 return 0;
1649 }
1650
fa4aa2d4 1651 pm_runtime_get_sync(host->dev);
d900f712 1652
d900f712
DK		 1653 seq_printf(s, "CON:\t\t0x%08x\n",
1654 OMAP_HSMMC_READ(host->base, CON));
1655 seq_printf(s, "HCTL:\t\t0x%08x\n",
1656 OMAP_HSMMC_READ(host->base, HCTL));
1657 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1658 OMAP_HSMMC_READ(host->base, SYSCTL));
1659 seq_printf(s, "IE:\t\t0x%08x\n",
1660 OMAP_HSMMC_READ(host->base, IE));
1661 seq_printf(s, "ISE:\t\t0x%08x\n",
1662 OMAP_HSMMC_READ(host->base, ISE));
1663 seq_printf(s, "CAPA:\t\t0x%08x\n",
1664 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1665
fa4aa2d4
B		 1666 pm_runtime_mark_last_busy(host->dev);
1667 pm_runtime_put_autosuspend(host->dev);
dd498eff 1668
d900f712
DK		 1669 return 0;
1670}
1671
70a3341a 1672static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1673{
70a3341a 1674 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1675}
1676
1677static const struct file_operations mmc_regs_fops = {
70a3341a 1678 .open = omap_hsmmc_regs_open,
d900f712
DK		 1679 .read = seq_read,
1680 .llseek = seq_lseek,
1681 .release = single_release,
1682};
1683
70a3341a 1684static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1685{
1686 if (mmc->debugfs_root)
1687 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1688 mmc, &mmc_regs_fops);
1689}
1690
1691#else
1692
70a3341a 1693static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1694{
1695}
1696
1697#endif
1698
46856a68
RN		 1699#ifdef CONFIG_OF
1700static u16 omap4_reg_offset = 0x100;
1701
1702static const struct of_device_id omap_mmc_of_match[] = {
1703 {
1704 .compatible = "ti,omap2-hsmmc",
1705 },
1706 {
1707 .compatible = "ti,omap3-hsmmc",
1708 },
1709 {
1710 .compatible = "ti,omap4-hsmmc",
1711 .data = &omap4_reg_offset,
1712 },
1713 {},
b6d085f6 1714};
46856a68
RN		 1715MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1716
1717static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1718{
1719 struct omap_mmc_platform_data *pdata;
1720 struct device_node *np = dev->of_node;
d8714e87 1721 u32 bus_width, max_freq;
46856a68
RN		 1722
1723 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1724 if (!pdata)
1725 return NULL; /* out of memory */
1726
1727 if (of_find_property(np, "ti,dual-volt", NULL))
1728 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1729
1730 /* This driver only supports 1 slot */
1731 pdata->nr_slots = 1;
1732 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1733 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1734
1735 if (of_find_property(np, "ti,non-removable", NULL)) {
1736 pdata->slots[0].nonremovable = true;
1737 pdata->slots[0].no_regulator_off_init = true;
1738 }
7f217794 1739 of_property_read_u32(np, "bus-width", &bus_width);
46856a68
RN		 1740 if (bus_width == 4)
1741 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1742 else if (bus_width == 8)
1743 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1744
1745 if (of_find_property(np, "ti,needs-special-reset", NULL))
1746 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1747
d8714e87
DM		 1748 if (!of_property_read_u32(np, "max-frequency", &max_freq))
1749 pdata->max_freq = max_freq;
1750
cd587096
HG		 1751 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1752 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1753
46856a68
RN		 1754 return pdata;
1755}
1756#else
1757static inline struct omap_mmc_platform_data
1758 *of_get_hsmmc_pdata(struct device *dev)
1759{
1760 return NULL;
1761}
1762#endif
1763
c3be1efd 1764static int omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1765{
1766 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1767 struct mmc_host *mmc;
70a3341a 1768 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1769 struct resource *res;
db0fefc5 1770 int ret, irq;
46856a68 1771 const struct of_device_id *match;
26b88520
RK		 1772 dma_cap_mask_t mask;
1773 unsigned tx_req, rx_req;
46b76035 1774 struct pinctrl *pinctrl;
46856a68
RN		 1775
1776 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1777 if (match) {
1778 pdata = of_get_hsmmc_pdata(&pdev->dev);
1779 if (match->data) {
efc9b736 1780 const u16 *offsetp = match->data;
46856a68
RN		 1781 pdata->reg_offset = *offsetp;
1782 }
1783 }
a45c6cb8
MC		 1784
1785 if (pdata == NULL) {
1786 dev_err(&pdev->dev, "Platform Data is missing\n");
1787 return -ENXIO;
1788 }
1789
1790 if (pdata->nr_slots == 0) {
1791 dev_err(&pdev->dev, "No Slots\n");
1792 return -ENXIO;
1793 }
1794
1795 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1796 irq = platform_get_irq(pdev, 0);
1797 if (res == NULL || irq < 0)
1798 return -ENXIO;
1799
984b203a 1800 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1801 if (res == NULL)
1802 return -EBUSY;
1803
db0fefc5
AH		 1804 ret = omap_hsmmc_gpio_init(pdata);
1805 if (ret)
1806 goto err;
1807
70a3341a 1808 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1809 if (!mmc) {
1810 ret = -ENOMEM;
db0fefc5 1811 goto err_alloc;
a45c6cb8
MC		 1812 }
1813
1814 host = mmc_priv(mmc);
1815 host->mmc = mmc;
1816 host->pdata = pdata;
1817 host->dev = &pdev->dev;
1818 host->use_dma = 1;
a45c6cb8
MC		 1819 host->dma_ch = -1;
1820 host->irq = irq;
a45c6cb8 1821 host->slot_id = 0;
fc307df8 1822 host->mapbase = res->start + pdata->reg_offset;
a45c6cb8 1823 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1824 host->power_mode = MMC_POWER_OFF;
9782aff8 1825 host->next_data.cookie = 1;
a45c6cb8
MC		 1826
1827 platform_set_drvdata(pdev, host);
a45c6cb8 1828
7a8c2cef 1829 mmc->ops = &omap_hsmmc_ops;
dd498eff 1830
e0eb2424
AH		 1831 /*
1832 * If regulator_disable can only put vcc_aux to sleep then there is
1833 * no off state.
1834 */
1835 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1836 mmc_slot(host).no_off = 1;
1837
d418ed87
DM		 1838 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1839
1840 if (pdata->max_freq > 0)
1841 mmc->f_max = pdata->max_freq;
1842 else
1843 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1844
4dffd7a2 1845 spin_lock_init(&host->irq_lock);
a45c6cb8 1846
6f7607cc 1847 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1848 if (IS_ERR(host->fclk)) {
1849 ret = PTR_ERR(host->fclk);
1850 host->fclk = NULL;
a45c6cb8
MC		 1851 goto err1;
1852 }
1853
9b68256c
PW		 1854 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1855 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1856 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1857 }
dd498eff 1858
fa4aa2d4
B		 1859 pm_runtime_enable(host->dev);
1860 pm_runtime_get_sync(host->dev);
1861 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1862 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1863
92a3aebf
B		 1864 omap_hsmmc_context_save(host);
1865
cd03d9a8
RN		 1866 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1867 /*
1868 * MMC can still work without debounce clock.
1869 */
1870 if (IS_ERR(host->dbclk)) {
cd03d9a8 1871 host->dbclk = NULL;
94c18149 1872 } else if (clk_prepare_enable(host->dbclk) != 0) {
cd03d9a8
RN		 1873 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1874 clk_put(host->dbclk);
1875 host->dbclk = NULL;
2bec0893 1876 }
a45c6cb8 1877
0ccd76d4
JY		 1878 /* Since we do only SG emulation, we can have as many segs
1879 * as we want. */
a36274e0 1880 mmc->max_segs = 1024;
0ccd76d4 1881
a45c6cb8
MC		 1882 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1883 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1884 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1885 mmc->max_seg_size = mmc->max_req_size;
1886
13189e78 1887 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1888 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1889
3a63833e
SG		 1890 mmc->caps |= mmc_slot(host).caps;
1891 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1892 mmc->caps |= MMC_CAP_4_BIT_DATA;
1893
191d1f1d 1894 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1895 mmc->caps |= MMC_CAP_NONREMOVABLE;
1896
6fdc75de
EP		 1897 mmc->pm_caps = mmc_slot(host).pm_caps;
1898
70a3341a 1899 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1900
b7bf773b
B		 1901 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1902 if (!res) {
1903 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
9c17d08c 1904 ret = -ENXIO;
b7bf773b
B		 1905 goto err_irq;
1906 }
26b88520 1907 tx_req = res->start;
b7bf773b
B		 1908
1909 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1910 if (!res) {
1911 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
9c17d08c 1912 ret = -ENXIO;
f3e2f1dd
GI		 1913 goto err_irq;
1914 }
26b88520 1915 rx_req = res->start;
a45c6cb8 1916
26b88520
RK		 1917 dma_cap_zero(mask);
1918 dma_cap_set(DMA_SLAVE, mask);
1919
1920 host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1921 if (!host->rx_chan) {
1922 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
04e8c7bc 1923 ret = -ENXIO;
26b88520
RK		 1924 goto err_irq;
1925 }
1926
1927 host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1928 if (!host->tx_chan) {
1929 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
04e8c7bc 1930 ret = -ENXIO;
26b88520 1931 goto err_irq;
c5c98927 1932 }
a45c6cb8
MC		 1933
1934 /* Request IRQ for MMC operations */
d9618e9f 1935 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1936 mmc_hostname(mmc), host);
1937 if (ret) {
b1e056ae 1938 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
a45c6cb8
MC		 1939 goto err_irq;
1940 }
1941
1942 if (pdata->init != NULL) {
1943 if (pdata->init(&pdev->dev) != 0) {
b1e056ae 1944 dev_err(mmc_dev(host->mmc),
70a3341a 1945 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1946 goto err_irq_cd_init;
1947 }
1948 }
db0fefc5 1949
b702b106 1950 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1951 ret = omap_hsmmc_reg_get(host);
1952 if (ret)
1953 goto err_reg;
1954 host->use_reg = 1;
1955 }
1956
b583f26d 1957 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1958
1959 /* Request IRQ for card detect */
e1a55f5e 1960 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1961 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1962 NULL,
1963 omap_hsmmc_detect,
db35f83e 1964 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
7efab4f3 1965 mmc_hostname(mmc), host);
a45c6cb8 1966 if (ret) {
b1e056ae 1967 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1968 "Unable to grab MMC CD IRQ\n");
1969 goto err_irq_cd;
1970 }
72f2e2c7 1971 pdata->suspend = omap_hsmmc_suspend_cdirq;
1972 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 1973 }
1974
b417577d 1975 omap_hsmmc_disable_irq(host);
a45c6cb8 1976
46b76035
DM		 1977 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1978 if (IS_ERR(pinctrl))
1979 dev_warn(&pdev->dev,
1980 "pins are not configured from the driver\n");
1981
b62f6228
AH		 1982 omap_hsmmc_protect_card(host);
1983
a45c6cb8
MC		 1984 mmc_add_host(mmc);
1985
191d1f1d 1986 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 1987 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1988 if (ret < 0)
1989 goto err_slot_name;
1990 }
191d1f1d 1991 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 1992 ret = device_create_file(&mmc->class_dev,
1993 &dev_attr_cover_switch);
1994 if (ret < 0)
db0fefc5 1995 goto err_slot_name;
a45c6cb8
MC		 1996 }
1997
70a3341a 1998 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 1999 pm_runtime_mark_last_busy(host->dev);
2000 pm_runtime_put_autosuspend(host->dev);
d900f712 2001
a45c6cb8
MC		 2002 return 0;
2003
a45c6cb8
MC		 2004err_slot_name:
2005 mmc_remove_host(mmc);
a45c6cb8 2006 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2007err_irq_cd:
2008 if (host->use_reg)
2009 omap_hsmmc_reg_put(host);
2010err_reg:
2011 if (host->pdata->cleanup)
2012 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2013err_irq_cd_init:
2014 free_irq(host->irq, host);
2015err_irq:
c5c98927
RK		 2016 if (host->tx_chan)
2017 dma_release_channel(host->tx_chan);
2018 if (host->rx_chan)
2019 dma_release_channel(host->rx_chan);
d59d77ed 2020 pm_runtime_put_sync(host->dev);
37f6190d 2021 pm_runtime_disable(host->dev);
a45c6cb8 2022 clk_put(host->fclk);
cd03d9a8 2023 if (host->dbclk) {
94c18149 2024 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 2025 clk_put(host->dbclk);
2026 }
a45c6cb8
MC		 2027err1:
2028 iounmap(host->base);
db0fefc5
AH		 2029 platform_set_drvdata(pdev, NULL);
2030 mmc_free_host(mmc);
2031err_alloc:
2032 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2033err:
48b332f9
RK		 2034 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2035 if (res)
2036 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2037 return ret;
2038}
2039
6e0ee714 2040static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2041{
70a3341a 2042 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2043 struct resource *res;
2044
927ce944
FB		 2045 pm_runtime_get_sync(host->dev);
2046 mmc_remove_host(host->mmc);
2047 if (host->use_reg)
2048 omap_hsmmc_reg_put(host);
2049 if (host->pdata->cleanup)
2050 host->pdata->cleanup(&pdev->dev);
2051 free_irq(host->irq, host);
2052 if (mmc_slot(host).card_detect_irq)
2053 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 2054
c5c98927
RK		 2055 if (host->tx_chan)
2056 dma_release_channel(host->tx_chan);
2057 if (host->rx_chan)
2058 dma_release_channel(host->rx_chan);
2059
927ce944
FB		 2060 pm_runtime_put_sync(host->dev);
2061 pm_runtime_disable(host->dev);
2062 clk_put(host->fclk);
cd03d9a8 2063 if (host->dbclk) {
94c18149 2064 clk_disable_unprepare(host->dbclk);
927ce944 2065 clk_put(host->dbclk);
a45c6cb8
MC		 2066 }
2067
9ea28ecb 2068 omap_hsmmc_gpio_free(host->pdata);
927ce944 2069 iounmap(host->base);
9d1f0286 2070 mmc_free_host(host->mmc);
927ce944 2071
a45c6cb8
MC		 2072 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2073 if (res)
984b203a 2074 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2075 platform_set_drvdata(pdev, NULL);
2076
2077 return 0;
2078}
2079
2080#ifdef CONFIG_PM
a48ce884
FB		 2081static int omap_hsmmc_prepare(struct device *dev)
2082{
2083 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2084
2085 if (host->pdata->suspend)
2086 return host->pdata->suspend(dev, host->slot_id);
2087
2088 return 0;
2089}
2090
2091static void omap_hsmmc_complete(struct device *dev)
2092{
2093 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2094
2095 if (host->pdata->resume)
2096 host->pdata->resume(dev, host->slot_id);
2097
2098}
2099
a791daa1 2100static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2101{
2102 int ret = 0;
927ce944 2103 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2104
927ce944 2105 if (!host)
a45c6cb8
MC		 2106 return 0;
2107
927ce944
FB		 2108 if (host && host->suspended)
2109 return 0;
fa4aa2d4 2110
927ce944
FB		 2111 pm_runtime_get_sync(host->dev);
2112 host->suspended = 1;
927ce944 2113 ret = mmc_suspend_host(host->mmc);
31f9d463 2114
927ce944
FB		 2115 if (ret) {
2116 host->suspended = 0;
927ce944
FB		 2117 goto err;
2118 }
31f9d463 2119
927ce944
FB		 2120 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2121 omap_hsmmc_disable_irq(host);
2122 OMAP_HSMMC_WRITE(host->base, HCTL,
2123 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2124 }
927ce944 2125
cd03d9a8 2126 if (host->dbclk)
94c18149 2127 clk_disable_unprepare(host->dbclk);
31f9d463
EP		 2128err:
2129 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2130 return ret;
2131}
2132
2133/* Routine to resume the MMC device */
a791daa1 2134static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2135{
2136 int ret = 0;
927ce944
FB		 2137 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2138
2139 if (!host)
2140 return 0;
a45c6cb8
MC		 2141
2142 if (host && !host->suspended)
2143 return 0;
2144
927ce944 2145 pm_runtime_get_sync(host->dev);
11dd62a7 2146
cd03d9a8 2147 if (host->dbclk)
94c18149 2148 clk_prepare_enable(host->dbclk);
2bec0893 2149
927ce944
FB		 2150 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2151 omap_hsmmc_conf_bus_power(host);
1b331e69 2152
927ce944 2153 omap_hsmmc_protect_card(host);
b62f6228 2154
927ce944
FB		 2155 /* Notify the core to resume the host */
2156 ret = mmc_resume_host(host->mmc);
2157 if (ret == 0)
2158 host->suspended = 0;
fa4aa2d4 2159
927ce944
FB		 2160 pm_runtime_mark_last_busy(host->dev);
2161 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2162
2163 return ret;
2164
a45c6cb8
MC		 2165}
2166
2167#else
a48ce884
FB		 2168#define omap_hsmmc_prepare NULL
2169#define omap_hsmmc_complete NULL
70a3341a 2170#define omap_hsmmc_suspend NULL
a48ce884 2171#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2172#endif
2173
fa4aa2d4
B		 2174static int omap_hsmmc_runtime_suspend(struct device *dev)
2175{
2176 struct omap_hsmmc_host *host;
2177
2178 host = platform_get_drvdata(to_platform_device(dev));
2179 omap_hsmmc_context_save(host);
927ce944 2180 dev_dbg(dev, "disabled\n");
fa4aa2d4
B		 2181
2182 return 0;
2183}
2184
2185static int omap_hsmmc_runtime_resume(struct device *dev)
2186{
2187 struct omap_hsmmc_host *host;
2188
2189 host = platform_get_drvdata(to_platform_device(dev));
2190 omap_hsmmc_context_restore(host);
927ce944 2191 dev_dbg(dev, "enabled\n");
fa4aa2d4
B		 2192
2193 return 0;
2194}
2195
a791daa1 2196static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2197 .suspend = omap_hsmmc_suspend,
2198 .resume = omap_hsmmc_resume,
a48ce884
FB		 2199 .prepare = omap_hsmmc_prepare,
2200 .complete = omap_hsmmc_complete,
fa4aa2d4
B		 2201 .runtime_suspend = omap_hsmmc_runtime_suspend,
2202 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2203};
2204
2205static struct platform_driver omap_hsmmc_driver = {
efa25fd3 2206 .probe = omap_hsmmc_probe,
0433c143 2207 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2208 .driver = {
2209 .name = DRIVER_NAME,
2210 .owner = THIS_MODULE,
a791daa1 2211 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2212 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2213 },
2214};
2215
b796450b 2216module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2217MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2218MODULE_LICENSE("GPL");
2219MODULE_ALIAS("platform:" DRIVER_NAME);
2220MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)