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mmc: omap_hsmmc: Enable HSPE bit for high speed cards
[linux-2.6-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712 21#include <linux/debugfs.h>
c5c98927 22#include <linux/dmaengine.h>
d900f712 23#include <linux/seq_file.h>
a45c6cb8
MC		 24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
a45c6cb8
MC		 28#include <linux/timer.h>
29#include <linux/clk.h>
46856a68
RN		 30#include <linux/of.h>
31#include <linux/of_gpio.h>
32#include <linux/of_device.h>
3451c067 33#include <linux/omap-dma.h>
a45c6cb8 34#include <linux/mmc/host.h>
13189e78 35#include <linux/mmc/core.h>
93caf8e6 36#include <linux/mmc/mmc.h>
a45c6cb8 37#include <linux/io.h>
db0fefc5
AH		 38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
46b76035 40#include <linux/pinctrl/consumer.h>
fa4aa2d4 41#include <linux/pm_runtime.h>
a45c6cb8 42#include <mach/hardware.h>
ce491cf8
TL		 43#include <plat/mmc.h>
44#include <plat/cpu.h>
a45c6cb8
MC		 45
46/* OMAP HSMMC Host Controller Registers */
11dd62a7 47#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 48#define OMAP_HSMMC_CON 0x002C
49#define OMAP_HSMMC_BLK 0x0104
50#define OMAP_HSMMC_ARG 0x0108
51#define OMAP_HSMMC_CMD 0x010C
52#define OMAP_HSMMC_RSP10 0x0110
53#define OMAP_HSMMC_RSP32 0x0114
54#define OMAP_HSMMC_RSP54 0x0118
55#define OMAP_HSMMC_RSP76 0x011C
56#define OMAP_HSMMC_DATA 0x0120
57#define OMAP_HSMMC_HCTL 0x0128
58#define OMAP_HSMMC_SYSCTL 0x012C
59#define OMAP_HSMMC_STAT 0x0130
60#define OMAP_HSMMC_IE 0x0134
61#define OMAP_HSMMC_ISE 0x0138
62#define OMAP_HSMMC_CAPA 0x0140
63
64#define VS18 (1 << 26)
65#define VS30 (1 << 25)
cd587096 66#define HSS (1 << 21)
a45c6cb8
MC		 67#define SDVS18 (0x5 << 9)
68#define SDVS30 (0x6 << 9)
eb250826 69#define SDVS33 (0x7 << 9)
1b331e69 70#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 71#define SDVSCLR 0xFFFFF1FF
72#define SDVSDET 0x00000400
73#define AUTOIDLE 0x1
74#define SDBP (1 << 8)
75#define DTO 0xe
76#define ICE 0x1
77#define ICS 0x2
78#define CEN (1 << 2)
79#define CLKD_MASK 0x0000FFC0
80#define CLKD_SHIFT 6
81#define DTO_MASK 0x000F0000
82#define DTO_SHIFT 16
83#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 84#define BWR_ENABLE (1 << 4)
85#define BRR_ENABLE (1 << 5)
93caf8e6 86#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 87#define INIT_STREAM (1 << 1)
88#define DP_SELECT (1 << 21)
89#define DDIR (1 << 4)
90#define DMA_EN 0x1
91#define MSBS (1 << 5)
92#define BCE (1 << 1)
93#define FOUR_BIT (1 << 1)
cd587096 94#define HSPE (1 << 2)
03b5d924 95#define DDR (1 << 19)
73153010 96#define DW8 (1 << 5)
a45c6cb8
MC		 97#define CC 0x1
98#define TC 0x02
99#define OD 0x1
100#define ERR (1 << 15)
101#define CMD_TIMEOUT (1 << 16)
102#define DATA_TIMEOUT (1 << 20)
103#define CMD_CRC (1 << 17)
104#define DATA_CRC (1 << 21)
105#define CARD_ERR (1 << 28)
106#define STAT_CLEAR 0xFFFFFFFF
107#define INIT_STREAM_CMD 0x00000000
108#define DUAL_VOLT_OCR_BIT 7
109#define SRC (1 << 25)
110#define SRD (1 << 26)
11dd62a7
DK		 111#define SOFTRESET (1 << 1)
112#define RESETDONE (1 << 0)
a45c6cb8 113
fa4aa2d4 114#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8 115#define MMC_TIMEOUT_MS 20
6b206efe
AS		 116#define OMAP_MMC_MIN_CLOCK 400000
117#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 118#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 119
120/*
121 * One controller can have multiple slots, like on some omap boards using
122 * omap.c controller driver. Luckily this is not currently done on any known
123 * omap_hsmmc.c device.
124 */
125#define mmc_slot(host) (host->pdata->slots[host->slot_id])
126
127/*
128 * MMC Host controller read/write API's
129 */
130#define OMAP_HSMMC_READ(base, reg) \
131 __raw_readl((base) + OMAP_HSMMC_##reg)
132
133#define OMAP_HSMMC_WRITE(base, reg, val) \
134 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
135
9782aff8
PF		 136struct omap_hsmmc_next {
137 unsigned int dma_len;
138 s32 cookie;
139};
140
70a3341a 141struct omap_hsmmc_host {
a45c6cb8
MC		 142 struct device *dev;
143 struct mmc_host *mmc;
144 struct mmc_request *mrq;
145 struct mmc_command *cmd;
146 struct mmc_data *data;
147 struct clk *fclk;
a45c6cb8 148 struct clk *dbclk;
db0fefc5
AH		 149 /*
150 * vcc == configured supply
151 * vcc_aux == optional
152 * - MMC1, supply for DAT4..DAT7
153 * - MMC2/MMC2, external level shifter voltage supply, for
154 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
155 */
156 struct regulator *vcc;
157 struct regulator *vcc_aux;
a45c6cb8
MC		 158 void __iomem *base;
159 resource_size_t mapbase;
4dffd7a2 160 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 161 unsigned int dma_len;
0ccd76d4 162 unsigned int dma_sg_idx;
a45c6cb8 163 unsigned char bus_mode;
a3621465 164 unsigned char power_mode;
a45c6cb8
MC		 165 int suspended;
166 int irq;
a45c6cb8 167 int use_dma, dma_ch;
c5c98927
RK		 168 struct dma_chan *tx_chan;
169 struct dma_chan *rx_chan;
a45c6cb8 170 int slot_id;
4a694dc9 171 int response_busy;
11dd62a7 172 int context_loss;
b62f6228
AH		 173 int protect_card;
174 int reqs_blocked;
db0fefc5 175 int use_reg;
b417577d 176 int req_in_progress;
9782aff8 177 struct omap_hsmmc_next next_data;
11dd62a7 178
a45c6cb8
MC		 179 struct omap_mmc_platform_data *pdata;
180};
181
db0fefc5
AH		 182static int omap_hsmmc_card_detect(struct device *dev, int slot)
183{
9ea28ecb
B		 184 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
185 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 186
187 /* NOTE: assumes card detect signal is active-low */
188 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
189}
190
191static int omap_hsmmc_get_wp(struct device *dev, int slot)
192{
9ea28ecb
B		 193 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
194 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 195
196 /* NOTE: assumes write protect signal is active-high */
197 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
198}
199
200static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
201{
9ea28ecb
B		 202 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
203 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 204
205 /* NOTE: assumes card detect signal is active-low */
206 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
207}
208
209#ifdef CONFIG_PM
210
211static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
212{
9ea28ecb
B		 213 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
214 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 215
216 disable_irq(mmc->slots[0].card_detect_irq);
217 return 0;
218}
219
220static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
221{
9ea28ecb
B		 222 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
223 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 224
225 enable_irq(mmc->slots[0].card_detect_irq);
226 return 0;
227}
228
229#else
230
231#define omap_hsmmc_suspend_cdirq NULL
232#define omap_hsmmc_resume_cdirq NULL
233
234#endif
235
b702b106
AH		 236#ifdef CONFIG_REGULATOR
237
69b07ece 238static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 239 int vdd)
240{
241 struct omap_hsmmc_host *host =
242 platform_get_drvdata(to_platform_device(dev));
243 int ret = 0;
244
245 /*
246 * If we don't see a Vcc regulator, assume it's a fixed
247 * voltage always-on regulator.
248 */
249 if (!host->vcc)
250 return 0;
1f84b71b
RN		 251 /*
252 * With DT, never turn OFF the regulator. This is because
253 * the pbias cell programming support is still missing when
254 * booting with Device tree
255 */
4d048f91 256 if (dev->of_node && !vdd)
1f84b71b 257 return 0;
db0fefc5
AH		 258
259 if (mmc_slot(host).before_set_reg)
260 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
261
262 /*
263 * Assume Vcc regulator is used only to power the card ... OMAP
264 * VDDS is used to power the pins, optionally with a transceiver to
265 * support cards using voltages other than VDDS (1.8V nominal). When a
266 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
267 *
268 * In some cases this regulator won't support enable/disable;
269 * e.g. it's a fixed rail for a WLAN chip.
270 *
271 * In other cases vcc_aux switches interface power. Example, for
272 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
273 * chips/cards need an interface voltage rail too.
274 */
275 if (power_on) {
99fc5131 276 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 277 /* Enable interface voltage rail, if needed */
278 if (ret == 0 && host->vcc_aux) {
279 ret = regulator_enable(host->vcc_aux);
280 if (ret < 0)
99fc5131
LW		 281 ret = mmc_regulator_set_ocr(host->mmc,
282 host->vcc, 0);
db0fefc5
AH		 283 }
284 } else {
99fc5131 285 /* Shut down the rail */
6da20c89
AH		 286 if (host->vcc_aux)
287 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 288 if (!ret) {
289 /* Then proceed to shut down the local regulator */
290 ret = mmc_regulator_set_ocr(host->mmc,
291 host->vcc, 0);
292 }
db0fefc5
AH		 293 }
294
295 if (mmc_slot(host).after_set_reg)
296 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
297
298 return ret;
299}
300
db0fefc5
AH		 301static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
302{
303 struct regulator *reg;
64be9782 304 int ocr_value = 0;
db0fefc5 305
db0fefc5
AH		 306 reg = regulator_get(host->dev, "vmmc");
307 if (IS_ERR(reg)) {
308 dev_dbg(host->dev, "vmmc regulator missing\n");
1fdc90fb 309 return PTR_ERR(reg);
db0fefc5 310 } else {
1fdc90fb 311 mmc_slot(host).set_power = omap_hsmmc_set_power;
db0fefc5 312 host->vcc = reg;
64be9782 313 ocr_value = mmc_regulator_get_ocrmask(reg);
314 if (!mmc_slot(host).ocr_mask) {
315 mmc_slot(host).ocr_mask = ocr_value;
316 } else {
317 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
2cecdf00 318 dev_err(host->dev, "ocrmask %x is not supported\n",
e3f1adb6 319 mmc_slot(host).ocr_mask);
64be9782 320 mmc_slot(host).ocr_mask = 0;
321 return -EINVAL;
322 }
323 }
db0fefc5
AH		 324
325 /* Allow an aux regulator */
326 reg = regulator_get(host->dev, "vmmc_aux");
327 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
328
b1c1df7a
B		 329 /* For eMMC do not power off when not in sleep state */
330 if (mmc_slot(host).no_regulator_off_init)
331 return 0;
db0fefc5
AH		 332 /*
333 * UGLY HACK: workaround regulator framework bugs.
334 * When the bootloader leaves a supply active, it's
335 * initialized with zero usecount ... and we can't
336 * disable it without first enabling it. Until the
337 * framework is fixed, we need a workaround like this
338 * (which is safe for MMC, but not in general).
339 */
e840ce13
AH		 340 if (regulator_is_enabled(host->vcc) > 0 ||
341 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
342 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
343
344 mmc_slot(host).set_power(host->dev, host->slot_id,
345 1, vdd);
346 mmc_slot(host).set_power(host->dev, host->slot_id,
347 0, 0);
db0fefc5
AH		 348 }
349 }
350
351 return 0;
db0fefc5
AH		 352}
353
354static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
355{
356 regulator_put(host->vcc);
357 regulator_put(host->vcc_aux);
358 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 359}
360
b702b106
AH		 361static inline int omap_hsmmc_have_reg(void)
362{
363 return 1;
364}
365
366#else
367
368static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
369{
370 return -EINVAL;
371}
372
373static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
374{
375}
376
377static inline int omap_hsmmc_have_reg(void)
378{
379 return 0;
380}
381
382#endif
383
384static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
385{
386 int ret;
387
388 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 389 if (pdata->slots[0].cover)
390 pdata->slots[0].get_cover_state =
391 omap_hsmmc_get_cover_state;
392 else
393 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
394 pdata->slots[0].card_detect_irq =
395 gpio_to_irq(pdata->slots[0].switch_pin);
396 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
397 if (ret)
398 return ret;
399 ret = gpio_direction_input(pdata->slots[0].switch_pin);
400 if (ret)
401 goto err_free_sp;
402 } else
403 pdata->slots[0].switch_pin = -EINVAL;
404
405 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
406 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
407 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
408 if (ret)
409 goto err_free_cd;
410 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
411 if (ret)
412 goto err_free_wp;
413 } else
414 pdata->slots[0].gpio_wp = -EINVAL;
415
416 return 0;
417
418err_free_wp:
419 gpio_free(pdata->slots[0].gpio_wp);
420err_free_cd:
421 if (gpio_is_valid(pdata->slots[0].switch_pin))
422err_free_sp:
423 gpio_free(pdata->slots[0].switch_pin);
424 return ret;
425}
426
427static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
428{
429 if (gpio_is_valid(pdata->slots[0].gpio_wp))
430 gpio_free(pdata->slots[0].gpio_wp);
431 if (gpio_is_valid(pdata->slots[0].switch_pin))
432 gpio_free(pdata->slots[0].switch_pin);
433}
434
e0c7f99b
AS		 435/*
436 * Start clock to the card
437 */
438static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
439{
440 OMAP_HSMMC_WRITE(host->base, SYSCTL,
441 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
442}
443
a45c6cb8
MC		 444/*
445 * Stop clock to the card
446 */
70a3341a 447static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 448{
449 OMAP_HSMMC_WRITE(host->base, SYSCTL,
450 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
451 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
7122bbb0 452 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
a45c6cb8
MC		 453}
454
93caf8e6
AH		 455static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
456 struct mmc_command *cmd)
b417577d
AH		 457{
458 unsigned int irq_mask;
459
460 if (host->use_dma)
461 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
462 else
463 irq_mask = INT_EN_MASK;
464
93caf8e6
AH		 465 /* Disable timeout for erases */
466 if (cmd->opcode == MMC_ERASE)
467 irq_mask &= ~DTO_ENABLE;
468
b417577d
AH		 469 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
470 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
471 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
472}
473
474static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
475{
476 OMAP_HSMMC_WRITE(host->base, ISE, 0);
477 OMAP_HSMMC_WRITE(host->base, IE, 0);
478 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
479}
480
ac330f44 481/* Calculate divisor for the given clock frequency */
d83b6e03 482static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 483{
484 u16 dsor = 0;
485
486 if (ios->clock) {
d83b6e03 487 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ac330f44
AS		 488 if (dsor > 250)
489 dsor = 250;
490 }
491
492 return dsor;
493}
494
5934df2f
AS		 495static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
496{
497 struct mmc_ios *ios = &host->mmc->ios;
498 unsigned long regval;
499 unsigned long timeout;
cd587096 500 unsigned long clkdiv;
5934df2f 501
8986d31b 502 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
5934df2f
AS		 503
504 omap_hsmmc_stop_clock(host);
505
506 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
507 regval = regval & ~(CLKD_MASK | DTO_MASK);
cd587096
HG		 508 clkdiv = calc_divisor(host, ios);
509 regval = regval | (clkdiv << 6) | (DTO << 16);
5934df2f
AS		 510 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
511 OMAP_HSMMC_WRITE(host->base, SYSCTL,
512 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
513
514 /* Wait till the ICS bit is set */
515 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
516 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
517 && time_before(jiffies, timeout))
518 cpu_relax();
519
cd587096
HG		 520 /*
521 * Enable High-Speed Support
522 * Pre-Requisites
523 * - Controller should support High-Speed-Enable Bit
524 * - Controller should not be using DDR Mode
525 * - Controller should advertise that it supports High Speed
526 * in capabilities register
527 * - MMC/SD clock coming out of controller > 25MHz
528 */
529 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
530 (ios->timing != MMC_TIMING_UHS_DDR50) &&
531 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
532 regval = OMAP_HSMMC_READ(host->base, HCTL);
533 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
534 regval |= HSPE;
535 else
536 regval &= ~HSPE;
537
538 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
539 }
540
5934df2f
AS		 541 omap_hsmmc_start_clock(host);
542}
543
3796fb8a
AS		 544static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
545{
546 struct mmc_ios *ios = &host->mmc->ios;
547 u32 con;
548
549 con = OMAP_HSMMC_READ(host->base, CON);
03b5d924
B		 550 if (ios->timing == MMC_TIMING_UHS_DDR50)
551 con |= DDR; /* configure in DDR mode */
552 else
553 con &= ~DDR;
3796fb8a
AS		 554 switch (ios->bus_width) {
555 case MMC_BUS_WIDTH_8:
556 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
557 break;
558 case MMC_BUS_WIDTH_4:
559 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
560 OMAP_HSMMC_WRITE(host->base, HCTL,
561 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
562 break;
563 case MMC_BUS_WIDTH_1:
564 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
565 OMAP_HSMMC_WRITE(host->base, HCTL,
566 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
567 break;
568 }
569}
570
571static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
572{
573 struct mmc_ios *ios = &host->mmc->ios;
574 u32 con;
575
576 con = OMAP_HSMMC_READ(host->base, CON);
577 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
578 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
579 else
580 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
581}
582
11dd62a7
DK		 583#ifdef CONFIG_PM
584
585/*
586 * Restore the MMC host context, if it was lost as result of a
587 * power state change.
588 */
70a3341a 589static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 590{
591 struct mmc_ios *ios = &host->mmc->ios;
592 struct omap_mmc_platform_data *pdata = host->pdata;
593 int context_loss = 0;
3796fb8a 594 u32 hctl, capa;
11dd62a7
DK		 595 unsigned long timeout;
596
597 if (pdata->get_context_loss_count) {
598 context_loss = pdata->get_context_loss_count(host->dev);
599 if (context_loss < 0)
600 return 1;
601 }
602
603 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
604 context_loss == host->context_loss ? "not " : "");
605 if (host->context_loss == context_loss)
606 return 1;
607
6c31b215
V		 608 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
609 return 1;
11dd62a7 610
c2200efb 611 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 612 if (host->power_mode != MMC_POWER_OFF &&
613 (1 << ios->vdd) <= MMC_VDD_23_24)
614 hctl = SDVS18;
615 else
616 hctl = SDVS30;
617 capa = VS30 | VS18;
618 } else {
619 hctl = SDVS18;
620 capa = VS18;
621 }
622
623 OMAP_HSMMC_WRITE(host->base, HCTL,
624 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
625
626 OMAP_HSMMC_WRITE(host->base, CAPA,
627 OMAP_HSMMC_READ(host->base, CAPA) | capa);
628
629 OMAP_HSMMC_WRITE(host->base, HCTL,
630 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
631
632 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
633 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
634 && time_before(jiffies, timeout))
635 ;
636
b417577d 637 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 638
639 /* Do not initialize card-specific things if the power is off */
640 if (host->power_mode == MMC_POWER_OFF)
641 goto out;
642
3796fb8a 643 omap_hsmmc_set_bus_width(host);
11dd62a7 644
5934df2f 645 omap_hsmmc_set_clock(host);
11dd62a7 646
3796fb8a
AS		 647 omap_hsmmc_set_bus_mode(host);
648
11dd62a7
DK		 649out:
650 host->context_loss = context_loss;
651
652 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
653 return 0;
654}
655
656/*
657 * Save the MMC host context (store the number of power state changes so far).
658 */
70a3341a 659static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 660{
661 struct omap_mmc_platform_data *pdata = host->pdata;
662 int context_loss;
663
664 if (pdata->get_context_loss_count) {
665 context_loss = pdata->get_context_loss_count(host->dev);
666 if (context_loss < 0)
667 return;
668 host->context_loss = context_loss;
669 }
670}
671
672#else
673
70a3341a 674static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 675{
676 return 0;
677}
678
70a3341a 679static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 680{
681}
682
683#endif
684
a45c6cb8
MC		 685/*
686 * Send init stream sequence to card
687 * before sending IDLE command
688 */
70a3341a 689static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 690{
691 int reg = 0;
692 unsigned long timeout;
693
b62f6228
AH		 694 if (host->protect_card)
695 return;
696
a45c6cb8 697 disable_irq(host->irq);
b417577d
AH		 698
699 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 700 OMAP_HSMMC_WRITE(host->base, CON,
701 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
702 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
703
704 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
705 while ((reg != CC) && time_before(jiffies, timeout))
706 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
707
708 OMAP_HSMMC_WRITE(host->base, CON,
709 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 710
711 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
712 OMAP_HSMMC_READ(host->base, STAT);
713
a45c6cb8
MC		 714 enable_irq(host->irq);
715}
716
717static inline
70a3341a 718int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 719{
720 int r = 1;
721
191d1f1d
DK		 722 if (mmc_slot(host).get_cover_state)
723 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 724 return r;
725}
726
727static ssize_t
70a3341a 728omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 729 char *buf)
730{
731 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 732 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 733
70a3341a
DK		 734 return sprintf(buf, "%s\n",
735 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 736}
737
70a3341a 738static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 739
740static ssize_t
70a3341a 741omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 742 char *buf)
743{
744 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 745 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 746
191d1f1d 747 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 748}
749
70a3341a 750static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 751
752/*
753 * Configure the response type and send the cmd.
754 */
755static void
70a3341a 756omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 757 struct mmc_data *data)
758{
759 int cmdreg = 0, resptype = 0, cmdtype = 0;
760
8986d31b 761 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
a45c6cb8
MC		 762 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
763 host->cmd = cmd;
764
93caf8e6 765 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 766
4a694dc9 767 host->response_busy = 0;
a45c6cb8
MC		 768 if (cmd->flags & MMC_RSP_PRESENT) {
769 if (cmd->flags & MMC_RSP_136)
770 resptype = 1;
4a694dc9
AH		 771 else if (cmd->flags & MMC_RSP_BUSY) {
772 resptype = 3;
773 host->response_busy = 1;
774 } else
a45c6cb8
MC		 775 resptype = 2;
776 }
777
778 /*
779 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
780 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
781 * a val of 0x3, rest 0x0.
782 */
783 if (cmd == host->mrq->stop)
784 cmdtype = 0x3;
785
786 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
787
788 if (data) {
789 cmdreg |= DP_SELECT | MSBS | BCE;
790 if (data->flags & MMC_DATA_READ)
791 cmdreg |= DDIR;
792 else
793 cmdreg &= ~(DDIR);
794 }
795
796 if (host->use_dma)
797 cmdreg |= DMA_EN;
798
b417577d 799 host->req_in_progress = 1;
4dffd7a2 800
a45c6cb8
MC		 801 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
802 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
803}
804
0ccd76d4 805static int
70a3341a 806omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 807{
808 if (data->flags & MMC_DATA_WRITE)
809 return DMA_TO_DEVICE;
810 else
811 return DMA_FROM_DEVICE;
812}
813
c5c98927
RK		 814static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
815 struct mmc_data *data)
816{
817 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
818}
819
b417577d
AH		 820static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
821{
822 int dma_ch;
31463b14 823 unsigned long flags;
b417577d 824
31463b14 825 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 826 host->req_in_progress = 0;
827 dma_ch = host->dma_ch;
31463b14 828 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 829
830 omap_hsmmc_disable_irq(host);
831 /* Do not complete the request if DMA is still in progress */
832 if (mrq->data && host->use_dma && dma_ch != -1)
833 return;
834 host->mrq = NULL;
835 mmc_request_done(host->mmc, mrq);
836}
837
a45c6cb8
MC		 838/*
839 * Notify the transfer complete to MMC core
840 */
841static void
70a3341a 842omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 843{
4a694dc9
AH		 844 if (!data) {
845 struct mmc_request *mrq = host->mrq;
846
23050103
AH		 847 /* TC before CC from CMD6 - don't know why, but it happens */
848 if (host->cmd && host->cmd->opcode == 6 &&
849 host->response_busy) {
850 host->response_busy = 0;
851 return;
852 }
853
b417577d 854 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 855 return;
856 }
857
a45c6cb8
MC		 858 host->data = NULL;
859
a45c6cb8
MC		 860 if (!data->error)
861 data->bytes_xfered += data->blocks * (data->blksz);
862 else
863 data->bytes_xfered = 0;
864
fe852273 865 if (!data->stop) {
b417577d 866 omap_hsmmc_request_done(host, data->mrq);
fe852273 867 return;
a45c6cb8 868 }
fe852273 869 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 870}
871
872/*
873 * Notify the core about command completion
874 */
875static void
70a3341a 876omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 877{
878 host->cmd = NULL;
879
880 if (cmd->flags & MMC_RSP_PRESENT) {
881 if (cmd->flags & MMC_RSP_136) {
882 /* response type 2 */
883 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
884 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
885 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
886 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
887 } else {
888 /* response types 1, 1b, 3, 4, 5, 6 */
889 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
890 }
891 }
b417577d
AH		 892 if ((host->data == NULL && !host->response_busy) || cmd->error)
893 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 894}
895
896/*
897 * DMA clean up for command errors
898 */
70a3341a 899static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 900{
b417577d 901 int dma_ch;
31463b14 902 unsigned long flags;
b417577d 903
82788ff5 904 host->data->error = errno;
a45c6cb8 905
31463b14 906 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 907 dma_ch = host->dma_ch;
908 host->dma_ch = -1;
31463b14 909 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 910
911 if (host->use_dma && dma_ch != -1) {
c5c98927
RK		 912 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
913
914 dmaengine_terminate_all(chan);
915 dma_unmap_sg(chan->device->dev,
916 host->data->sg, host->data->sg_len,
70a3341a 917 omap_hsmmc_get_dma_dir(host, host->data));
c5c98927 918
053bf34f 919 host->data->host_cookie = 0;
a45c6cb8
MC		 920 }
921 host->data = NULL;
a45c6cb8
MC		 922}
923
924/*
925 * Readable error output
926 */
927#ifdef CONFIG_MMC_DEBUG
699b958b 928static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 929{
930 /* --- means reserved bit without definition at documentation */
70a3341a 931 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 932 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
933 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
934 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
935 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 936 };
937 char res[256];
938 char *buf = res;
939 int len, i;
940
941 len = sprintf(buf, "MMC IRQ 0x%x :", status);
942 buf += len;
943
70a3341a 944 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 945 if (status & (1 << i)) {
70a3341a 946 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 947 buf += len;
948 }
949
8986d31b 950 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
a45c6cb8 951}
699b958b
AH		 952#else
953static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
954 u32 status)
955{
956}
a45c6cb8
MC		 957#endif /* CONFIG_MMC_DEBUG */
958
3ebf74b1
JP		 959/*
960 * MMC controller internal state machines reset
961 *
962 * Used to reset command or data internal state machines, using respectively
963 * SRC or SRD bit of SYSCTL register
964 * Can be called from interrupt context
965 */
70a3341a
DK		 966static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
967 unsigned long bit)
3ebf74b1
JP		 968{
969 unsigned long i = 0;
970 unsigned long limit = (loops_per_jiffy *
971 msecs_to_jiffies(MMC_TIMEOUT_MS));
972
973 OMAP_HSMMC_WRITE(host->base, SYSCTL,
974 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
975
07ad64b6
MC		 976 /*
977 * OMAP4 ES2 and greater has an updated reset logic.
978 * Monitor a 0->1 transition first
979 */
980 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 981 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 982 && (i++ < limit))
983 cpu_relax();
984 }
985 i = 0;
986
3ebf74b1
JP		 987 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
988 (i++ < limit))
989 cpu_relax();
990
991 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
992 dev_err(mmc_dev(host->mmc),
993 "Timeout waiting on controller reset in %s\n",
994 __func__);
995}
a45c6cb8 996
25e1897b
B		 997static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
998 int err, int end_cmd)
ae4bf788 999{
25e1897b 1000 if (end_cmd) {
94d4f272 1001 omap_hsmmc_reset_controller_fsm(host, SRC);
25e1897b
B		 1002 if (host->cmd)
1003 host->cmd->error = err;
1004 }
ae4bf788
V		 1005
1006 if (host->data) {
1007 omap_hsmmc_reset_controller_fsm(host, SRD);
1008 omap_hsmmc_dma_cleanup(host, err);
dc7745bd
B		 1009 } else if (host->mrq && host->mrq->cmd)
1010 host->mrq->cmd->error = err;
ae4bf788
V		 1011}
1012
b417577d 1013static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1014{
a45c6cb8 1015 struct mmc_data *data;
b417577d
AH		 1016 int end_cmd = 0, end_trans = 0;
1017
a45c6cb8 1018 data = host->data;
8986d31b 1019 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
a45c6cb8
MC		 1020
1021 if (status & ERR) {
699b958b 1022 omap_hsmmc_dbg_report_irq(host, status);
25e1897b
B		 1023
1024 if (status & (CMD_TIMEOUT | CMD_CRC))
1025 end_cmd = 1;
ae4bf788 1026 if (status & (CMD_TIMEOUT | DATA_TIMEOUT))
25e1897b 1027 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
ae4bf788 1028 else if (status & (CMD_CRC | DATA_CRC))
25e1897b 1029 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
ae4bf788 1030
ae4bf788 1031 if (host->data || host->response_busy) {
25e1897b 1032 end_trans = !end_cmd;
ae4bf788 1033 host->response_busy = 0;
a45c6cb8
MC		 1034 }
1035 }
1036
a8fe29d8 1037 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1038 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1039 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1040 omap_hsmmc_xfer_done(host, data);
b417577d 1041}
a45c6cb8 1042
b417577d
AH		 1043/*
1044 * MMC controller IRQ handler
1045 */
1046static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1047{
1048 struct omap_hsmmc_host *host = dev_id;
1049 int status;
1050
1051 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1052 while (status & INT_EN_MASK && host->req_in_progress) {
b417577d 1053 omap_hsmmc_do_irq(host, status);
1f6b9fa4 1054
b417577d 1055 /* Flush posted write */
1f6b9fa4 1056 OMAP_HSMMC_WRITE(host->base, STAT, status);
b417577d 1057 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1058 }
4dffd7a2 1059
a45c6cb8
MC		 1060 return IRQ_HANDLED;
1061}
1062
70a3341a 1063static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1064{
1065 unsigned long i;
1066
1067 OMAP_HSMMC_WRITE(host->base, HCTL,
1068 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1069 for (i = 0; i < loops_per_jiffy; i++) {
1070 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1071 break;
1072 cpu_relax();
1073 }
1074}
1075
a45c6cb8 1076/*
eb250826
DB		 1077 * Switch MMC interface voltage ... only relevant for MMC1.
1078 *
1079 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1080 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1081 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1082 */
70a3341a 1083static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1084{
1085 u32 reg_val = 0;
1086 int ret;
1087
1088 /* Disable the clocks */
fa4aa2d4 1089 pm_runtime_put_sync(host->dev);
cd03d9a8 1090 if (host->dbclk)
94c18149 1091 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1092
1093 /* Turn the power off */
1094 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1095
1096 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1097 if (!ret)
1098 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1099 vdd);
fa4aa2d4 1100 pm_runtime_get_sync(host->dev);
cd03d9a8 1101 if (host->dbclk)
94c18149 1102 clk_prepare_enable(host->dbclk);
2bec0893 1103
a45c6cb8
MC		 1104 if (ret != 0)
1105 goto err;
1106
a45c6cb8
MC		 1107 OMAP_HSMMC_WRITE(host->base, HCTL,
1108 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1109 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1110
a45c6cb8
MC		 1111 /*
1112 * If a MMC dual voltage card is detected, the set_ios fn calls
1113 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1114 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1115 *
eb250826
DB		 1116 * Cope with a bit of slop in the range ... per data sheets:
1117 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1118 * but recommended values are 1.71V to 1.89V
1119 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1120 * but recommended values are 2.7V to 3.3V
1121 *
1122 * Board setup code shouldn't permit anything very out-of-range.
1123 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1124 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1125 */
eb250826 1126 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1127 reg_val |= SDVS18;
eb250826
DB		 1128 else
1129 reg_val |= SDVS30;
a45c6cb8
MC		 1130
1131 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1132 set_sd_bus_power(host);
a45c6cb8
MC		 1133
1134 return 0;
1135err:
1136 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1137 return ret;
1138}
1139
b62f6228
AH		 1140/* Protect the card while the cover is open */
1141static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1142{
1143 if (!mmc_slot(host).get_cover_state)
1144 return;
1145
1146 host->reqs_blocked = 0;
1147 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1148 if (host->protect_card) {
2cecdf00 1149 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1150 "card is now accessible\n",
1151 mmc_hostname(host->mmc));
1152 host->protect_card = 0;
1153 }
1154 } else {
1155 if (!host->protect_card) {
2cecdf00 1156 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1157 "card is now inaccessible\n",
1158 mmc_hostname(host->mmc));
1159 host->protect_card = 1;
1160 }
1161 }
1162}
1163
a45c6cb8 1164/*
7efab4f3 1165 * irq handler to notify the core about card insertion/removal
a45c6cb8 1166 */
7efab4f3 1167static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1168{
7efab4f3 1169 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1170 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1171 int carddetect;
1172
1173 if (host->suspended)
7efab4f3 1174 return IRQ_HANDLED;
a6b2240d
AH		 1175
1176 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1177
191d1f1d 1178 if (slot->card_detect)
db0fefc5 1179 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1180 else {
1181 omap_hsmmc_protect_card(host);
a6b2240d 1182 carddetect = -ENOSYS;
b62f6228 1183 }
a45c6cb8 1184
cdeebadd 1185 if (carddetect)
a45c6cb8 1186 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1187 else
a45c6cb8 1188 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1189 return IRQ_HANDLED;
1190}
1191
c5c98927 1192static void omap_hsmmc_dma_callback(void *param)
a45c6cb8 1193{
c5c98927
RK		 1194 struct omap_hsmmc_host *host = param;
1195 struct dma_chan *chan;
770d7432 1196 struct mmc_data *data;
c5c98927 1197 int req_in_progress;
a45c6cb8 1198
c5c98927 1199 spin_lock_irq(&host->irq_lock);
b417577d 1200 if (host->dma_ch < 0) {
c5c98927 1201 spin_unlock_irq(&host->irq_lock);
a45c6cb8 1202 return;
b417577d 1203 }
a45c6cb8 1204
770d7432 1205 data = host->mrq->data;
c5c98927 1206 chan = omap_hsmmc_get_dma_chan(host, data);
9782aff8 1207 if (!data->host_cookie)
c5c98927
RK		 1208 dma_unmap_sg(chan->device->dev,
1209 data->sg, data->sg_len,
9782aff8 1210 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1211
1212 req_in_progress = host->req_in_progress;
a45c6cb8 1213 host->dma_ch = -1;
c5c98927 1214 spin_unlock_irq(&host->irq_lock);
b417577d
AH		 1215
1216 /* If DMA has finished after TC, complete the request */
1217 if (!req_in_progress) {
1218 struct mmc_request *mrq = host->mrq;
1219
1220 host->mrq = NULL;
1221 mmc_request_done(host->mmc, mrq);
1222 }
a45c6cb8
MC		 1223}
1224
9782aff8
PF		 1225static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1226 struct mmc_data *data,
c5c98927 1227 struct omap_hsmmc_next *next,
26b88520 1228 struct dma_chan *chan)
9782aff8
PF		 1229{
1230 int dma_len;
1231
1232 if (!next && data->host_cookie &&
1233 data->host_cookie != host->next_data.cookie) {
2cecdf00 1234 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1235 " host->next_data.cookie %d\n",
1236 __func__, data->host_cookie, host->next_data.cookie);
1237 data->host_cookie = 0;
1238 }
1239
1240 /* Check if next job is already prepared */
1241 if (next ||
1242 (!next && data->host_cookie != host->next_data.cookie)) {
26b88520 1243 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
9782aff8
PF		 1244 omap_hsmmc_get_dma_dir(host, data));
1245
1246 } else {
1247 dma_len = host->next_data.dma_len;
1248 host->next_data.dma_len = 0;
1249 }
1250
1251
1252 if (dma_len == 0)
1253 return -EINVAL;
1254
1255 if (next) {
1256 next->dma_len = dma_len;
1257 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1258 } else
1259 host->dma_len = dma_len;
1260
1261 return 0;
1262}
1263
a45c6cb8
MC		 1264/*
1265 * Routine to configure and start DMA for the MMC card
1266 */
70a3341a
DK		 1267static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1268 struct mmc_request *req)
a45c6cb8 1269{
26b88520
RK		 1270 struct dma_slave_config cfg;
1271 struct dma_async_tx_descriptor *tx;
1272 int ret = 0, i;
a45c6cb8 1273 struct mmc_data *data = req->data;
c5c98927 1274 struct dma_chan *chan;
a45c6cb8 1275
0ccd76d4 1276 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1277 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1278 struct scatterlist *sgl;
1279
1280 sgl = data->sg + i;
1281 if (sgl->length % data->blksz)
1282 return -EINVAL;
1283 }
1284 if ((data->blksz % 4) != 0)
1285 /* REVISIT: The MMC buffer increments only when MSB is written.
1286 * Return error for blksz which is non multiple of four.
1287 */
1288 return -EINVAL;
1289
b417577d 1290 BUG_ON(host->dma_ch != -1);
a45c6cb8 1291
c5c98927 1292 chan = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1293
26b88520
RK		 1294 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1295 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1296 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1297 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1298 cfg.src_maxburst = data->blksz / 4;
1299 cfg.dst_maxburst = data->blksz / 4;
c5c98927 1300
26b88520
RK		 1301 ret = dmaengine_slave_config(chan, &cfg);
1302 if (ret)
a45c6cb8 1303 return ret;
c5c98927 1304
26b88520 1305 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
9782aff8
PF		 1306 if (ret)
1307 return ret;
a45c6cb8 1308
26b88520
RK		 1309 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1310 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1311 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1312 if (!tx) {
1313 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1314 /* FIXME: cleanup */
1315 return -1;
1316 }
a45c6cb8 1317
26b88520
RK		 1318 tx->callback = omap_hsmmc_dma_callback;
1319 tx->callback_param = host;
a45c6cb8 1320
26b88520
RK		 1321 /* Does not fail */
1322 dmaengine_submit(tx);
c5c98927 1323
26b88520 1324 host->dma_ch = 1;
c5c98927 1325
26b88520 1326 dma_async_issue_pending(chan);
a45c6cb8 1327
a45c6cb8
MC		 1328 return 0;
1329}
1330
70a3341a 1331static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1332 unsigned int timeout_ns,
1333 unsigned int timeout_clks)
a45c6cb8
MC		 1334{
1335 unsigned int timeout, cycle_ns;
1336 uint32_t reg, clkd, dto = 0;
1337
1338 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1339 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1340 if (clkd == 0)
1341 clkd = 1;
1342
1343 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1344 timeout = timeout_ns / cycle_ns;
1345 timeout += timeout_clks;
a45c6cb8
MC		 1346 if (timeout) {
1347 while ((timeout & 0x80000000) == 0) {
1348 dto += 1;
1349 timeout <<= 1;
1350 }
1351 dto = 31 - dto;
1352 timeout <<= 1;
1353 if (timeout && dto)
1354 dto += 1;
1355 if (dto >= 13)
1356 dto -= 13;
1357 else
1358 dto = 0;
1359 if (dto > 14)
1360 dto = 14;
1361 }
1362
1363 reg &= ~DTO_MASK;
1364 reg |= dto << DTO_SHIFT;
1365 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1366}
1367
1368/*
1369 * Configure block length for MMC/SD cards and initiate the transfer.
1370 */
1371static int
70a3341a 1372omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1373{
1374 int ret;
1375 host->data = req->data;
1376
1377 if (req->data == NULL) {
a45c6cb8 1378 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1379 /*
1380 * Set an arbitrary 100ms data timeout for commands with
1381 * busy signal.
1382 */
1383 if (req->cmd->flags & MMC_RSP_BUSY)
1384 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1385 return 0;
1386 }
1387
1388 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1389 | (req->data->blocks << 16));
e2bf08d6 1390 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1391
a45c6cb8 1392 if (host->use_dma) {
70a3341a 1393 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1394 if (ret != 0) {
1395 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1396 return ret;
1397 }
1398 }
1399 return 0;
1400}
1401
9782aff8
PF		 1402static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1403 int err)
1404{
1405 struct omap_hsmmc_host *host = mmc_priv(mmc);
1406 struct mmc_data *data = mrq->data;
1407
26b88520 1408 if (host->use_dma && data->host_cookie) {
c5c98927 1409 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1410
26b88520
RK		 1411 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1412 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1413 data->host_cookie = 0;
1414 }
1415}
1416
1417static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1418 bool is_first_req)
1419{
1420 struct omap_hsmmc_host *host = mmc_priv(mmc);
1421
1422 if (mrq->data->host_cookie) {
1423 mrq->data->host_cookie = 0;
1424 return ;
1425 }
1426
c5c98927
RK		 1427 if (host->use_dma) {
1428 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
c5c98927 1429
9782aff8 1430 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
26b88520 1431 &host->next_data, c))
9782aff8 1432 mrq->data->host_cookie = 0;
c5c98927 1433 }
9782aff8
PF		 1434}
1435
a45c6cb8
MC		 1436/*
1437 * Request function. for read/write operation
1438 */
70a3341a 1439static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1440{
70a3341a 1441 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1442 int err;
a45c6cb8 1443
b417577d
AH		 1444 BUG_ON(host->req_in_progress);
1445 BUG_ON(host->dma_ch != -1);
1446 if (host->protect_card) {
1447 if (host->reqs_blocked < 3) {
1448 /*
1449 * Ensure the controller is left in a consistent
1450 * state by resetting the command and data state
1451 * machines.
1452 */
1453 omap_hsmmc_reset_controller_fsm(host, SRD);
1454 omap_hsmmc_reset_controller_fsm(host, SRC);
1455 host->reqs_blocked += 1;
1456 }
1457 req->cmd->error = -EBADF;
1458 if (req->data)
1459 req->data->error = -EBADF;
1460 req->cmd->retries = 0;
1461 mmc_request_done(mmc, req);
1462 return;
1463 } else if (host->reqs_blocked)
1464 host->reqs_blocked = 0;
a45c6cb8
MC		 1465 WARN_ON(host->mrq != NULL);
1466 host->mrq = req;
70a3341a 1467 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1468 if (err) {
1469 req->cmd->error = err;
1470 if (req->data)
1471 req->data->error = err;
1472 host->mrq = NULL;
1473 mmc_request_done(mmc, req);
1474 return;
1475 }
1476
70a3341a 1477 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1478}
1479
a45c6cb8 1480/* Routine to configure clock values. Exposed API to core */
70a3341a 1481static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1482{
70a3341a 1483 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1484 int do_send_init_stream = 0;
a45c6cb8 1485
fa4aa2d4 1486 pm_runtime_get_sync(host->dev);
5e2ea617 1487
a3621465
AH		 1488 if (ios->power_mode != host->power_mode) {
1489 switch (ios->power_mode) {
1490 case MMC_POWER_OFF:
1491 mmc_slot(host).set_power(host->dev, host->slot_id,
1492 0, 0);
1493 break;
1494 case MMC_POWER_UP:
1495 mmc_slot(host).set_power(host->dev, host->slot_id,
1496 1, ios->vdd);
1497 break;
1498 case MMC_POWER_ON:
1499 do_send_init_stream = 1;
1500 break;
1501 }
1502 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1503 }
1504
dd498eff
DK		 1505 /* FIXME: set registers based only on changes to ios */
1506
3796fb8a 1507 omap_hsmmc_set_bus_width(host);
a45c6cb8 1508
4621d5f8 1509 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1510 /* Only MMC1 can interface at 3V without some flavor
1511 * of external transceiver; but they all handle 1.8V.
1512 */
a45c6cb8 1513 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1f84b71b
RN		 1514 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1515 /*
1516 * With pbias cell programming missing, this
1517 * can't be allowed when booting with device
1518 * tree.
1519 */
4d048f91 1520 !host->dev->of_node) {
a45c6cb8
MC		 1521 /*
1522 * The mmc_select_voltage fn of the core does
1523 * not seem to set the power_mode to
1524 * MMC_POWER_UP upon recalculating the voltage.
1525 * vdd 1.8v.
1526 */
70a3341a
DK		 1527 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1528 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1529 "Switch operation failed\n");
1530 }
1531 }
1532
5934df2f 1533 omap_hsmmc_set_clock(host);
a45c6cb8 1534
a3621465 1535 if (do_send_init_stream)
a45c6cb8
MC		 1536 send_init_stream(host);
1537
3796fb8a 1538 omap_hsmmc_set_bus_mode(host);
5e2ea617 1539
fa4aa2d4 1540 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1541}
1542
1543static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1544{
70a3341a 1545 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1546
191d1f1d 1547 if (!mmc_slot(host).card_detect)
a45c6cb8 1548 return -ENOSYS;
db0fefc5 1549 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1550}
1551
1552static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1553{
70a3341a 1554 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1555
191d1f1d 1556 if (!mmc_slot(host).get_ro)
a45c6cb8 1557 return -ENOSYS;
191d1f1d 1558 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1559}
1560
4816858c
GI		 1561static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1562{
1563 struct omap_hsmmc_host *host = mmc_priv(mmc);
1564
1565 if (mmc_slot(host).init_card)
1566 mmc_slot(host).init_card(card);
1567}
1568
70a3341a 1569static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1570{
1571 u32 hctl, capa, value;
1572
1573 /* Only MMC1 supports 3.0V */
4621d5f8 1574 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1575 hctl = SDVS30;
1576 capa = VS30 | VS18;
1577 } else {
1578 hctl = SDVS18;
1579 capa = VS18;
1580 }
1581
1582 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1583 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1584
1585 value = OMAP_HSMMC_READ(host->base, CAPA);
1586 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1587
1b331e69 1588 /* Set SD bus power bit */
e13bb300 1589 set_sd_bus_power(host);
1b331e69
KK		 1590}
1591
70a3341a 1592static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1593{
70a3341a 1594 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1595
fa4aa2d4
B		 1596 pm_runtime_get_sync(host->dev);
1597
dd498eff
DK		 1598 return 0;
1599}
1600
907d2e7c 1601static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
dd498eff 1602{
70a3341a 1603 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1604
fa4aa2d4
B		 1605 pm_runtime_mark_last_busy(host->dev);
1606 pm_runtime_put_autosuspend(host->dev);
1607
dd498eff
DK		 1608 return 0;
1609}
1610
70a3341a
DK		 1611static const struct mmc_host_ops omap_hsmmc_ops = {
1612 .enable = omap_hsmmc_enable_fclk,
1613 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1614 .post_req = omap_hsmmc_post_req,
1615 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1616 .request = omap_hsmmc_request,
1617 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1618 .get_cd = omap_hsmmc_get_cd,
1619 .get_ro = omap_hsmmc_get_ro,
4816858c 1620 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1621 /* NYET -- enable_sdio_irq */
1622};
1623
d900f712
DK		 1624#ifdef CONFIG_DEBUG_FS
1625
70a3341a 1626static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1627{
1628 struct mmc_host *mmc = s->private;
70a3341a 1629 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1630 int context_loss = 0;
1631
70a3341a
DK		 1632 if (host->pdata->get_context_loss_count)
1633 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1634
907d2e7c
AH		 1635 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1636 mmc->index, host->context_loss, context_loss);
5e2ea617 1637
7a8c2cef 1638 if (host->suspended) {
dd498eff
DK		 1639 seq_printf(s, "host suspended, can't read registers\n");
1640 return 0;
1641 }
1642
fa4aa2d4 1643 pm_runtime_get_sync(host->dev);
d900f712 1644
d900f712
DK		 1645 seq_printf(s, "CON:\t\t0x%08x\n",
1646 OMAP_HSMMC_READ(host->base, CON));
1647 seq_printf(s, "HCTL:\t\t0x%08x\n",
1648 OMAP_HSMMC_READ(host->base, HCTL));
1649 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1650 OMAP_HSMMC_READ(host->base, SYSCTL));
1651 seq_printf(s, "IE:\t\t0x%08x\n",
1652 OMAP_HSMMC_READ(host->base, IE));
1653 seq_printf(s, "ISE:\t\t0x%08x\n",
1654 OMAP_HSMMC_READ(host->base, ISE));
1655 seq_printf(s, "CAPA:\t\t0x%08x\n",
1656 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1657
fa4aa2d4
B		 1658 pm_runtime_mark_last_busy(host->dev);
1659 pm_runtime_put_autosuspend(host->dev);
dd498eff 1660
d900f712
DK		 1661 return 0;
1662}
1663
70a3341a 1664static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1665{
70a3341a 1666 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1667}
1668
1669static const struct file_operations mmc_regs_fops = {
70a3341a 1670 .open = omap_hsmmc_regs_open,
d900f712
DK		 1671 .read = seq_read,
1672 .llseek = seq_lseek,
1673 .release = single_release,
1674};
1675
70a3341a 1676static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1677{
1678 if (mmc->debugfs_root)
1679 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1680 mmc, &mmc_regs_fops);
1681}
1682
1683#else
1684
70a3341a 1685static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1686{
1687}
1688
1689#endif
1690
46856a68
RN		 1691#ifdef CONFIG_OF
1692static u16 omap4_reg_offset = 0x100;
1693
1694static const struct of_device_id omap_mmc_of_match[] = {
1695 {
1696 .compatible = "ti,omap2-hsmmc",
1697 },
1698 {
1699 .compatible = "ti,omap3-hsmmc",
1700 },
1701 {
1702 .compatible = "ti,omap4-hsmmc",
1703 .data = &omap4_reg_offset,
1704 },
1705 {},
b6d085f6 1706};
46856a68
RN		 1707MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1708
1709static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1710{
1711 struct omap_mmc_platform_data *pdata;
1712 struct device_node *np = dev->of_node;
d8714e87 1713 u32 bus_width, max_freq;
46856a68
RN		 1714
1715 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1716 if (!pdata)
1717 return NULL; /* out of memory */
1718
1719 if (of_find_property(np, "ti,dual-volt", NULL))
1720 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1721
1722 /* This driver only supports 1 slot */
1723 pdata->nr_slots = 1;
1724 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1725 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1726
1727 if (of_find_property(np, "ti,non-removable", NULL)) {
1728 pdata->slots[0].nonremovable = true;
1729 pdata->slots[0].no_regulator_off_init = true;
1730 }
7f217794 1731 of_property_read_u32(np, "bus-width", &bus_width);
46856a68
RN		 1732 if (bus_width == 4)
1733 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1734 else if (bus_width == 8)
1735 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1736
1737 if (of_find_property(np, "ti,needs-special-reset", NULL))
1738 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1739
d8714e87
DM		 1740 if (!of_property_read_u32(np, "max-frequency", &max_freq))
1741 pdata->max_freq = max_freq;
1742
cd587096
HG		 1743 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1744 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1745
46856a68
RN		 1746 return pdata;
1747}
1748#else
1749static inline struct omap_mmc_platform_data
1750 *of_get_hsmmc_pdata(struct device *dev)
1751{
1752 return NULL;
1753}
1754#endif
1755
efa25fd3 1756static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1757{
1758 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1759 struct mmc_host *mmc;
70a3341a 1760 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1761 struct resource *res;
db0fefc5 1762 int ret, irq;
46856a68 1763 const struct of_device_id *match;
26b88520
RK		 1764 dma_cap_mask_t mask;
1765 unsigned tx_req, rx_req;
46b76035 1766 struct pinctrl *pinctrl;
46856a68
RN		 1767
1768 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1769 if (match) {
1770 pdata = of_get_hsmmc_pdata(&pdev->dev);
1771 if (match->data) {
efc9b736 1772 const u16 *offsetp = match->data;
46856a68
RN		 1773 pdata->reg_offset = *offsetp;
1774 }
1775 }
a45c6cb8
MC		 1776
1777 if (pdata == NULL) {
1778 dev_err(&pdev->dev, "Platform Data is missing\n");
1779 return -ENXIO;
1780 }
1781
1782 if (pdata->nr_slots == 0) {
1783 dev_err(&pdev->dev, "No Slots\n");
1784 return -ENXIO;
1785 }
1786
1787 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1788 irq = platform_get_irq(pdev, 0);
1789 if (res == NULL || irq < 0)
1790 return -ENXIO;
1791
984b203a 1792 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1793 if (res == NULL)
1794 return -EBUSY;
1795
db0fefc5
AH		 1796 ret = omap_hsmmc_gpio_init(pdata);
1797 if (ret)
1798 goto err;
1799
70a3341a 1800 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1801 if (!mmc) {
1802 ret = -ENOMEM;
db0fefc5 1803 goto err_alloc;
a45c6cb8
MC		 1804 }
1805
1806 host = mmc_priv(mmc);
1807 host->mmc = mmc;
1808 host->pdata = pdata;
1809 host->dev = &pdev->dev;
1810 host->use_dma = 1;
a45c6cb8
MC		 1811 host->dma_ch = -1;
1812 host->irq = irq;
a45c6cb8 1813 host->slot_id = 0;
fc307df8 1814 host->mapbase = res->start + pdata->reg_offset;
a45c6cb8 1815 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1816 host->power_mode = MMC_POWER_OFF;
9782aff8 1817 host->next_data.cookie = 1;
a45c6cb8
MC		 1818
1819 platform_set_drvdata(pdev, host);
a45c6cb8 1820
7a8c2cef 1821 mmc->ops = &omap_hsmmc_ops;
dd498eff 1822
e0eb2424
AH		 1823 /*
1824 * If regulator_disable can only put vcc_aux to sleep then there is
1825 * no off state.
1826 */
1827 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1828 mmc_slot(host).no_off = 1;
1829
d418ed87
DM		 1830 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1831
1832 if (pdata->max_freq > 0)
1833 mmc->f_max = pdata->max_freq;
1834 else
1835 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1836
4dffd7a2 1837 spin_lock_init(&host->irq_lock);
a45c6cb8 1838
6f7607cc 1839 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1840 if (IS_ERR(host->fclk)) {
1841 ret = PTR_ERR(host->fclk);
1842 host->fclk = NULL;
a45c6cb8
MC		 1843 goto err1;
1844 }
1845
9b68256c
PW		 1846 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1847 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1848 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1849 }
dd498eff 1850
fa4aa2d4
B		 1851 pm_runtime_enable(host->dev);
1852 pm_runtime_get_sync(host->dev);
1853 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1854 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1855
92a3aebf
B		 1856 omap_hsmmc_context_save(host);
1857
cd03d9a8
RN		 1858 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1859 /*
1860 * MMC can still work without debounce clock.
1861 */
1862 if (IS_ERR(host->dbclk)) {
cd03d9a8 1863 host->dbclk = NULL;
94c18149 1864 } else if (clk_prepare_enable(host->dbclk) != 0) {
cd03d9a8
RN		 1865 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1866 clk_put(host->dbclk);
1867 host->dbclk = NULL;
2bec0893 1868 }
a45c6cb8 1869
0ccd76d4
JY		 1870 /* Since we do only SG emulation, we can have as many segs
1871 * as we want. */
a36274e0 1872 mmc->max_segs = 1024;
0ccd76d4 1873
a45c6cb8
MC		 1874 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1875 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1876 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1877 mmc->max_seg_size = mmc->max_req_size;
1878
13189e78 1879 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1880 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1881
3a63833e
SG		 1882 mmc->caps |= mmc_slot(host).caps;
1883 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1884 mmc->caps |= MMC_CAP_4_BIT_DATA;
1885
191d1f1d 1886 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1887 mmc->caps |= MMC_CAP_NONREMOVABLE;
1888
6fdc75de
EP		 1889 mmc->pm_caps = mmc_slot(host).pm_caps;
1890
70a3341a 1891 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1892
b7bf773b
B		 1893 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1894 if (!res) {
1895 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
9c17d08c 1896 ret = -ENXIO;
b7bf773b
B		 1897 goto err_irq;
1898 }
26b88520 1899 tx_req = res->start;
b7bf773b
B		 1900
1901 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1902 if (!res) {
1903 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
9c17d08c 1904 ret = -ENXIO;
f3e2f1dd
GI		 1905 goto err_irq;
1906 }
26b88520 1907 rx_req = res->start;
a45c6cb8 1908
26b88520
RK		 1909 dma_cap_zero(mask);
1910 dma_cap_set(DMA_SLAVE, mask);
1911
1912 host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1913 if (!host->rx_chan) {
1914 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
04e8c7bc 1915 ret = -ENXIO;
26b88520
RK		 1916 goto err_irq;
1917 }
1918
1919 host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1920 if (!host->tx_chan) {
1921 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
04e8c7bc 1922 ret = -ENXIO;
26b88520 1923 goto err_irq;
c5c98927 1924 }
a45c6cb8
MC		 1925
1926 /* Request IRQ for MMC operations */
d9618e9f 1927 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1928 mmc_hostname(mmc), host);
1929 if (ret) {
1930 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1931 goto err_irq;
1932 }
1933
1934 if (pdata->init != NULL) {
1935 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 1936 dev_dbg(mmc_dev(host->mmc),
1937 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1938 goto err_irq_cd_init;
1939 }
1940 }
db0fefc5 1941
b702b106 1942 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1943 ret = omap_hsmmc_reg_get(host);
1944 if (ret)
1945 goto err_reg;
1946 host->use_reg = 1;
1947 }
1948
b583f26d 1949 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1950
1951 /* Request IRQ for card detect */
e1a55f5e 1952 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1953 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1954 NULL,
1955 omap_hsmmc_detect,
db35f83e 1956 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
7efab4f3 1957 mmc_hostname(mmc), host);
a45c6cb8
MC		 1958 if (ret) {
1959 dev_dbg(mmc_dev(host->mmc),
1960 "Unable to grab MMC CD IRQ\n");
1961 goto err_irq_cd;
1962 }
72f2e2c7 1963 pdata->suspend = omap_hsmmc_suspend_cdirq;
1964 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 1965 }
1966
b417577d 1967 omap_hsmmc_disable_irq(host);
a45c6cb8 1968
46b76035
DM		 1969 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1970 if (IS_ERR(pinctrl))
1971 dev_warn(&pdev->dev,
1972 "pins are not configured from the driver\n");
1973
b62f6228
AH		 1974 omap_hsmmc_protect_card(host);
1975
a45c6cb8
MC		 1976 mmc_add_host(mmc);
1977
191d1f1d 1978 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 1979 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1980 if (ret < 0)
1981 goto err_slot_name;
1982 }
191d1f1d 1983 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 1984 ret = device_create_file(&mmc->class_dev,
1985 &dev_attr_cover_switch);
1986 if (ret < 0)
db0fefc5 1987 goto err_slot_name;
a45c6cb8
MC		 1988 }
1989
70a3341a 1990 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 1991 pm_runtime_mark_last_busy(host->dev);
1992 pm_runtime_put_autosuspend(host->dev);
d900f712 1993
a45c6cb8
MC		 1994 return 0;
1995
a45c6cb8
MC		 1996err_slot_name:
1997 mmc_remove_host(mmc);
a45c6cb8 1998 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 1999err_irq_cd:
2000 if (host->use_reg)
2001 omap_hsmmc_reg_put(host);
2002err_reg:
2003 if (host->pdata->cleanup)
2004 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2005err_irq_cd_init:
2006 free_irq(host->irq, host);
2007err_irq:
c5c98927
RK		 2008 if (host->tx_chan)
2009 dma_release_channel(host->tx_chan);
2010 if (host->rx_chan)
2011 dma_release_channel(host->rx_chan);
d59d77ed 2012 pm_runtime_put_sync(host->dev);
37f6190d 2013 pm_runtime_disable(host->dev);
a45c6cb8 2014 clk_put(host->fclk);
cd03d9a8 2015 if (host->dbclk) {
94c18149 2016 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 2017 clk_put(host->dbclk);
2018 }
a45c6cb8
MC		 2019err1:
2020 iounmap(host->base);
db0fefc5
AH		 2021 platform_set_drvdata(pdev, NULL);
2022 mmc_free_host(mmc);
2023err_alloc:
2024 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2025err:
48b332f9
RK		 2026 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2027 if (res)
2028 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2029 return ret;
2030}
2031
efa25fd3 2032static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2033{
70a3341a 2034 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2035 struct resource *res;
2036
927ce944
FB		 2037 pm_runtime_get_sync(host->dev);
2038 mmc_remove_host(host->mmc);
2039 if (host->use_reg)
2040 omap_hsmmc_reg_put(host);
2041 if (host->pdata->cleanup)
2042 host->pdata->cleanup(&pdev->dev);
2043 free_irq(host->irq, host);
2044 if (mmc_slot(host).card_detect_irq)
2045 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 2046
c5c98927
RK		 2047 if (host->tx_chan)
2048 dma_release_channel(host->tx_chan);
2049 if (host->rx_chan)
2050 dma_release_channel(host->rx_chan);
2051
927ce944
FB		 2052 pm_runtime_put_sync(host->dev);
2053 pm_runtime_disable(host->dev);
2054 clk_put(host->fclk);
cd03d9a8 2055 if (host->dbclk) {
94c18149 2056 clk_disable_unprepare(host->dbclk);
927ce944 2057 clk_put(host->dbclk);
a45c6cb8
MC		 2058 }
2059
9ea28ecb 2060 omap_hsmmc_gpio_free(host->pdata);
927ce944 2061 iounmap(host->base);
9d1f0286 2062 mmc_free_host(host->mmc);
927ce944 2063
a45c6cb8
MC		 2064 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2065 if (res)
984b203a 2066 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2067 platform_set_drvdata(pdev, NULL);
2068
2069 return 0;
2070}
2071
2072#ifdef CONFIG_PM
a791daa1 2073static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2074{
2075 int ret = 0;
927ce944 2076 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2077
927ce944 2078 if (!host)
a45c6cb8
MC		 2079 return 0;
2080
927ce944
FB		 2081 if (host && host->suspended)
2082 return 0;
fa4aa2d4 2083
927ce944
FB		 2084 pm_runtime_get_sync(host->dev);
2085 host->suspended = 1;
2086 if (host->pdata->suspend) {
2087 ret = host->pdata->suspend(dev, host->slot_id);
31f9d463 2088 if (ret) {
927ce944
FB		 2089 dev_dbg(dev, "Unable to handle MMC board"
2090 " level suspend\n");
a6b2240d 2091 host->suspended = 0;
927ce944 2092 return ret;
a6b2240d 2093 }
927ce944
FB		 2094 }
2095 ret = mmc_suspend_host(host->mmc);
31f9d463 2096
927ce944
FB		 2097 if (ret) {
2098 host->suspended = 0;
2099 if (host->pdata->resume) {
c4c8eeb4 2100 if (host->pdata->resume(dev, host->slot_id))
927ce944 2101 dev_dbg(dev, "Unmask interrupt failed\n");
31f9d463 2102 }
927ce944
FB		 2103 goto err;
2104 }
31f9d463 2105
927ce944
FB		 2106 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2107 omap_hsmmc_disable_irq(host);
2108 OMAP_HSMMC_WRITE(host->base, HCTL,
2109 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2110 }
927ce944 2111
cd03d9a8 2112 if (host->dbclk)
94c18149 2113 clk_disable_unprepare(host->dbclk);
31f9d463
EP		 2114err:
2115 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2116 return ret;
2117}
2118
2119/* Routine to resume the MMC device */
a791daa1 2120static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2121{
2122 int ret = 0;
927ce944
FB		 2123 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2124
2125 if (!host)
2126 return 0;
a45c6cb8
MC		 2127
2128 if (host && !host->suspended)
2129 return 0;
2130
927ce944 2131 pm_runtime_get_sync(host->dev);
11dd62a7 2132
cd03d9a8 2133 if (host->dbclk)
94c18149 2134 clk_prepare_enable(host->dbclk);
2bec0893 2135
927ce944
FB		 2136 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2137 omap_hsmmc_conf_bus_power(host);
1b331e69 2138
927ce944
FB		 2139 if (host->pdata->resume) {
2140 ret = host->pdata->resume(dev, host->slot_id);
2141 if (ret)
2142 dev_dbg(dev, "Unmask interrupt failed\n");
2143 }
a45c6cb8 2144
927ce944 2145 omap_hsmmc_protect_card(host);
b62f6228 2146
927ce944
FB		 2147 /* Notify the core to resume the host */
2148 ret = mmc_resume_host(host->mmc);
2149 if (ret == 0)
2150 host->suspended = 0;
fa4aa2d4 2151
927ce944
FB		 2152 pm_runtime_mark_last_busy(host->dev);
2153 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2154
2155 return ret;
2156
a45c6cb8
MC		 2157}
2158
2159#else
70a3341a
DK		 2160#define omap_hsmmc_suspend NULL
2161#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2162#endif
2163
fa4aa2d4
B		 2164static int omap_hsmmc_runtime_suspend(struct device *dev)
2165{
2166 struct omap_hsmmc_host *host;
2167
2168 host = platform_get_drvdata(to_platform_device(dev));
2169 omap_hsmmc_context_save(host);
927ce944 2170 dev_dbg(dev, "disabled\n");
fa4aa2d4
B		 2171
2172 return 0;
2173}
2174
2175static int omap_hsmmc_runtime_resume(struct device *dev)
2176{
2177 struct omap_hsmmc_host *host;
2178
2179 host = platform_get_drvdata(to_platform_device(dev));
2180 omap_hsmmc_context_restore(host);
927ce944 2181 dev_dbg(dev, "enabled\n");
fa4aa2d4
B		 2182
2183 return 0;
2184}
2185
a791daa1 2186static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2187 .suspend = omap_hsmmc_suspend,
2188 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2189 .runtime_suspend = omap_hsmmc_runtime_suspend,
2190 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2191};
2192
2193static struct platform_driver omap_hsmmc_driver = {
efa25fd3
FB		 2194 .probe = omap_hsmmc_probe,
2195 .remove = __devexit_p(omap_hsmmc_remove),
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MC		 2196 .driver = {
2197 .name = DRIVER_NAME,
2198 .owner = THIS_MODULE,
a791daa1 2199 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2200 .of_match_table = of_match_ptr(omap_mmc_of_match),
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MC		 2201 },
2202};
2203
b796450b 2204module_platform_driver(omap_hsmmc_driver);
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MC		 2205MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2206MODULE_LICENSE("GPL");
2207MODULE_ALIAS("platform:" DRIVER_NAME);
2208MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)