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mmc: tegra: support SDHCI SPEC 300
[linux-2.6-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712
DK		 21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
a45c6cb8
MC		 23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
a45c6cb8
MC		 27#include <linux/timer.h>
28#include <linux/clk.h>
46856a68
RN		 29#include <linux/of.h>
30#include <linux/of_gpio.h>
31#include <linux/of_device.h>
a45c6cb8 32#include <linux/mmc/host.h>
13189e78 33#include <linux/mmc/core.h>
93caf8e6 34#include <linux/mmc/mmc.h>
a45c6cb8
MC		 35#include <linux/io.h>
36#include <linux/semaphore.h>
db0fefc5
AH		 37#include <linux/gpio.h>
38#include <linux/regulator/consumer.h>
fa4aa2d4 39#include <linux/pm_runtime.h>
ce491cf8 40#include <plat/dma.h>
a45c6cb8 41#include <mach/hardware.h>
ce491cf8
TL		 42#include <plat/board.h>
43#include <plat/mmc.h>
44#include <plat/cpu.h>
a45c6cb8
MC		 45
46/* OMAP HSMMC Host Controller Registers */
47#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 48#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 49#define OMAP_HSMMC_CON 0x002C
50#define OMAP_HSMMC_BLK 0x0104
51#define OMAP_HSMMC_ARG 0x0108
52#define OMAP_HSMMC_CMD 0x010C
53#define OMAP_HSMMC_RSP10 0x0110
54#define OMAP_HSMMC_RSP32 0x0114
55#define OMAP_HSMMC_RSP54 0x0118
56#define OMAP_HSMMC_RSP76 0x011C
57#define OMAP_HSMMC_DATA 0x0120
58#define OMAP_HSMMC_HCTL 0x0128
59#define OMAP_HSMMC_SYSCTL 0x012C
60#define OMAP_HSMMC_STAT 0x0130
61#define OMAP_HSMMC_IE 0x0134
62#define OMAP_HSMMC_ISE 0x0138
63#define OMAP_HSMMC_CAPA 0x0140
64
65#define VS18 (1 << 26)
66#define VS30 (1 << 25)
67#define SDVS18 (0x5 << 9)
68#define SDVS30 (0x6 << 9)
eb250826 69#define SDVS33 (0x7 << 9)
1b331e69 70#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 71#define SDVSCLR 0xFFFFF1FF
72#define SDVSDET 0x00000400
73#define AUTOIDLE 0x1
74#define SDBP (1 << 8)
75#define DTO 0xe
76#define ICE 0x1
77#define ICS 0x2
78#define CEN (1 << 2)
79#define CLKD_MASK 0x0000FFC0
80#define CLKD_SHIFT 6
81#define DTO_MASK 0x000F0000
82#define DTO_SHIFT 16
83#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 84#define BWR_ENABLE (1 << 4)
85#define BRR_ENABLE (1 << 5)
93caf8e6 86#define DTO_ENABLE (1 << 20)
a45c6cb8 87#define INIT_STREAM (1 << 1)
dba3c29e 88#define ACEN_ACMD12 (1 << 2)
a45c6cb8
MC		 89#define DP_SELECT (1 << 21)
90#define DDIR (1 << 4)
91#define DMA_EN 0x1
92#define MSBS (1 << 5)
93#define BCE (1 << 1)
94#define FOUR_BIT (1 << 1)
03b5d924 95#define DDR (1 << 19)
73153010 96#define DW8 (1 << 5)
a45c6cb8
MC		 97#define CC 0x1
98#define TC 0x02
99#define OD 0x1
100#define ERR (1 << 15)
101#define CMD_TIMEOUT (1 << 16)
102#define DATA_TIMEOUT (1 << 20)
103#define CMD_CRC (1 << 17)
104#define DATA_CRC (1 << 21)
105#define CARD_ERR (1 << 28)
106#define STAT_CLEAR 0xFFFFFFFF
107#define INIT_STREAM_CMD 0x00000000
108#define DUAL_VOLT_OCR_BIT 7
109#define SRC (1 << 25)
110#define SRD (1 << 26)
11dd62a7
DK		 111#define SOFTRESET (1 << 1)
112#define RESETDONE (1 << 0)
a45c6cb8 113
fa4aa2d4 114#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8 115#define MMC_TIMEOUT_MS 20
6b206efe
AS		 116#define OMAP_MMC_MIN_CLOCK 400000
117#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 118#define DRIVER_NAME "omap_hsmmc"
a45c6cb8 119
dba3c29e 120#define AUTO_CMD12 (1 << 0) /* Auto CMD12 support */
a45c6cb8
MC		 121/*
122 * One controller can have multiple slots, like on some omap boards using
123 * omap.c controller driver. Luckily this is not currently done on any known
124 * omap_hsmmc.c device.
125 */
126#define mmc_slot(host) (host->pdata->slots[host->slot_id])
127
128/*
129 * MMC Host controller read/write API's
130 */
131#define OMAP_HSMMC_READ(base, reg) \
132 __raw_readl((base) + OMAP_HSMMC_##reg)
133
134#define OMAP_HSMMC_WRITE(base, reg, val) \
135 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
136
9782aff8
PF		 137struct omap_hsmmc_next {
138 unsigned int dma_len;
139 s32 cookie;
140};
141
70a3341a 142struct omap_hsmmc_host {
a45c6cb8
MC		 143 struct device *dev;
144 struct mmc_host *mmc;
145 struct mmc_request *mrq;
146 struct mmc_command *cmd;
147 struct mmc_data *data;
148 struct clk *fclk;
a45c6cb8 149 struct clk *dbclk;
db0fefc5
AH		 150 /*
151 * vcc == configured supply
152 * vcc_aux == optional
153 * - MMC1, supply for DAT4..DAT7
154 * - MMC2/MMC2, external level shifter voltage supply, for
155 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
156 */
157 struct regulator *vcc;
158 struct regulator *vcc_aux;
a45c6cb8
MC		 159 void __iomem *base;
160 resource_size_t mapbase;
4dffd7a2 161 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 162 unsigned int dma_len;
0ccd76d4 163 unsigned int dma_sg_idx;
a45c6cb8 164 unsigned char bus_mode;
a3621465 165 unsigned char power_mode;
a45c6cb8
MC		 166 u32 *buffer;
167 u32 bytesleft;
168 int suspended;
169 int irq;
a45c6cb8 170 int use_dma, dma_ch;
f3e2f1dd 171 int dma_line_tx, dma_line_rx;
a45c6cb8 172 int slot_id;
4a694dc9 173 int response_busy;
11dd62a7 174 int context_loss;
623821f7 175 int vdd;
b62f6228
AH		 176 int protect_card;
177 int reqs_blocked;
db0fefc5 178 int use_reg;
b417577d 179 int req_in_progress;
dba3c29e 180 unsigned int flags;
9782aff8 181 struct omap_hsmmc_next next_data;
11dd62a7 182
a45c6cb8
MC		 183 struct omap_mmc_platform_data *pdata;
184};
185
db0fefc5
AH		 186static int omap_hsmmc_card_detect(struct device *dev, int slot)
187{
188 struct omap_mmc_platform_data *mmc = dev->platform_data;
189
190 /* NOTE: assumes card detect signal is active-low */
191 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
192}
193
194static int omap_hsmmc_get_wp(struct device *dev, int slot)
195{
196 struct omap_mmc_platform_data *mmc = dev->platform_data;
197
198 /* NOTE: assumes write protect signal is active-high */
199 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
200}
201
202static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
203{
204 struct omap_mmc_platform_data *mmc = dev->platform_data;
205
206 /* NOTE: assumes card detect signal is active-low */
207 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
208}
209
210#ifdef CONFIG_PM
211
212static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
213{
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
215
216 disable_irq(mmc->slots[0].card_detect_irq);
217 return 0;
218}
219
220static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
221{
222 struct omap_mmc_platform_data *mmc = dev->platform_data;
223
224 enable_irq(mmc->slots[0].card_detect_irq);
225 return 0;
226}
227
228#else
229
230#define omap_hsmmc_suspend_cdirq NULL
231#define omap_hsmmc_resume_cdirq NULL
232
233#endif
234
b702b106
AH		 235#ifdef CONFIG_REGULATOR
236
69b07ece 237static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 238 int vdd)
239{
240 struct omap_hsmmc_host *host =
241 platform_get_drvdata(to_platform_device(dev));
242 int ret = 0;
243
244 /*
245 * If we don't see a Vcc regulator, assume it's a fixed
246 * voltage always-on regulator.
247 */
248 if (!host->vcc)
249 return 0;
1f84b71b
RN		 250 /*
251 * With DT, never turn OFF the regulator. This is because
252 * the pbias cell programming support is still missing when
253 * booting with Device tree
254 */
4d048f91 255 if (dev->of_node && !vdd)
1f84b71b 256 return 0;
db0fefc5
AH		 257
258 if (mmc_slot(host).before_set_reg)
259 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
260
261 /*
262 * Assume Vcc regulator is used only to power the card ... OMAP
263 * VDDS is used to power the pins, optionally with a transceiver to
264 * support cards using voltages other than VDDS (1.8V nominal). When a
265 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
266 *
267 * In some cases this regulator won't support enable/disable;
268 * e.g. it's a fixed rail for a WLAN chip.
269 *
270 * In other cases vcc_aux switches interface power. Example, for
271 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
272 * chips/cards need an interface voltage rail too.
273 */
274 if (power_on) {
99fc5131 275 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 276 /* Enable interface voltage rail, if needed */
277 if (ret == 0 && host->vcc_aux) {
278 ret = regulator_enable(host->vcc_aux);
279 if (ret < 0)
99fc5131
LW		 280 ret = mmc_regulator_set_ocr(host->mmc,
281 host->vcc, 0);
db0fefc5
AH		 282 }
283 } else {
99fc5131 284 /* Shut down the rail */
6da20c89
AH		 285 if (host->vcc_aux)
286 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 287 if (!ret) {
288 /* Then proceed to shut down the local regulator */
289 ret = mmc_regulator_set_ocr(host->mmc,
290 host->vcc, 0);
291 }
db0fefc5
AH		 292 }
293
294 if (mmc_slot(host).after_set_reg)
295 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
296
297 return ret;
298}
299
db0fefc5
AH		 300static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
301{
302 struct regulator *reg;
64be9782 303 int ocr_value = 0;
db0fefc5 304
1cb9af49 305 mmc_slot(host).set_power = omap_hsmmc_set_power;
db0fefc5
AH		 306
307 reg = regulator_get(host->dev, "vmmc");
308 if (IS_ERR(reg)) {
309 dev_dbg(host->dev, "vmmc regulator missing\n");
db0fefc5
AH		 310 } else {
311 host->vcc = reg;
64be9782 312 ocr_value = mmc_regulator_get_ocrmask(reg);
313 if (!mmc_slot(host).ocr_mask) {
314 mmc_slot(host).ocr_mask = ocr_value;
315 } else {
316 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
2cecdf00 317 dev_err(host->dev, "ocrmask %x is not supported\n",
e3f1adb6 318 mmc_slot(host).ocr_mask);
64be9782 319 mmc_slot(host).ocr_mask = 0;
320 return -EINVAL;
321 }
322 }
db0fefc5
AH		 323
324 /* Allow an aux regulator */
325 reg = regulator_get(host->dev, "vmmc_aux");
326 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
327
b1c1df7a
B		 328 /* For eMMC do not power off when not in sleep state */
329 if (mmc_slot(host).no_regulator_off_init)
330 return 0;
db0fefc5
AH		 331 /*
332 * UGLY HACK: workaround regulator framework bugs.
333 * When the bootloader leaves a supply active, it's
334 * initialized with zero usecount ... and we can't
335 * disable it without first enabling it. Until the
336 * framework is fixed, we need a workaround like this
337 * (which is safe for MMC, but not in general).
338 */
e840ce13
AH		 339 if (regulator_is_enabled(host->vcc) > 0 ||
340 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
341 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
342
343 mmc_slot(host).set_power(host->dev, host->slot_id,
344 1, vdd);
345 mmc_slot(host).set_power(host->dev, host->slot_id,
346 0, 0);
db0fefc5
AH		 347 }
348 }
349
350 return 0;
db0fefc5
AH		 351}
352
353static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
354{
355 regulator_put(host->vcc);
356 regulator_put(host->vcc_aux);
357 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 358}
359
b702b106
AH		 360static inline int omap_hsmmc_have_reg(void)
361{
362 return 1;
363}
364
365#else
366
367static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
368{
369 return -EINVAL;
370}
371
372static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
373{
374}
375
376static inline int omap_hsmmc_have_reg(void)
377{
378 return 0;
379}
380
381#endif
382
383static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
384{
385 int ret;
386
387 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 388 if (pdata->slots[0].cover)
389 pdata->slots[0].get_cover_state =
390 omap_hsmmc_get_cover_state;
391 else
392 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
393 pdata->slots[0].card_detect_irq =
394 gpio_to_irq(pdata->slots[0].switch_pin);
395 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
396 if (ret)
397 return ret;
398 ret = gpio_direction_input(pdata->slots[0].switch_pin);
399 if (ret)
400 goto err_free_sp;
401 } else
402 pdata->slots[0].switch_pin = -EINVAL;
403
404 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
405 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
406 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
407 if (ret)
408 goto err_free_cd;
409 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
410 if (ret)
411 goto err_free_wp;
412 } else
413 pdata->slots[0].gpio_wp = -EINVAL;
414
415 return 0;
416
417err_free_wp:
418 gpio_free(pdata->slots[0].gpio_wp);
419err_free_cd:
420 if (gpio_is_valid(pdata->slots[0].switch_pin))
421err_free_sp:
422 gpio_free(pdata->slots[0].switch_pin);
423 return ret;
424}
425
426static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
427{
428 if (gpio_is_valid(pdata->slots[0].gpio_wp))
429 gpio_free(pdata->slots[0].gpio_wp);
430 if (gpio_is_valid(pdata->slots[0].switch_pin))
431 gpio_free(pdata->slots[0].switch_pin);
432}
433
e0c7f99b
AS		 434/*
435 * Start clock to the card
436 */
437static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
438{
439 OMAP_HSMMC_WRITE(host->base, SYSCTL,
440 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
441}
442
a45c6cb8
MC		 443/*
444 * Stop clock to the card
445 */
70a3341a 446static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 447{
448 OMAP_HSMMC_WRITE(host->base, SYSCTL,
449 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
450 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
451 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
452}
453
93caf8e6
AH		 454static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
455 struct mmc_command *cmd)
b417577d
AH		 456{
457 unsigned int irq_mask;
458
459 if (host->use_dma)
460 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
461 else
462 irq_mask = INT_EN_MASK;
463
93caf8e6
AH		 464 /* Disable timeout for erases */
465 if (cmd->opcode == MMC_ERASE)
466 irq_mask &= ~DTO_ENABLE;
467
b417577d
AH		 468 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
469 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
470 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
471}
472
473static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
474{
475 OMAP_HSMMC_WRITE(host->base, ISE, 0);
476 OMAP_HSMMC_WRITE(host->base, IE, 0);
477 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
478}
479
ac330f44 480/* Calculate divisor for the given clock frequency */
d83b6e03 481static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 482{
483 u16 dsor = 0;
484
485 if (ios->clock) {
d83b6e03 486 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ac330f44
AS		 487 if (dsor > 250)
488 dsor = 250;
489 }
490
491 return dsor;
492}
493
5934df2f
AS		 494static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
495{
496 struct mmc_ios *ios = &host->mmc->ios;
497 unsigned long regval;
498 unsigned long timeout;
499
500 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
501
502 omap_hsmmc_stop_clock(host);
503
504 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
505 regval = regval & ~(CLKD_MASK | DTO_MASK);
d83b6e03 506 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
5934df2f
AS		 507 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
508 OMAP_HSMMC_WRITE(host->base, SYSCTL,
509 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
510
511 /* Wait till the ICS bit is set */
512 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
513 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
514 && time_before(jiffies, timeout))
515 cpu_relax();
516
517 omap_hsmmc_start_clock(host);
518}
519
3796fb8a
AS		 520static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
521{
522 struct mmc_ios *ios = &host->mmc->ios;
523 u32 con;
524
525 con = OMAP_HSMMC_READ(host->base, CON);
03b5d924
B		 526 if (ios->timing == MMC_TIMING_UHS_DDR50)
527 con |= DDR; /* configure in DDR mode */
528 else
529 con &= ~DDR;
3796fb8a
AS		 530 switch (ios->bus_width) {
531 case MMC_BUS_WIDTH_8:
532 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
533 break;
534 case MMC_BUS_WIDTH_4:
535 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
536 OMAP_HSMMC_WRITE(host->base, HCTL,
537 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
538 break;
539 case MMC_BUS_WIDTH_1:
540 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
541 OMAP_HSMMC_WRITE(host->base, HCTL,
542 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
543 break;
544 }
545}
546
547static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
548{
549 struct mmc_ios *ios = &host->mmc->ios;
550 u32 con;
551
552 con = OMAP_HSMMC_READ(host->base, CON);
553 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
554 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
555 else
556 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
557}
558
11dd62a7
DK		 559#ifdef CONFIG_PM
560
561/*
562 * Restore the MMC host context, if it was lost as result of a
563 * power state change.
564 */
70a3341a 565static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 566{
567 struct mmc_ios *ios = &host->mmc->ios;
568 struct omap_mmc_platform_data *pdata = host->pdata;
569 int context_loss = 0;
3796fb8a 570 u32 hctl, capa;
11dd62a7
DK		 571 unsigned long timeout;
572
573 if (pdata->get_context_loss_count) {
574 context_loss = pdata->get_context_loss_count(host->dev);
575 if (context_loss < 0)
576 return 1;
577 }
578
579 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
580 context_loss == host->context_loss ? "not " : "");
581 if (host->context_loss == context_loss)
582 return 1;
583
584 /* Wait for hardware reset */
585 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
586 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
587 && time_before(jiffies, timeout))
588 ;
589
590 /* Do software reset */
591 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
592 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
593 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
594 && time_before(jiffies, timeout))
595 ;
596
597 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
598 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
599
c2200efb 600 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 601 if (host->power_mode != MMC_POWER_OFF &&
602 (1 << ios->vdd) <= MMC_VDD_23_24)
603 hctl = SDVS18;
604 else
605 hctl = SDVS30;
606 capa = VS30 | VS18;
607 } else {
608 hctl = SDVS18;
609 capa = VS18;
610 }
611
612 OMAP_HSMMC_WRITE(host->base, HCTL,
613 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
614
615 OMAP_HSMMC_WRITE(host->base, CAPA,
616 OMAP_HSMMC_READ(host->base, CAPA) | capa);
617
618 OMAP_HSMMC_WRITE(host->base, HCTL,
619 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
620
621 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
622 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
623 && time_before(jiffies, timeout))
624 ;
625
b417577d 626 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 627
628 /* Do not initialize card-specific things if the power is off */
629 if (host->power_mode == MMC_POWER_OFF)
630 goto out;
631
3796fb8a 632 omap_hsmmc_set_bus_width(host);
11dd62a7 633
5934df2f 634 omap_hsmmc_set_clock(host);
11dd62a7 635
3796fb8a
AS		 636 omap_hsmmc_set_bus_mode(host);
637
11dd62a7
DK		 638out:
639 host->context_loss = context_loss;
640
641 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
642 return 0;
643}
644
645/*
646 * Save the MMC host context (store the number of power state changes so far).
647 */
70a3341a 648static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 649{
650 struct omap_mmc_platform_data *pdata = host->pdata;
651 int context_loss;
652
653 if (pdata->get_context_loss_count) {
654 context_loss = pdata->get_context_loss_count(host->dev);
655 if (context_loss < 0)
656 return;
657 host->context_loss = context_loss;
658 }
659}
660
661#else
662
70a3341a 663static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 664{
665 return 0;
666}
667
70a3341a 668static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 669{
670}
671
672#endif
673
a45c6cb8
MC		 674/*
675 * Send init stream sequence to card
676 * before sending IDLE command
677 */
70a3341a 678static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 679{
680 int reg = 0;
681 unsigned long timeout;
682
b62f6228
AH		 683 if (host->protect_card)
684 return;
685
a45c6cb8 686 disable_irq(host->irq);
b417577d
AH		 687
688 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 689 OMAP_HSMMC_WRITE(host->base, CON,
690 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
691 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
692
693 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
694 while ((reg != CC) && time_before(jiffies, timeout))
695 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
696
697 OMAP_HSMMC_WRITE(host->base, CON,
698 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 699
700 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
701 OMAP_HSMMC_READ(host->base, STAT);
702
a45c6cb8
MC		 703 enable_irq(host->irq);
704}
705
706static inline
70a3341a 707int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 708{
709 int r = 1;
710
191d1f1d
DK		 711 if (mmc_slot(host).get_cover_state)
712 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 713 return r;
714}
715
716static ssize_t
70a3341a 717omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 718 char *buf)
719{
720 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 721 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 722
70a3341a
DK		 723 return sprintf(buf, "%s\n",
724 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 725}
726
70a3341a 727static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 728
729static ssize_t
70a3341a 730omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 731 char *buf)
732{
733 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 734 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 735
191d1f1d 736 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 737}
738
70a3341a 739static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 740
741/*
742 * Configure the response type and send the cmd.
743 */
744static void
70a3341a 745omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 746 struct mmc_data *data)
747{
748 int cmdreg = 0, resptype = 0, cmdtype = 0;
749
750 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
751 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
752 host->cmd = cmd;
753
93caf8e6 754 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 755
4a694dc9 756 host->response_busy = 0;
a45c6cb8
MC		 757 if (cmd->flags & MMC_RSP_PRESENT) {
758 if (cmd->flags & MMC_RSP_136)
759 resptype = 1;
4a694dc9
AH		 760 else if (cmd->flags & MMC_RSP_BUSY) {
761 resptype = 3;
762 host->response_busy = 1;
763 } else
a45c6cb8
MC		 764 resptype = 2;
765 }
766
767 /*
768 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
769 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
770 * a val of 0x3, rest 0x0.
771 */
772 if (cmd == host->mrq->stop)
773 cmdtype = 0x3;
774
775 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
dba3c29e
B		 776 if ((host->flags & AUTO_CMD12) && mmc_op_multi(cmd->opcode))
777 cmdreg |= ACEN_ACMD12;
a45c6cb8
MC		 778
779 if (data) {
780 cmdreg |= DP_SELECT | MSBS | BCE;
781 if (data->flags & MMC_DATA_READ)
782 cmdreg |= DDIR;
783 else
784 cmdreg &= ~(DDIR);
785 }
786
787 if (host->use_dma)
788 cmdreg |= DMA_EN;
789
b417577d 790 host->req_in_progress = 1;
4dffd7a2 791
a45c6cb8
MC		 792 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
793 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
794}
795
0ccd76d4 796static int
70a3341a 797omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 798{
799 if (data->flags & MMC_DATA_WRITE)
800 return DMA_TO_DEVICE;
801 else
802 return DMA_FROM_DEVICE;
803}
804
b417577d
AH		 805static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
806{
807 int dma_ch;
31463b14 808 unsigned long flags;
b417577d 809
31463b14 810 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 811 host->req_in_progress = 0;
812 dma_ch = host->dma_ch;
31463b14 813 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 814
815 omap_hsmmc_disable_irq(host);
816 /* Do not complete the request if DMA is still in progress */
817 if (mrq->data && host->use_dma && dma_ch != -1)
818 return;
819 host->mrq = NULL;
820 mmc_request_done(host->mmc, mrq);
821}
822
a45c6cb8
MC		 823/*
824 * Notify the transfer complete to MMC core
825 */
826static void
70a3341a 827omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 828{
4a694dc9
AH		 829 if (!data) {
830 struct mmc_request *mrq = host->mrq;
831
23050103
AH		 832 /* TC before CC from CMD6 - don't know why, but it happens */
833 if (host->cmd && host->cmd->opcode == 6 &&
834 host->response_busy) {
835 host->response_busy = 0;
836 return;
837 }
838
b417577d 839 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 840 return;
841 }
842
a45c6cb8
MC		 843 host->data = NULL;
844
a45c6cb8
MC		 845 if (!data->error)
846 data->bytes_xfered += data->blocks * (data->blksz);
847 else
848 data->bytes_xfered = 0;
849
dba3c29e
B		 850 if (data->stop && ((!(host->flags & AUTO_CMD12)) || data->error)) {
851 omap_hsmmc_start_command(host, data->stop, NULL);
852 } else {
853 if (data->stop)
854 data->stop->resp[0] = OMAP_HSMMC_READ(host->base,
855 RSP76);
b417577d 856 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8 857 }
a45c6cb8
MC		 858}
859
860/*
861 * Notify the core about command completion
862 */
863static void
70a3341a 864omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 865{
866 host->cmd = NULL;
867
868 if (cmd->flags & MMC_RSP_PRESENT) {
869 if (cmd->flags & MMC_RSP_136) {
870 /* response type 2 */
871 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
872 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
873 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
874 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
875 } else {
876 /* response types 1, 1b, 3, 4, 5, 6 */
877 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
878 }
879 }
b417577d
AH		 880 if ((host->data == NULL && !host->response_busy) || cmd->error)
881 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 882}
883
884/*
885 * DMA clean up for command errors
886 */
70a3341a 887static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 888{
b417577d 889 int dma_ch;
31463b14 890 unsigned long flags;
b417577d 891
82788ff5 892 host->data->error = errno;
a45c6cb8 893
31463b14 894 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 895 dma_ch = host->dma_ch;
896 host->dma_ch = -1;
31463b14 897 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 898
899 if (host->use_dma && dma_ch != -1) {
a9120c33
PF		 900 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
901 host->data->sg_len,
70a3341a 902 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 903 omap_free_dma(dma_ch);
053bf34f 904 host->data->host_cookie = 0;
a45c6cb8
MC		 905 }
906 host->data = NULL;
a45c6cb8
MC		 907}
908
909/*
910 * Readable error output
911 */
912#ifdef CONFIG_MMC_DEBUG
699b958b 913static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 914{
915 /* --- means reserved bit without definition at documentation */
70a3341a 916 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 917 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
918 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
919 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
920 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 921 };
922 char res[256];
923 char *buf = res;
924 int len, i;
925
926 len = sprintf(buf, "MMC IRQ 0x%x :", status);
927 buf += len;
928
70a3341a 929 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 930 if (status & (1 << i)) {
70a3341a 931 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 932 buf += len;
933 }
934
935 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
936}
699b958b
AH		 937#else
938static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
939 u32 status)
940{
941}
a45c6cb8
MC		 942#endif /* CONFIG_MMC_DEBUG */
943
3ebf74b1
JP		 944/*
945 * MMC controller internal state machines reset
946 *
947 * Used to reset command or data internal state machines, using respectively
948 * SRC or SRD bit of SYSCTL register
949 * Can be called from interrupt context
950 */
70a3341a
DK		 951static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
952 unsigned long bit)
3ebf74b1
JP		 953{
954 unsigned long i = 0;
955 unsigned long limit = (loops_per_jiffy *
956 msecs_to_jiffies(MMC_TIMEOUT_MS));
957
958 OMAP_HSMMC_WRITE(host->base, SYSCTL,
959 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
960
07ad64b6
MC		 961 /*
962 * OMAP4 ES2 and greater has an updated reset logic.
963 * Monitor a 0->1 transition first
964 */
965 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 966 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 967 && (i++ < limit))
968 cpu_relax();
969 }
970 i = 0;
971
3ebf74b1
JP		 972 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
973 (i++ < limit))
974 cpu_relax();
975
976 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
977 dev_err(mmc_dev(host->mmc),
978 "Timeout waiting on controller reset in %s\n",
979 __func__);
980}
a45c6cb8 981
b417577d 982static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 983{
a45c6cb8 984 struct mmc_data *data;
b417577d
AH		 985 int end_cmd = 0, end_trans = 0;
986
987 if (!host->req_in_progress) {
988 do {
989 OMAP_HSMMC_WRITE(host->base, STAT, status);
990 /* Flush posted write */
991 status = OMAP_HSMMC_READ(host->base, STAT);
992 } while (status & INT_EN_MASK);
993 return;
a45c6cb8
MC		 994 }
995
996 data = host->data;
a45c6cb8
MC		 997 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
998
999 if (status & ERR) {
699b958b 1000 omap_hsmmc_dbg_report_irq(host, status);
a45c6cb8
MC		 1001 if ((status & CMD_TIMEOUT) ||
1002 (status & CMD_CRC)) {
1003 if (host->cmd) {
1004 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1005 omap_hsmmc_reset_controller_fsm(host,
1006 SRC);
a45c6cb8
MC		 1007 host->cmd->error = -ETIMEDOUT;
1008 } else {
1009 host->cmd->error = -EILSEQ;
1010 }
1011 end_cmd = 1;
1012 }
4a694dc9
AH		 1013 if (host->data || host->response_busy) {
1014 if (host->data)
70a3341a
DK		 1015 omap_hsmmc_dma_cleanup(host,
1016 -ETIMEDOUT);
4a694dc9 1017 host->response_busy = 0;
70a3341a 1018 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1019 }
a45c6cb8
MC		 1020 }
1021 if ((status & DATA_TIMEOUT) ||
1022 (status & DATA_CRC)) {
4a694dc9
AH		 1023 if (host->data || host->response_busy) {
1024 int err = (status & DATA_TIMEOUT) ?
1025 -ETIMEDOUT : -EILSEQ;
1026
1027 if (host->data)
70a3341a 1028 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1029 else
4a694dc9
AH		 1030 host->mrq->cmd->error = err;
1031 host->response_busy = 0;
70a3341a 1032 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1033 end_trans = 1;
1034 }
1035 }
1036 if (status & CARD_ERR) {
1037 dev_dbg(mmc_dev(host->mmc),
1038 "Ignoring card err CMD%d\n", host->cmd->opcode);
1039 if (host->cmd)
1040 end_cmd = 1;
1041 if (host->data)
1042 end_trans = 1;
1043 }
1044 }
1045
1046 OMAP_HSMMC_WRITE(host->base, STAT, status);
1047
a8fe29d8 1048 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1049 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1050 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1051 omap_hsmmc_xfer_done(host, data);
b417577d 1052}
a45c6cb8 1053
b417577d
AH		 1054/*
1055 * MMC controller IRQ handler
1056 */
1057static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1058{
1059 struct omap_hsmmc_host *host = dev_id;
1060 int status;
1061
1062 status = OMAP_HSMMC_READ(host->base, STAT);
1063 do {
1064 omap_hsmmc_do_irq(host, status);
1065 /* Flush posted write */
1066 status = OMAP_HSMMC_READ(host->base, STAT);
1067 } while (status & INT_EN_MASK);
4dffd7a2 1068
a45c6cb8
MC		 1069 return IRQ_HANDLED;
1070}
1071
70a3341a 1072static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1073{
1074 unsigned long i;
1075
1076 OMAP_HSMMC_WRITE(host->base, HCTL,
1077 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1078 for (i = 0; i < loops_per_jiffy; i++) {
1079 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1080 break;
1081 cpu_relax();
1082 }
1083}
1084
a45c6cb8 1085/*
eb250826
DB		 1086 * Switch MMC interface voltage ... only relevant for MMC1.
1087 *
1088 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1089 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1090 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1091 */
70a3341a 1092static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1093{
1094 u32 reg_val = 0;
1095 int ret;
1096
1097 /* Disable the clocks */
fa4aa2d4 1098 pm_runtime_put_sync(host->dev);
cd03d9a8 1099 if (host->dbclk)
2bec0893 1100 clk_disable(host->dbclk);
a45c6cb8
MC		 1101
1102 /* Turn the power off */
1103 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1104
1105 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1106 if (!ret)
1107 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1108 vdd);
fa4aa2d4 1109 pm_runtime_get_sync(host->dev);
cd03d9a8 1110 if (host->dbclk)
2bec0893
AH		 1111 clk_enable(host->dbclk);
1112
a45c6cb8
MC		 1113 if (ret != 0)
1114 goto err;
1115
a45c6cb8
MC		 1116 OMAP_HSMMC_WRITE(host->base, HCTL,
1117 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1118 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1119
a45c6cb8
MC		 1120 /*
1121 * If a MMC dual voltage card is detected, the set_ios fn calls
1122 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1123 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1124 *
eb250826
DB		 1125 * Cope with a bit of slop in the range ... per data sheets:
1126 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1127 * but recommended values are 1.71V to 1.89V
1128 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1129 * but recommended values are 2.7V to 3.3V
1130 *
1131 * Board setup code shouldn't permit anything very out-of-range.
1132 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1133 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1134 */
eb250826 1135 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1136 reg_val |= SDVS18;
eb250826
DB		 1137 else
1138 reg_val |= SDVS30;
a45c6cb8
MC		 1139
1140 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1141 set_sd_bus_power(host);
a45c6cb8
MC		 1142
1143 return 0;
1144err:
1145 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1146 return ret;
1147}
1148
b62f6228
AH		 1149/* Protect the card while the cover is open */
1150static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1151{
1152 if (!mmc_slot(host).get_cover_state)
1153 return;
1154
1155 host->reqs_blocked = 0;
1156 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1157 if (host->protect_card) {
2cecdf00 1158 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1159 "card is now accessible\n",
1160 mmc_hostname(host->mmc));
1161 host->protect_card = 0;
1162 }
1163 } else {
1164 if (!host->protect_card) {
2cecdf00 1165 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1166 "card is now inaccessible\n",
1167 mmc_hostname(host->mmc));
1168 host->protect_card = 1;
1169 }
1170 }
1171}
1172
a45c6cb8 1173/*
7efab4f3 1174 * irq handler to notify the core about card insertion/removal
a45c6cb8 1175 */
7efab4f3 1176static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1177{
7efab4f3 1178 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1179 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1180 int carddetect;
1181
1182 if (host->suspended)
7efab4f3 1183 return IRQ_HANDLED;
a6b2240d
AH		 1184
1185 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1186
191d1f1d 1187 if (slot->card_detect)
db0fefc5 1188 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1189 else {
1190 omap_hsmmc_protect_card(host);
a6b2240d 1191 carddetect = -ENOSYS;
b62f6228 1192 }
a45c6cb8 1193
cdeebadd 1194 if (carddetect)
a45c6cb8 1195 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1196 else
a45c6cb8 1197 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1198 return IRQ_HANDLED;
1199}
1200
70a3341a 1201static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1202 struct mmc_data *data)
1203{
1204 int sync_dev;
1205
f3e2f1dd
GI		 1206 if (data->flags & MMC_DATA_WRITE)
1207 sync_dev = host->dma_line_tx;
1208 else
1209 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1210 return sync_dev;
1211}
1212
70a3341a 1213static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1214 struct mmc_data *data,
1215 struct scatterlist *sgl)
1216{
1217 int blksz, nblk, dma_ch;
1218
1219 dma_ch = host->dma_ch;
1220 if (data->flags & MMC_DATA_WRITE) {
1221 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1222 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1223 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1224 sg_dma_address(sgl), 0, 0);
1225 } else {
1226 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1227 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1228 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1229 sg_dma_address(sgl), 0, 0);
1230 }
1231
1232 blksz = host->data->blksz;
1233 nblk = sg_dma_len(sgl) / blksz;
1234
1235 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1236 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1237 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1238 !(data->flags & MMC_DATA_WRITE));
1239
1240 omap_start_dma(dma_ch);
1241}
1242
a45c6cb8
MC		 1243/*
1244 * DMA call back function
1245 */
b417577d 1246static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1247{
b417577d 1248 struct omap_hsmmc_host *host = cb_data;
770d7432 1249 struct mmc_data *data;
b417577d 1250 int dma_ch, req_in_progress;
31463b14 1251 unsigned long flags;
a45c6cb8 1252
f3584e5e
V		 1253 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1254 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1255 ch_status);
1256 return;
1257 }
a45c6cb8 1258
31463b14 1259 spin_lock_irqsave(&host->irq_lock, flags);
b417577d 1260 if (host->dma_ch < 0) {
31463b14 1261 spin_unlock_irqrestore(&host->irq_lock, flags);
a45c6cb8 1262 return;
b417577d 1263 }
a45c6cb8 1264
770d7432 1265 data = host->mrq->data;
0ccd76d4
JY		 1266 host->dma_sg_idx++;
1267 if (host->dma_sg_idx < host->dma_len) {
1268 /* Fire up the next transfer. */
b417577d
AH		 1269 omap_hsmmc_config_dma_params(host, data,
1270 data->sg + host->dma_sg_idx);
31463b14 1271 spin_unlock_irqrestore(&host->irq_lock, flags);
0ccd76d4
JY		 1272 return;
1273 }
1274
9782aff8
PF		 1275 if (!data->host_cookie)
1276 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1277 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1278
1279 req_in_progress = host->req_in_progress;
1280 dma_ch = host->dma_ch;
a45c6cb8 1281 host->dma_ch = -1;
31463b14 1282 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 1283
1284 omap_free_dma(dma_ch);
1285
1286 /* If DMA has finished after TC, complete the request */
1287 if (!req_in_progress) {
1288 struct mmc_request *mrq = host->mrq;
1289
1290 host->mrq = NULL;
1291 mmc_request_done(host->mmc, mrq);
1292 }
a45c6cb8
MC		 1293}
1294
9782aff8
PF		 1295static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1296 struct mmc_data *data,
1297 struct omap_hsmmc_next *next)
1298{
1299 int dma_len;
1300
1301 if (!next && data->host_cookie &&
1302 data->host_cookie != host->next_data.cookie) {
2cecdf00 1303 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1304 " host->next_data.cookie %d\n",
1305 __func__, data->host_cookie, host->next_data.cookie);
1306 data->host_cookie = 0;
1307 }
1308
1309 /* Check if next job is already prepared */
1310 if (next ||
1311 (!next && data->host_cookie != host->next_data.cookie)) {
1312 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1313 data->sg_len,
1314 omap_hsmmc_get_dma_dir(host, data));
1315
1316 } else {
1317 dma_len = host->next_data.dma_len;
1318 host->next_data.dma_len = 0;
1319 }
1320
1321
1322 if (dma_len == 0)
1323 return -EINVAL;
1324
1325 if (next) {
1326 next->dma_len = dma_len;
1327 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1328 } else
1329 host->dma_len = dma_len;
1330
1331 return 0;
1332}
1333
a45c6cb8
MC		 1334/*
1335 * Routine to configure and start DMA for the MMC card
1336 */
70a3341a
DK		 1337static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1338 struct mmc_request *req)
a45c6cb8 1339{
b417577d 1340 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1341 struct mmc_data *data = req->data;
1342
0ccd76d4 1343 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1344 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1345 struct scatterlist *sgl;
1346
1347 sgl = data->sg + i;
1348 if (sgl->length % data->blksz)
1349 return -EINVAL;
1350 }
1351 if ((data->blksz % 4) != 0)
1352 /* REVISIT: The MMC buffer increments only when MSB is written.
1353 * Return error for blksz which is non multiple of four.
1354 */
1355 return -EINVAL;
1356
b417577d 1357 BUG_ON(host->dma_ch != -1);
a45c6cb8 1358
70a3341a
DK		 1359 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1360 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1361 if (ret != 0) {
0ccd76d4 1362 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1363 "%s: omap_request_dma() failed with %d\n",
1364 mmc_hostname(host->mmc), ret);
1365 return ret;
1366 }
9782aff8
PF		 1367 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1368 if (ret)
1369 return ret;
a45c6cb8 1370
a45c6cb8 1371 host->dma_ch = dma_ch;
0ccd76d4 1372 host->dma_sg_idx = 0;
a45c6cb8 1373
70a3341a 1374 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1375
a45c6cb8
MC		 1376 return 0;
1377}
1378
70a3341a 1379static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1380 unsigned int timeout_ns,
1381 unsigned int timeout_clks)
a45c6cb8
MC		 1382{
1383 unsigned int timeout, cycle_ns;
1384 uint32_t reg, clkd, dto = 0;
1385
1386 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1387 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1388 if (clkd == 0)
1389 clkd = 1;
1390
1391 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1392 timeout = timeout_ns / cycle_ns;
1393 timeout += timeout_clks;
a45c6cb8
MC		 1394 if (timeout) {
1395 while ((timeout & 0x80000000) == 0) {
1396 dto += 1;
1397 timeout <<= 1;
1398 }
1399 dto = 31 - dto;
1400 timeout <<= 1;
1401 if (timeout && dto)
1402 dto += 1;
1403 if (dto >= 13)
1404 dto -= 13;
1405 else
1406 dto = 0;
1407 if (dto > 14)
1408 dto = 14;
1409 }
1410
1411 reg &= ~DTO_MASK;
1412 reg |= dto << DTO_SHIFT;
1413 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1414}
1415
1416/*
1417 * Configure block length for MMC/SD cards and initiate the transfer.
1418 */
1419static int
70a3341a 1420omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1421{
1422 int ret;
1423 host->data = req->data;
1424
1425 if (req->data == NULL) {
a45c6cb8 1426 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1427 /*
1428 * Set an arbitrary 100ms data timeout for commands with
1429 * busy signal.
1430 */
1431 if (req->cmd->flags & MMC_RSP_BUSY)
1432 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1433 return 0;
1434 }
1435
1436 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1437 | (req->data->blocks << 16));
e2bf08d6 1438 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1439
a45c6cb8 1440 if (host->use_dma) {
70a3341a 1441 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1442 if (ret != 0) {
1443 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1444 return ret;
1445 }
1446 }
1447 return 0;
1448}
1449
9782aff8
PF		 1450static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1451 int err)
1452{
1453 struct omap_hsmmc_host *host = mmc_priv(mmc);
1454 struct mmc_data *data = mrq->data;
1455
1456 if (host->use_dma) {
053bf34f
PF		 1457 if (data->host_cookie)
1458 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1459 data->sg_len,
1460 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1461 data->host_cookie = 0;
1462 }
1463}
1464
1465static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1466 bool is_first_req)
1467{
1468 struct omap_hsmmc_host *host = mmc_priv(mmc);
1469
1470 if (mrq->data->host_cookie) {
1471 mrq->data->host_cookie = 0;
1472 return ;
1473 }
1474
1475 if (host->use_dma)
1476 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1477 &host->next_data))
1478 mrq->data->host_cookie = 0;
1479}
1480
a45c6cb8
MC		 1481/*
1482 * Request function. for read/write operation
1483 */
70a3341a 1484static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1485{
70a3341a 1486 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1487 int err;
a45c6cb8 1488
b417577d
AH		 1489 BUG_ON(host->req_in_progress);
1490 BUG_ON(host->dma_ch != -1);
1491 if (host->protect_card) {
1492 if (host->reqs_blocked < 3) {
1493 /*
1494 * Ensure the controller is left in a consistent
1495 * state by resetting the command and data state
1496 * machines.
1497 */
1498 omap_hsmmc_reset_controller_fsm(host, SRD);
1499 omap_hsmmc_reset_controller_fsm(host, SRC);
1500 host->reqs_blocked += 1;
1501 }
1502 req->cmd->error = -EBADF;
1503 if (req->data)
1504 req->data->error = -EBADF;
1505 req->cmd->retries = 0;
1506 mmc_request_done(mmc, req);
1507 return;
1508 } else if (host->reqs_blocked)
1509 host->reqs_blocked = 0;
a45c6cb8
MC		 1510 WARN_ON(host->mrq != NULL);
1511 host->mrq = req;
70a3341a 1512 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1513 if (err) {
1514 req->cmd->error = err;
1515 if (req->data)
1516 req->data->error = err;
1517 host->mrq = NULL;
1518 mmc_request_done(mmc, req);
1519 return;
1520 }
1521
70a3341a 1522 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1523}
1524
a45c6cb8 1525/* Routine to configure clock values. Exposed API to core */
70a3341a 1526static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1527{
70a3341a 1528 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1529 int do_send_init_stream = 0;
a45c6cb8 1530
fa4aa2d4 1531 pm_runtime_get_sync(host->dev);
5e2ea617 1532
a3621465
AH		 1533 if (ios->power_mode != host->power_mode) {
1534 switch (ios->power_mode) {
1535 case MMC_POWER_OFF:
1536 mmc_slot(host).set_power(host->dev, host->slot_id,
1537 0, 0);
623821f7 1538 host->vdd = 0;
a3621465
AH		 1539 break;
1540 case MMC_POWER_UP:
1541 mmc_slot(host).set_power(host->dev, host->slot_id,
1542 1, ios->vdd);
623821f7 1543 host->vdd = ios->vdd;
a3621465
AH		 1544 break;
1545 case MMC_POWER_ON:
1546 do_send_init_stream = 1;
1547 break;
1548 }
1549 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1550 }
1551
dd498eff
DK		 1552 /* FIXME: set registers based only on changes to ios */
1553
3796fb8a 1554 omap_hsmmc_set_bus_width(host);
a45c6cb8 1555
4621d5f8 1556 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1557 /* Only MMC1 can interface at 3V without some flavor
1558 * of external transceiver; but they all handle 1.8V.
1559 */
a45c6cb8 1560 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1f84b71b
RN		 1561 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1562 /*
1563 * With pbias cell programming missing, this
1564 * can't be allowed when booting with device
1565 * tree.
1566 */
4d048f91 1567 !host->dev->of_node) {
a45c6cb8
MC		 1568 /*
1569 * The mmc_select_voltage fn of the core does
1570 * not seem to set the power_mode to
1571 * MMC_POWER_UP upon recalculating the voltage.
1572 * vdd 1.8v.
1573 */
70a3341a
DK		 1574 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1575 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1576 "Switch operation failed\n");
1577 }
1578 }
1579
5934df2f 1580 omap_hsmmc_set_clock(host);
a45c6cb8 1581
a3621465 1582 if (do_send_init_stream)
a45c6cb8
MC		 1583 send_init_stream(host);
1584
3796fb8a 1585 omap_hsmmc_set_bus_mode(host);
5e2ea617 1586
fa4aa2d4 1587 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1588}
1589
1590static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1591{
70a3341a 1592 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1593
191d1f1d 1594 if (!mmc_slot(host).card_detect)
a45c6cb8 1595 return -ENOSYS;
db0fefc5 1596 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1597}
1598
1599static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1600{
70a3341a 1601 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1602
191d1f1d 1603 if (!mmc_slot(host).get_ro)
a45c6cb8 1604 return -ENOSYS;
191d1f1d 1605 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1606}
1607
4816858c
GI		 1608static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1609{
1610 struct omap_hsmmc_host *host = mmc_priv(mmc);
1611
1612 if (mmc_slot(host).init_card)
1613 mmc_slot(host).init_card(card);
1614}
1615
70a3341a 1616static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1617{
1618 u32 hctl, capa, value;
1619
1620 /* Only MMC1 supports 3.0V */
4621d5f8 1621 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1622 hctl = SDVS30;
1623 capa = VS30 | VS18;
1624 } else {
1625 hctl = SDVS18;
1626 capa = VS18;
1627 }
1628
1629 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1630 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1631
1632 value = OMAP_HSMMC_READ(host->base, CAPA);
1633 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1634
1635 /* Set the controller to AUTO IDLE mode */
1636 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1637 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1638
1639 /* Set SD bus power bit */
e13bb300 1640 set_sd_bus_power(host);
1b331e69
KK		 1641}
1642
70a3341a 1643static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1644{
70a3341a 1645 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1646
fa4aa2d4
B		 1647 pm_runtime_get_sync(host->dev);
1648
dd498eff
DK		 1649 return 0;
1650}
1651
907d2e7c 1652static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
dd498eff 1653{
70a3341a 1654 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1655
fa4aa2d4
B		 1656 pm_runtime_mark_last_busy(host->dev);
1657 pm_runtime_put_autosuspend(host->dev);
1658
dd498eff
DK		 1659 return 0;
1660}
1661
70a3341a
DK		 1662static const struct mmc_host_ops omap_hsmmc_ops = {
1663 .enable = omap_hsmmc_enable_fclk,
1664 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1665 .post_req = omap_hsmmc_post_req,
1666 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1667 .request = omap_hsmmc_request,
1668 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1669 .get_cd = omap_hsmmc_get_cd,
1670 .get_ro = omap_hsmmc_get_ro,
4816858c 1671 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1672 /* NYET -- enable_sdio_irq */
1673};
1674
d900f712
DK		 1675#ifdef CONFIG_DEBUG_FS
1676
70a3341a 1677static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1678{
1679 struct mmc_host *mmc = s->private;
70a3341a 1680 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1681 int context_loss = 0;
1682
70a3341a
DK		 1683 if (host->pdata->get_context_loss_count)
1684 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1685
907d2e7c
AH		 1686 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1687 mmc->index, host->context_loss, context_loss);
5e2ea617 1688
7a8c2cef 1689 if (host->suspended) {
dd498eff
DK		 1690 seq_printf(s, "host suspended, can't read registers\n");
1691 return 0;
1692 }
1693
fa4aa2d4 1694 pm_runtime_get_sync(host->dev);
d900f712
DK		 1695
1696 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1697 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1698 seq_printf(s, "CON:\t\t0x%08x\n",
1699 OMAP_HSMMC_READ(host->base, CON));
1700 seq_printf(s, "HCTL:\t\t0x%08x\n",
1701 OMAP_HSMMC_READ(host->base, HCTL));
1702 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1703 OMAP_HSMMC_READ(host->base, SYSCTL));
1704 seq_printf(s, "IE:\t\t0x%08x\n",
1705 OMAP_HSMMC_READ(host->base, IE));
1706 seq_printf(s, "ISE:\t\t0x%08x\n",
1707 OMAP_HSMMC_READ(host->base, ISE));
1708 seq_printf(s, "CAPA:\t\t0x%08x\n",
1709 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1710
fa4aa2d4
B		 1711 pm_runtime_mark_last_busy(host->dev);
1712 pm_runtime_put_autosuspend(host->dev);
dd498eff 1713
d900f712
DK		 1714 return 0;
1715}
1716
70a3341a 1717static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1718{
70a3341a 1719 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1720}
1721
1722static const struct file_operations mmc_regs_fops = {
70a3341a 1723 .open = omap_hsmmc_regs_open,
d900f712
DK		 1724 .read = seq_read,
1725 .llseek = seq_lseek,
1726 .release = single_release,
1727};
1728
70a3341a 1729static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1730{
1731 if (mmc->debugfs_root)
1732 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1733 mmc, &mmc_regs_fops);
1734}
1735
1736#else
1737
70a3341a 1738static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1739{
1740}
1741
1742#endif
1743
46856a68
RN		 1744#ifdef CONFIG_OF
1745static u16 omap4_reg_offset = 0x100;
1746
1747static const struct of_device_id omap_mmc_of_match[] = {
1748 {
1749 .compatible = "ti,omap2-hsmmc",
1750 },
1751 {
1752 .compatible = "ti,omap3-hsmmc",
1753 },
1754 {
1755 .compatible = "ti,omap4-hsmmc",
1756 .data = &omap4_reg_offset,
1757 },
1758 {},
b6d085f6 1759};
46856a68
RN		 1760MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1761
1762static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1763{
1764 struct omap_mmc_platform_data *pdata;
1765 struct device_node *np = dev->of_node;
1766 u32 bus_width;
1767
1768 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1769 if (!pdata)
1770 return NULL; /* out of memory */
1771
1772 if (of_find_property(np, "ti,dual-volt", NULL))
1773 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1774
1775 /* This driver only supports 1 slot */
1776 pdata->nr_slots = 1;
1777 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1778 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1779
1780 if (of_find_property(np, "ti,non-removable", NULL)) {
1781 pdata->slots[0].nonremovable = true;
1782 pdata->slots[0].no_regulator_off_init = true;
1783 }
1784 of_property_read_u32(np, "ti,bus-width", &bus_width);
1785 if (bus_width == 4)
1786 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1787 else if (bus_width == 8)
1788 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1789
1790 if (of_find_property(np, "ti,needs-special-reset", NULL))
1791 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1792
1793 return pdata;
1794}
1795#else
1796static inline struct omap_mmc_platform_data
1797 *of_get_hsmmc_pdata(struct device *dev)
1798{
1799 return NULL;
1800}
1801#endif
1802
efa25fd3 1803static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1804{
1805 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1806 struct mmc_host *mmc;
70a3341a 1807 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1808 struct resource *res;
db0fefc5 1809 int ret, irq;
46856a68
RN		 1810 const struct of_device_id *match;
1811
1812 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1813 if (match) {
1814 pdata = of_get_hsmmc_pdata(&pdev->dev);
1815 if (match->data) {
1816 u16 *offsetp = match->data;
1817 pdata->reg_offset = *offsetp;
1818 }
1819 }
a45c6cb8
MC		 1820
1821 if (pdata == NULL) {
1822 dev_err(&pdev->dev, "Platform Data is missing\n");
1823 return -ENXIO;
1824 }
1825
1826 if (pdata->nr_slots == 0) {
1827 dev_err(&pdev->dev, "No Slots\n");
1828 return -ENXIO;
1829 }
1830
1831 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1832 irq = platform_get_irq(pdev, 0);
1833 if (res == NULL || irq < 0)
1834 return -ENXIO;
1835
984b203a 1836 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1837 if (res == NULL)
1838 return -EBUSY;
1839
db0fefc5
AH		 1840 ret = omap_hsmmc_gpio_init(pdata);
1841 if (ret)
1842 goto err;
1843
70a3341a 1844 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1845 if (!mmc) {
1846 ret = -ENOMEM;
db0fefc5 1847 goto err_alloc;
a45c6cb8
MC		 1848 }
1849
1850 host = mmc_priv(mmc);
1851 host->mmc = mmc;
1852 host->pdata = pdata;
1853 host->dev = &pdev->dev;
1854 host->use_dma = 1;
1855 host->dev->dma_mask = &pdata->dma_mask;
1856 host->dma_ch = -1;
1857 host->irq = irq;
a45c6cb8 1858 host->slot_id = 0;
fc307df8 1859 host->mapbase = res->start + pdata->reg_offset;
a45c6cb8 1860 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1861 host->power_mode = MMC_POWER_OFF;
dba3c29e 1862 host->flags = AUTO_CMD12;
9782aff8 1863 host->next_data.cookie = 1;
a45c6cb8
MC		 1864
1865 platform_set_drvdata(pdev, host);
a45c6cb8 1866
7a8c2cef 1867 mmc->ops = &omap_hsmmc_ops;
dd498eff 1868
e0eb2424
AH		 1869 /*
1870 * If regulator_disable can only put vcc_aux to sleep then there is
1871 * no off state.
1872 */
1873 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1874 mmc_slot(host).no_off = 1;
1875
d418ed87
DM		 1876 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1877
1878 if (pdata->max_freq > 0)
1879 mmc->f_max = pdata->max_freq;
1880 else
1881 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1882
4dffd7a2 1883 spin_lock_init(&host->irq_lock);
a45c6cb8 1884
6f7607cc 1885 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1886 if (IS_ERR(host->fclk)) {
1887 ret = PTR_ERR(host->fclk);
1888 host->fclk = NULL;
a45c6cb8
MC		 1889 goto err1;
1890 }
1891
9b68256c
PW		 1892 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1893 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1894 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1895 }
dd498eff 1896
fa4aa2d4
B		 1897 pm_runtime_enable(host->dev);
1898 pm_runtime_get_sync(host->dev);
1899 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1900 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1901
92a3aebf
B		 1902 omap_hsmmc_context_save(host);
1903
cd03d9a8
RN		 1904 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1905 /*
1906 * MMC can still work without debounce clock.
1907 */
1908 if (IS_ERR(host->dbclk)) {
1909 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1910 host->dbclk = NULL;
1911 } else if (clk_enable(host->dbclk) != 0) {
1912 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1913 clk_put(host->dbclk);
1914 host->dbclk = NULL;
2bec0893 1915 }
a45c6cb8 1916
0ccd76d4
JY		 1917 /* Since we do only SG emulation, we can have as many segs
1918 * as we want. */
a36274e0 1919 mmc->max_segs = 1024;
0ccd76d4 1920
a45c6cb8
MC		 1921 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1922 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1923 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1924 mmc->max_seg_size = mmc->max_req_size;
1925
13189e78 1926 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1927 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1928
3a63833e
SG		 1929 mmc->caps |= mmc_slot(host).caps;
1930 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1931 mmc->caps |= MMC_CAP_4_BIT_DATA;
1932
191d1f1d 1933 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1934 mmc->caps |= MMC_CAP_NONREMOVABLE;
1935
6fdc75de
EP		 1936 mmc->pm_caps = mmc_slot(host).pm_caps;
1937
70a3341a 1938 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1939
b7bf773b
B		 1940 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1941 if (!res) {
1942 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1943 goto err_irq;
1944 }
1945 host->dma_line_tx = res->start;
1946
1947 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1948 if (!res) {
1949 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
f3e2f1dd
GI		 1950 goto err_irq;
1951 }
b7bf773b 1952 host->dma_line_rx = res->start;
a45c6cb8
MC		 1953
1954 /* Request IRQ for MMC operations */
d9618e9f 1955 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1956 mmc_hostname(mmc), host);
1957 if (ret) {
1958 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1959 goto err_irq;
1960 }
1961
1962 if (pdata->init != NULL) {
1963 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 1964 dev_dbg(mmc_dev(host->mmc),
1965 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1966 goto err_irq_cd_init;
1967 }
1968 }
db0fefc5 1969
b702b106 1970 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1971 ret = omap_hsmmc_reg_get(host);
1972 if (ret)
1973 goto err_reg;
1974 host->use_reg = 1;
1975 }
1976
b583f26d 1977 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1978
1979 /* Request IRQ for card detect */
e1a55f5e 1980 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1981 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1982 NULL,
1983 omap_hsmmc_detect,
1984 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1985 mmc_hostname(mmc), host);
a45c6cb8
MC		 1986 if (ret) {
1987 dev_dbg(mmc_dev(host->mmc),
1988 "Unable to grab MMC CD IRQ\n");
1989 goto err_irq_cd;
1990 }
72f2e2c7 1991 pdata->suspend = omap_hsmmc_suspend_cdirq;
1992 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 1993 }
1994
b417577d 1995 omap_hsmmc_disable_irq(host);
a45c6cb8 1996
b62f6228
AH		 1997 omap_hsmmc_protect_card(host);
1998
a45c6cb8
MC		 1999 mmc_add_host(mmc);
2000
191d1f1d 2001 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2002 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2003 if (ret < 0)
2004 goto err_slot_name;
2005 }
191d1f1d 2006 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2007 ret = device_create_file(&mmc->class_dev,
2008 &dev_attr_cover_switch);
2009 if (ret < 0)
db0fefc5 2010 goto err_slot_name;
a45c6cb8
MC		 2011 }
2012
70a3341a 2013 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2014 pm_runtime_mark_last_busy(host->dev);
2015 pm_runtime_put_autosuspend(host->dev);
d900f712 2016
a45c6cb8
MC		 2017 return 0;
2018
a45c6cb8
MC		 2019err_slot_name:
2020 mmc_remove_host(mmc);
a45c6cb8 2021 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2022err_irq_cd:
2023 if (host->use_reg)
2024 omap_hsmmc_reg_put(host);
2025err_reg:
2026 if (host->pdata->cleanup)
2027 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2028err_irq_cd_init:
2029 free_irq(host->irq, host);
2030err_irq:
d59d77ed 2031 pm_runtime_put_sync(host->dev);
37f6190d 2032 pm_runtime_disable(host->dev);
a45c6cb8 2033 clk_put(host->fclk);
cd03d9a8 2034 if (host->dbclk) {
a45c6cb8
MC		 2035 clk_disable(host->dbclk);
2036 clk_put(host->dbclk);
2037 }
a45c6cb8
MC		 2038err1:
2039 iounmap(host->base);
db0fefc5
AH		 2040 platform_set_drvdata(pdev, NULL);
2041 mmc_free_host(mmc);
2042err_alloc:
2043 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2044err:
984b203a 2045 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2046 return ret;
2047}
2048
efa25fd3 2049static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2050{
70a3341a 2051 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2052 struct resource *res;
2053
927ce944
FB		 2054 pm_runtime_get_sync(host->dev);
2055 mmc_remove_host(host->mmc);
2056 if (host->use_reg)
2057 omap_hsmmc_reg_put(host);
2058 if (host->pdata->cleanup)
2059 host->pdata->cleanup(&pdev->dev);
2060 free_irq(host->irq, host);
2061 if (mmc_slot(host).card_detect_irq)
2062 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 2063
927ce944
FB		 2064 pm_runtime_put_sync(host->dev);
2065 pm_runtime_disable(host->dev);
2066 clk_put(host->fclk);
cd03d9a8 2067 if (host->dbclk) {
927ce944
FB		 2068 clk_disable(host->dbclk);
2069 clk_put(host->dbclk);
a45c6cb8
MC		 2070 }
2071
927ce944
FB		 2072 mmc_free_host(host->mmc);
2073 iounmap(host->base);
2074 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2075
a45c6cb8
MC		 2076 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2077 if (res)
984b203a 2078 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2079 platform_set_drvdata(pdev, NULL);
2080
2081 return 0;
2082}
2083
2084#ifdef CONFIG_PM
a791daa1 2085static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2086{
2087 int ret = 0;
927ce944 2088 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2089
927ce944 2090 if (!host)
a45c6cb8
MC		 2091 return 0;
2092
927ce944
FB		 2093 if (host && host->suspended)
2094 return 0;
fa4aa2d4 2095
927ce944
FB		 2096 pm_runtime_get_sync(host->dev);
2097 host->suspended = 1;
2098 if (host->pdata->suspend) {
2099 ret = host->pdata->suspend(dev, host->slot_id);
31f9d463 2100 if (ret) {
927ce944
FB		 2101 dev_dbg(dev, "Unable to handle MMC board"
2102 " level suspend\n");
a6b2240d 2103 host->suspended = 0;
927ce944 2104 return ret;
a6b2240d 2105 }
927ce944
FB		 2106 }
2107 ret = mmc_suspend_host(host->mmc);
31f9d463 2108
927ce944
FB		 2109 if (ret) {
2110 host->suspended = 0;
2111 if (host->pdata->resume) {
2112 ret = host->pdata->resume(dev, host->slot_id);
2113 if (ret)
2114 dev_dbg(dev, "Unmask interrupt failed\n");
31f9d463 2115 }
927ce944
FB		 2116 goto err;
2117 }
31f9d463 2118
927ce944
FB		 2119 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2120 omap_hsmmc_disable_irq(host);
2121 OMAP_HSMMC_WRITE(host->base, HCTL,
2122 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2123 }
927ce944 2124
cd03d9a8 2125 if (host->dbclk)
927ce944 2126 clk_disable(host->dbclk);
31f9d463
EP		 2127err:
2128 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2129 return ret;
2130}
2131
2132/* Routine to resume the MMC device */
a791daa1 2133static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2134{
2135 int ret = 0;
927ce944
FB		 2136 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2137
2138 if (!host)
2139 return 0;
a45c6cb8
MC		 2140
2141 if (host && !host->suspended)
2142 return 0;
2143
927ce944 2144 pm_runtime_get_sync(host->dev);
11dd62a7 2145
cd03d9a8 2146 if (host->dbclk)
927ce944 2147 clk_enable(host->dbclk);
2bec0893 2148
927ce944
FB		 2149 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2150 omap_hsmmc_conf_bus_power(host);
1b331e69 2151
927ce944
FB		 2152 if (host->pdata->resume) {
2153 ret = host->pdata->resume(dev, host->slot_id);
2154 if (ret)
2155 dev_dbg(dev, "Unmask interrupt failed\n");
2156 }
a45c6cb8 2157
927ce944 2158 omap_hsmmc_protect_card(host);
b62f6228 2159
927ce944
FB		 2160 /* Notify the core to resume the host */
2161 ret = mmc_resume_host(host->mmc);
2162 if (ret == 0)
2163 host->suspended = 0;
fa4aa2d4 2164
927ce944
FB		 2165 pm_runtime_mark_last_busy(host->dev);
2166 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2167
2168 return ret;
2169
a45c6cb8
MC		 2170}
2171
2172#else
70a3341a
DK		 2173#define omap_hsmmc_suspend NULL
2174#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2175#endif
2176
fa4aa2d4
B		 2177static int omap_hsmmc_runtime_suspend(struct device *dev)
2178{
2179 struct omap_hsmmc_host *host;
2180
2181 host = platform_get_drvdata(to_platform_device(dev));
2182 omap_hsmmc_context_save(host);
927ce944 2183 dev_dbg(dev, "disabled\n");
fa4aa2d4
B		 2184
2185 return 0;
2186}
2187
2188static int omap_hsmmc_runtime_resume(struct device *dev)
2189{
2190 struct omap_hsmmc_host *host;
2191
2192 host = platform_get_drvdata(to_platform_device(dev));
2193 omap_hsmmc_context_restore(host);
927ce944 2194 dev_dbg(dev, "enabled\n");
fa4aa2d4
B		 2195
2196 return 0;
2197}
2198
a791daa1 2199static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2200 .suspend = omap_hsmmc_suspend,
2201 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2202 .runtime_suspend = omap_hsmmc_runtime_suspend,
2203 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2204};
2205
2206static struct platform_driver omap_hsmmc_driver = {
efa25fd3
FB		 2207 .probe = omap_hsmmc_probe,
2208 .remove = __devexit_p(omap_hsmmc_remove),
a45c6cb8
MC		 2209 .driver = {
2210 .name = DRIVER_NAME,
2211 .owner = THIS_MODULE,
a791daa1 2212 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2213 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2214 },
2215};
2216
b796450b 2217module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2218MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2219MODULE_LICENSE("GPL");
2220MODULE_ALIAS("platform:" DRIVER_NAME);
2221MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)