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mmc: core: Add default timeout value for CMD6
[linux-2.6-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712
DK		 21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
a45c6cb8
MC		 23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <linux/workqueue.h>
28#include <linux/timer.h>
29#include <linux/clk.h>
30#include <linux/mmc/host.h>
13189e78 31#include <linux/mmc/core.h>
93caf8e6 32#include <linux/mmc/mmc.h>
a45c6cb8
MC		 33#include <linux/io.h>
34#include <linux/semaphore.h>
db0fefc5
AH		 35#include <linux/gpio.h>
36#include <linux/regulator/consumer.h>
fa4aa2d4 37#include <linux/pm_runtime.h>
ce491cf8 38#include <plat/dma.h>
a45c6cb8 39#include <mach/hardware.h>
ce491cf8
TL		 40#include <plat/board.h>
41#include <plat/mmc.h>
42#include <plat/cpu.h>
a45c6cb8
MC		 43
44/* OMAP HSMMC Host Controller Registers */
45#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 46#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 47#define OMAP_HSMMC_CON 0x002C
48#define OMAP_HSMMC_BLK 0x0104
49#define OMAP_HSMMC_ARG 0x0108
50#define OMAP_HSMMC_CMD 0x010C
51#define OMAP_HSMMC_RSP10 0x0110
52#define OMAP_HSMMC_RSP32 0x0114
53#define OMAP_HSMMC_RSP54 0x0118
54#define OMAP_HSMMC_RSP76 0x011C
55#define OMAP_HSMMC_DATA 0x0120
56#define OMAP_HSMMC_HCTL 0x0128
57#define OMAP_HSMMC_SYSCTL 0x012C
58#define OMAP_HSMMC_STAT 0x0130
59#define OMAP_HSMMC_IE 0x0134
60#define OMAP_HSMMC_ISE 0x0138
61#define OMAP_HSMMC_CAPA 0x0140
62
63#define VS18 (1 << 26)
64#define VS30 (1 << 25)
65#define SDVS18 (0x5 << 9)
66#define SDVS30 (0x6 << 9)
eb250826 67#define SDVS33 (0x7 << 9)
1b331e69 68#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 69#define SDVSCLR 0xFFFFF1FF
70#define SDVSDET 0x00000400
71#define AUTOIDLE 0x1
72#define SDBP (1 << 8)
73#define DTO 0xe
74#define ICE 0x1
75#define ICS 0x2
76#define CEN (1 << 2)
77#define CLKD_MASK 0x0000FFC0
78#define CLKD_SHIFT 6
79#define DTO_MASK 0x000F0000
80#define DTO_SHIFT 16
81#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 82#define BWR_ENABLE (1 << 4)
83#define BRR_ENABLE (1 << 5)
93caf8e6 84#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 85#define INIT_STREAM (1 << 1)
86#define DP_SELECT (1 << 21)
87#define DDIR (1 << 4)
88#define DMA_EN 0x1
89#define MSBS (1 << 5)
90#define BCE (1 << 1)
91#define FOUR_BIT (1 << 1)
73153010 92#define DW8 (1 << 5)
a45c6cb8
MC		 93#define CC 0x1
94#define TC 0x02
95#define OD 0x1
96#define ERR (1 << 15)
97#define CMD_TIMEOUT (1 << 16)
98#define DATA_TIMEOUT (1 << 20)
99#define CMD_CRC (1 << 17)
100#define DATA_CRC (1 << 21)
101#define CARD_ERR (1 << 28)
102#define STAT_CLEAR 0xFFFFFFFF
103#define INIT_STREAM_CMD 0x00000000
104#define DUAL_VOLT_OCR_BIT 7
105#define SRC (1 << 25)
106#define SRD (1 << 26)
11dd62a7
DK		 107#define SOFTRESET (1 << 1)
108#define RESETDONE (1 << 0)
a45c6cb8
MC		 109
110/*
111 * FIXME: Most likely all the data using these _DEVID defines should come
112 * from the platform_data, or implemented in controller and slot specific
113 * functions.
114 */
115#define OMAP_MMC1_DEVID 0
116#define OMAP_MMC2_DEVID 1
f3e2f1dd 117#define OMAP_MMC3_DEVID 2
82cf818d 118#define OMAP_MMC4_DEVID 3
119#define OMAP_MMC5_DEVID 4
a45c6cb8 120
fa4aa2d4 121#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8
MC		 122#define MMC_TIMEOUT_MS 20
123#define OMAP_MMC_MASTER_CLOCK 96000000
6b206efe
AS		 124#define OMAP_MMC_MIN_CLOCK 400000
125#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 126#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 127
128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
9782aff8
PF		 144struct omap_hsmmc_next {
145 unsigned int dma_len;
146 s32 cookie;
147};
148
70a3341a 149struct omap_hsmmc_host {
a45c6cb8
MC		 150 struct device *dev;
151 struct mmc_host *mmc;
152 struct mmc_request *mrq;
153 struct mmc_command *cmd;
154 struct mmc_data *data;
155 struct clk *fclk;
a45c6cb8 156 struct clk *dbclk;
db0fefc5
AH		 157 /*
158 * vcc == configured supply
159 * vcc_aux == optional
160 * - MMC1, supply for DAT4..DAT7
161 * - MMC2/MMC2, external level shifter voltage supply, for
162 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
163 */
164 struct regulator *vcc;
165 struct regulator *vcc_aux;
a45c6cb8
MC		 166 struct work_struct mmc_carddetect_work;
167 void __iomem *base;
168 resource_size_t mapbase;
4dffd7a2 169 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 170 unsigned int id;
171 unsigned int dma_len;
0ccd76d4 172 unsigned int dma_sg_idx;
a45c6cb8 173 unsigned char bus_mode;
a3621465 174 unsigned char power_mode;
a45c6cb8
MC		 175 u32 *buffer;
176 u32 bytesleft;
177 int suspended;
178 int irq;
a45c6cb8 179 int use_dma, dma_ch;
f3e2f1dd 180 int dma_line_tx, dma_line_rx;
a45c6cb8 181 int slot_id;
2bec0893 182 int got_dbclk;
4a694dc9 183 int response_busy;
11dd62a7 184 int context_loss;
dd498eff 185 int dpm_state;
623821f7 186 int vdd;
b62f6228
AH		 187 int protect_card;
188 int reqs_blocked;
db0fefc5 189 int use_reg;
b417577d 190 int req_in_progress;
9782aff8 191 struct omap_hsmmc_next next_data;
11dd62a7 192
a45c6cb8
MC		 193 struct omap_mmc_platform_data *pdata;
194};
195
db0fefc5
AH		 196static int omap_hsmmc_card_detect(struct device *dev, int slot)
197{
198 struct omap_mmc_platform_data *mmc = dev->platform_data;
199
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
202}
203
204static int omap_hsmmc_get_wp(struct device *dev, int slot)
205{
206 struct omap_mmc_platform_data *mmc = dev->platform_data;
207
208 /* NOTE: assumes write protect signal is active-high */
209 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
210}
211
212static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
213{
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
215
216 /* NOTE: assumes card detect signal is active-low */
217 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
218}
219
220#ifdef CONFIG_PM
221
222static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
223{
224 struct omap_mmc_platform_data *mmc = dev->platform_data;
225
226 disable_irq(mmc->slots[0].card_detect_irq);
227 return 0;
228}
229
230static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
231{
232 struct omap_mmc_platform_data *mmc = dev->platform_data;
233
234 enable_irq(mmc->slots[0].card_detect_irq);
235 return 0;
236}
237
238#else
239
240#define omap_hsmmc_suspend_cdirq NULL
241#define omap_hsmmc_resume_cdirq NULL
242
243#endif
244
b702b106
AH		 245#ifdef CONFIG_REGULATOR
246
db0fefc5
AH		 247static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
248 int vdd)
249{
250 struct omap_hsmmc_host *host =
251 platform_get_drvdata(to_platform_device(dev));
252 int ret;
253
254 if (mmc_slot(host).before_set_reg)
255 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
256
257 if (power_on)
99fc5131 258 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5 259 else
99fc5131 260 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5
AH		 261
262 if (mmc_slot(host).after_set_reg)
263 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
264
265 return ret;
266}
267
7715db5a 268static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 269 int vdd)
270{
271 struct omap_hsmmc_host *host =
272 platform_get_drvdata(to_platform_device(dev));
273 int ret = 0;
274
275 /*
276 * If we don't see a Vcc regulator, assume it's a fixed
277 * voltage always-on regulator.
278 */
279 if (!host->vcc)
280 return 0;
281
282 if (mmc_slot(host).before_set_reg)
283 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
284
285 /*
286 * Assume Vcc regulator is used only to power the card ... OMAP
287 * VDDS is used to power the pins, optionally with a transceiver to
288 * support cards using voltages other than VDDS (1.8V nominal). When a
289 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
290 *
291 * In some cases this regulator won't support enable/disable;
292 * e.g. it's a fixed rail for a WLAN chip.
293 *
294 * In other cases vcc_aux switches interface power. Example, for
295 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
296 * chips/cards need an interface voltage rail too.
297 */
298 if (power_on) {
99fc5131 299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 300 /* Enable interface voltage rail, if needed */
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
303 if (ret < 0)
99fc5131
LW		 304 ret = mmc_regulator_set_ocr(host->mmc,
305 host->vcc, 0);
db0fefc5
AH		 306 }
307 } else {
99fc5131 308 /* Shut down the rail */
6da20c89
AH		 309 if (host->vcc_aux)
310 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 311 if (!ret) {
312 /* Then proceed to shut down the local regulator */
313 ret = mmc_regulator_set_ocr(host->mmc,
314 host->vcc, 0);
315 }
db0fefc5
AH		 316 }
317
318 if (mmc_slot(host).after_set_reg)
319 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
320
321 return ret;
322}
323
7715db5a
KK		 324static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
325 int vdd)
326{
327 return 0;
328}
329
db0fefc5
AH		 330static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
331 int vdd, int cardsleep)
332{
333 struct omap_hsmmc_host *host =
334 platform_get_drvdata(to_platform_device(dev));
335 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
336
337 return regulator_set_mode(host->vcc, mode);
338}
339
7715db5a 340static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
db0fefc5
AH		 341 int vdd, int cardsleep)
342{
343 struct omap_hsmmc_host *host =
344 platform_get_drvdata(to_platform_device(dev));
345 int err, mode;
346
347 /*
348 * If we don't see a Vcc regulator, assume it's a fixed
349 * voltage always-on regulator.
350 */
351 if (!host->vcc)
352 return 0;
353
354 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
355
356 if (!host->vcc_aux)
357 return regulator_set_mode(host->vcc, mode);
358
359 if (cardsleep) {
360 /* VCC can be turned off if card is asleep */
361 if (sleep)
99fc5131 362 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5 363 else
99fc5131 364 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 365 } else
366 err = regulator_set_mode(host->vcc, mode);
367 if (err)
368 return err;
e0eb2424
AH		 369
370 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
371 return regulator_set_mode(host->vcc_aux, mode);
372
373 if (sleep)
374 return regulator_disable(host->vcc_aux);
375 else
376 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 377}
378
7715db5a
KK		 379static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
380 int vdd, int cardsleep)
381{
382 return 0;
383}
384
db0fefc5
AH		 385static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
386{
387 struct regulator *reg;
388 int ret = 0;
64be9782 389 int ocr_value = 0;
db0fefc5
AH		 390
391 switch (host->id) {
392 case OMAP_MMC1_DEVID:
393 /* On-chip level shifting via PBIAS0/PBIAS1 */
394 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
395 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
396 break;
397 case OMAP_MMC2_DEVID:
398 case OMAP_MMC3_DEVID:
7715db5a 399 case OMAP_MMC5_DEVID:
db0fefc5 400 /* Off-chip level shifting, or none */
7715db5a
KK		 401 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
402 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
db0fefc5 403 break;
7715db5a
KK		 404 case OMAP_MMC4_DEVID:
405 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
406 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
db0fefc5
AH		 407 default:
408 pr_err("MMC%d configuration not supported!\n", host->id);
409 return -EINVAL;
410 }
411
412 reg = regulator_get(host->dev, "vmmc");
413 if (IS_ERR(reg)) {
414 dev_dbg(host->dev, "vmmc regulator missing\n");
415 /*
416 * HACK: until fixed.c regulator is usable,
417 * we don't require a main regulator
418 * for MMC2 or MMC3
419 */
420 if (host->id == OMAP_MMC1_DEVID) {
421 ret = PTR_ERR(reg);
422 goto err;
423 }
424 } else {
425 host->vcc = reg;
64be9782 426 ocr_value = mmc_regulator_get_ocrmask(reg);
427 if (!mmc_slot(host).ocr_mask) {
428 mmc_slot(host).ocr_mask = ocr_value;
429 } else {
430 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
431 pr_err("MMC%d ocrmask %x is not supported\n",
432 host->id, mmc_slot(host).ocr_mask);
433 mmc_slot(host).ocr_mask = 0;
434 return -EINVAL;
435 }
436 }
db0fefc5
AH		 437
438 /* Allow an aux regulator */
439 reg = regulator_get(host->dev, "vmmc_aux");
440 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
441
b1c1df7a
B		 442 /* For eMMC do not power off when not in sleep state */
443 if (mmc_slot(host).no_regulator_off_init)
444 return 0;
db0fefc5
AH		 445 /*
446 * UGLY HACK: workaround regulator framework bugs.
447 * When the bootloader leaves a supply active, it's
448 * initialized with zero usecount ... and we can't
449 * disable it without first enabling it. Until the
450 * framework is fixed, we need a workaround like this
451 * (which is safe for MMC, but not in general).
452 */
453 if (regulator_is_enabled(host->vcc) > 0) {
454 regulator_enable(host->vcc);
455 regulator_disable(host->vcc);
456 }
457 if (host->vcc_aux) {
458 if (regulator_is_enabled(reg) > 0) {
459 regulator_enable(reg);
460 regulator_disable(reg);
461 }
462 }
463 }
464
465 return 0;
466
467err:
468 mmc_slot(host).set_power = NULL;
469 mmc_slot(host).set_sleep = NULL;
470 return ret;
471}
472
473static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
474{
475 regulator_put(host->vcc);
476 regulator_put(host->vcc_aux);
477 mmc_slot(host).set_power = NULL;
478 mmc_slot(host).set_sleep = NULL;
479}
480
b702b106
AH		 481static inline int omap_hsmmc_have_reg(void)
482{
483 return 1;
484}
485
486#else
487
488static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
489{
490 return -EINVAL;
491}
492
493static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
494{
495}
496
497static inline int omap_hsmmc_have_reg(void)
498{
499 return 0;
500}
501
502#endif
503
504static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
505{
506 int ret;
507
508 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 509 if (pdata->slots[0].cover)
510 pdata->slots[0].get_cover_state =
511 omap_hsmmc_get_cover_state;
512 else
513 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
514 pdata->slots[0].card_detect_irq =
515 gpio_to_irq(pdata->slots[0].switch_pin);
516 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
517 if (ret)
518 return ret;
519 ret = gpio_direction_input(pdata->slots[0].switch_pin);
520 if (ret)
521 goto err_free_sp;
522 } else
523 pdata->slots[0].switch_pin = -EINVAL;
524
525 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
526 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
527 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
528 if (ret)
529 goto err_free_cd;
530 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
531 if (ret)
532 goto err_free_wp;
533 } else
534 pdata->slots[0].gpio_wp = -EINVAL;
535
536 return 0;
537
538err_free_wp:
539 gpio_free(pdata->slots[0].gpio_wp);
540err_free_cd:
541 if (gpio_is_valid(pdata->slots[0].switch_pin))
542err_free_sp:
543 gpio_free(pdata->slots[0].switch_pin);
544 return ret;
545}
546
547static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
548{
549 if (gpio_is_valid(pdata->slots[0].gpio_wp))
550 gpio_free(pdata->slots[0].gpio_wp);
551 if (gpio_is_valid(pdata->slots[0].switch_pin))
552 gpio_free(pdata->slots[0].switch_pin);
553}
554
e0c7f99b
AS		 555/*
556 * Start clock to the card
557 */
558static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
559{
560 OMAP_HSMMC_WRITE(host->base, SYSCTL,
561 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
562}
563
a45c6cb8
MC		 564/*
565 * Stop clock to the card
566 */
70a3341a 567static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 568{
569 OMAP_HSMMC_WRITE(host->base, SYSCTL,
570 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
571 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
572 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
573}
574
93caf8e6
AH		 575static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
576 struct mmc_command *cmd)
b417577d
AH		 577{
578 unsigned int irq_mask;
579
580 if (host->use_dma)
581 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
582 else
583 irq_mask = INT_EN_MASK;
584
93caf8e6
AH		 585 /* Disable timeout for erases */
586 if (cmd->opcode == MMC_ERASE)
587 irq_mask &= ~DTO_ENABLE;
588
b417577d
AH		 589 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
590 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
591 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
592}
593
594static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
595{
596 OMAP_HSMMC_WRITE(host->base, ISE, 0);
597 OMAP_HSMMC_WRITE(host->base, IE, 0);
598 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
599}
600
ac330f44
AS		 601/* Calculate divisor for the given clock frequency */
602static u16 calc_divisor(struct mmc_ios *ios)
603{
604 u16 dsor = 0;
605
606 if (ios->clock) {
607 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
608 if (dsor > 250)
609 dsor = 250;
610 }
611
612 return dsor;
613}
614
5934df2f
AS		 615static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
616{
617 struct mmc_ios *ios = &host->mmc->ios;
618 unsigned long regval;
619 unsigned long timeout;
620
621 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
622
623 omap_hsmmc_stop_clock(host);
624
625 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
626 regval = regval & ~(CLKD_MASK | DTO_MASK);
627 regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
628 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
629 OMAP_HSMMC_WRITE(host->base, SYSCTL,
630 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
631
632 /* Wait till the ICS bit is set */
633 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
634 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
635 && time_before(jiffies, timeout))
636 cpu_relax();
637
638 omap_hsmmc_start_clock(host);
639}
640
3796fb8a
AS		 641static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
642{
643 struct mmc_ios *ios = &host->mmc->ios;
644 u32 con;
645
646 con = OMAP_HSMMC_READ(host->base, CON);
647 switch (ios->bus_width) {
648 case MMC_BUS_WIDTH_8:
649 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
650 break;
651 case MMC_BUS_WIDTH_4:
652 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
653 OMAP_HSMMC_WRITE(host->base, HCTL,
654 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
655 break;
656 case MMC_BUS_WIDTH_1:
657 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
660 break;
661 }
662}
663
664static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
665{
666 struct mmc_ios *ios = &host->mmc->ios;
667 u32 con;
668
669 con = OMAP_HSMMC_READ(host->base, CON);
670 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
671 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
672 else
673 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
674}
675
11dd62a7
DK		 676#ifdef CONFIG_PM
677
678/*
679 * Restore the MMC host context, if it was lost as result of a
680 * power state change.
681 */
70a3341a 682static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 683{
684 struct mmc_ios *ios = &host->mmc->ios;
685 struct omap_mmc_platform_data *pdata = host->pdata;
686 int context_loss = 0;
3796fb8a 687 u32 hctl, capa;
11dd62a7
DK		 688 unsigned long timeout;
689
690 if (pdata->get_context_loss_count) {
691 context_loss = pdata->get_context_loss_count(host->dev);
692 if (context_loss < 0)
693 return 1;
694 }
695
696 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
697 context_loss == host->context_loss ? "not " : "");
698 if (host->context_loss == context_loss)
699 return 1;
700
701 /* Wait for hardware reset */
702 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
703 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
704 && time_before(jiffies, timeout))
705 ;
706
707 /* Do software reset */
708 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
709 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
710 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
711 && time_before(jiffies, timeout))
712 ;
713
714 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
715 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
716
717 if (host->id == OMAP_MMC1_DEVID) {
718 if (host->power_mode != MMC_POWER_OFF &&
719 (1 << ios->vdd) <= MMC_VDD_23_24)
720 hctl = SDVS18;
721 else
722 hctl = SDVS30;
723 capa = VS30 | VS18;
724 } else {
725 hctl = SDVS18;
726 capa = VS18;
727 }
728
729 OMAP_HSMMC_WRITE(host->base, HCTL,
730 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
731
732 OMAP_HSMMC_WRITE(host->base, CAPA,
733 OMAP_HSMMC_READ(host->base, CAPA) | capa);
734
735 OMAP_HSMMC_WRITE(host->base, HCTL,
736 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
737
738 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
739 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
740 && time_before(jiffies, timeout))
741 ;
742
b417577d 743 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 744
745 /* Do not initialize card-specific things if the power is off */
746 if (host->power_mode == MMC_POWER_OFF)
747 goto out;
748
3796fb8a 749 omap_hsmmc_set_bus_width(host);
11dd62a7 750
5934df2f 751 omap_hsmmc_set_clock(host);
11dd62a7 752
3796fb8a
AS		 753 omap_hsmmc_set_bus_mode(host);
754
11dd62a7
DK		 755out:
756 host->context_loss = context_loss;
757
758 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
759 return 0;
760}
761
762/*
763 * Save the MMC host context (store the number of power state changes so far).
764 */
70a3341a 765static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 766{
767 struct omap_mmc_platform_data *pdata = host->pdata;
768 int context_loss;
769
770 if (pdata->get_context_loss_count) {
771 context_loss = pdata->get_context_loss_count(host->dev);
772 if (context_loss < 0)
773 return;
774 host->context_loss = context_loss;
775 }
776}
777
778#else
779
70a3341a 780static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 781{
782 return 0;
783}
784
70a3341a 785static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 786{
787}
788
789#endif
790
a45c6cb8
MC		 791/*
792 * Send init stream sequence to card
793 * before sending IDLE command
794 */
70a3341a 795static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 796{
797 int reg = 0;
798 unsigned long timeout;
799
b62f6228
AH		 800 if (host->protect_card)
801 return;
802
a45c6cb8 803 disable_irq(host->irq);
b417577d
AH		 804
805 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 806 OMAP_HSMMC_WRITE(host->base, CON,
807 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
808 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
809
810 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
811 while ((reg != CC) && time_before(jiffies, timeout))
812 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
813
814 OMAP_HSMMC_WRITE(host->base, CON,
815 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 816
817 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
818 OMAP_HSMMC_READ(host->base, STAT);
819
a45c6cb8
MC		 820 enable_irq(host->irq);
821}
822
823static inline
70a3341a 824int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 825{
826 int r = 1;
827
191d1f1d
DK		 828 if (mmc_slot(host).get_cover_state)
829 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 830 return r;
831}
832
833static ssize_t
70a3341a 834omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 835 char *buf)
836{
837 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 838 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 839
70a3341a
DK		 840 return sprintf(buf, "%s\n",
841 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 842}
843
70a3341a 844static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 845
846static ssize_t
70a3341a 847omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 848 char *buf)
849{
850 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 851 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 852
191d1f1d 853 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 854}
855
70a3341a 856static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 857
858/*
859 * Configure the response type and send the cmd.
860 */
861static void
70a3341a 862omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 863 struct mmc_data *data)
864{
865 int cmdreg = 0, resptype = 0, cmdtype = 0;
866
867 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
868 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
869 host->cmd = cmd;
870
93caf8e6 871 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 872
4a694dc9 873 host->response_busy = 0;
a45c6cb8
MC		 874 if (cmd->flags & MMC_RSP_PRESENT) {
875 if (cmd->flags & MMC_RSP_136)
876 resptype = 1;
4a694dc9
AH		 877 else if (cmd->flags & MMC_RSP_BUSY) {
878 resptype = 3;
879 host->response_busy = 1;
880 } else
a45c6cb8
MC		 881 resptype = 2;
882 }
883
884 /*
885 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
886 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
887 * a val of 0x3, rest 0x0.
888 */
889 if (cmd == host->mrq->stop)
890 cmdtype = 0x3;
891
892 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
893
894 if (data) {
895 cmdreg |= DP_SELECT | MSBS | BCE;
896 if (data->flags & MMC_DATA_READ)
897 cmdreg |= DDIR;
898 else
899 cmdreg &= ~(DDIR);
900 }
901
902 if (host->use_dma)
903 cmdreg |= DMA_EN;
904
b417577d 905 host->req_in_progress = 1;
4dffd7a2 906
a45c6cb8
MC		 907 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
908 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
909}
910
0ccd76d4 911static int
70a3341a 912omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 913{
914 if (data->flags & MMC_DATA_WRITE)
915 return DMA_TO_DEVICE;
916 else
917 return DMA_FROM_DEVICE;
918}
919
b417577d
AH		 920static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
921{
922 int dma_ch;
923
924 spin_lock(&host->irq_lock);
925 host->req_in_progress = 0;
926 dma_ch = host->dma_ch;
927 spin_unlock(&host->irq_lock);
928
929 omap_hsmmc_disable_irq(host);
930 /* Do not complete the request if DMA is still in progress */
931 if (mrq->data && host->use_dma && dma_ch != -1)
932 return;
933 host->mrq = NULL;
934 mmc_request_done(host->mmc, mrq);
935}
936
a45c6cb8
MC		 937/*
938 * Notify the transfer complete to MMC core
939 */
940static void
70a3341a 941omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 942{
4a694dc9
AH		 943 if (!data) {
944 struct mmc_request *mrq = host->mrq;
945
23050103
AH		 946 /* TC before CC from CMD6 - don't know why, but it happens */
947 if (host->cmd && host->cmd->opcode == 6 &&
948 host->response_busy) {
949 host->response_busy = 0;
950 return;
951 }
952
b417577d 953 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 954 return;
955 }
956
a45c6cb8
MC		 957 host->data = NULL;
958
a45c6cb8
MC		 959 if (!data->error)
960 data->bytes_xfered += data->blocks * (data->blksz);
961 else
962 data->bytes_xfered = 0;
963
964 if (!data->stop) {
b417577d 965 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 966 return;
967 }
70a3341a 968 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 969}
970
971/*
972 * Notify the core about command completion
973 */
974static void
70a3341a 975omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 976{
977 host->cmd = NULL;
978
979 if (cmd->flags & MMC_RSP_PRESENT) {
980 if (cmd->flags & MMC_RSP_136) {
981 /* response type 2 */
982 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
983 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
984 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
985 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
986 } else {
987 /* response types 1, 1b, 3, 4, 5, 6 */
988 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
989 }
990 }
b417577d
AH		 991 if ((host->data == NULL && !host->response_busy) || cmd->error)
992 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 993}
994
995/*
996 * DMA clean up for command errors
997 */
70a3341a 998static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 999{
b417577d
AH		 1000 int dma_ch;
1001
82788ff5 1002 host->data->error = errno;
a45c6cb8 1003
b417577d
AH		 1004 spin_lock(&host->irq_lock);
1005 dma_ch = host->dma_ch;
1006 host->dma_ch = -1;
1007 spin_unlock(&host->irq_lock);
1008
1009 if (host->use_dma && dma_ch != -1) {
a9120c33
PF		 1010 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1011 host->data->sg_len,
70a3341a 1012 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 1013 omap_free_dma(dma_ch);
a45c6cb8
MC		 1014 }
1015 host->data = NULL;
a45c6cb8
MC		 1016}
1017
1018/*
1019 * Readable error output
1020 */
1021#ifdef CONFIG_MMC_DEBUG
699b958b 1022static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 1023{
1024 /* --- means reserved bit without definition at documentation */
70a3341a 1025 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 1026 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1027 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1028 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1029 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 1030 };
1031 char res[256];
1032 char *buf = res;
1033 int len, i;
1034
1035 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1036 buf += len;
1037
70a3341a 1038 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 1039 if (status & (1 << i)) {
70a3341a 1040 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 1041 buf += len;
1042 }
1043
1044 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1045}
699b958b
AH		 1046#else
1047static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1048 u32 status)
1049{
1050}
a45c6cb8
MC		 1051#endif /* CONFIG_MMC_DEBUG */
1052
3ebf74b1
JP		 1053/*
1054 * MMC controller internal state machines reset
1055 *
1056 * Used to reset command or data internal state machines, using respectively
1057 * SRC or SRD bit of SYSCTL register
1058 * Can be called from interrupt context
1059 */
70a3341a
DK		 1060static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1061 unsigned long bit)
3ebf74b1
JP		 1062{
1063 unsigned long i = 0;
1064 unsigned long limit = (loops_per_jiffy *
1065 msecs_to_jiffies(MMC_TIMEOUT_MS));
1066
1067 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1068 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1069
07ad64b6
MC		 1070 /*
1071 * OMAP4 ES2 and greater has an updated reset logic.
1072 * Monitor a 0->1 transition first
1073 */
1074 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1075 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 1076 && (i++ < limit))
1077 cpu_relax();
1078 }
1079 i = 0;
1080
3ebf74b1
JP		 1081 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1082 (i++ < limit))
1083 cpu_relax();
1084
1085 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1086 dev_err(mmc_dev(host->mmc),
1087 "Timeout waiting on controller reset in %s\n",
1088 __func__);
1089}
a45c6cb8 1090
b417577d 1091static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1092{
a45c6cb8 1093 struct mmc_data *data;
b417577d
AH		 1094 int end_cmd = 0, end_trans = 0;
1095
1096 if (!host->req_in_progress) {
1097 do {
1098 OMAP_HSMMC_WRITE(host->base, STAT, status);
1099 /* Flush posted write */
1100 status = OMAP_HSMMC_READ(host->base, STAT);
1101 } while (status & INT_EN_MASK);
1102 return;
a45c6cb8
MC		 1103 }
1104
1105 data = host->data;
a45c6cb8
MC		 1106 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1107
1108 if (status & ERR) {
699b958b 1109 omap_hsmmc_dbg_report_irq(host, status);
a45c6cb8
MC		 1110 if ((status & CMD_TIMEOUT) ||
1111 (status & CMD_CRC)) {
1112 if (host->cmd) {
1113 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1114 omap_hsmmc_reset_controller_fsm(host,
1115 SRC);
a45c6cb8
MC		 1116 host->cmd->error = -ETIMEDOUT;
1117 } else {
1118 host->cmd->error = -EILSEQ;
1119 }
1120 end_cmd = 1;
1121 }
4a694dc9
AH		 1122 if (host->data || host->response_busy) {
1123 if (host->data)
70a3341a
DK		 1124 omap_hsmmc_dma_cleanup(host,
1125 -ETIMEDOUT);
4a694dc9 1126 host->response_busy = 0;
70a3341a 1127 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1128 }
a45c6cb8
MC		 1129 }
1130 if ((status & DATA_TIMEOUT) ||
1131 (status & DATA_CRC)) {
4a694dc9
AH		 1132 if (host->data || host->response_busy) {
1133 int err = (status & DATA_TIMEOUT) ?
1134 -ETIMEDOUT : -EILSEQ;
1135
1136 if (host->data)
70a3341a 1137 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1138 else
4a694dc9
AH		 1139 host->mrq->cmd->error = err;
1140 host->response_busy = 0;
70a3341a 1141 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1142 end_trans = 1;
1143 }
1144 }
1145 if (status & CARD_ERR) {
1146 dev_dbg(mmc_dev(host->mmc),
1147 "Ignoring card err CMD%d\n", host->cmd->opcode);
1148 if (host->cmd)
1149 end_cmd = 1;
1150 if (host->data)
1151 end_trans = 1;
1152 }
1153 }
1154
1155 OMAP_HSMMC_WRITE(host->base, STAT, status);
1156
a8fe29d8 1157 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1158 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1159 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1160 omap_hsmmc_xfer_done(host, data);
b417577d 1161}
a45c6cb8 1162
b417577d
AH		 1163/*
1164 * MMC controller IRQ handler
1165 */
1166static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1167{
1168 struct omap_hsmmc_host *host = dev_id;
1169 int status;
1170
1171 status = OMAP_HSMMC_READ(host->base, STAT);
1172 do {
1173 omap_hsmmc_do_irq(host, status);
1174 /* Flush posted write */
1175 status = OMAP_HSMMC_READ(host->base, STAT);
1176 } while (status & INT_EN_MASK);
4dffd7a2 1177
a45c6cb8
MC		 1178 return IRQ_HANDLED;
1179}
1180
70a3341a 1181static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1182{
1183 unsigned long i;
1184
1185 OMAP_HSMMC_WRITE(host->base, HCTL,
1186 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1187 for (i = 0; i < loops_per_jiffy; i++) {
1188 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1189 break;
1190 cpu_relax();
1191 }
1192}
1193
a45c6cb8 1194/*
eb250826
DB		 1195 * Switch MMC interface voltage ... only relevant for MMC1.
1196 *
1197 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1198 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1199 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1200 */
70a3341a 1201static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1202{
1203 u32 reg_val = 0;
1204 int ret;
1205
1206 /* Disable the clocks */
fa4aa2d4 1207 pm_runtime_put_sync(host->dev);
2bec0893
AH		 1208 if (host->got_dbclk)
1209 clk_disable(host->dbclk);
a45c6cb8
MC		 1210
1211 /* Turn the power off */
1212 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1213
1214 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1215 if (!ret)
1216 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1217 vdd);
fa4aa2d4 1218 pm_runtime_get_sync(host->dev);
2bec0893
AH		 1219 if (host->got_dbclk)
1220 clk_enable(host->dbclk);
1221
a45c6cb8
MC		 1222 if (ret != 0)
1223 goto err;
1224
a45c6cb8
MC		 1225 OMAP_HSMMC_WRITE(host->base, HCTL,
1226 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1227 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1228
a45c6cb8
MC		 1229 /*
1230 * If a MMC dual voltage card is detected, the set_ios fn calls
1231 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1232 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1233 *
eb250826
DB		 1234 * Cope with a bit of slop in the range ... per data sheets:
1235 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1236 * but recommended values are 1.71V to 1.89V
1237 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1238 * but recommended values are 2.7V to 3.3V
1239 *
1240 * Board setup code shouldn't permit anything very out-of-range.
1241 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1242 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1243 */
eb250826 1244 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1245 reg_val |= SDVS18;
eb250826
DB		 1246 else
1247 reg_val |= SDVS30;
a45c6cb8
MC		 1248
1249 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1250 set_sd_bus_power(host);
a45c6cb8
MC		 1251
1252 return 0;
1253err:
1254 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1255 return ret;
1256}
1257
b62f6228
AH		 1258/* Protect the card while the cover is open */
1259static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1260{
1261 if (!mmc_slot(host).get_cover_state)
1262 return;
1263
1264 host->reqs_blocked = 0;
1265 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1266 if (host->protect_card) {
1267 printk(KERN_INFO "%s: cover is closed, "
1268 "card is now accessible\n",
1269 mmc_hostname(host->mmc));
1270 host->protect_card = 0;
1271 }
1272 } else {
1273 if (!host->protect_card) {
1274 printk(KERN_INFO "%s: cover is open, "
1275 "card is now inaccessible\n",
1276 mmc_hostname(host->mmc));
1277 host->protect_card = 1;
1278 }
1279 }
1280}
1281
a45c6cb8
MC		 1282/*
1283 * Work Item to notify the core about card insertion/removal
1284 */
70a3341a 1285static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1286{
70a3341a
DK		 1287 struct omap_hsmmc_host *host =
1288 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1289 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1290 int carddetect;
1291
1292 if (host->suspended)
1293 return;
1294
1295 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1296
191d1f1d 1297 if (slot->card_detect)
db0fefc5 1298 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1299 else {
1300 omap_hsmmc_protect_card(host);
a6b2240d 1301 carddetect = -ENOSYS;
b62f6228 1302 }
a45c6cb8 1303
cdeebadd 1304 if (carddetect)
a45c6cb8 1305 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1306 else
a45c6cb8 1307 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1308}
1309
1310/*
1311 * ISR for handling card insertion and removal
1312 */
70a3341a 1313static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1314{
70a3341a 1315 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1316
a6b2240d
AH		 1317 if (host->suspended)
1318 return IRQ_HANDLED;
a45c6cb8
MC		 1319 schedule_work(&host->mmc_carddetect_work);
1320
1321 return IRQ_HANDLED;
1322}
1323
70a3341a 1324static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1325 struct mmc_data *data)
1326{
1327 int sync_dev;
1328
f3e2f1dd
GI		 1329 if (data->flags & MMC_DATA_WRITE)
1330 sync_dev = host->dma_line_tx;
1331 else
1332 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1333 return sync_dev;
1334}
1335
70a3341a 1336static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1337 struct mmc_data *data,
1338 struct scatterlist *sgl)
1339{
1340 int blksz, nblk, dma_ch;
1341
1342 dma_ch = host->dma_ch;
1343 if (data->flags & MMC_DATA_WRITE) {
1344 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1345 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1346 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1347 sg_dma_address(sgl), 0, 0);
1348 } else {
1349 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1350 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1351 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1352 sg_dma_address(sgl), 0, 0);
1353 }
1354
1355 blksz = host->data->blksz;
1356 nblk = sg_dma_len(sgl) / blksz;
1357
1358 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1359 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1360 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1361 !(data->flags & MMC_DATA_WRITE));
1362
1363 omap_start_dma(dma_ch);
1364}
1365
a45c6cb8
MC		 1366/*
1367 * DMA call back function
1368 */
b417577d 1369static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1370{
b417577d 1371 struct omap_hsmmc_host *host = cb_data;
770d7432 1372 struct mmc_data *data;
b417577d 1373 int dma_ch, req_in_progress;
a45c6cb8 1374
f3584e5e
V		 1375 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1376 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1377 ch_status);
1378 return;
1379 }
a45c6cb8 1380
b417577d
AH		 1381 spin_lock(&host->irq_lock);
1382 if (host->dma_ch < 0) {
1383 spin_unlock(&host->irq_lock);
a45c6cb8 1384 return;
b417577d 1385 }
a45c6cb8 1386
770d7432 1387 data = host->mrq->data;
0ccd76d4
JY		 1388 host->dma_sg_idx++;
1389 if (host->dma_sg_idx < host->dma_len) {
1390 /* Fire up the next transfer. */
b417577d
AH		 1391 omap_hsmmc_config_dma_params(host, data,
1392 data->sg + host->dma_sg_idx);
1393 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1394 return;
1395 }
1396
9782aff8
PF		 1397 if (!data->host_cookie)
1398 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1399 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1400
1401 req_in_progress = host->req_in_progress;
1402 dma_ch = host->dma_ch;
a45c6cb8 1403 host->dma_ch = -1;
b417577d
AH		 1404 spin_unlock(&host->irq_lock);
1405
1406 omap_free_dma(dma_ch);
1407
1408 /* If DMA has finished after TC, complete the request */
1409 if (!req_in_progress) {
1410 struct mmc_request *mrq = host->mrq;
1411
1412 host->mrq = NULL;
1413 mmc_request_done(host->mmc, mrq);
1414 }
a45c6cb8
MC		 1415}
1416
9782aff8
PF		 1417static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1418 struct mmc_data *data,
1419 struct omap_hsmmc_next *next)
1420{
1421 int dma_len;
1422
1423 if (!next && data->host_cookie &&
1424 data->host_cookie != host->next_data.cookie) {
1425 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1426 " host->next_data.cookie %d\n",
1427 __func__, data->host_cookie, host->next_data.cookie);
1428 data->host_cookie = 0;
1429 }
1430
1431 /* Check if next job is already prepared */
1432 if (next ||
1433 (!next && data->host_cookie != host->next_data.cookie)) {
1434 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1435 data->sg_len,
1436 omap_hsmmc_get_dma_dir(host, data));
1437
1438 } else {
1439 dma_len = host->next_data.dma_len;
1440 host->next_data.dma_len = 0;
1441 }
1442
1443
1444 if (dma_len == 0)
1445 return -EINVAL;
1446
1447 if (next) {
1448 next->dma_len = dma_len;
1449 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1450 } else
1451 host->dma_len = dma_len;
1452
1453 return 0;
1454}
1455
a45c6cb8
MC		 1456/*
1457 * Routine to configure and start DMA for the MMC card
1458 */
70a3341a
DK		 1459static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1460 struct mmc_request *req)
a45c6cb8 1461{
b417577d 1462 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1463 struct mmc_data *data = req->data;
1464
0ccd76d4 1465 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1466 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1467 struct scatterlist *sgl;
1468
1469 sgl = data->sg + i;
1470 if (sgl->length % data->blksz)
1471 return -EINVAL;
1472 }
1473 if ((data->blksz % 4) != 0)
1474 /* REVISIT: The MMC buffer increments only when MSB is written.
1475 * Return error for blksz which is non multiple of four.
1476 */
1477 return -EINVAL;
1478
b417577d 1479 BUG_ON(host->dma_ch != -1);
a45c6cb8 1480
70a3341a
DK		 1481 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1482 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1483 if (ret != 0) {
0ccd76d4 1484 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1485 "%s: omap_request_dma() failed with %d\n",
1486 mmc_hostname(host->mmc), ret);
1487 return ret;
1488 }
9782aff8
PF		 1489 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1490 if (ret)
1491 return ret;
a45c6cb8 1492
a45c6cb8 1493 host->dma_ch = dma_ch;
0ccd76d4 1494 host->dma_sg_idx = 0;
a45c6cb8 1495
70a3341a 1496 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1497
a45c6cb8
MC		 1498 return 0;
1499}
1500
70a3341a 1501static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1502 unsigned int timeout_ns,
1503 unsigned int timeout_clks)
a45c6cb8
MC		 1504{
1505 unsigned int timeout, cycle_ns;
1506 uint32_t reg, clkd, dto = 0;
1507
1508 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1509 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1510 if (clkd == 0)
1511 clkd = 1;
1512
1513 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1514 timeout = timeout_ns / cycle_ns;
1515 timeout += timeout_clks;
a45c6cb8
MC		 1516 if (timeout) {
1517 while ((timeout & 0x80000000) == 0) {
1518 dto += 1;
1519 timeout <<= 1;
1520 }
1521 dto = 31 - dto;
1522 timeout <<= 1;
1523 if (timeout && dto)
1524 dto += 1;
1525 if (dto >= 13)
1526 dto -= 13;
1527 else
1528 dto = 0;
1529 if (dto > 14)
1530 dto = 14;
1531 }
1532
1533 reg &= ~DTO_MASK;
1534 reg |= dto << DTO_SHIFT;
1535 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1536}
1537
1538/*
1539 * Configure block length for MMC/SD cards and initiate the transfer.
1540 */
1541static int
70a3341a 1542omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1543{
1544 int ret;
1545 host->data = req->data;
1546
1547 if (req->data == NULL) {
a45c6cb8 1548 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1549 /*
1550 * Set an arbitrary 100ms data timeout for commands with
1551 * busy signal.
1552 */
1553 if (req->cmd->flags & MMC_RSP_BUSY)
1554 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1555 return 0;
1556 }
1557
1558 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1559 | (req->data->blocks << 16));
e2bf08d6 1560 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1561
a45c6cb8 1562 if (host->use_dma) {
70a3341a 1563 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1564 if (ret != 0) {
1565 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1566 return ret;
1567 }
1568 }
1569 return 0;
1570}
1571
9782aff8
PF		 1572static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1573 int err)
1574{
1575 struct omap_hsmmc_host *host = mmc_priv(mmc);
1576 struct mmc_data *data = mrq->data;
1577
1578 if (host->use_dma) {
1579 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1580 omap_hsmmc_get_dma_dir(host, data));
1581 data->host_cookie = 0;
1582 }
1583}
1584
1585static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1586 bool is_first_req)
1587{
1588 struct omap_hsmmc_host *host = mmc_priv(mmc);
1589
1590 if (mrq->data->host_cookie) {
1591 mrq->data->host_cookie = 0;
1592 return ;
1593 }
1594
1595 if (host->use_dma)
1596 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1597 &host->next_data))
1598 mrq->data->host_cookie = 0;
1599}
1600
a45c6cb8
MC		 1601/*
1602 * Request function. for read/write operation
1603 */
70a3341a 1604static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1605{
70a3341a 1606 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1607 int err;
a45c6cb8 1608
b417577d
AH		 1609 BUG_ON(host->req_in_progress);
1610 BUG_ON(host->dma_ch != -1);
1611 if (host->protect_card) {
1612 if (host->reqs_blocked < 3) {
1613 /*
1614 * Ensure the controller is left in a consistent
1615 * state by resetting the command and data state
1616 * machines.
1617 */
1618 omap_hsmmc_reset_controller_fsm(host, SRD);
1619 omap_hsmmc_reset_controller_fsm(host, SRC);
1620 host->reqs_blocked += 1;
1621 }
1622 req->cmd->error = -EBADF;
1623 if (req->data)
1624 req->data->error = -EBADF;
1625 req->cmd->retries = 0;
1626 mmc_request_done(mmc, req);
1627 return;
1628 } else if (host->reqs_blocked)
1629 host->reqs_blocked = 0;
a45c6cb8
MC		 1630 WARN_ON(host->mrq != NULL);
1631 host->mrq = req;
70a3341a 1632 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1633 if (err) {
1634 req->cmd->error = err;
1635 if (req->data)
1636 req->data->error = err;
1637 host->mrq = NULL;
1638 mmc_request_done(mmc, req);
1639 return;
1640 }
1641
70a3341a 1642 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1643}
1644
a45c6cb8 1645/* Routine to configure clock values. Exposed API to core */
70a3341a 1646static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1647{
70a3341a 1648 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1649 int do_send_init_stream = 0;
a45c6cb8 1650
fa4aa2d4 1651 pm_runtime_get_sync(host->dev);
5e2ea617 1652
a3621465
AH		 1653 if (ios->power_mode != host->power_mode) {
1654 switch (ios->power_mode) {
1655 case MMC_POWER_OFF:
1656 mmc_slot(host).set_power(host->dev, host->slot_id,
1657 0, 0);
623821f7 1658 host->vdd = 0;
a3621465
AH		 1659 break;
1660 case MMC_POWER_UP:
1661 mmc_slot(host).set_power(host->dev, host->slot_id,
1662 1, ios->vdd);
623821f7 1663 host->vdd = ios->vdd;
a3621465
AH		 1664 break;
1665 case MMC_POWER_ON:
1666 do_send_init_stream = 1;
1667 break;
1668 }
1669 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1670 }
1671
dd498eff
DK		 1672 /* FIXME: set registers based only on changes to ios */
1673
3796fb8a 1674 omap_hsmmc_set_bus_width(host);
a45c6cb8 1675
4621d5f8 1676 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1677 /* Only MMC1 can interface at 3V without some flavor
1678 * of external transceiver; but they all handle 1.8V.
1679 */
a45c6cb8
MC		 1680 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1681 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1682 /*
1683 * The mmc_select_voltage fn of the core does
1684 * not seem to set the power_mode to
1685 * MMC_POWER_UP upon recalculating the voltage.
1686 * vdd 1.8v.
1687 */
70a3341a
DK		 1688 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1689 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1690 "Switch operation failed\n");
1691 }
1692 }
1693
5934df2f 1694 omap_hsmmc_set_clock(host);
a45c6cb8 1695
a3621465 1696 if (do_send_init_stream)
a45c6cb8
MC		 1697 send_init_stream(host);
1698
3796fb8a 1699 omap_hsmmc_set_bus_mode(host);
5e2ea617 1700
fa4aa2d4 1701 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1702}
1703
1704static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1705{
70a3341a 1706 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1707
191d1f1d 1708 if (!mmc_slot(host).card_detect)
a45c6cb8 1709 return -ENOSYS;
db0fefc5 1710 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1711}
1712
1713static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1714{
70a3341a 1715 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1716
191d1f1d 1717 if (!mmc_slot(host).get_ro)
a45c6cb8 1718 return -ENOSYS;
191d1f1d 1719 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1720}
1721
4816858c
GI		 1722static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1723{
1724 struct omap_hsmmc_host *host = mmc_priv(mmc);
1725
1726 if (mmc_slot(host).init_card)
1727 mmc_slot(host).init_card(card);
1728}
1729
70a3341a 1730static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1731{
1732 u32 hctl, capa, value;
1733
1734 /* Only MMC1 supports 3.0V */
4621d5f8 1735 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1736 hctl = SDVS30;
1737 capa = VS30 | VS18;
1738 } else {
1739 hctl = SDVS18;
1740 capa = VS18;
1741 }
1742
1743 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1744 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1745
1746 value = OMAP_HSMMC_READ(host->base, CAPA);
1747 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1748
1749 /* Set the controller to AUTO IDLE mode */
1750 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1751 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1752
1753 /* Set SD bus power bit */
e13bb300 1754 set_sd_bus_power(host);
1b331e69
KK		 1755}
1756
70a3341a 1757static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1758{
70a3341a 1759 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1760
fa4aa2d4
B		 1761 pm_runtime_get_sync(host->dev);
1762
dd498eff
DK		 1763 return 0;
1764}
1765
70a3341a 1766static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1767{
70a3341a 1768 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1769
fa4aa2d4
B		 1770 pm_runtime_mark_last_busy(host->dev);
1771 pm_runtime_put_autosuspend(host->dev);
1772
dd498eff
DK		 1773 return 0;
1774}
1775
70a3341a
DK		 1776static const struct mmc_host_ops omap_hsmmc_ops = {
1777 .enable = omap_hsmmc_enable_fclk,
1778 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1779 .post_req = omap_hsmmc_post_req,
1780 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1781 .request = omap_hsmmc_request,
1782 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1783 .get_cd = omap_hsmmc_get_cd,
1784 .get_ro = omap_hsmmc_get_ro,
4816858c 1785 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1786 /* NYET -- enable_sdio_irq */
1787};
1788
d900f712
DK		 1789#ifdef CONFIG_DEBUG_FS
1790
70a3341a 1791static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1792{
1793 struct mmc_host *mmc = s->private;
70a3341a 1794 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1795 int context_loss = 0;
1796
70a3341a
DK		 1797 if (host->pdata->get_context_loss_count)
1798 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1799
5e2ea617
AH		 1800 seq_printf(s, "mmc%d:\n"
1801 " enabled:\t%d\n"
dd498eff 1802 " dpm_state:\t%d\n"
5e2ea617 1803 " nesting_cnt:\t%d\n"
11dd62a7 1804 " ctx_loss:\t%d:%d\n"
5e2ea617 1805 "\nregs:\n",
dd498eff
DK		 1806 mmc->index, mmc->enabled ? 1 : 0,
1807 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1808 host->context_loss, context_loss);
5e2ea617 1809
7a8c2cef 1810 if (host->suspended) {
dd498eff
DK		 1811 seq_printf(s, "host suspended, can't read registers\n");
1812 return 0;
1813 }
1814
fa4aa2d4 1815 pm_runtime_get_sync(host->dev);
d900f712
DK		 1816
1817 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1818 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1819 seq_printf(s, "CON:\t\t0x%08x\n",
1820 OMAP_HSMMC_READ(host->base, CON));
1821 seq_printf(s, "HCTL:\t\t0x%08x\n",
1822 OMAP_HSMMC_READ(host->base, HCTL));
1823 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1824 OMAP_HSMMC_READ(host->base, SYSCTL));
1825 seq_printf(s, "IE:\t\t0x%08x\n",
1826 OMAP_HSMMC_READ(host->base, IE));
1827 seq_printf(s, "ISE:\t\t0x%08x\n",
1828 OMAP_HSMMC_READ(host->base, ISE));
1829 seq_printf(s, "CAPA:\t\t0x%08x\n",
1830 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1831
fa4aa2d4
B		 1832 pm_runtime_mark_last_busy(host->dev);
1833 pm_runtime_put_autosuspend(host->dev);
dd498eff 1834
d900f712
DK		 1835 return 0;
1836}
1837
70a3341a 1838static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1839{
70a3341a 1840 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1841}
1842
1843static const struct file_operations mmc_regs_fops = {
70a3341a 1844 .open = omap_hsmmc_regs_open,
d900f712
DK		 1845 .read = seq_read,
1846 .llseek = seq_lseek,
1847 .release = single_release,
1848};
1849
70a3341a 1850static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1851{
1852 if (mmc->debugfs_root)
1853 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1854 mmc, &mmc_regs_fops);
1855}
1856
1857#else
1858
70a3341a 1859static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1860{
1861}
1862
1863#endif
1864
70a3341a 1865static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1866{
1867 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1868 struct mmc_host *mmc;
70a3341a 1869 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1870 struct resource *res;
db0fefc5 1871 int ret, irq;
a45c6cb8
MC		 1872
1873 if (pdata == NULL) {
1874 dev_err(&pdev->dev, "Platform Data is missing\n");
1875 return -ENXIO;
1876 }
1877
1878 if (pdata->nr_slots == 0) {
1879 dev_err(&pdev->dev, "No Slots\n");
1880 return -ENXIO;
1881 }
1882
1883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1884 irq = platform_get_irq(pdev, 0);
1885 if (res == NULL || irq < 0)
1886 return -ENXIO;
1887
91a0b089 1888 res->start += pdata->reg_offset;
1889 res->end += pdata->reg_offset;
984b203a 1890 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1891 if (res == NULL)
1892 return -EBUSY;
1893
db0fefc5
AH		 1894 ret = omap_hsmmc_gpio_init(pdata);
1895 if (ret)
1896 goto err;
1897
70a3341a 1898 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1899 if (!mmc) {
1900 ret = -ENOMEM;
db0fefc5 1901 goto err_alloc;
a45c6cb8
MC		 1902 }
1903
1904 host = mmc_priv(mmc);
1905 host->mmc = mmc;
1906 host->pdata = pdata;
1907 host->dev = &pdev->dev;
1908 host->use_dma = 1;
1909 host->dev->dma_mask = &pdata->dma_mask;
1910 host->dma_ch = -1;
1911 host->irq = irq;
1912 host->id = pdev->id;
1913 host->slot_id = 0;
1914 host->mapbase = res->start;
1915 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1916 host->power_mode = MMC_POWER_OFF;
9782aff8 1917 host->next_data.cookie = 1;
a45c6cb8
MC		 1918
1919 platform_set_drvdata(pdev, host);
70a3341a 1920 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 1921
7a8c2cef 1922 mmc->ops = &omap_hsmmc_ops;
dd498eff 1923
e0eb2424
AH		 1924 /*
1925 * If regulator_disable can only put vcc_aux to sleep then there is
1926 * no off state.
1927 */
1928 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1929 mmc_slot(host).no_off = 1;
1930
6b206efe
AS		 1931 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1932 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1933
4dffd7a2 1934 spin_lock_init(&host->irq_lock);
a45c6cb8 1935
6f7607cc 1936 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1937 if (IS_ERR(host->fclk)) {
1938 ret = PTR_ERR(host->fclk);
1939 host->fclk = NULL;
a45c6cb8
MC		 1940 goto err1;
1941 }
1942
70a3341a 1943 omap_hsmmc_context_save(host);
11dd62a7 1944
5e2ea617 1945 mmc->caps |= MMC_CAP_DISABLE;
dd498eff 1946
fa4aa2d4
B		 1947 pm_runtime_enable(host->dev);
1948 pm_runtime_get_sync(host->dev);
1949 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1950 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1951
2bec0893
AH		 1952 if (cpu_is_omap2430()) {
1953 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1954 /*
1955 * MMC can still work without debounce clock.
1956 */
1957 if (IS_ERR(host->dbclk))
1958 dev_warn(mmc_dev(host->mmc),
1959 "Failed to get debounce clock\n");
a45c6cb8 1960 else
2bec0893
AH		 1961 host->got_dbclk = 1;
1962
1963 if (host->got_dbclk)
1964 if (clk_enable(host->dbclk) != 0)
1965 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1966 " clk failed\n");
1967 }
a45c6cb8 1968
0ccd76d4
JY		 1969 /* Since we do only SG emulation, we can have as many segs
1970 * as we want. */
a36274e0 1971 mmc->max_segs = 1024;
0ccd76d4 1972
a45c6cb8
MC		 1973 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1974 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1975 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1976 mmc->max_seg_size = mmc->max_req_size;
1977
13189e78 1978 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1979 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1980
3a63833e
SG		 1981 mmc->caps |= mmc_slot(host).caps;
1982 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1983 mmc->caps |= MMC_CAP_4_BIT_DATA;
1984
191d1f1d 1985 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1986 mmc->caps |= MMC_CAP_NONREMOVABLE;
1987
70a3341a 1988 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1989
f3e2f1dd
GI		 1990 /* Select DMA lines */
1991 switch (host->id) {
1992 case OMAP_MMC1_DEVID:
1993 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1994 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1995 break;
1996 case OMAP_MMC2_DEVID:
1997 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1998 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1999 break;
2000 case OMAP_MMC3_DEVID:
2001 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2002 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2003 break;
82cf818d 2004 case OMAP_MMC4_DEVID:
2005 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2006 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2007 break;
2008 case OMAP_MMC5_DEVID:
2009 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2010 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2011 break;
f3e2f1dd
GI		 2012 default:
2013 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2014 goto err_irq;
2015 }
a45c6cb8
MC		 2016
2017 /* Request IRQ for MMC operations */
d9618e9f 2018 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 2019 mmc_hostname(mmc), host);
2020 if (ret) {
2021 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2022 goto err_irq;
2023 }
2024
2025 if (pdata->init != NULL) {
2026 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2027 dev_dbg(mmc_dev(host->mmc),
2028 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2029 goto err_irq_cd_init;
2030 }
2031 }
db0fefc5 2032
b702b106 2033 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2034 ret = omap_hsmmc_reg_get(host);
2035 if (ret)
2036 goto err_reg;
2037 host->use_reg = 1;
2038 }
2039
b583f26d 2040 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2041
2042 /* Request IRQ for card detect */
e1a55f5e 2043 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2044 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2045 omap_hsmmc_cd_handler,
d9618e9f 2046 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
a45c6cb8
MC		 2047 mmc_hostname(mmc), host);
2048 if (ret) {
2049 dev_dbg(mmc_dev(host->mmc),
2050 "Unable to grab MMC CD IRQ\n");
2051 goto err_irq_cd;
2052 }
72f2e2c7 2053 pdata->suspend = omap_hsmmc_suspend_cdirq;
2054 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 2055 }
2056
b417577d 2057 omap_hsmmc_disable_irq(host);
a45c6cb8 2058
b62f6228
AH		 2059 omap_hsmmc_protect_card(host);
2060
a45c6cb8
MC		 2061 mmc_add_host(mmc);
2062
191d1f1d 2063 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2064 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2065 if (ret < 0)
2066 goto err_slot_name;
2067 }
191d1f1d 2068 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2069 ret = device_create_file(&mmc->class_dev,
2070 &dev_attr_cover_switch);
2071 if (ret < 0)
db0fefc5 2072 goto err_slot_name;
a45c6cb8
MC		 2073 }
2074
70a3341a 2075 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2076 pm_runtime_mark_last_busy(host->dev);
2077 pm_runtime_put_autosuspend(host->dev);
d900f712 2078
a45c6cb8
MC		 2079 return 0;
2080
a45c6cb8
MC		 2081err_slot_name:
2082 mmc_remove_host(mmc);
a45c6cb8 2083 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2084err_irq_cd:
2085 if (host->use_reg)
2086 omap_hsmmc_reg_put(host);
2087err_reg:
2088 if (host->pdata->cleanup)
2089 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2090err_irq_cd_init:
2091 free_irq(host->irq, host);
2092err_irq:
fa4aa2d4
B		 2093 pm_runtime_mark_last_busy(host->dev);
2094 pm_runtime_put_autosuspend(host->dev);
a45c6cb8 2095 clk_put(host->fclk);
2bec0893 2096 if (host->got_dbclk) {
a45c6cb8
MC		 2097 clk_disable(host->dbclk);
2098 clk_put(host->dbclk);
2099 }
a45c6cb8
MC		 2100err1:
2101 iounmap(host->base);
db0fefc5
AH		 2102 platform_set_drvdata(pdev, NULL);
2103 mmc_free_host(mmc);
2104err_alloc:
2105 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2106err:
984b203a 2107 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2108 return ret;
2109}
2110
70a3341a 2111static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2112{
70a3341a 2113 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2114 struct resource *res;
2115
2116 if (host) {
fa4aa2d4 2117 pm_runtime_get_sync(host->dev);
a45c6cb8 2118 mmc_remove_host(host->mmc);
db0fefc5
AH		 2119 if (host->use_reg)
2120 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2121 if (host->pdata->cleanup)
2122 host->pdata->cleanup(&pdev->dev);
2123 free_irq(host->irq, host);
2124 if (mmc_slot(host).card_detect_irq)
2125 free_irq(mmc_slot(host).card_detect_irq, host);
0d9ee5b2 2126 flush_work_sync(&host->mmc_carddetect_work);
a45c6cb8 2127
fa4aa2d4
B		 2128 pm_runtime_put_sync(host->dev);
2129 pm_runtime_disable(host->dev);
a45c6cb8 2130 clk_put(host->fclk);
2bec0893 2131 if (host->got_dbclk) {
a45c6cb8
MC		 2132 clk_disable(host->dbclk);
2133 clk_put(host->dbclk);
2134 }
2135
2136 mmc_free_host(host->mmc);
2137 iounmap(host->base);
db0fefc5 2138 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2139 }
2140
2141 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2142 if (res)
984b203a 2143 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2144 platform_set_drvdata(pdev, NULL);
2145
2146 return 0;
2147}
2148
2149#ifdef CONFIG_PM
a791daa1 2150static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2151{
2152 int ret = 0;
a791daa1 2153 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2154 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2155
2156 if (host && host->suspended)
2157 return 0;
2158
2159 if (host) {
fa4aa2d4 2160 pm_runtime_get_sync(host->dev);
a6b2240d
AH		 2161 host->suspended = 1;
2162 if (host->pdata->suspend) {
2163 ret = host->pdata->suspend(&pdev->dev,
2164 host->slot_id);
2165 if (ret) {
2166 dev_dbg(mmc_dev(host->mmc),
2167 "Unable to handle MMC board"
2168 " level suspend\n");
2169 host->suspended = 0;
2170 return ret;
2171 }
2172 }
2173 cancel_work_sync(&host->mmc_carddetect_work);
1a13f8fa 2174 ret = mmc_suspend_host(host->mmc);
fa4aa2d4 2175
a45c6cb8 2176 if (ret == 0) {
b417577d 2177 omap_hsmmc_disable_irq(host);
0683af48 2178 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2179 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2bec0893
AH		 2180 if (host->got_dbclk)
2181 clk_disable(host->dbclk);
a6b2240d
AH		 2182 } else {
2183 host->suspended = 0;
2184 if (host->pdata->resume) {
2185 ret = host->pdata->resume(&pdev->dev,
2186 host->slot_id);
2187 if (ret)
2188 dev_dbg(mmc_dev(host->mmc),
2189 "Unmask interrupt failed\n");
2190 }
a6b2240d 2191 }
fa4aa2d4 2192 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2193 }
2194 return ret;
2195}
2196
2197/* Routine to resume the MMC device */
a791daa1 2198static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2199{
2200 int ret = 0;
a791daa1 2201 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2202 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2203
2204 if (host && !host->suspended)
2205 return 0;
2206
2207 if (host) {
fa4aa2d4 2208 pm_runtime_get_sync(host->dev);
11dd62a7 2209
2bec0893
AH		 2210 if (host->got_dbclk)
2211 clk_enable(host->dbclk);
2212
70a3341a 2213 omap_hsmmc_conf_bus_power(host);
1b331e69 2214
a45c6cb8
MC		 2215 if (host->pdata->resume) {
2216 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2217 if (ret)
2218 dev_dbg(mmc_dev(host->mmc),
2219 "Unmask interrupt failed\n");
2220 }
2221
b62f6228
AH		 2222 omap_hsmmc_protect_card(host);
2223
a45c6cb8
MC		 2224 /* Notify the core to resume the host */
2225 ret = mmc_resume_host(host->mmc);
2226 if (ret == 0)
2227 host->suspended = 0;
fa4aa2d4
B		 2228
2229 pm_runtime_mark_last_busy(host->dev);
2230 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2231 }
2232
2233 return ret;
2234
a45c6cb8
MC		 2235}
2236
2237#else
70a3341a
DK		 2238#define omap_hsmmc_suspend NULL
2239#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2240#endif
2241
fa4aa2d4
B		 2242static int omap_hsmmc_runtime_suspend(struct device *dev)
2243{
2244 struct omap_hsmmc_host *host;
2245
2246 host = platform_get_drvdata(to_platform_device(dev));
2247 omap_hsmmc_context_save(host);
2248 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2249
2250 return 0;
2251}
2252
2253static int omap_hsmmc_runtime_resume(struct device *dev)
2254{
2255 struct omap_hsmmc_host *host;
2256
2257 host = platform_get_drvdata(to_platform_device(dev));
2258 omap_hsmmc_context_restore(host);
2259 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2260
2261 return 0;
2262}
2263
a791daa1 2264static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2265 .suspend = omap_hsmmc_suspend,
2266 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2267 .runtime_suspend = omap_hsmmc_runtime_suspend,
2268 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2269};
2270
2271static struct platform_driver omap_hsmmc_driver = {
2272 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2273 .driver = {
2274 .name = DRIVER_NAME,
2275 .owner = THIS_MODULE,
a791daa1 2276 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2277 },
2278};
2279
70a3341a 2280static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2281{
2282 /* Register the MMC driver */
8753298a 2283 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2284}
2285
70a3341a 2286static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2287{
2288 /* Unregister MMC driver */
70a3341a 2289 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2290}
2291
70a3341a
DK		 2292module_init(omap_hsmmc_init);
2293module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2294
2295MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2296MODULE_LICENSE("GPL");
2297MODULE_ALIAS("platform:" DRIVER_NAME);
2298MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)