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ARM: OMAP: mmc-twl4030: add regulator sleep / wake function
[linux-2.6-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
30#include <linux/io.h>
31#include <linux/semaphore.h>
32#include <mach/dma.h>
33#include <mach/hardware.h>
34#include <mach/board.h>
35#include <mach/mmc.h>
36#include <mach/cpu.h>
37
38/* OMAP HSMMC Host Controller Registers */
39#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 40#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 41#define OMAP_HSMMC_CON 0x002C
42#define OMAP_HSMMC_BLK 0x0104
43#define OMAP_HSMMC_ARG 0x0108
44#define OMAP_HSMMC_CMD 0x010C
45#define OMAP_HSMMC_RSP10 0x0110
46#define OMAP_HSMMC_RSP32 0x0114
47#define OMAP_HSMMC_RSP54 0x0118
48#define OMAP_HSMMC_RSP76 0x011C
49#define OMAP_HSMMC_DATA 0x0120
50#define OMAP_HSMMC_HCTL 0x0128
51#define OMAP_HSMMC_SYSCTL 0x012C
52#define OMAP_HSMMC_STAT 0x0130
53#define OMAP_HSMMC_IE 0x0134
54#define OMAP_HSMMC_ISE 0x0138
55#define OMAP_HSMMC_CAPA 0x0140
56
57#define VS18 (1 << 26)
58#define VS30 (1 << 25)
59#define SDVS18 (0x5 << 9)
60#define SDVS30 (0x6 << 9)
eb250826 61#define SDVS33 (0x7 << 9)
1b331e69 62#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 63#define SDVSCLR 0xFFFFF1FF
64#define SDVSDET 0x00000400
65#define AUTOIDLE 0x1
66#define SDBP (1 << 8)
67#define DTO 0xe
68#define ICE 0x1
69#define ICS 0x2
70#define CEN (1 << 2)
71#define CLKD_MASK 0x0000FFC0
72#define CLKD_SHIFT 6
73#define DTO_MASK 0x000F0000
74#define DTO_SHIFT 16
75#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 76#define BWR_ENABLE (1 << 4)
77#define BRR_ENABLE (1 << 5)
a45c6cb8
MC		 78#define INIT_STREAM (1 << 1)
79#define DP_SELECT (1 << 21)
80#define DDIR (1 << 4)
81#define DMA_EN 0x1
82#define MSBS (1 << 5)
83#define BCE (1 << 1)
84#define FOUR_BIT (1 << 1)
73153010 85#define DW8 (1 << 5)
a45c6cb8
MC		 86#define CC 0x1
87#define TC 0x02
88#define OD 0x1
89#define ERR (1 << 15)
90#define CMD_TIMEOUT (1 << 16)
91#define DATA_TIMEOUT (1 << 20)
92#define CMD_CRC (1 << 17)
93#define DATA_CRC (1 << 21)
94#define CARD_ERR (1 << 28)
95#define STAT_CLEAR 0xFFFFFFFF
96#define INIT_STREAM_CMD 0x00000000
97#define DUAL_VOLT_OCR_BIT 7
98#define SRC (1 << 25)
99#define SRD (1 << 26)
11dd62a7
DK		 100#define SOFTRESET (1 << 1)
101#define RESETDONE (1 << 0)
a45c6cb8
MC		 102
103/*
104 * FIXME: Most likely all the data using these _DEVID defines should come
105 * from the platform_data, or implemented in controller and slot specific
106 * functions.
107 */
108#define OMAP_MMC1_DEVID 0
109#define OMAP_MMC2_DEVID 1
f3e2f1dd 110#define OMAP_MMC3_DEVID 2
a45c6cb8 111
a45c6cb8
MC		 112#define MMC_TIMEOUT_MS 20
113#define OMAP_MMC_MASTER_CLOCK 96000000
114#define DRIVER_NAME "mmci-omap-hs"
115
dd498eff
DK		 116/* Timeouts for entering power saving states on inactivity, msec */
117#define OMAP_MMC_DISABLED_TIMEOUT 100
118#define OMAP_MMC_OFF_TIMEOUT 1000
119
a45c6cb8
MC		 120/*
121 * One controller can have multiple slots, like on some omap boards using
122 * omap.c controller driver. Luckily this is not currently done on any known
123 * omap_hsmmc.c device.
124 */
125#define mmc_slot(host) (host->pdata->slots[host->slot_id])
126
127/*
128 * MMC Host controller read/write API's
129 */
130#define OMAP_HSMMC_READ(base, reg) \
131 __raw_readl((base) + OMAP_HSMMC_##reg)
132
133#define OMAP_HSMMC_WRITE(base, reg, val) \
134 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
135
136struct mmc_omap_host {
137 struct device *dev;
138 struct mmc_host *mmc;
139 struct mmc_request *mrq;
140 struct mmc_command *cmd;
141 struct mmc_data *data;
142 struct clk *fclk;
143 struct clk *iclk;
144 struct clk *dbclk;
145 struct semaphore sem;
146 struct work_struct mmc_carddetect_work;
147 void __iomem *base;
148 resource_size_t mapbase;
149 unsigned int id;
150 unsigned int dma_len;
0ccd76d4 151 unsigned int dma_sg_idx;
a45c6cb8 152 unsigned char bus_mode;
a3621465 153 unsigned char power_mode;
a45c6cb8
MC		 154 u32 *buffer;
155 u32 bytesleft;
156 int suspended;
157 int irq;
a45c6cb8 158 int use_dma, dma_ch;
f3e2f1dd 159 int dma_line_tx, dma_line_rx;
a45c6cb8
MC		 160 int slot_id;
161 int dbclk_enabled;
4a694dc9 162 int response_busy;
11dd62a7 163 int context_loss;
dd498eff 164 int dpm_state;
11dd62a7 165
a45c6cb8
MC		 166 struct omap_mmc_platform_data *pdata;
167};
168
169/*
170 * Stop clock to the card
171 */
172static void omap_mmc_stop_clock(struct mmc_omap_host *host)
173{
174 OMAP_HSMMC_WRITE(host->base, SYSCTL,
175 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
176 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
177 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
178}
179
11dd62a7
DK		 180#ifdef CONFIG_PM
181
182/*
183 * Restore the MMC host context, if it was lost as result of a
184 * power state change.
185 */
186static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
187{
188 struct mmc_ios *ios = &host->mmc->ios;
189 struct omap_mmc_platform_data *pdata = host->pdata;
190 int context_loss = 0;
191 u32 hctl, capa, con;
192 u16 dsor = 0;
193 unsigned long timeout;
194
195 if (pdata->get_context_loss_count) {
196 context_loss = pdata->get_context_loss_count(host->dev);
197 if (context_loss < 0)
198 return 1;
199 }
200
201 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
202 context_loss == host->context_loss ? "not " : "");
203 if (host->context_loss == context_loss)
204 return 1;
205
206 /* Wait for hardware reset */
207 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
208 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
209 && time_before(jiffies, timeout))
210 ;
211
212 /* Do software reset */
213 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
214 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
215 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
216 && time_before(jiffies, timeout))
217 ;
218
219 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
220 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
221
222 if (host->id == OMAP_MMC1_DEVID) {
223 if (host->power_mode != MMC_POWER_OFF &&
224 (1 << ios->vdd) <= MMC_VDD_23_24)
225 hctl = SDVS18;
226 else
227 hctl = SDVS30;
228 capa = VS30 | VS18;
229 } else {
230 hctl = SDVS18;
231 capa = VS18;
232 }
233
234 OMAP_HSMMC_WRITE(host->base, HCTL,
235 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
236
237 OMAP_HSMMC_WRITE(host->base, CAPA,
238 OMAP_HSMMC_READ(host->base, CAPA) | capa);
239
240 OMAP_HSMMC_WRITE(host->base, HCTL,
241 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
242
243 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
244 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
245 && time_before(jiffies, timeout))
246 ;
247
248 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
249 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
250 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
251
252 /* Do not initialize card-specific things if the power is off */
253 if (host->power_mode == MMC_POWER_OFF)
254 goto out;
255
256 con = OMAP_HSMMC_READ(host->base, CON);
257 switch (ios->bus_width) {
258 case MMC_BUS_WIDTH_8:
259 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
260 break;
261 case MMC_BUS_WIDTH_4:
262 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
263 OMAP_HSMMC_WRITE(host->base, HCTL,
264 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
265 break;
266 case MMC_BUS_WIDTH_1:
267 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
268 OMAP_HSMMC_WRITE(host->base, HCTL,
269 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
270 break;
271 }
272
273 if (ios->clock) {
274 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
275 if (dsor < 1)
276 dsor = 1;
277
278 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
279 dsor++;
280
281 if (dsor > 250)
282 dsor = 250;
283 }
284
285 OMAP_HSMMC_WRITE(host->base, SYSCTL,
286 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
287 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
288 OMAP_HSMMC_WRITE(host->base, SYSCTL,
289 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
290
291 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
292 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
293 && time_before(jiffies, timeout))
294 ;
295
296 OMAP_HSMMC_WRITE(host->base, SYSCTL,
297 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
298
299 con = OMAP_HSMMC_READ(host->base, CON);
300 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
301 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
302 else
303 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
304out:
305 host->context_loss = context_loss;
306
307 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
308 return 0;
309}
310
311/*
312 * Save the MMC host context (store the number of power state changes so far).
313 */
314static void omap_mmc_save_ctx(struct mmc_omap_host *host)
315{
316 struct omap_mmc_platform_data *pdata = host->pdata;
317 int context_loss;
318
319 if (pdata->get_context_loss_count) {
320 context_loss = pdata->get_context_loss_count(host->dev);
321 if (context_loss < 0)
322 return;
323 host->context_loss = context_loss;
324 }
325}
326
327#else
328
329static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
330{
331 return 0;
332}
333
334static void omap_mmc_save_ctx(struct mmc_omap_host *host)
335{
336}
337
338#endif
339
a45c6cb8
MC		 340/*
341 * Send init stream sequence to card
342 * before sending IDLE command
343 */
344static void send_init_stream(struct mmc_omap_host *host)
345{
346 int reg = 0;
347 unsigned long timeout;
348
349 disable_irq(host->irq);
350 OMAP_HSMMC_WRITE(host->base, CON,
351 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
352 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
353
354 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
355 while ((reg != CC) && time_before(jiffies, timeout))
356 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
357
358 OMAP_HSMMC_WRITE(host->base, CON,
359 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
360 enable_irq(host->irq);
361}
362
363static inline
364int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
365{
366 int r = 1;
367
368 if (host->pdata->slots[host->slot_id].get_cover_state)
369 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
370 host->slot_id);
371 return r;
372}
373
374static ssize_t
375mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
376 char *buf)
377{
378 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
379 struct mmc_omap_host *host = mmc_priv(mmc);
380
381 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
382 "open");
383}
384
385static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
386
387static ssize_t
388mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
389 char *buf)
390{
391 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
392 struct mmc_omap_host *host = mmc_priv(mmc);
393 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
394
e68fdabc 395 return sprintf(buf, "%s\n", slot.name);
a45c6cb8
MC		 396}
397
398static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
399
400/*
401 * Configure the response type and send the cmd.
402 */
403static void
404mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
405 struct mmc_data *data)
406{
407 int cmdreg = 0, resptype = 0, cmdtype = 0;
408
409 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
410 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
411 host->cmd = cmd;
412
413 /*
414 * Clear status bits and enable interrupts
415 */
416 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
417 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
ccdfe3a6
AG		 418
419 if (host->use_dma)
420 OMAP_HSMMC_WRITE(host->base, IE,
421 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
422 else
423 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8 424
4a694dc9 425 host->response_busy = 0;
a45c6cb8
MC		 426 if (cmd->flags & MMC_RSP_PRESENT) {
427 if (cmd->flags & MMC_RSP_136)
428 resptype = 1;
4a694dc9
AH		 429 else if (cmd->flags & MMC_RSP_BUSY) {
430 resptype = 3;
431 host->response_busy = 1;
432 } else
a45c6cb8
MC		 433 resptype = 2;
434 }
435
436 /*
437 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
438 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
439 * a val of 0x3, rest 0x0.
440 */
441 if (cmd == host->mrq->stop)
442 cmdtype = 0x3;
443
444 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
445
446 if (data) {
447 cmdreg |= DP_SELECT | MSBS | BCE;
448 if (data->flags & MMC_DATA_READ)
449 cmdreg |= DDIR;
450 else
451 cmdreg &= ~(DDIR);
452 }
453
454 if (host->use_dma)
455 cmdreg |= DMA_EN;
456
457 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
458 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
459}
460
0ccd76d4
JY		 461static int
462mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
463{
464 if (data->flags & MMC_DATA_WRITE)
465 return DMA_TO_DEVICE;
466 else
467 return DMA_FROM_DEVICE;
468}
469
a45c6cb8
MC		 470/*
471 * Notify the transfer complete to MMC core
472 */
473static void
474mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
475{
4a694dc9
AH		 476 if (!data) {
477 struct mmc_request *mrq = host->mrq;
478
479 host->mrq = NULL;
4a694dc9
AH		 480 mmc_request_done(host->mmc, mrq);
481 return;
482 }
483
a45c6cb8
MC		 484 host->data = NULL;
485
486 if (host->use_dma && host->dma_ch != -1)
487 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
0ccd76d4 488 mmc_omap_get_dma_dir(host, data));
a45c6cb8
MC		 489
490 if (!data->error)
491 data->bytes_xfered += data->blocks * (data->blksz);
492 else
493 data->bytes_xfered = 0;
494
495 if (!data->stop) {
496 host->mrq = NULL;
497 mmc_request_done(host->mmc, data->mrq);
498 return;
499 }
500 mmc_omap_start_command(host, data->stop, NULL);
501}
502
503/*
504 * Notify the core about command completion
505 */
506static void
507mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
508{
509 host->cmd = NULL;
510
511 if (cmd->flags & MMC_RSP_PRESENT) {
512 if (cmd->flags & MMC_RSP_136) {
513 /* response type 2 */
514 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
515 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
516 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
517 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
518 } else {
519 /* response types 1, 1b, 3, 4, 5, 6 */
520 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
521 }
522 }
4a694dc9 523 if ((host->data == NULL && !host->response_busy) || cmd->error) {
a45c6cb8
MC		 524 host->mrq = NULL;
525 mmc_request_done(host->mmc, cmd->mrq);
526 }
527}
528
529/*
530 * DMA clean up for command errors
531 */
82788ff5 532static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
a45c6cb8 533{
82788ff5 534 host->data->error = errno;
a45c6cb8
MC		 535
536 if (host->use_dma && host->dma_ch != -1) {
537 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
0ccd76d4 538 mmc_omap_get_dma_dir(host, host->data));
a45c6cb8
MC		 539 omap_free_dma(host->dma_ch);
540 host->dma_ch = -1;
541 up(&host->sem);
542 }
543 host->data = NULL;
a45c6cb8
MC		 544}
545
546/*
547 * Readable error output
548 */
549#ifdef CONFIG_MMC_DEBUG
550static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
551{
552 /* --- means reserved bit without definition at documentation */
553 static const char *mmc_omap_status_bits[] = {
554 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
555 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
556 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
557 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
558 };
559 char res[256];
560 char *buf = res;
561 int len, i;
562
563 len = sprintf(buf, "MMC IRQ 0x%x :", status);
564 buf += len;
565
566 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
567 if (status & (1 << i)) {
568 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
569 buf += len;
570 }
571
572 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
573}
574#endif /* CONFIG_MMC_DEBUG */
575
3ebf74b1
JP		 576/*
577 * MMC controller internal state machines reset
578 *
579 * Used to reset command or data internal state machines, using respectively
580 * SRC or SRD bit of SYSCTL register
581 * Can be called from interrupt context
582 */
583static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
584 unsigned long bit)
585{
586 unsigned long i = 0;
587 unsigned long limit = (loops_per_jiffy *
588 msecs_to_jiffies(MMC_TIMEOUT_MS));
589
590 OMAP_HSMMC_WRITE(host->base, SYSCTL,
591 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
592
593 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
594 (i++ < limit))
595 cpu_relax();
596
597 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
598 dev_err(mmc_dev(host->mmc),
599 "Timeout waiting on controller reset in %s\n",
600 __func__);
601}
a45c6cb8
MC		 602
603/*
604 * MMC controller IRQ handler
605 */
606static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
607{
608 struct mmc_omap_host *host = dev_id;
609 struct mmc_data *data;
610 int end_cmd = 0, end_trans = 0, status;
611
4a694dc9 612 if (host->mrq == NULL) {
a45c6cb8
MC		 613 OMAP_HSMMC_WRITE(host->base, STAT,
614 OMAP_HSMMC_READ(host->base, STAT));
00adadc1
KH		 615 /* Flush posted write */
616 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8
MC		 617 return IRQ_HANDLED;
618 }
619
620 data = host->data;
621 status = OMAP_HSMMC_READ(host->base, STAT);
622 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
623
624 if (status & ERR) {
625#ifdef CONFIG_MMC_DEBUG
626 mmc_omap_report_irq(host, status);
627#endif
628 if ((status & CMD_TIMEOUT) ||
629 (status & CMD_CRC)) {
630 if (host->cmd) {
631 if (status & CMD_TIMEOUT) {
3ebf74b1 632 mmc_omap_reset_controller_fsm(host, SRC);
a45c6cb8
MC		 633 host->cmd->error = -ETIMEDOUT;
634 } else {
635 host->cmd->error = -EILSEQ;
636 }
637 end_cmd = 1;
638 }
4a694dc9
AH		 639 if (host->data || host->response_busy) {
640 if (host->data)
641 mmc_dma_cleanup(host, -ETIMEDOUT);
642 host->response_busy = 0;
3ebf74b1 643 mmc_omap_reset_controller_fsm(host, SRD);
c232f457 644 }
a45c6cb8
MC		 645 }
646 if ((status & DATA_TIMEOUT) ||
647 (status & DATA_CRC)) {
4a694dc9
AH		 648 if (host->data || host->response_busy) {
649 int err = (status & DATA_TIMEOUT) ?
650 -ETIMEDOUT : -EILSEQ;
651
652 if (host->data)
653 mmc_dma_cleanup(host, err);
a45c6cb8 654 else
4a694dc9
AH		 655 host->mrq->cmd->error = err;
656 host->response_busy = 0;
3ebf74b1 657 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 658 end_trans = 1;
659 }
660 }
661 if (status & CARD_ERR) {
662 dev_dbg(mmc_dev(host->mmc),
663 "Ignoring card err CMD%d\n", host->cmd->opcode);
664 if (host->cmd)
665 end_cmd = 1;
666 if (host->data)
667 end_trans = 1;
668 }
669 }
670
671 OMAP_HSMMC_WRITE(host->base, STAT, status);
00adadc1
KH		 672 /* Flush posted write */
673 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8 674
a8fe29d8 675 if (end_cmd || ((status & CC) && host->cmd))
a45c6cb8
MC		 676 mmc_omap_cmd_done(host, host->cmd);
677 if (end_trans || (status & TC))
678 mmc_omap_xfer_done(host, data);
679
680 return IRQ_HANDLED;
681}
682
e13bb300
AH		 683static void set_sd_bus_power(struct mmc_omap_host *host)
684{
685 unsigned long i;
686
687 OMAP_HSMMC_WRITE(host->base, HCTL,
688 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
689 for (i = 0; i < loops_per_jiffy; i++) {
690 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
691 break;
692 cpu_relax();
693 }
694}
695
a45c6cb8 696/*
eb250826
DB		 697 * Switch MMC interface voltage ... only relevant for MMC1.
698 *
699 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
700 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
701 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8
MC		 702 */
703static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
704{
705 u32 reg_val = 0;
706 int ret;
707
708 /* Disable the clocks */
709 clk_disable(host->fclk);
710 clk_disable(host->iclk);
711 clk_disable(host->dbclk);
712
713 /* Turn the power off */
714 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
715 if (ret != 0)
716 goto err;
717
718 /* Turn the power ON with given VDD 1.8 or 3.0v */
719 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
720 if (ret != 0)
721 goto err;
722
723 clk_enable(host->fclk);
724 clk_enable(host->iclk);
725 clk_enable(host->dbclk);
726
727 OMAP_HSMMC_WRITE(host->base, HCTL,
728 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
729 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 730
a45c6cb8
MC		 731 /*
732 * If a MMC dual voltage card is detected, the set_ios fn calls
733 * this fn with VDD bit set for 1.8V. Upon card removal from the
734 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
735 *
eb250826
DB		 736 * Cope with a bit of slop in the range ... per data sheets:
737 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
738 * but recommended values are 1.71V to 1.89V
739 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
740 * but recommended values are 2.7V to 3.3V
741 *
742 * Board setup code shouldn't permit anything very out-of-range.
743 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
744 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 745 */
eb250826 746 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 747 reg_val |= SDVS18;
eb250826
DB		 748 else
749 reg_val |= SDVS30;
a45c6cb8
MC		 750
751 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 752 set_sd_bus_power(host);
a45c6cb8
MC		 753
754 return 0;
755err:
756 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
757 return ret;
758}
759
760/*
761 * Work Item to notify the core about card insertion/removal
762 */
763static void mmc_omap_detect(struct work_struct *work)
764{
765 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
766 mmc_carddetect_work);
249d0fa9 767 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 768 int carddetect;
769
770 if (host->suspended)
771 return;
772
773 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 774
e1a55f5e 775 if (mmc_slot(host).card_detect)
a6b2240d 776 carddetect = slot->card_detect(slot->card_detect_irq);
e1a55f5e 777 else
a6b2240d 778 carddetect = -ENOSYS;
a45c6cb8 779
a6b2240d 780 if (carddetect) {
a45c6cb8
MC		 781 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
782 } else {
5e2ea617 783 mmc_host_enable(host->mmc);
3ebf74b1 784 mmc_omap_reset_controller_fsm(host, SRD);
5e2ea617 785 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 786 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
787 }
788}
789
790/*
791 * ISR for handling card insertion and removal
792 */
793static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
794{
795 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
796
a6b2240d
AH		 797 if (host->suspended)
798 return IRQ_HANDLED;
a45c6cb8
MC		 799 schedule_work(&host->mmc_carddetect_work);
800
801 return IRQ_HANDLED;
802}
803
0ccd76d4
JY		 804static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
805 struct mmc_data *data)
806{
807 int sync_dev;
808
f3e2f1dd
GI		 809 if (data->flags & MMC_DATA_WRITE)
810 sync_dev = host->dma_line_tx;
811 else
812 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 813 return sync_dev;
814}
815
816static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
817 struct mmc_data *data,
818 struct scatterlist *sgl)
819{
820 int blksz, nblk, dma_ch;
821
822 dma_ch = host->dma_ch;
823 if (data->flags & MMC_DATA_WRITE) {
824 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
825 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
826 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
827 sg_dma_address(sgl), 0, 0);
828 } else {
829 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
830 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
831 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
832 sg_dma_address(sgl), 0, 0);
833 }
834
835 blksz = host->data->blksz;
836 nblk = sg_dma_len(sgl) / blksz;
837
838 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
839 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
840 mmc_omap_get_dma_sync_dev(host, data),
841 !(data->flags & MMC_DATA_WRITE));
842
843 omap_start_dma(dma_ch);
844}
845
a45c6cb8
MC		 846/*
847 * DMA call back function
848 */
849static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
850{
851 struct mmc_omap_host *host = data;
852
853 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
854 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
855
856 if (host->dma_ch < 0)
857 return;
858
0ccd76d4
JY		 859 host->dma_sg_idx++;
860 if (host->dma_sg_idx < host->dma_len) {
861 /* Fire up the next transfer. */
862 mmc_omap_config_dma_params(host, host->data,
863 host->data->sg + host->dma_sg_idx);
864 return;
865 }
866
a45c6cb8
MC		 867 omap_free_dma(host->dma_ch);
868 host->dma_ch = -1;
869 /*
870 * DMA Callback: run in interrupt context.
85b84322 871 * mutex_unlock will throw a kernel warning if used.
a45c6cb8
MC		 872 */
873 up(&host->sem);
874}
875
a45c6cb8
MC		 876/*
877 * Routine to configure and start DMA for the MMC card
878 */
879static int
880mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
881{
0ccd76d4 882 int dma_ch = 0, ret = 0, err = 1, i;
a45c6cb8
MC		 883 struct mmc_data *data = req->data;
884
0ccd76d4 885 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 886 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 887 struct scatterlist *sgl;
888
889 sgl = data->sg + i;
890 if (sgl->length % data->blksz)
891 return -EINVAL;
892 }
893 if ((data->blksz % 4) != 0)
894 /* REVISIT: The MMC buffer increments only when MSB is written.
895 * Return error for blksz which is non multiple of four.
896 */
897 return -EINVAL;
898
a45c6cb8
MC		 899 /*
900 * If for some reason the DMA transfer is still active,
901 * we wait for timeout period and free the dma
902 */
903 if (host->dma_ch != -1) {
904 set_current_state(TASK_UNINTERRUPTIBLE);
905 schedule_timeout(100);
906 if (down_trylock(&host->sem)) {
907 omap_free_dma(host->dma_ch);
908 host->dma_ch = -1;
909 up(&host->sem);
910 return err;
911 }
912 } else {
913 if (down_trylock(&host->sem))
914 return err;
915 }
916
0ccd76d4
JY		 917 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
918 mmc_omap_dma_cb,host, &dma_ch);
a45c6cb8 919 if (ret != 0) {
0ccd76d4 920 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 921 "%s: omap_request_dma() failed with %d\n",
922 mmc_hostname(host->mmc), ret);
923 return ret;
924 }
925
926 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
0ccd76d4 927 data->sg_len, mmc_omap_get_dma_dir(host, data));
a45c6cb8 928 host->dma_ch = dma_ch;
0ccd76d4 929 host->dma_sg_idx = 0;
a45c6cb8 930
0ccd76d4 931 mmc_omap_config_dma_params(host, data, data->sg);
a45c6cb8 932
a45c6cb8
MC		 933 return 0;
934}
935
936static void set_data_timeout(struct mmc_omap_host *host,
937 struct mmc_request *req)
938{
939 unsigned int timeout, cycle_ns;
940 uint32_t reg, clkd, dto = 0;
941
942 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
943 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
944 if (clkd == 0)
945 clkd = 1;
946
947 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
948 timeout = req->data->timeout_ns / cycle_ns;
949 timeout += req->data->timeout_clks;
950 if (timeout) {
951 while ((timeout & 0x80000000) == 0) {
952 dto += 1;
953 timeout <<= 1;
954 }
955 dto = 31 - dto;
956 timeout <<= 1;
957 if (timeout && dto)
958 dto += 1;
959 if (dto >= 13)
960 dto -= 13;
961 else
962 dto = 0;
963 if (dto > 14)
964 dto = 14;
965 }
966
967 reg &= ~DTO_MASK;
968 reg |= dto << DTO_SHIFT;
969 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
970}
971
972/*
973 * Configure block length for MMC/SD cards and initiate the transfer.
974 */
975static int
976mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
977{
978 int ret;
979 host->data = req->data;
980
981 if (req->data == NULL) {
a45c6cb8
MC		 982 OMAP_HSMMC_WRITE(host->base, BLK, 0);
983 return 0;
984 }
985
986 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
987 | (req->data->blocks << 16));
988 set_data_timeout(host, req);
989
a45c6cb8
MC		 990 if (host->use_dma) {
991 ret = mmc_omap_start_dma_transfer(host, req);
992 if (ret != 0) {
993 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
994 return ret;
995 }
996 }
997 return 0;
998}
999
1000/*
1001 * Request function. for read/write operation
1002 */
1003static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
1004{
1005 struct mmc_omap_host *host = mmc_priv(mmc);
a3f406f8 1006 int err;
a45c6cb8
MC		 1007
1008 WARN_ON(host->mrq != NULL);
1009 host->mrq = req;
a3f406f8
JL		 1010 err = mmc_omap_prepare_data(host, req);
1011 if (err) {
1012 req->cmd->error = err;
1013 if (req->data)
1014 req->data->error = err;
1015 host->mrq = NULL;
1016 mmc_request_done(mmc, req);
1017 return;
1018 }
1019
a45c6cb8
MC		 1020 mmc_omap_start_command(host, req->cmd, req->data);
1021}
1022
1023
1024/* Routine to configure clock values. Exposed API to core */
1025static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1026{
1027 struct mmc_omap_host *host = mmc_priv(mmc);
1028 u16 dsor = 0;
1029 unsigned long regval;
1030 unsigned long timeout;
73153010 1031 u32 con;
a3621465 1032 int do_send_init_stream = 0;
a45c6cb8 1033
5e2ea617
AH		 1034 mmc_host_enable(host->mmc);
1035
a3621465
AH		 1036 if (ios->power_mode != host->power_mode) {
1037 switch (ios->power_mode) {
1038 case MMC_POWER_OFF:
1039 mmc_slot(host).set_power(host->dev, host->slot_id,
1040 0, 0);
1041 break;
1042 case MMC_POWER_UP:
1043 mmc_slot(host).set_power(host->dev, host->slot_id,
1044 1, ios->vdd);
1045 break;
1046 case MMC_POWER_ON:
1047 do_send_init_stream = 1;
1048 break;
1049 }
1050 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1051 }
1052
dd498eff
DK		 1053 /* FIXME: set registers based only on changes to ios */
1054
73153010 1055 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1056 switch (mmc->ios.bus_width) {
73153010
JL		 1057 case MMC_BUS_WIDTH_8:
1058 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1059 break;
a45c6cb8 1060 case MMC_BUS_WIDTH_4:
73153010 1061 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1062 OMAP_HSMMC_WRITE(host->base, HCTL,
1063 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1064 break;
1065 case MMC_BUS_WIDTH_1:
73153010 1066 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1067 OMAP_HSMMC_WRITE(host->base, HCTL,
1068 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1069 break;
1070 }
1071
1072 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 1073 /* Only MMC1 can interface at 3V without some flavor
1074 * of external transceiver; but they all handle 1.8V.
1075 */
a45c6cb8
MC		 1076 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1077 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1078 /*
1079 * The mmc_select_voltage fn of the core does
1080 * not seem to set the power_mode to
1081 * MMC_POWER_UP upon recalculating the voltage.
1082 * vdd 1.8v.
1083 */
1084 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
1085 dev_dbg(mmc_dev(host->mmc),
1086 "Switch operation failed\n");
1087 }
1088 }
1089
1090 if (ios->clock) {
1091 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1092 if (dsor < 1)
1093 dsor = 1;
1094
1095 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1096 dsor++;
1097
1098 if (dsor > 250)
1099 dsor = 250;
1100 }
1101 omap_mmc_stop_clock(host);
1102 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1103 regval = regval & ~(CLKD_MASK);
1104 regval = regval | (dsor << 6) | (DTO << 16);
1105 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1106 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1107 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1108
1109 /* Wait till the ICS bit is set */
1110 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1111 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1112 && time_before(jiffies, timeout))
1113 msleep(1);
1114
1115 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1116 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1117
a3621465 1118 if (do_send_init_stream)
a45c6cb8
MC		 1119 send_init_stream(host);
1120
abb28e73 1121 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1122 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1123 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1124 else
1125 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1126
dd498eff
DK		 1127 if (host->power_mode == MMC_POWER_OFF)
1128 mmc_host_disable(host->mmc);
1129 else
1130 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1131}
1132
1133static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1134{
1135 struct mmc_omap_host *host = mmc_priv(mmc);
1136 struct omap_mmc_platform_data *pdata = host->pdata;
1137
1138 if (!pdata->slots[0].card_detect)
1139 return -ENOSYS;
1140 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
1141}
1142
1143static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1144{
1145 struct mmc_omap_host *host = mmc_priv(mmc);
1146 struct omap_mmc_platform_data *pdata = host->pdata;
1147
1148 if (!pdata->slots[0].get_ro)
1149 return -ENOSYS;
1150 return pdata->slots[0].get_ro(host->dev, 0);
1151}
1152
1b331e69
KK		 1153static void omap_hsmmc_init(struct mmc_omap_host *host)
1154{
1155 u32 hctl, capa, value;
1156
1157 /* Only MMC1 supports 3.0V */
1158 if (host->id == OMAP_MMC1_DEVID) {
1159 hctl = SDVS30;
1160 capa = VS30 | VS18;
1161 } else {
1162 hctl = SDVS18;
1163 capa = VS18;
1164 }
1165
1166 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1167 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1168
1169 value = OMAP_HSMMC_READ(host->base, CAPA);
1170 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1171
1172 /* Set the controller to AUTO IDLE mode */
1173 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1174 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1175
1176 /* Set SD bus power bit */
e13bb300 1177 set_sd_bus_power(host);
1b331e69
KK		 1178}
1179
dd498eff
DK		 1180/*
1181 * Dynamic power saving handling, FSM:
1182 * ENABLED -> DISABLED -> OFF
1183 * ^___________| |
1184 * |______________________|
1185 *
1186 * ENABLED: mmc host is fully functional
1187 * DISABLED: fclk is off
1188 * OFF: fclk is off,voltage regulator is off
1189 *
1190 * Transition handlers return the timeout for the next state transition
1191 * or negative error.
1192 */
1193
1194enum {ENABLED = 0, DISABLED, OFF};
1195
1196/* Handler for [ENABLED -> DISABLED] transition */
1197static int omap_mmc_enabled_to_disabled(struct mmc_omap_host *host)
1198{
1199 omap_mmc_save_ctx(host);
1200 clk_disable(host->fclk);
1201 host->dpm_state = DISABLED;
1202
1203 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1204
1205 if (host->power_mode == MMC_POWER_OFF)
1206 return 0;
1207
1208 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1209}
1210
1211/* Handler for [DISABLED -> OFF] transition */
1212static int omap_mmc_disabled_to_off(struct mmc_omap_host *host)
1213{
1214 int new_state;
1215
1216 dev_dbg(mmc_dev(host->mmc), "DISABLED -> OFF\n");
1217
1218 if (!mmc_try_claim_host(host->mmc))
1219 return 0;
1220
1221 clk_enable(host->fclk);
1222
1223 omap_mmc_restore_ctx(host);
1224
1225 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1226 mmc_slot(host).card_detect ||
1227 (mmc_slot(host).get_cover_state &&
1228 mmc_slot(host).get_cover_state(host->dev, host->slot_id))) {
1229 mmc_power_save_host(host->mmc);
1230 new_state = OFF;
1231 } else
1232 new_state = DISABLED;
1233
1234 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1235 OMAP_HSMMC_WRITE(host->base, IE, 0);
1236 OMAP_HSMMC_WRITE(host->base, HCTL,
1237 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1238
1239 clk_disable(host->fclk);
1240 clk_disable(host->iclk);
1241 clk_disable(host->dbclk);
1242
1243 host->dpm_state = new_state;
1244
1245 mmc_release_host(host->mmc);
1246
1247 return 0;
1248}
1249
1250/* Handler for [DISABLED -> ENABLED] transition */
1251static int omap_mmc_disabled_to_enabled(struct mmc_omap_host *host)
1252{
1253 int err;
1254
1255 err = clk_enable(host->fclk);
1256 if (err < 0)
1257 return err;
1258
1259 omap_mmc_restore_ctx(host);
1260
1261 host->dpm_state = ENABLED;
1262
1263 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1264
1265 return 0;
1266}
1267
1268/* Handler for [OFF -> ENABLED] transition */
1269static int omap_mmc_off_to_enabled(struct mmc_omap_host *host)
1270{
1271 clk_enable(host->fclk);
1272 clk_enable(host->iclk);
1273
1274 if (clk_enable(host->dbclk))
1275 dev_dbg(mmc_dev(host->mmc),
1276 "Enabling debounce clk failed\n");
1277
1278 omap_mmc_restore_ctx(host);
1279 omap_hsmmc_init(host);
1280 mmc_power_restore_host(host->mmc);
1281
1282 host->dpm_state = ENABLED;
1283
1284 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1285
1286 return 0;
1287}
1288
1289/*
1290 * Bring MMC host to ENABLED from any other PM state.
1291 */
1292static int omap_mmc_enable(struct mmc_host *mmc)
1293{
1294 struct mmc_omap_host *host = mmc_priv(mmc);
1295
1296 switch (host->dpm_state) {
1297 case DISABLED:
1298 return omap_mmc_disabled_to_enabled(host);
1299 case OFF:
1300 return omap_mmc_off_to_enabled(host);
1301 default:
1302 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1303 return -EINVAL;
1304 }
1305}
1306
1307/*
1308 * Bring MMC host in PM state (one level deeper).
1309 */
1310static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
1311{
1312 struct mmc_omap_host *host = mmc_priv(mmc);
1313
1314 switch (host->dpm_state) {
1315 case ENABLED: {
1316 int delay;
1317
1318 delay = omap_mmc_enabled_to_disabled(host);
1319 if (lazy || delay < 0)
1320 return delay;
1321 return 0;
1322 }
1323 case DISABLED:
1324 return omap_mmc_disabled_to_off(host);
1325 default:
1326 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1327 return -EINVAL;
1328 }
1329}
1330
1331static int omap_mmc_enable_fclk(struct mmc_host *mmc)
1332{
1333 struct mmc_omap_host *host = mmc_priv(mmc);
1334 int err;
1335
1336 err = clk_enable(host->fclk);
1337 if (err)
1338 return err;
1339 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1340 omap_mmc_restore_ctx(host);
1341 return 0;
1342}
1343
1344static int omap_mmc_disable_fclk(struct mmc_host *mmc, int lazy)
1345{
1346 struct mmc_omap_host *host = mmc_priv(mmc);
1347
1348 omap_mmc_save_ctx(host);
1349 clk_disable(host->fclk);
1350 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1351 return 0;
1352}
1353
1354static const struct mmc_host_ops mmc_omap_ops = {
1355 .enable = omap_mmc_enable_fclk,
1356 .disable = omap_mmc_disable_fclk,
1357 .request = omap_mmc_request,
1358 .set_ios = omap_mmc_set_ios,
1359 .get_cd = omap_hsmmc_get_cd,
1360 .get_ro = omap_hsmmc_get_ro,
1361 /* NYET -- enable_sdio_irq */
1362};
1363
1364static const struct mmc_host_ops mmc_omap_ps_ops = {
5e2ea617
AH		 1365 .enable = omap_mmc_enable,
1366 .disable = omap_mmc_disable,
a45c6cb8
MC		 1367 .request = omap_mmc_request,
1368 .set_ios = omap_mmc_set_ios,
1369 .get_cd = omap_hsmmc_get_cd,
1370 .get_ro = omap_hsmmc_get_ro,
1371 /* NYET -- enable_sdio_irq */
1372};
1373
d900f712
DK		 1374#ifdef CONFIG_DEBUG_FS
1375
1376static int mmc_regs_show(struct seq_file *s, void *data)
1377{
1378 struct mmc_host *mmc = s->private;
1379 struct mmc_omap_host *host = mmc_priv(mmc);
11dd62a7
DK		 1380 struct omap_mmc_platform_data *pdata = host->pdata;
1381 int context_loss = 0;
1382
1383 if (pdata->get_context_loss_count)
1384 context_loss = pdata->get_context_loss_count(host->dev);
d900f712 1385
5e2ea617
AH		 1386 seq_printf(s, "mmc%d:\n"
1387 " enabled:\t%d\n"
dd498eff 1388 " dpm_state:\t%d\n"
5e2ea617 1389 " nesting_cnt:\t%d\n"
11dd62a7 1390 " ctx_loss:\t%d:%d\n"
5e2ea617 1391 "\nregs:\n",
dd498eff
DK		 1392 mmc->index, mmc->enabled ? 1 : 0,
1393 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1394 host->context_loss, context_loss);
5e2ea617 1395
dd498eff
DK		 1396 if (host->suspended || host->dpm_state == OFF) {
1397 seq_printf(s, "host suspended, can't read registers\n");
1398 return 0;
1399 }
1400
5e2ea617
AH		 1401 if (clk_enable(host->fclk) != 0) {
1402 seq_printf(s, "can't read the regs\n");
dd498eff 1403 return 0;
5e2ea617 1404 }
d900f712
DK		 1405
1406 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1407 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1408 seq_printf(s, "CON:\t\t0x%08x\n",
1409 OMAP_HSMMC_READ(host->base, CON));
1410 seq_printf(s, "HCTL:\t\t0x%08x\n",
1411 OMAP_HSMMC_READ(host->base, HCTL));
1412 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1413 OMAP_HSMMC_READ(host->base, SYSCTL));
1414 seq_printf(s, "IE:\t\t0x%08x\n",
1415 OMAP_HSMMC_READ(host->base, IE));
1416 seq_printf(s, "ISE:\t\t0x%08x\n",
1417 OMAP_HSMMC_READ(host->base, ISE));
1418 seq_printf(s, "CAPA:\t\t0x%08x\n",
1419 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1420
1421 clk_disable(host->fclk);
dd498eff 1422
d900f712
DK		 1423 return 0;
1424}
1425
1426static int mmc_regs_open(struct inode *inode, struct file *file)
1427{
1428 return single_open(file, mmc_regs_show, inode->i_private);
1429}
1430
1431static const struct file_operations mmc_regs_fops = {
1432 .open = mmc_regs_open,
1433 .read = seq_read,
1434 .llseek = seq_lseek,
1435 .release = single_release,
1436};
1437
1438static void omap_mmc_debugfs(struct mmc_host *mmc)
1439{
1440 if (mmc->debugfs_root)
1441 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1442 mmc, &mmc_regs_fops);
1443}
1444
1445#else
1446
1447static void omap_mmc_debugfs(struct mmc_host *mmc)
1448{
1449}
1450
1451#endif
1452
a45c6cb8
MC		 1453static int __init omap_mmc_probe(struct platform_device *pdev)
1454{
1455 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1456 struct mmc_host *mmc;
1457 struct mmc_omap_host *host = NULL;
1458 struct resource *res;
1459 int ret = 0, irq;
a45c6cb8
MC		 1460
1461 if (pdata == NULL) {
1462 dev_err(&pdev->dev, "Platform Data is missing\n");
1463 return -ENXIO;
1464 }
1465
1466 if (pdata->nr_slots == 0) {
1467 dev_err(&pdev->dev, "No Slots\n");
1468 return -ENXIO;
1469 }
1470
1471 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1472 irq = platform_get_irq(pdev, 0);
1473 if (res == NULL || irq < 0)
1474 return -ENXIO;
1475
1476 res = request_mem_region(res->start, res->end - res->start + 1,
1477 pdev->name);
1478 if (res == NULL)
1479 return -EBUSY;
1480
1481 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1482 if (!mmc) {
1483 ret = -ENOMEM;
1484 goto err;
1485 }
1486
1487 host = mmc_priv(mmc);
1488 host->mmc = mmc;
1489 host->pdata = pdata;
1490 host->dev = &pdev->dev;
1491 host->use_dma = 1;
1492 host->dev->dma_mask = &pdata->dma_mask;
1493 host->dma_ch = -1;
1494 host->irq = irq;
1495 host->id = pdev->id;
1496 host->slot_id = 0;
1497 host->mapbase = res->start;
1498 host->base = ioremap(host->mapbase, SZ_4K);
a3621465 1499 host->power_mode = -1;
a45c6cb8
MC		 1500
1501 platform_set_drvdata(pdev, host);
1502 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1503
dd498eff
DK		 1504 if (pdata->slots[host->slot_id].power_saving)
1505 mmc->ops = &mmc_omap_ps_ops;
1506 else
1507 mmc->ops = &mmc_omap_ops;
1508
a45c6cb8
MC		 1509 mmc->f_min = 400000;
1510 mmc->f_max = 52000000;
1511
1512 sema_init(&host->sem, 1);
1513
6f7607cc 1514 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 1515 if (IS_ERR(host->iclk)) {
1516 ret = PTR_ERR(host->iclk);
1517 host->iclk = NULL;
1518 goto err1;
1519 }
6f7607cc 1520 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1521 if (IS_ERR(host->fclk)) {
1522 ret = PTR_ERR(host->fclk);
1523 host->fclk = NULL;
1524 clk_put(host->iclk);
1525 goto err1;
1526 }
1527
11dd62a7
DK		 1528 omap_mmc_save_ctx(host);
1529
5e2ea617 1530 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 1531 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
1532 /* we start off in DISABLED state */
1533 host->dpm_state = DISABLED;
1534
5e2ea617 1535 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 1536 clk_put(host->iclk);
1537 clk_put(host->fclk);
1538 goto err1;
1539 }
1540
1541 if (clk_enable(host->iclk) != 0) {
5e2ea617 1542 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1543 clk_put(host->iclk);
1544 clk_put(host->fclk);
1545 goto err1;
1546 }
1547
1548 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1549 /*
1550 * MMC can still work without debounce clock.
1551 */
1552 if (IS_ERR(host->dbclk))
1553 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1554 else
1555 if (clk_enable(host->dbclk) != 0)
1556 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1557 " clk failed\n");
1558 else
1559 host->dbclk_enabled = 1;
1560
0ccd76d4
JY		 1561 /* Since we do only SG emulation, we can have as many segs
1562 * as we want. */
1563 mmc->max_phys_segs = 1024;
1564 mmc->max_hw_segs = 1024;
1565
a45c6cb8
MC		 1566 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1567 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1568 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1569 mmc->max_seg_size = mmc->max_req_size;
1570
a45c6cb8
MC		 1571 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1572
73153010
JL		 1573 if (pdata->slots[host->slot_id].wires >= 8)
1574 mmc->caps |= MMC_CAP_8_BIT_DATA;
1575 else if (pdata->slots[host->slot_id].wires >= 4)
a45c6cb8
MC		 1576 mmc->caps |= MMC_CAP_4_BIT_DATA;
1577
23d99bb9
AH		 1578 if (pdata->slots[host->slot_id].nonremovable)
1579 mmc->caps |= MMC_CAP_NONREMOVABLE;
1580
1b331e69 1581 omap_hsmmc_init(host);
a45c6cb8 1582
f3e2f1dd
GI		 1583 /* Select DMA lines */
1584 switch (host->id) {
1585 case OMAP_MMC1_DEVID:
1586 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1587 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1588 break;
1589 case OMAP_MMC2_DEVID:
1590 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1591 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1592 break;
1593 case OMAP_MMC3_DEVID:
1594 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1595 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1596 break;
1597 default:
1598 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1599 goto err_irq;
1600 }
a45c6cb8
MC		 1601
1602 /* Request IRQ for MMC operations */
1603 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1604 mmc_hostname(mmc), host);
1605 if (ret) {
1606 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1607 goto err_irq;
1608 }
1609
b583f26d 1610 /* initialize power supplies, gpios, etc */
a45c6cb8
MC		 1611 if (pdata->init != NULL) {
1612 if (pdata->init(&pdev->dev) != 0) {
b583f26d 1613 dev_dbg(mmc_dev(host->mmc), "late init error\n");
a45c6cb8
MC		 1614 goto err_irq_cd_init;
1615 }
1616 }
b583f26d 1617 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1618
1619 /* Request IRQ for card detect */
e1a55f5e 1620 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8
MC		 1621 ret = request_irq(mmc_slot(host).card_detect_irq,
1622 omap_mmc_cd_handler,
1623 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1624 | IRQF_DISABLED,
1625 mmc_hostname(mmc), host);
1626 if (ret) {
1627 dev_dbg(mmc_dev(host->mmc),
1628 "Unable to grab MMC CD IRQ\n");
1629 goto err_irq_cd;
1630 }
1631 }
1632
1633 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1634 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1635
5e2ea617
AH		 1636 mmc_host_lazy_disable(host->mmc);
1637
a45c6cb8
MC		 1638 mmc_add_host(mmc);
1639
1640 if (host->pdata->slots[host->slot_id].name != NULL) {
1641 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1642 if (ret < 0)
1643 goto err_slot_name;
1644 }
e1a55f5e
AH		 1645 if (mmc_slot(host).card_detect_irq &&
1646 host->pdata->slots[host->slot_id].get_cover_state) {
a45c6cb8
MC		 1647 ret = device_create_file(&mmc->class_dev,
1648 &dev_attr_cover_switch);
1649 if (ret < 0)
1650 goto err_cover_switch;
1651 }
1652
d900f712
DK		 1653 omap_mmc_debugfs(mmc);
1654
a45c6cb8
MC		 1655 return 0;
1656
1657err_cover_switch:
1658 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1659err_slot_name:
1660 mmc_remove_host(mmc);
1661err_irq_cd:
1662 free_irq(mmc_slot(host).card_detect_irq, host);
1663err_irq_cd_init:
1664 free_irq(host->irq, host);
1665err_irq:
5e2ea617 1666 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1667 clk_disable(host->iclk);
1668 clk_put(host->fclk);
1669 clk_put(host->iclk);
1670 if (host->dbclk_enabled) {
1671 clk_disable(host->dbclk);
1672 clk_put(host->dbclk);
1673 }
1674
1675err1:
1676 iounmap(host->base);
1677err:
1678 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1679 release_mem_region(res->start, res->end - res->start + 1);
1680 if (host)
1681 mmc_free_host(mmc);
1682 return ret;
1683}
1684
1685static int omap_mmc_remove(struct platform_device *pdev)
1686{
1687 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1688 struct resource *res;
1689
1690 if (host) {
5e2ea617 1691 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1692 mmc_remove_host(host->mmc);
1693 if (host->pdata->cleanup)
1694 host->pdata->cleanup(&pdev->dev);
1695 free_irq(host->irq, host);
1696 if (mmc_slot(host).card_detect_irq)
1697 free_irq(mmc_slot(host).card_detect_irq, host);
1698 flush_scheduled_work();
1699
5e2ea617 1700 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1701 clk_disable(host->iclk);
1702 clk_put(host->fclk);
1703 clk_put(host->iclk);
1704 if (host->dbclk_enabled) {
1705 clk_disable(host->dbclk);
1706 clk_put(host->dbclk);
1707 }
1708
1709 mmc_free_host(host->mmc);
1710 iounmap(host->base);
1711 }
1712
1713 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1714 if (res)
1715 release_mem_region(res->start, res->end - res->start + 1);
1716 platform_set_drvdata(pdev, NULL);
1717
1718 return 0;
1719}
1720
1721#ifdef CONFIG_PM
1722static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1723{
1724 int ret = 0;
1725 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1726
1727 if (host && host->suspended)
1728 return 0;
1729
1730 if (host) {
a6b2240d
AH		 1731 host->suspended = 1;
1732 if (host->pdata->suspend) {
1733 ret = host->pdata->suspend(&pdev->dev,
1734 host->slot_id);
1735 if (ret) {
1736 dev_dbg(mmc_dev(host->mmc),
1737 "Unable to handle MMC board"
1738 " level suspend\n");
1739 host->suspended = 0;
1740 return ret;
1741 }
1742 }
1743 cancel_work_sync(&host->mmc_carddetect_work);
5e2ea617 1744 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1745 ret = mmc_suspend_host(host->mmc, state);
1746 if (ret == 0) {
a45c6cb8
MC		 1747 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1748 OMAP_HSMMC_WRITE(host->base, IE, 0);
1749
a45c6cb8 1750
0683af48
JL		 1751 OMAP_HSMMC_WRITE(host->base, HCTL,
1752 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 1753 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1754 clk_disable(host->iclk);
1755 clk_disable(host->dbclk);
a6b2240d
AH		 1756 } else {
1757 host->suspended = 0;
1758 if (host->pdata->resume) {
1759 ret = host->pdata->resume(&pdev->dev,
1760 host->slot_id);
1761 if (ret)
1762 dev_dbg(mmc_dev(host->mmc),
1763 "Unmask interrupt failed\n");
1764 }
5e2ea617 1765 mmc_host_disable(host->mmc);
a6b2240d 1766 }
a45c6cb8
MC		 1767
1768 }
1769 return ret;
1770}
1771
1772/* Routine to resume the MMC device */
1773static int omap_mmc_resume(struct platform_device *pdev)
1774{
1775 int ret = 0;
1776 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1777
1778 if (host && !host->suspended)
1779 return 0;
1780
1781 if (host) {
a45c6cb8 1782 ret = clk_enable(host->iclk);
11dd62a7 1783 if (ret)
a45c6cb8 1784 goto clk_en_err;
a45c6cb8
MC		 1785
1786 if (clk_enable(host->dbclk) != 0)
1787 dev_dbg(mmc_dev(host->mmc),
1788 "Enabling debounce clk failed\n");
1789
11dd62a7
DK		 1790 if (mmc_host_enable(host->mmc) != 0) {
1791 clk_disable(host->iclk);
1792 goto clk_en_err;
1793 }
1794
1b331e69
KK		 1795 omap_hsmmc_init(host);
1796
a45c6cb8
MC		 1797 if (host->pdata->resume) {
1798 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1799 if (ret)
1800 dev_dbg(mmc_dev(host->mmc),
1801 "Unmask interrupt failed\n");
1802 }
1803
1804 /* Notify the core to resume the host */
1805 ret = mmc_resume_host(host->mmc);
1806 if (ret == 0)
1807 host->suspended = 0;
5e2ea617 1808 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1809 }
1810
1811 return ret;
1812
1813clk_en_err:
1814 dev_dbg(mmc_dev(host->mmc),
1815 "Failed to enable MMC clocks during resume\n");
1816 return ret;
1817}
1818
1819#else
1820#define omap_mmc_suspend NULL
1821#define omap_mmc_resume NULL
1822#endif
1823
1824static struct platform_driver omap_mmc_driver = {
a45c6cb8
MC		 1825 .remove = omap_mmc_remove,
1826 .suspend = omap_mmc_suspend,
1827 .resume = omap_mmc_resume,
1828 .driver = {
1829 .name = DRIVER_NAME,
1830 .owner = THIS_MODULE,
1831 },
1832};
1833
1834static int __init omap_mmc_init(void)
1835{
1836 /* Register the MMC driver */
f400cd8c 1837 return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
a45c6cb8
MC		 1838}
1839
1840static void __exit omap_mmc_cleanup(void)
1841{
1842 /* Unregister MMC driver */
1843 platform_driver_unregister(&omap_mmc_driver);
1844}
1845
1846module_init(omap_mmc_init);
1847module_exit(omap_mmc_cleanup);
1848
1849MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1850MODULE_LICENSE("GPL");
1851MODULE_ALIAS("platform:" DRIVER_NAME);
1852MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)