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omap_hsmmc: Add 8-bit bus width mode support
[linux-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
23#include <linux/platform_device.h>
24#include <linux/workqueue.h>
25#include <linux/timer.h>
26#include <linux/clk.h>
27#include <linux/mmc/host.h>
28#include <linux/io.h>
29#include <linux/semaphore.h>
30#include <mach/dma.h>
31#include <mach/hardware.h>
32#include <mach/board.h>
33#include <mach/mmc.h>
34#include <mach/cpu.h>
35
36/* OMAP HSMMC Host Controller Registers */
37#define OMAP_HSMMC_SYSCONFIG 0x0010
38#define OMAP_HSMMC_CON 0x002C
39#define OMAP_HSMMC_BLK 0x0104
40#define OMAP_HSMMC_ARG 0x0108
41#define OMAP_HSMMC_CMD 0x010C
42#define OMAP_HSMMC_RSP10 0x0110
43#define OMAP_HSMMC_RSP32 0x0114
44#define OMAP_HSMMC_RSP54 0x0118
45#define OMAP_HSMMC_RSP76 0x011C
46#define OMAP_HSMMC_DATA 0x0120
47#define OMAP_HSMMC_HCTL 0x0128
48#define OMAP_HSMMC_SYSCTL 0x012C
49#define OMAP_HSMMC_STAT 0x0130
50#define OMAP_HSMMC_IE 0x0134
51#define OMAP_HSMMC_ISE 0x0138
52#define OMAP_HSMMC_CAPA 0x0140
53
54#define VS18 (1 << 26)
55#define VS30 (1 << 25)
56#define SDVS18 (0x5 << 9)
57#define SDVS30 (0x6 << 9)
eb250826 58#define SDVS33 (0x7 << 9)
1b331e69 59#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 60#define SDVSCLR 0xFFFFF1FF
61#define SDVSDET 0x00000400
62#define AUTOIDLE 0x1
63#define SDBP (1 << 8)
64#define DTO 0xe
65#define ICE 0x1
66#define ICS 0x2
67#define CEN (1 << 2)
68#define CLKD_MASK 0x0000FFC0
69#define CLKD_SHIFT 6
70#define DTO_MASK 0x000F0000
71#define DTO_SHIFT 16
72#define INT_EN_MASK 0x307F0033
73#define INIT_STREAM (1 << 1)
74#define DP_SELECT (1 << 21)
75#define DDIR (1 << 4)
76#define DMA_EN 0x1
77#define MSBS (1 << 5)
78#define BCE (1 << 1)
79#define FOUR_BIT (1 << 1)
73153010 80#define DW8 (1 << 5)
a45c6cb8
MC		 81#define CC 0x1
82#define TC 0x02
83#define OD 0x1
84#define ERR (1 << 15)
85#define CMD_TIMEOUT (1 << 16)
86#define DATA_TIMEOUT (1 << 20)
87#define CMD_CRC (1 << 17)
88#define DATA_CRC (1 << 21)
89#define CARD_ERR (1 << 28)
90#define STAT_CLEAR 0xFFFFFFFF
91#define INIT_STREAM_CMD 0x00000000
92#define DUAL_VOLT_OCR_BIT 7
93#define SRC (1 << 25)
94#define SRD (1 << 26)
95
96/*
97 * FIXME: Most likely all the data using these _DEVID defines should come
98 * from the platform_data, or implemented in controller and slot specific
99 * functions.
100 */
101#define OMAP_MMC1_DEVID 0
102#define OMAP_MMC2_DEVID 1
103
a45c6cb8
MC		 104#define MMC_TIMEOUT_MS 20
105#define OMAP_MMC_MASTER_CLOCK 96000000
106#define DRIVER_NAME "mmci-omap-hs"
107
108/*
109 * One controller can have multiple slots, like on some omap boards using
110 * omap.c controller driver. Luckily this is not currently done on any known
111 * omap_hsmmc.c device.
112 */
113#define mmc_slot(host) (host->pdata->slots[host->slot_id])
114
115/*
116 * MMC Host controller read/write API's
117 */
118#define OMAP_HSMMC_READ(base, reg) \
119 __raw_readl((base) + OMAP_HSMMC_##reg)
120
121#define OMAP_HSMMC_WRITE(base, reg, val) \
122 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
123
124struct mmc_omap_host {
125 struct device *dev;
126 struct mmc_host *mmc;
127 struct mmc_request *mrq;
128 struct mmc_command *cmd;
129 struct mmc_data *data;
130 struct clk *fclk;
131 struct clk *iclk;
132 struct clk *dbclk;
133 struct semaphore sem;
134 struct work_struct mmc_carddetect_work;
135 void __iomem *base;
136 resource_size_t mapbase;
137 unsigned int id;
138 unsigned int dma_len;
0ccd76d4 139 unsigned int dma_sg_idx;
a45c6cb8 140 unsigned char bus_mode;
a45c6cb8
MC		 141 u32 *buffer;
142 u32 bytesleft;
143 int suspended;
144 int irq;
145 int carddetect;
146 int use_dma, dma_ch;
a45c6cb8
MC		 147 int slot_id;
148 int dbclk_enabled;
4a694dc9 149 int response_busy;
a45c6cb8
MC		 150 struct omap_mmc_platform_data *pdata;
151};
152
153/*
154 * Stop clock to the card
155 */
156static void omap_mmc_stop_clock(struct mmc_omap_host *host)
157{
158 OMAP_HSMMC_WRITE(host->base, SYSCTL,
159 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
160 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
161 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
162}
163
164/*
165 * Send init stream sequence to card
166 * before sending IDLE command
167 */
168static void send_init_stream(struct mmc_omap_host *host)
169{
170 int reg = 0;
171 unsigned long timeout;
172
173 disable_irq(host->irq);
174 OMAP_HSMMC_WRITE(host->base, CON,
175 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
176 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
177
178 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
179 while ((reg != CC) && time_before(jiffies, timeout))
180 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
181
182 OMAP_HSMMC_WRITE(host->base, CON,
183 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
184 enable_irq(host->irq);
185}
186
187static inline
188int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
189{
190 int r = 1;
191
192 if (host->pdata->slots[host->slot_id].get_cover_state)
193 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
194 host->slot_id);
195 return r;
196}
197
198static ssize_t
199mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
200 char *buf)
201{
202 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
203 struct mmc_omap_host *host = mmc_priv(mmc);
204
205 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
206 "open");
207}
208
209static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
210
211static ssize_t
212mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
213 char *buf)
214{
215 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
216 struct mmc_omap_host *host = mmc_priv(mmc);
217 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
218
219 return sprintf(buf, "slot:%s\n", slot.name);
220}
221
222static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
223
224/*
225 * Configure the response type and send the cmd.
226 */
227static void
228mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
229 struct mmc_data *data)
230{
231 int cmdreg = 0, resptype = 0, cmdtype = 0;
232
233 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
234 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
235 host->cmd = cmd;
236
237 /*
238 * Clear status bits and enable interrupts
239 */
240 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
241 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
242 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
243
4a694dc9 244 host->response_busy = 0;
a45c6cb8
MC		 245 if (cmd->flags & MMC_RSP_PRESENT) {
246 if (cmd->flags & MMC_RSP_136)
247 resptype = 1;
4a694dc9
AH		 248 else if (cmd->flags & MMC_RSP_BUSY) {
249 resptype = 3;
250 host->response_busy = 1;
251 } else
a45c6cb8
MC		 252 resptype = 2;
253 }
254
255 /*
256 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
257 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
258 * a val of 0x3, rest 0x0.
259 */
260 if (cmd == host->mrq->stop)
261 cmdtype = 0x3;
262
263 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
264
265 if (data) {
266 cmdreg |= DP_SELECT | MSBS | BCE;
267 if (data->flags & MMC_DATA_READ)
268 cmdreg |= DDIR;
269 else
270 cmdreg &= ~(DDIR);
271 }
272
273 if (host->use_dma)
274 cmdreg |= DMA_EN;
275
276 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
277 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
278}
279
0ccd76d4
JY		 280static int
281mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
282{
283 if (data->flags & MMC_DATA_WRITE)
284 return DMA_TO_DEVICE;
285 else
286 return DMA_FROM_DEVICE;
287}
288
a45c6cb8
MC		 289/*
290 * Notify the transfer complete to MMC core
291 */
292static void
293mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
294{
4a694dc9
AH		 295 if (!data) {
296 struct mmc_request *mrq = host->mrq;
297
298 host->mrq = NULL;
299 mmc_omap_fclk_lazy_disable(host);
300 mmc_request_done(host->mmc, mrq);
301 return;
302 }
303
a45c6cb8
MC		 304 host->data = NULL;
305
306 if (host->use_dma && host->dma_ch != -1)
307 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
0ccd76d4 308 mmc_omap_get_dma_dir(host, data));
a45c6cb8
MC		 309
310 if (!data->error)
311 data->bytes_xfered += data->blocks * (data->blksz);
312 else
313 data->bytes_xfered = 0;
314
315 if (!data->stop) {
316 host->mrq = NULL;
317 mmc_request_done(host->mmc, data->mrq);
318 return;
319 }
320 mmc_omap_start_command(host, data->stop, NULL);
321}
322
323/*
324 * Notify the core about command completion
325 */
326static void
327mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
328{
329 host->cmd = NULL;
330
331 if (cmd->flags & MMC_RSP_PRESENT) {
332 if (cmd->flags & MMC_RSP_136) {
333 /* response type 2 */
334 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
335 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
336 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
337 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
338 } else {
339 /* response types 1, 1b, 3, 4, 5, 6 */
340 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
341 }
342 }
4a694dc9 343 if ((host->data == NULL && !host->response_busy) || cmd->error) {
a45c6cb8
MC		 344 host->mrq = NULL;
345 mmc_request_done(host->mmc, cmd->mrq);
346 }
347}
348
349/*
350 * DMA clean up for command errors
351 */
82788ff5 352static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
a45c6cb8 353{
82788ff5 354 host->data->error = errno;
a45c6cb8
MC		 355
356 if (host->use_dma && host->dma_ch != -1) {
357 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
0ccd76d4 358 mmc_omap_get_dma_dir(host, host->data));
a45c6cb8
MC		 359 omap_free_dma(host->dma_ch);
360 host->dma_ch = -1;
361 up(&host->sem);
362 }
363 host->data = NULL;
a45c6cb8
MC		 364}
365
366/*
367 * Readable error output
368 */
369#ifdef CONFIG_MMC_DEBUG
370static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
371{
372 /* --- means reserved bit without definition at documentation */
373 static const char *mmc_omap_status_bits[] = {
374 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
375 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
376 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
377 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
378 };
379 char res[256];
380 char *buf = res;
381 int len, i;
382
383 len = sprintf(buf, "MMC IRQ 0x%x :", status);
384 buf += len;
385
386 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
387 if (status & (1 << i)) {
388 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
389 buf += len;
390 }
391
392 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
393}
394#endif /* CONFIG_MMC_DEBUG */
395
3ebf74b1
JP		 396/*
397 * MMC controller internal state machines reset
398 *
399 * Used to reset command or data internal state machines, using respectively
400 * SRC or SRD bit of SYSCTL register
401 * Can be called from interrupt context
402 */
403static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
404 unsigned long bit)
405{
406 unsigned long i = 0;
407 unsigned long limit = (loops_per_jiffy *
408 msecs_to_jiffies(MMC_TIMEOUT_MS));
409
410 OMAP_HSMMC_WRITE(host->base, SYSCTL,
411 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
412
413 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
414 (i++ < limit))
415 cpu_relax();
416
417 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
418 dev_err(mmc_dev(host->mmc),
419 "Timeout waiting on controller reset in %s\n",
420 __func__);
421}
a45c6cb8
MC		 422
423/*
424 * MMC controller IRQ handler
425 */
426static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
427{
428 struct mmc_omap_host *host = dev_id;
429 struct mmc_data *data;
430 int end_cmd = 0, end_trans = 0, status;
431
4a694dc9 432 if (host->mrq == NULL) {
a45c6cb8
MC		 433 OMAP_HSMMC_WRITE(host->base, STAT,
434 OMAP_HSMMC_READ(host->base, STAT));
435 return IRQ_HANDLED;
436 }
437
438 data = host->data;
439 status = OMAP_HSMMC_READ(host->base, STAT);
440 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
441
442 if (status & ERR) {
443#ifdef CONFIG_MMC_DEBUG
444 mmc_omap_report_irq(host, status);
445#endif
446 if ((status & CMD_TIMEOUT) ||
447 (status & CMD_CRC)) {
448 if (host->cmd) {
449 if (status & CMD_TIMEOUT) {
3ebf74b1 450 mmc_omap_reset_controller_fsm(host, SRC);
a45c6cb8
MC		 451 host->cmd->error = -ETIMEDOUT;
452 } else {
453 host->cmd->error = -EILSEQ;
454 }
455 end_cmd = 1;
456 }
4a694dc9
AH		 457 if (host->data || host->response_busy) {
458 if (host->data)
459 mmc_dma_cleanup(host, -ETIMEDOUT);
460 host->response_busy = 0;
3ebf74b1 461 mmc_omap_reset_controller_fsm(host, SRD);
c232f457 462 }
a45c6cb8
MC		 463 }
464 if ((status & DATA_TIMEOUT) ||
465 (status & DATA_CRC)) {
4a694dc9
AH		 466 if (host->data || host->response_busy) {
467 int err = (status & DATA_TIMEOUT) ?
468 -ETIMEDOUT : -EILSEQ;
469
470 if (host->data)
471 mmc_dma_cleanup(host, err);
a45c6cb8 472 else
4a694dc9
AH		 473 host->mrq->cmd->error = err;
474 host->response_busy = 0;
3ebf74b1 475 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 476 end_trans = 1;
477 }
478 }
479 if (status & CARD_ERR) {
480 dev_dbg(mmc_dev(host->mmc),
481 "Ignoring card err CMD%d\n", host->cmd->opcode);
482 if (host->cmd)
483 end_cmd = 1;
484 if (host->data)
485 end_trans = 1;
486 }
487 }
488
489 OMAP_HSMMC_WRITE(host->base, STAT, status);
490
491 if (end_cmd || (status & CC))
492 mmc_omap_cmd_done(host, host->cmd);
493 if (end_trans || (status & TC))
494 mmc_omap_xfer_done(host, data);
495
496 return IRQ_HANDLED;
497}
498
499/*
eb250826
DB		 500 * Switch MMC interface voltage ... only relevant for MMC1.
501 *
502 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
503 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
504 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8
MC		 505 */
506static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
507{
508 u32 reg_val = 0;
509 int ret;
510
511 /* Disable the clocks */
512 clk_disable(host->fclk);
513 clk_disable(host->iclk);
514 clk_disable(host->dbclk);
515
516 /* Turn the power off */
517 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
518 if (ret != 0)
519 goto err;
520
521 /* Turn the power ON with given VDD 1.8 or 3.0v */
522 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
523 if (ret != 0)
524 goto err;
525
526 clk_enable(host->fclk);
527 clk_enable(host->iclk);
528 clk_enable(host->dbclk);
529
530 OMAP_HSMMC_WRITE(host->base, HCTL,
531 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
532 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 533
a45c6cb8
MC		 534 /*
535 * If a MMC dual voltage card is detected, the set_ios fn calls
536 * this fn with VDD bit set for 1.8V. Upon card removal from the
537 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
538 *
eb250826
DB		 539 * Cope with a bit of slop in the range ... per data sheets:
540 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
541 * but recommended values are 1.71V to 1.89V
542 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
543 * but recommended values are 2.7V to 3.3V
544 *
545 * Board setup code shouldn't permit anything very out-of-range.
546 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
547 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 548 */
eb250826 549 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 550 reg_val |= SDVS18;
eb250826
DB		 551 else
552 reg_val |= SDVS30;
a45c6cb8
MC		 553
554 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
555
556 OMAP_HSMMC_WRITE(host->base, HCTL,
557 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
558
559 return 0;
560err:
561 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
562 return ret;
563}
564
565/*
566 * Work Item to notify the core about card insertion/removal
567 */
568static void mmc_omap_detect(struct work_struct *work)
569{
570 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
571 mmc_carddetect_work);
249d0fa9
DB		 572 struct omap_mmc_slot_data *slot = &mmc_slot(host);
573
574 host->carddetect = slot->card_detect(slot->card_detect_irq);
a45c6cb8
MC		 575
576 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
577 if (host->carddetect) {
578 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
579 } else {
3ebf74b1 580 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 581 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
582 }
583}
584
585/*
586 * ISR for handling card insertion and removal
587 */
588static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
589{
590 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
591
a45c6cb8
MC		 592 schedule_work(&host->mmc_carddetect_work);
593
594 return IRQ_HANDLED;
595}
596
0ccd76d4
JY		 597static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
598 struct mmc_data *data)
599{
600 int sync_dev;
601
602 if (data->flags & MMC_DATA_WRITE) {
603 if (host->id == OMAP_MMC1_DEVID)
604 sync_dev = OMAP24XX_DMA_MMC1_TX;
605 else
606 sync_dev = OMAP24XX_DMA_MMC2_TX;
607 } else {
608 if (host->id == OMAP_MMC1_DEVID)
609 sync_dev = OMAP24XX_DMA_MMC1_RX;
610 else
611 sync_dev = OMAP24XX_DMA_MMC2_RX;
612 }
613 return sync_dev;
614}
615
616static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
617 struct mmc_data *data,
618 struct scatterlist *sgl)
619{
620 int blksz, nblk, dma_ch;
621
622 dma_ch = host->dma_ch;
623 if (data->flags & MMC_DATA_WRITE) {
624 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
625 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
626 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
627 sg_dma_address(sgl), 0, 0);
628 } else {
629 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
630 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
631 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
632 sg_dma_address(sgl), 0, 0);
633 }
634
635 blksz = host->data->blksz;
636 nblk = sg_dma_len(sgl) / blksz;
637
638 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
639 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
640 mmc_omap_get_dma_sync_dev(host, data),
641 !(data->flags & MMC_DATA_WRITE));
642
643 omap_start_dma(dma_ch);
644}
645
a45c6cb8
MC		 646/*
647 * DMA call back function
648 */
649static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
650{
651 struct mmc_omap_host *host = data;
652
653 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
654 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
655
656 if (host->dma_ch < 0)
657 return;
658
0ccd76d4
JY		 659 host->dma_sg_idx++;
660 if (host->dma_sg_idx < host->dma_len) {
661 /* Fire up the next transfer. */
662 mmc_omap_config_dma_params(host, host->data,
663 host->data->sg + host->dma_sg_idx);
664 return;
665 }
666
a45c6cb8
MC		 667 omap_free_dma(host->dma_ch);
668 host->dma_ch = -1;
669 /*
670 * DMA Callback: run in interrupt context.
671 * mutex_unlock will through a kernel warning if used.
672 */
673 up(&host->sem);
674}
675
a45c6cb8
MC		 676/*
677 * Routine to configure and start DMA for the MMC card
678 */
679static int
680mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
681{
0ccd76d4 682 int dma_ch = 0, ret = 0, err = 1, i;
a45c6cb8
MC		 683 struct mmc_data *data = req->data;
684
0ccd76d4
JY		 685 /* Sanity check: all the SG entries must be aligned by block size. */
686 for (i = 0; i < host->dma_len; i++) {
687 struct scatterlist *sgl;
688
689 sgl = data->sg + i;
690 if (sgl->length % data->blksz)
691 return -EINVAL;
692 }
693 if ((data->blksz % 4) != 0)
694 /* REVISIT: The MMC buffer increments only when MSB is written.
695 * Return error for blksz which is non multiple of four.
696 */
697 return -EINVAL;
698
a45c6cb8
MC		 699 /*
700 * If for some reason the DMA transfer is still active,
701 * we wait for timeout period and free the dma
702 */
703 if (host->dma_ch != -1) {
704 set_current_state(TASK_UNINTERRUPTIBLE);
705 schedule_timeout(100);
706 if (down_trylock(&host->sem)) {
707 omap_free_dma(host->dma_ch);
708 host->dma_ch = -1;
709 up(&host->sem);
710 return err;
711 }
712 } else {
713 if (down_trylock(&host->sem))
714 return err;
715 }
716
0ccd76d4
JY		 717 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
718 mmc_omap_dma_cb,host, &dma_ch);
a45c6cb8 719 if (ret != 0) {
0ccd76d4 720 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 721 "%s: omap_request_dma() failed with %d\n",
722 mmc_hostname(host->mmc), ret);
723 return ret;
724 }
725
726 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
0ccd76d4 727 data->sg_len, mmc_omap_get_dma_dir(host, data));
a45c6cb8 728 host->dma_ch = dma_ch;
0ccd76d4 729 host->dma_sg_idx = 0;
a45c6cb8 730
0ccd76d4 731 mmc_omap_config_dma_params(host, data, data->sg);
a45c6cb8 732
a45c6cb8
MC		 733 return 0;
734}
735
736static void set_data_timeout(struct mmc_omap_host *host,
737 struct mmc_request *req)
738{
739 unsigned int timeout, cycle_ns;
740 uint32_t reg, clkd, dto = 0;
741
742 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
743 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
744 if (clkd == 0)
745 clkd = 1;
746
747 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
748 timeout = req->data->timeout_ns / cycle_ns;
749 timeout += req->data->timeout_clks;
750 if (timeout) {
751 while ((timeout & 0x80000000) == 0) {
752 dto += 1;
753 timeout <<= 1;
754 }
755 dto = 31 - dto;
756 timeout <<= 1;
757 if (timeout && dto)
758 dto += 1;
759 if (dto >= 13)
760 dto -= 13;
761 else
762 dto = 0;
763 if (dto > 14)
764 dto = 14;
765 }
766
767 reg &= ~DTO_MASK;
768 reg |= dto << DTO_SHIFT;
769 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
770}
771
772/*
773 * Configure block length for MMC/SD cards and initiate the transfer.
774 */
775static int
776mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
777{
778 int ret;
779 host->data = req->data;
780
781 if (req->data == NULL) {
a45c6cb8
MC		 782 OMAP_HSMMC_WRITE(host->base, BLK, 0);
783 return 0;
784 }
785
786 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
787 | (req->data->blocks << 16));
788 set_data_timeout(host, req);
789
a45c6cb8
MC		 790 if (host->use_dma) {
791 ret = mmc_omap_start_dma_transfer(host, req);
792 if (ret != 0) {
793 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
794 return ret;
795 }
796 }
797 return 0;
798}
799
800/*
801 * Request function. for read/write operation
802 */
803static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
804{
805 struct mmc_omap_host *host = mmc_priv(mmc);
806
807 WARN_ON(host->mrq != NULL);
808 host->mrq = req;
809 mmc_omap_prepare_data(host, req);
810 mmc_omap_start_command(host, req->cmd, req->data);
811}
812
813
814/* Routine to configure clock values. Exposed API to core */
815static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
816{
817 struct mmc_omap_host *host = mmc_priv(mmc);
818 u16 dsor = 0;
819 unsigned long regval;
820 unsigned long timeout;
73153010 821 u32 con;
a45c6cb8
MC		 822
823 switch (ios->power_mode) {
824 case MMC_POWER_OFF:
825 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 826 break;
827 case MMC_POWER_UP:
828 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
829 break;
830 }
831
73153010 832 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 833 switch (mmc->ios.bus_width) {
73153010
JL		 834 case MMC_BUS_WIDTH_8:
835 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
836 break;
a45c6cb8 837 case MMC_BUS_WIDTH_4:
73153010 838 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 839 OMAP_HSMMC_WRITE(host->base, HCTL,
840 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
841 break;
842 case MMC_BUS_WIDTH_1:
73153010 843 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 844 OMAP_HSMMC_WRITE(host->base, HCTL,
845 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
846 break;
847 }
848
849 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 850 /* Only MMC1 can interface at 3V without some flavor
851 * of external transceiver; but they all handle 1.8V.
852 */
a45c6cb8
MC		 853 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
854 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
855 /*
856 * The mmc_select_voltage fn of the core does
857 * not seem to set the power_mode to
858 * MMC_POWER_UP upon recalculating the voltage.
859 * vdd 1.8v.
860 */
861 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
862 dev_dbg(mmc_dev(host->mmc),
863 "Switch operation failed\n");
864 }
865 }
866
867 if (ios->clock) {
868 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
869 if (dsor < 1)
870 dsor = 1;
871
872 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
873 dsor++;
874
875 if (dsor > 250)
876 dsor = 250;
877 }
878 omap_mmc_stop_clock(host);
879 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
880 regval = regval & ~(CLKD_MASK);
881 regval = regval | (dsor << 6) | (DTO << 16);
882 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
883 OMAP_HSMMC_WRITE(host->base, SYSCTL,
884 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
885
886 /* Wait till the ICS bit is set */
887 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
888 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
889 && time_before(jiffies, timeout))
890 msleep(1);
891
892 OMAP_HSMMC_WRITE(host->base, SYSCTL,
893 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
894
895 if (ios->power_mode == MMC_POWER_ON)
896 send_init_stream(host);
897
898 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
899 OMAP_HSMMC_WRITE(host->base, CON,
900 OMAP_HSMMC_READ(host->base, CON) | OD);
901}
902
903static int omap_hsmmc_get_cd(struct mmc_host *mmc)
904{
905 struct mmc_omap_host *host = mmc_priv(mmc);
906 struct omap_mmc_platform_data *pdata = host->pdata;
907
908 if (!pdata->slots[0].card_detect)
909 return -ENOSYS;
910 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
911}
912
913static int omap_hsmmc_get_ro(struct mmc_host *mmc)
914{
915 struct mmc_omap_host *host = mmc_priv(mmc);
916 struct omap_mmc_platform_data *pdata = host->pdata;
917
918 if (!pdata->slots[0].get_ro)
919 return -ENOSYS;
920 return pdata->slots[0].get_ro(host->dev, 0);
921}
922
1b331e69
KK		 923static void omap_hsmmc_init(struct mmc_omap_host *host)
924{
925 u32 hctl, capa, value;
926
927 /* Only MMC1 supports 3.0V */
928 if (host->id == OMAP_MMC1_DEVID) {
929 hctl = SDVS30;
930 capa = VS30 | VS18;
931 } else {
932 hctl = SDVS18;
933 capa = VS18;
934 }
935
936 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
937 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
938
939 value = OMAP_HSMMC_READ(host->base, CAPA);
940 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
941
942 /* Set the controller to AUTO IDLE mode */
943 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
944 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
945
946 /* Set SD bus power bit */
947 value = OMAP_HSMMC_READ(host->base, HCTL);
948 OMAP_HSMMC_WRITE(host->base, HCTL, value | SDBP);
949}
950
a45c6cb8
MC		 951static struct mmc_host_ops mmc_omap_ops = {
952 .request = omap_mmc_request,
953 .set_ios = omap_mmc_set_ios,
954 .get_cd = omap_hsmmc_get_cd,
955 .get_ro = omap_hsmmc_get_ro,
956 /* NYET -- enable_sdio_irq */
957};
958
959static int __init omap_mmc_probe(struct platform_device *pdev)
960{
961 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
962 struct mmc_host *mmc;
963 struct mmc_omap_host *host = NULL;
964 struct resource *res;
965 int ret = 0, irq;
a45c6cb8
MC		 966
967 if (pdata == NULL) {
968 dev_err(&pdev->dev, "Platform Data is missing\n");
969 return -ENXIO;
970 }
971
972 if (pdata->nr_slots == 0) {
973 dev_err(&pdev->dev, "No Slots\n");
974 return -ENXIO;
975 }
976
977 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
978 irq = platform_get_irq(pdev, 0);
979 if (res == NULL || irq < 0)
980 return -ENXIO;
981
982 res = request_mem_region(res->start, res->end - res->start + 1,
983 pdev->name);
984 if (res == NULL)
985 return -EBUSY;
986
987 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
988 if (!mmc) {
989 ret = -ENOMEM;
990 goto err;
991 }
992
993 host = mmc_priv(mmc);
994 host->mmc = mmc;
995 host->pdata = pdata;
996 host->dev = &pdev->dev;
997 host->use_dma = 1;
998 host->dev->dma_mask = &pdata->dma_mask;
999 host->dma_ch = -1;
1000 host->irq = irq;
1001 host->id = pdev->id;
1002 host->slot_id = 0;
1003 host->mapbase = res->start;
1004 host->base = ioremap(host->mapbase, SZ_4K);
1005
1006 platform_set_drvdata(pdev, host);
1007 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1008
1009 mmc->ops = &mmc_omap_ops;
1010 mmc->f_min = 400000;
1011 mmc->f_max = 52000000;
1012
1013 sema_init(&host->sem, 1);
1014
1015 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
1016 if (IS_ERR(host->iclk)) {
1017 ret = PTR_ERR(host->iclk);
1018 host->iclk = NULL;
1019 goto err1;
1020 }
1021 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
1022 if (IS_ERR(host->fclk)) {
1023 ret = PTR_ERR(host->fclk);
1024 host->fclk = NULL;
1025 clk_put(host->iclk);
1026 goto err1;
1027 }
1028
1029 if (clk_enable(host->fclk) != 0) {
1030 clk_put(host->iclk);
1031 clk_put(host->fclk);
1032 goto err1;
1033 }
1034
1035 if (clk_enable(host->iclk) != 0) {
1036 clk_disable(host->fclk);
1037 clk_put(host->iclk);
1038 clk_put(host->fclk);
1039 goto err1;
1040 }
1041
1042 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1043 /*
1044 * MMC can still work without debounce clock.
1045 */
1046 if (IS_ERR(host->dbclk))
1047 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1048 else
1049 if (clk_enable(host->dbclk) != 0)
1050 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1051 " clk failed\n");
1052 else
1053 host->dbclk_enabled = 1;
1054
0ccd76d4
JY		 1055 /* Since we do only SG emulation, we can have as many segs
1056 * as we want. */
1057 mmc->max_phys_segs = 1024;
1058 mmc->max_hw_segs = 1024;
1059
a45c6cb8
MC		 1060 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1061 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1062 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1063 mmc->max_seg_size = mmc->max_req_size;
1064
1065 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1066 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1067
73153010
JL		 1068 if (pdata->slots[host->slot_id].wires >= 8)
1069 mmc->caps |= MMC_CAP_8_BIT_DATA;
1070 else if (pdata->slots[host->slot_id].wires >= 4)
a45c6cb8
MC		 1071 mmc->caps |= MMC_CAP_4_BIT_DATA;
1072
1b331e69 1073 omap_hsmmc_init(host);
a45c6cb8
MC		 1074
1075 /* Request IRQ for MMC operations */
1076 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1077 mmc_hostname(mmc), host);
1078 if (ret) {
1079 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1080 goto err_irq;
1081 }
1082
1083 if (pdata->init != NULL) {
1084 if (pdata->init(&pdev->dev) != 0) {
1085 dev_dbg(mmc_dev(host->mmc),
1086 "Unable to configure MMC IRQs\n");
1087 goto err_irq_cd_init;
1088 }
1089 }
1090
1091 /* Request IRQ for card detect */
1092 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1093 ret = request_irq(mmc_slot(host).card_detect_irq,
1094 omap_mmc_cd_handler,
1095 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1096 | IRQF_DISABLED,
1097 mmc_hostname(mmc), host);
1098 if (ret) {
1099 dev_dbg(mmc_dev(host->mmc),
1100 "Unable to grab MMC CD IRQ\n");
1101 goto err_irq_cd;
1102 }
1103 }
1104
1105 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1106 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1107
1108 mmc_add_host(mmc);
1109
1110 if (host->pdata->slots[host->slot_id].name != NULL) {
1111 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1112 if (ret < 0)
1113 goto err_slot_name;
1114 }
1115 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1116 host->pdata->slots[host->slot_id].get_cover_state) {
1117 ret = device_create_file(&mmc->class_dev,
1118 &dev_attr_cover_switch);
1119 if (ret < 0)
1120 goto err_cover_switch;
1121 }
1122
1123 return 0;
1124
1125err_cover_switch:
1126 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1127err_slot_name:
1128 mmc_remove_host(mmc);
1129err_irq_cd:
1130 free_irq(mmc_slot(host).card_detect_irq, host);
1131err_irq_cd_init:
1132 free_irq(host->irq, host);
1133err_irq:
1134 clk_disable(host->fclk);
1135 clk_disable(host->iclk);
1136 clk_put(host->fclk);
1137 clk_put(host->iclk);
1138 if (host->dbclk_enabled) {
1139 clk_disable(host->dbclk);
1140 clk_put(host->dbclk);
1141 }
1142
1143err1:
1144 iounmap(host->base);
1145err:
1146 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1147 release_mem_region(res->start, res->end - res->start + 1);
1148 if (host)
1149 mmc_free_host(mmc);
1150 return ret;
1151}
1152
1153static int omap_mmc_remove(struct platform_device *pdev)
1154{
1155 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1156 struct resource *res;
1157
1158 if (host) {
1159 mmc_remove_host(host->mmc);
1160 if (host->pdata->cleanup)
1161 host->pdata->cleanup(&pdev->dev);
1162 free_irq(host->irq, host);
1163 if (mmc_slot(host).card_detect_irq)
1164 free_irq(mmc_slot(host).card_detect_irq, host);
1165 flush_scheduled_work();
1166
1167 clk_disable(host->fclk);
1168 clk_disable(host->iclk);
1169 clk_put(host->fclk);
1170 clk_put(host->iclk);
1171 if (host->dbclk_enabled) {
1172 clk_disable(host->dbclk);
1173 clk_put(host->dbclk);
1174 }
1175
1176 mmc_free_host(host->mmc);
1177 iounmap(host->base);
1178 }
1179
1180 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1181 if (res)
1182 release_mem_region(res->start, res->end - res->start + 1);
1183 platform_set_drvdata(pdev, NULL);
1184
1185 return 0;
1186}
1187
1188#ifdef CONFIG_PM
1189static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1190{
1191 int ret = 0;
1192 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1193
1194 if (host && host->suspended)
1195 return 0;
1196
1197 if (host) {
1198 ret = mmc_suspend_host(host->mmc, state);
1199 if (ret == 0) {
1200 host->suspended = 1;
1201
1202 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1203 OMAP_HSMMC_WRITE(host->base, IE, 0);
1204
1205 if (host->pdata->suspend) {
1206 ret = host->pdata->suspend(&pdev->dev,
1207 host->slot_id);
1208 if (ret)
1209 dev_dbg(mmc_dev(host->mmc),
1210 "Unable to handle MMC board"
1211 " level suspend\n");
1212 }
1213
eb250826
DB		 1214 if (host->id == OMAP_MMC1_DEVID
1215 && !(OMAP_HSMMC_READ(host->base, HCTL)
1216 & SDVSDET)) {
a45c6cb8
MC		 1217 OMAP_HSMMC_WRITE(host->base, HCTL,
1218 OMAP_HSMMC_READ(host->base, HCTL)
1219 & SDVSCLR);
1220 OMAP_HSMMC_WRITE(host->base, HCTL,
1221 OMAP_HSMMC_READ(host->base, HCTL)
1222 | SDVS30);
1223 OMAP_HSMMC_WRITE(host->base, HCTL,
1224 OMAP_HSMMC_READ(host->base, HCTL)
1225 | SDBP);
1226 }
1227
1228 clk_disable(host->fclk);
1229 clk_disable(host->iclk);
1230 clk_disable(host->dbclk);
1231 }
1232
1233 }
1234 return ret;
1235}
1236
1237/* Routine to resume the MMC device */
1238static int omap_mmc_resume(struct platform_device *pdev)
1239{
1240 int ret = 0;
1241 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1242
1243 if (host && !host->suspended)
1244 return 0;
1245
1246 if (host) {
1247
1248 ret = clk_enable(host->fclk);
1249 if (ret)
1250 goto clk_en_err;
1251
1252 ret = clk_enable(host->iclk);
1253 if (ret) {
1254 clk_disable(host->fclk);
1255 clk_put(host->fclk);
1256 goto clk_en_err;
1257 }
1258
1259 if (clk_enable(host->dbclk) != 0)
1260 dev_dbg(mmc_dev(host->mmc),
1261 "Enabling debounce clk failed\n");
1262
1b331e69
KK		 1263 omap_hsmmc_init(host);
1264
a45c6cb8
MC		 1265 if (host->pdata->resume) {
1266 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1267 if (ret)
1268 dev_dbg(mmc_dev(host->mmc),
1269 "Unmask interrupt failed\n");
1270 }
1271
1272 /* Notify the core to resume the host */
1273 ret = mmc_resume_host(host->mmc);
1274 if (ret == 0)
1275 host->suspended = 0;
1276 }
1277
1278 return ret;
1279
1280clk_en_err:
1281 dev_dbg(mmc_dev(host->mmc),
1282 "Failed to enable MMC clocks during resume\n");
1283 return ret;
1284}
1285
1286#else
1287#define omap_mmc_suspend NULL
1288#define omap_mmc_resume NULL
1289#endif
1290
1291static struct platform_driver omap_mmc_driver = {
1292 .probe = omap_mmc_probe,
1293 .remove = omap_mmc_remove,
1294 .suspend = omap_mmc_suspend,
1295 .resume = omap_mmc_resume,
1296 .driver = {
1297 .name = DRIVER_NAME,
1298 .owner = THIS_MODULE,
1299 },
1300};
1301
1302static int __init omap_mmc_init(void)
1303{
1304 /* Register the MMC driver */
1305 return platform_driver_register(&omap_mmc_driver);
1306}
1307
1308static void __exit omap_mmc_cleanup(void)
1309{
1310 /* Unregister MMC driver */
1311 platform_driver_unregister(&omap_mmc_driver);
1312}
1313
1314module_init(omap_mmc_init);
1315module_exit(omap_mmc_cleanup);
1316
1317MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1318MODULE_LICENSE("GPL");
1319MODULE_ALIAS("platform:" DRIVER_NAME);
1320MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)