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mmc: sdhci-spear: add pm callbacks to support hibernation
[linux-2.6-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712
DK		 21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
a45c6cb8
MC		 23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
a45c6cb8
MC		 27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
93caf8e6 31#include <linux/mmc/mmc.h>
a45c6cb8
MC		 32#include <linux/io.h>
33#include <linux/semaphore.h>
db0fefc5
AH		 34#include <linux/gpio.h>
35#include <linux/regulator/consumer.h>
fa4aa2d4 36#include <linux/pm_runtime.h>
ce491cf8 37#include <plat/dma.h>
a45c6cb8 38#include <mach/hardware.h>
ce491cf8
TL		 39#include <plat/board.h>
40#include <plat/mmc.h>
41#include <plat/cpu.h>
a45c6cb8
MC		 42
43/* OMAP HSMMC Host Controller Registers */
44#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 45#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 46#define OMAP_HSMMC_CON 0x002C
47#define OMAP_HSMMC_BLK 0x0104
48#define OMAP_HSMMC_ARG 0x0108
49#define OMAP_HSMMC_CMD 0x010C
50#define OMAP_HSMMC_RSP10 0x0110
51#define OMAP_HSMMC_RSP32 0x0114
52#define OMAP_HSMMC_RSP54 0x0118
53#define OMAP_HSMMC_RSP76 0x011C
54#define OMAP_HSMMC_DATA 0x0120
55#define OMAP_HSMMC_HCTL 0x0128
56#define OMAP_HSMMC_SYSCTL 0x012C
57#define OMAP_HSMMC_STAT 0x0130
58#define OMAP_HSMMC_IE 0x0134
59#define OMAP_HSMMC_ISE 0x0138
60#define OMAP_HSMMC_CAPA 0x0140
61
62#define VS18 (1 << 26)
63#define VS30 (1 << 25)
64#define SDVS18 (0x5 << 9)
65#define SDVS30 (0x6 << 9)
eb250826 66#define SDVS33 (0x7 << 9)
1b331e69 67#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 68#define SDVSCLR 0xFFFFF1FF
69#define SDVSDET 0x00000400
70#define AUTOIDLE 0x1
71#define SDBP (1 << 8)
72#define DTO 0xe
73#define ICE 0x1
74#define ICS 0x2
75#define CEN (1 << 2)
76#define CLKD_MASK 0x0000FFC0
77#define CLKD_SHIFT 6
78#define DTO_MASK 0x000F0000
79#define DTO_SHIFT 16
80#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 81#define BWR_ENABLE (1 << 4)
82#define BRR_ENABLE (1 << 5)
93caf8e6 83#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 84#define INIT_STREAM (1 << 1)
85#define DP_SELECT (1 << 21)
86#define DDIR (1 << 4)
87#define DMA_EN 0x1
88#define MSBS (1 << 5)
89#define BCE (1 << 1)
90#define FOUR_BIT (1 << 1)
73153010 91#define DW8 (1 << 5)
a45c6cb8
MC		 92#define CC 0x1
93#define TC 0x02
94#define OD 0x1
95#define ERR (1 << 15)
96#define CMD_TIMEOUT (1 << 16)
97#define DATA_TIMEOUT (1 << 20)
98#define CMD_CRC (1 << 17)
99#define DATA_CRC (1 << 21)
100#define CARD_ERR (1 << 28)
101#define STAT_CLEAR 0xFFFFFFFF
102#define INIT_STREAM_CMD 0x00000000
103#define DUAL_VOLT_OCR_BIT 7
104#define SRC (1 << 25)
105#define SRD (1 << 26)
11dd62a7
DK		 106#define SOFTRESET (1 << 1)
107#define RESETDONE (1 << 0)
a45c6cb8 108
fa4aa2d4 109#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8 110#define MMC_TIMEOUT_MS 20
6b206efe
AS		 111#define OMAP_MMC_MIN_CLOCK 400000
112#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 113#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 114
115/*
116 * One controller can have multiple slots, like on some omap boards using
117 * omap.c controller driver. Luckily this is not currently done on any known
118 * omap_hsmmc.c device.
119 */
120#define mmc_slot(host) (host->pdata->slots[host->slot_id])
121
122/*
123 * MMC Host controller read/write API's
124 */
125#define OMAP_HSMMC_READ(base, reg) \
126 __raw_readl((base) + OMAP_HSMMC_##reg)
127
128#define OMAP_HSMMC_WRITE(base, reg, val) \
129 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
130
9782aff8
PF		 131struct omap_hsmmc_next {
132 unsigned int dma_len;
133 s32 cookie;
134};
135
70a3341a 136struct omap_hsmmc_host {
a45c6cb8
MC		 137 struct device *dev;
138 struct mmc_host *mmc;
139 struct mmc_request *mrq;
140 struct mmc_command *cmd;
141 struct mmc_data *data;
142 struct clk *fclk;
a45c6cb8 143 struct clk *dbclk;
db0fefc5
AH		 144 /*
145 * vcc == configured supply
146 * vcc_aux == optional
147 * - MMC1, supply for DAT4..DAT7
148 * - MMC2/MMC2, external level shifter voltage supply, for
149 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
150 */
151 struct regulator *vcc;
152 struct regulator *vcc_aux;
a45c6cb8
MC		 153 void __iomem *base;
154 resource_size_t mapbase;
4dffd7a2 155 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 156 unsigned int dma_len;
0ccd76d4 157 unsigned int dma_sg_idx;
a45c6cb8 158 unsigned char bus_mode;
a3621465 159 unsigned char power_mode;
a45c6cb8
MC		 160 u32 *buffer;
161 u32 bytesleft;
162 int suspended;
163 int irq;
a45c6cb8 164 int use_dma, dma_ch;
f3e2f1dd 165 int dma_line_tx, dma_line_rx;
a45c6cb8 166 int slot_id;
2bec0893 167 int got_dbclk;
4a694dc9 168 int response_busy;
11dd62a7 169 int context_loss;
dd498eff 170 int dpm_state;
623821f7 171 int vdd;
b62f6228
AH		 172 int protect_card;
173 int reqs_blocked;
db0fefc5 174 int use_reg;
b417577d 175 int req_in_progress;
9782aff8 176 struct omap_hsmmc_next next_data;
11dd62a7 177
a45c6cb8
MC		 178 struct omap_mmc_platform_data *pdata;
179};
180
db0fefc5
AH		 181static int omap_hsmmc_card_detect(struct device *dev, int slot)
182{
183 struct omap_mmc_platform_data *mmc = dev->platform_data;
184
185 /* NOTE: assumes card detect signal is active-low */
186 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
187}
188
189static int omap_hsmmc_get_wp(struct device *dev, int slot)
190{
191 struct omap_mmc_platform_data *mmc = dev->platform_data;
192
193 /* NOTE: assumes write protect signal is active-high */
194 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
195}
196
197static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
198{
199 struct omap_mmc_platform_data *mmc = dev->platform_data;
200
201 /* NOTE: assumes card detect signal is active-low */
202 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
203}
204
205#ifdef CONFIG_PM
206
207static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
208{
209 struct omap_mmc_platform_data *mmc = dev->platform_data;
210
211 disable_irq(mmc->slots[0].card_detect_irq);
212 return 0;
213}
214
215static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
216{
217 struct omap_mmc_platform_data *mmc = dev->platform_data;
218
219 enable_irq(mmc->slots[0].card_detect_irq);
220 return 0;
221}
222
223#else
224
225#define omap_hsmmc_suspend_cdirq NULL
226#define omap_hsmmc_resume_cdirq NULL
227
228#endif
229
b702b106
AH		 230#ifdef CONFIG_REGULATOR
231
69b07ece 232static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 233 int vdd)
234{
235 struct omap_hsmmc_host *host =
236 platform_get_drvdata(to_platform_device(dev));
237 int ret = 0;
238
239 /*
240 * If we don't see a Vcc regulator, assume it's a fixed
241 * voltage always-on regulator.
242 */
243 if (!host->vcc)
244 return 0;
245
246 if (mmc_slot(host).before_set_reg)
247 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
248
249 /*
250 * Assume Vcc regulator is used only to power the card ... OMAP
251 * VDDS is used to power the pins, optionally with a transceiver to
252 * support cards using voltages other than VDDS (1.8V nominal). When a
253 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
254 *
255 * In some cases this regulator won't support enable/disable;
256 * e.g. it's a fixed rail for a WLAN chip.
257 *
258 * In other cases vcc_aux switches interface power. Example, for
259 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
260 * chips/cards need an interface voltage rail too.
261 */
262 if (power_on) {
99fc5131 263 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 264 /* Enable interface voltage rail, if needed */
265 if (ret == 0 && host->vcc_aux) {
266 ret = regulator_enable(host->vcc_aux);
267 if (ret < 0)
99fc5131
LW		 268 ret = mmc_regulator_set_ocr(host->mmc,
269 host->vcc, 0);
db0fefc5
AH		 270 }
271 } else {
99fc5131 272 /* Shut down the rail */
6da20c89
AH		 273 if (host->vcc_aux)
274 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 275 if (!ret) {
276 /* Then proceed to shut down the local regulator */
277 ret = mmc_regulator_set_ocr(host->mmc,
278 host->vcc, 0);
279 }
db0fefc5
AH		 280 }
281
282 if (mmc_slot(host).after_set_reg)
283 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
284
285 return ret;
286}
287
db0fefc5
AH		 288static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
289{
290 struct regulator *reg;
64be9782 291 int ocr_value = 0;
db0fefc5 292
1cb9af49 293 mmc_slot(host).set_power = omap_hsmmc_set_power;
db0fefc5
AH		 294
295 reg = regulator_get(host->dev, "vmmc");
296 if (IS_ERR(reg)) {
297 dev_dbg(host->dev, "vmmc regulator missing\n");
db0fefc5
AH		 298 } else {
299 host->vcc = reg;
64be9782 300 ocr_value = mmc_regulator_get_ocrmask(reg);
301 if (!mmc_slot(host).ocr_mask) {
302 mmc_slot(host).ocr_mask = ocr_value;
303 } else {
304 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
e3f1adb6
RN		 305 pr_err("MMC ocrmask %x is not supported\n",
306 mmc_slot(host).ocr_mask);
64be9782 307 mmc_slot(host).ocr_mask = 0;
308 return -EINVAL;
309 }
310 }
db0fefc5
AH		 311
312 /* Allow an aux regulator */
313 reg = regulator_get(host->dev, "vmmc_aux");
314 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
315
b1c1df7a
B		 316 /* For eMMC do not power off when not in sleep state */
317 if (mmc_slot(host).no_regulator_off_init)
318 return 0;
db0fefc5
AH		 319 /*
320 * UGLY HACK: workaround regulator framework bugs.
321 * When the bootloader leaves a supply active, it's
322 * initialized with zero usecount ... and we can't
323 * disable it without first enabling it. Until the
324 * framework is fixed, we need a workaround like this
325 * (which is safe for MMC, but not in general).
326 */
e840ce13
AH		 327 if (regulator_is_enabled(host->vcc) > 0 ||
328 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
329 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
330
331 mmc_slot(host).set_power(host->dev, host->slot_id,
332 1, vdd);
333 mmc_slot(host).set_power(host->dev, host->slot_id,
334 0, 0);
db0fefc5
AH		 335 }
336 }
337
338 return 0;
db0fefc5
AH		 339}
340
341static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
342{
343 regulator_put(host->vcc);
344 regulator_put(host->vcc_aux);
345 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 346}
347
b702b106
AH		 348static inline int omap_hsmmc_have_reg(void)
349{
350 return 1;
351}
352
353#else
354
355static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
356{
357 return -EINVAL;
358}
359
360static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
361{
362}
363
364static inline int omap_hsmmc_have_reg(void)
365{
366 return 0;
367}
368
369#endif
370
371static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
372{
373 int ret;
374
375 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 376 if (pdata->slots[0].cover)
377 pdata->slots[0].get_cover_state =
378 omap_hsmmc_get_cover_state;
379 else
380 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
381 pdata->slots[0].card_detect_irq =
382 gpio_to_irq(pdata->slots[0].switch_pin);
383 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
384 if (ret)
385 return ret;
386 ret = gpio_direction_input(pdata->slots[0].switch_pin);
387 if (ret)
388 goto err_free_sp;
389 } else
390 pdata->slots[0].switch_pin = -EINVAL;
391
392 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
393 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
394 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
395 if (ret)
396 goto err_free_cd;
397 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
398 if (ret)
399 goto err_free_wp;
400 } else
401 pdata->slots[0].gpio_wp = -EINVAL;
402
403 return 0;
404
405err_free_wp:
406 gpio_free(pdata->slots[0].gpio_wp);
407err_free_cd:
408 if (gpio_is_valid(pdata->slots[0].switch_pin))
409err_free_sp:
410 gpio_free(pdata->slots[0].switch_pin);
411 return ret;
412}
413
414static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
415{
416 if (gpio_is_valid(pdata->slots[0].gpio_wp))
417 gpio_free(pdata->slots[0].gpio_wp);
418 if (gpio_is_valid(pdata->slots[0].switch_pin))
419 gpio_free(pdata->slots[0].switch_pin);
420}
421
e0c7f99b
AS		 422/*
423 * Start clock to the card
424 */
425static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
426{
427 OMAP_HSMMC_WRITE(host->base, SYSCTL,
428 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
429}
430
a45c6cb8
MC		 431/*
432 * Stop clock to the card
433 */
70a3341a 434static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 435{
436 OMAP_HSMMC_WRITE(host->base, SYSCTL,
437 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
438 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
439 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
440}
441
93caf8e6
AH		 442static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
443 struct mmc_command *cmd)
b417577d
AH		 444{
445 unsigned int irq_mask;
446
447 if (host->use_dma)
448 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
449 else
450 irq_mask = INT_EN_MASK;
451
93caf8e6
AH		 452 /* Disable timeout for erases */
453 if (cmd->opcode == MMC_ERASE)
454 irq_mask &= ~DTO_ENABLE;
455
b417577d
AH		 456 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
457 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
458 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
459}
460
461static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
462{
463 OMAP_HSMMC_WRITE(host->base, ISE, 0);
464 OMAP_HSMMC_WRITE(host->base, IE, 0);
465 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
466}
467
ac330f44 468/* Calculate divisor for the given clock frequency */
d83b6e03 469static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 470{
471 u16 dsor = 0;
472
473 if (ios->clock) {
d83b6e03 474 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ac330f44
AS		 475 if (dsor > 250)
476 dsor = 250;
477 }
478
479 return dsor;
480}
481
5934df2f
AS		 482static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
483{
484 struct mmc_ios *ios = &host->mmc->ios;
485 unsigned long regval;
486 unsigned long timeout;
487
488 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
489
490 omap_hsmmc_stop_clock(host);
491
492 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
493 regval = regval & ~(CLKD_MASK | DTO_MASK);
d83b6e03 494 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
5934df2f
AS		 495 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
496 OMAP_HSMMC_WRITE(host->base, SYSCTL,
497 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
498
499 /* Wait till the ICS bit is set */
500 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
501 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
502 && time_before(jiffies, timeout))
503 cpu_relax();
504
505 omap_hsmmc_start_clock(host);
506}
507
3796fb8a
AS		 508static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
509{
510 struct mmc_ios *ios = &host->mmc->ios;
511 u32 con;
512
513 con = OMAP_HSMMC_READ(host->base, CON);
514 switch (ios->bus_width) {
515 case MMC_BUS_WIDTH_8:
516 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
517 break;
518 case MMC_BUS_WIDTH_4:
519 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
520 OMAP_HSMMC_WRITE(host->base, HCTL,
521 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
522 break;
523 case MMC_BUS_WIDTH_1:
524 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
525 OMAP_HSMMC_WRITE(host->base, HCTL,
526 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
527 break;
528 }
529}
530
531static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
532{
533 struct mmc_ios *ios = &host->mmc->ios;
534 u32 con;
535
536 con = OMAP_HSMMC_READ(host->base, CON);
537 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
538 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
539 else
540 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
541}
542
11dd62a7
DK		 543#ifdef CONFIG_PM
544
545/*
546 * Restore the MMC host context, if it was lost as result of a
547 * power state change.
548 */
70a3341a 549static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 550{
551 struct mmc_ios *ios = &host->mmc->ios;
552 struct omap_mmc_platform_data *pdata = host->pdata;
553 int context_loss = 0;
3796fb8a 554 u32 hctl, capa;
11dd62a7
DK		 555 unsigned long timeout;
556
557 if (pdata->get_context_loss_count) {
558 context_loss = pdata->get_context_loss_count(host->dev);
559 if (context_loss < 0)
560 return 1;
561 }
562
563 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
564 context_loss == host->context_loss ? "not " : "");
565 if (host->context_loss == context_loss)
566 return 1;
567
568 /* Wait for hardware reset */
569 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
570 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
571 && time_before(jiffies, timeout))
572 ;
573
574 /* Do software reset */
575 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
576 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
577 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
578 && time_before(jiffies, timeout))
579 ;
580
581 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
582 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
583
c2200efb 584 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 585 if (host->power_mode != MMC_POWER_OFF &&
586 (1 << ios->vdd) <= MMC_VDD_23_24)
587 hctl = SDVS18;
588 else
589 hctl = SDVS30;
590 capa = VS30 | VS18;
591 } else {
592 hctl = SDVS18;
593 capa = VS18;
594 }
595
596 OMAP_HSMMC_WRITE(host->base, HCTL,
597 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
598
599 OMAP_HSMMC_WRITE(host->base, CAPA,
600 OMAP_HSMMC_READ(host->base, CAPA) | capa);
601
602 OMAP_HSMMC_WRITE(host->base, HCTL,
603 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
604
605 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
606 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
607 && time_before(jiffies, timeout))
608 ;
609
b417577d 610 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 611
612 /* Do not initialize card-specific things if the power is off */
613 if (host->power_mode == MMC_POWER_OFF)
614 goto out;
615
3796fb8a 616 omap_hsmmc_set_bus_width(host);
11dd62a7 617
5934df2f 618 omap_hsmmc_set_clock(host);
11dd62a7 619
3796fb8a
AS		 620 omap_hsmmc_set_bus_mode(host);
621
11dd62a7
DK		 622out:
623 host->context_loss = context_loss;
624
625 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
626 return 0;
627}
628
629/*
630 * Save the MMC host context (store the number of power state changes so far).
631 */
70a3341a 632static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 633{
634 struct omap_mmc_platform_data *pdata = host->pdata;
635 int context_loss;
636
637 if (pdata->get_context_loss_count) {
638 context_loss = pdata->get_context_loss_count(host->dev);
639 if (context_loss < 0)
640 return;
641 host->context_loss = context_loss;
642 }
643}
644
645#else
646
70a3341a 647static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 648{
649 return 0;
650}
651
70a3341a 652static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 653{
654}
655
656#endif
657
a45c6cb8
MC		 658/*
659 * Send init stream sequence to card
660 * before sending IDLE command
661 */
70a3341a 662static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 663{
664 int reg = 0;
665 unsigned long timeout;
666
b62f6228
AH		 667 if (host->protect_card)
668 return;
669
a45c6cb8 670 disable_irq(host->irq);
b417577d
AH		 671
672 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 673 OMAP_HSMMC_WRITE(host->base, CON,
674 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
675 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
676
677 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
678 while ((reg != CC) && time_before(jiffies, timeout))
679 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
680
681 OMAP_HSMMC_WRITE(host->base, CON,
682 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 683
684 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
685 OMAP_HSMMC_READ(host->base, STAT);
686
a45c6cb8
MC		 687 enable_irq(host->irq);
688}
689
690static inline
70a3341a 691int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 692{
693 int r = 1;
694
191d1f1d
DK		 695 if (mmc_slot(host).get_cover_state)
696 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 697 return r;
698}
699
700static ssize_t
70a3341a 701omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 702 char *buf)
703{
704 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 705 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 706
70a3341a
DK		 707 return sprintf(buf, "%s\n",
708 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 709}
710
70a3341a 711static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 712
713static ssize_t
70a3341a 714omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 715 char *buf)
716{
717 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 718 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 719
191d1f1d 720 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 721}
722
70a3341a 723static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 724
725/*
726 * Configure the response type and send the cmd.
727 */
728static void
70a3341a 729omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 730 struct mmc_data *data)
731{
732 int cmdreg = 0, resptype = 0, cmdtype = 0;
733
734 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
735 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
736 host->cmd = cmd;
737
93caf8e6 738 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 739
4a694dc9 740 host->response_busy = 0;
a45c6cb8
MC		 741 if (cmd->flags & MMC_RSP_PRESENT) {
742 if (cmd->flags & MMC_RSP_136)
743 resptype = 1;
4a694dc9
AH		 744 else if (cmd->flags & MMC_RSP_BUSY) {
745 resptype = 3;
746 host->response_busy = 1;
747 } else
a45c6cb8
MC		 748 resptype = 2;
749 }
750
751 /*
752 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
753 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
754 * a val of 0x3, rest 0x0.
755 */
756 if (cmd == host->mrq->stop)
757 cmdtype = 0x3;
758
759 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
760
761 if (data) {
762 cmdreg |= DP_SELECT | MSBS | BCE;
763 if (data->flags & MMC_DATA_READ)
764 cmdreg |= DDIR;
765 else
766 cmdreg &= ~(DDIR);
767 }
768
769 if (host->use_dma)
770 cmdreg |= DMA_EN;
771
b417577d 772 host->req_in_progress = 1;
4dffd7a2 773
a45c6cb8
MC		 774 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
775 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
776}
777
0ccd76d4 778static int
70a3341a 779omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 780{
781 if (data->flags & MMC_DATA_WRITE)
782 return DMA_TO_DEVICE;
783 else
784 return DMA_FROM_DEVICE;
785}
786
b417577d
AH		 787static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
788{
789 int dma_ch;
790
791 spin_lock(&host->irq_lock);
792 host->req_in_progress = 0;
793 dma_ch = host->dma_ch;
794 spin_unlock(&host->irq_lock);
795
796 omap_hsmmc_disable_irq(host);
797 /* Do not complete the request if DMA is still in progress */
798 if (mrq->data && host->use_dma && dma_ch != -1)
799 return;
800 host->mrq = NULL;
801 mmc_request_done(host->mmc, mrq);
802}
803
a45c6cb8
MC		 804/*
805 * Notify the transfer complete to MMC core
806 */
807static void
70a3341a 808omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 809{
4a694dc9
AH		 810 if (!data) {
811 struct mmc_request *mrq = host->mrq;
812
23050103
AH		 813 /* TC before CC from CMD6 - don't know why, but it happens */
814 if (host->cmd && host->cmd->opcode == 6 &&
815 host->response_busy) {
816 host->response_busy = 0;
817 return;
818 }
819
b417577d 820 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 821 return;
822 }
823
a45c6cb8
MC		 824 host->data = NULL;
825
a45c6cb8
MC		 826 if (!data->error)
827 data->bytes_xfered += data->blocks * (data->blksz);
828 else
829 data->bytes_xfered = 0;
830
831 if (!data->stop) {
b417577d 832 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 833 return;
834 }
70a3341a 835 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 836}
837
838/*
839 * Notify the core about command completion
840 */
841static void
70a3341a 842omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 843{
844 host->cmd = NULL;
845
846 if (cmd->flags & MMC_RSP_PRESENT) {
847 if (cmd->flags & MMC_RSP_136) {
848 /* response type 2 */
849 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
850 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
851 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
852 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
853 } else {
854 /* response types 1, 1b, 3, 4, 5, 6 */
855 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
856 }
857 }
b417577d
AH		 858 if ((host->data == NULL && !host->response_busy) || cmd->error)
859 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 860}
861
862/*
863 * DMA clean up for command errors
864 */
70a3341a 865static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 866{
b417577d
AH		 867 int dma_ch;
868
82788ff5 869 host->data->error = errno;
a45c6cb8 870
b417577d
AH		 871 spin_lock(&host->irq_lock);
872 dma_ch = host->dma_ch;
873 host->dma_ch = -1;
874 spin_unlock(&host->irq_lock);
875
876 if (host->use_dma && dma_ch != -1) {
a9120c33
PF		 877 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
878 host->data->sg_len,
70a3341a 879 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 880 omap_free_dma(dma_ch);
053bf34f 881 host->data->host_cookie = 0;
a45c6cb8
MC		 882 }
883 host->data = NULL;
a45c6cb8
MC		 884}
885
886/*
887 * Readable error output
888 */
889#ifdef CONFIG_MMC_DEBUG
699b958b 890static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 891{
892 /* --- means reserved bit without definition at documentation */
70a3341a 893 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 894 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
895 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
896 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
897 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 898 };
899 char res[256];
900 char *buf = res;
901 int len, i;
902
903 len = sprintf(buf, "MMC IRQ 0x%x :", status);
904 buf += len;
905
70a3341a 906 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 907 if (status & (1 << i)) {
70a3341a 908 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 909 buf += len;
910 }
911
912 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
913}
699b958b
AH		 914#else
915static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
916 u32 status)
917{
918}
a45c6cb8
MC		 919#endif /* CONFIG_MMC_DEBUG */
920
3ebf74b1
JP		 921/*
922 * MMC controller internal state machines reset
923 *
924 * Used to reset command or data internal state machines, using respectively
925 * SRC or SRD bit of SYSCTL register
926 * Can be called from interrupt context
927 */
70a3341a
DK		 928static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
929 unsigned long bit)
3ebf74b1
JP		 930{
931 unsigned long i = 0;
932 unsigned long limit = (loops_per_jiffy *
933 msecs_to_jiffies(MMC_TIMEOUT_MS));
934
935 OMAP_HSMMC_WRITE(host->base, SYSCTL,
936 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
937
07ad64b6
MC		 938 /*
939 * OMAP4 ES2 and greater has an updated reset logic.
940 * Monitor a 0->1 transition first
941 */
942 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 943 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 944 && (i++ < limit))
945 cpu_relax();
946 }
947 i = 0;
948
3ebf74b1
JP		 949 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
950 (i++ < limit))
951 cpu_relax();
952
953 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
954 dev_err(mmc_dev(host->mmc),
955 "Timeout waiting on controller reset in %s\n",
956 __func__);
957}
a45c6cb8 958
b417577d 959static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 960{
a45c6cb8 961 struct mmc_data *data;
b417577d
AH		 962 int end_cmd = 0, end_trans = 0;
963
964 if (!host->req_in_progress) {
965 do {
966 OMAP_HSMMC_WRITE(host->base, STAT, status);
967 /* Flush posted write */
968 status = OMAP_HSMMC_READ(host->base, STAT);
969 } while (status & INT_EN_MASK);
970 return;
a45c6cb8
MC		 971 }
972
973 data = host->data;
a45c6cb8
MC		 974 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
975
976 if (status & ERR) {
699b958b 977 omap_hsmmc_dbg_report_irq(host, status);
a45c6cb8
MC		 978 if ((status & CMD_TIMEOUT) ||
979 (status & CMD_CRC)) {
980 if (host->cmd) {
981 if (status & CMD_TIMEOUT) {
70a3341a
DK		 982 omap_hsmmc_reset_controller_fsm(host,
983 SRC);
a45c6cb8
MC		 984 host->cmd->error = -ETIMEDOUT;
985 } else {
986 host->cmd->error = -EILSEQ;
987 }
988 end_cmd = 1;
989 }
4a694dc9
AH		 990 if (host->data || host->response_busy) {
991 if (host->data)
70a3341a
DK		 992 omap_hsmmc_dma_cleanup(host,
993 -ETIMEDOUT);
4a694dc9 994 host->response_busy = 0;
70a3341a 995 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 996 }
a45c6cb8
MC		 997 }
998 if ((status & DATA_TIMEOUT) ||
999 (status & DATA_CRC)) {
4a694dc9
AH		 1000 if (host->data || host->response_busy) {
1001 int err = (status & DATA_TIMEOUT) ?
1002 -ETIMEDOUT : -EILSEQ;
1003
1004 if (host->data)
70a3341a 1005 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1006 else
4a694dc9
AH		 1007 host->mrq->cmd->error = err;
1008 host->response_busy = 0;
70a3341a 1009 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1010 end_trans = 1;
1011 }
1012 }
1013 if (status & CARD_ERR) {
1014 dev_dbg(mmc_dev(host->mmc),
1015 "Ignoring card err CMD%d\n", host->cmd->opcode);
1016 if (host->cmd)
1017 end_cmd = 1;
1018 if (host->data)
1019 end_trans = 1;
1020 }
1021 }
1022
1023 OMAP_HSMMC_WRITE(host->base, STAT, status);
1024
a8fe29d8 1025 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1026 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1027 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1028 omap_hsmmc_xfer_done(host, data);
b417577d 1029}
a45c6cb8 1030
b417577d
AH		 1031/*
1032 * MMC controller IRQ handler
1033 */
1034static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1035{
1036 struct omap_hsmmc_host *host = dev_id;
1037 int status;
1038
1039 status = OMAP_HSMMC_READ(host->base, STAT);
1040 do {
1041 omap_hsmmc_do_irq(host, status);
1042 /* Flush posted write */
1043 status = OMAP_HSMMC_READ(host->base, STAT);
1044 } while (status & INT_EN_MASK);
4dffd7a2 1045
a45c6cb8
MC		 1046 return IRQ_HANDLED;
1047}
1048
70a3341a 1049static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1050{
1051 unsigned long i;
1052
1053 OMAP_HSMMC_WRITE(host->base, HCTL,
1054 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1055 for (i = 0; i < loops_per_jiffy; i++) {
1056 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1057 break;
1058 cpu_relax();
1059 }
1060}
1061
a45c6cb8 1062/*
eb250826
DB		 1063 * Switch MMC interface voltage ... only relevant for MMC1.
1064 *
1065 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1066 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1067 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1068 */
70a3341a 1069static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1070{
1071 u32 reg_val = 0;
1072 int ret;
1073
1074 /* Disable the clocks */
fa4aa2d4 1075 pm_runtime_put_sync(host->dev);
2bec0893
AH		 1076 if (host->got_dbclk)
1077 clk_disable(host->dbclk);
a45c6cb8
MC		 1078
1079 /* Turn the power off */
1080 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1081
1082 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1083 if (!ret)
1084 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1085 vdd);
fa4aa2d4 1086 pm_runtime_get_sync(host->dev);
2bec0893
AH		 1087 if (host->got_dbclk)
1088 clk_enable(host->dbclk);
1089
a45c6cb8
MC		 1090 if (ret != 0)
1091 goto err;
1092
a45c6cb8
MC		 1093 OMAP_HSMMC_WRITE(host->base, HCTL,
1094 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1095 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1096
a45c6cb8
MC		 1097 /*
1098 * If a MMC dual voltage card is detected, the set_ios fn calls
1099 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1100 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1101 *
eb250826
DB		 1102 * Cope with a bit of slop in the range ... per data sheets:
1103 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1104 * but recommended values are 1.71V to 1.89V
1105 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1106 * but recommended values are 2.7V to 3.3V
1107 *
1108 * Board setup code shouldn't permit anything very out-of-range.
1109 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1110 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1111 */
eb250826 1112 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1113 reg_val |= SDVS18;
eb250826
DB		 1114 else
1115 reg_val |= SDVS30;
a45c6cb8
MC		 1116
1117 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1118 set_sd_bus_power(host);
a45c6cb8
MC		 1119
1120 return 0;
1121err:
1122 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1123 return ret;
1124}
1125
b62f6228
AH		 1126/* Protect the card while the cover is open */
1127static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1128{
1129 if (!mmc_slot(host).get_cover_state)
1130 return;
1131
1132 host->reqs_blocked = 0;
1133 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1134 if (host->protect_card) {
a3c76eb9 1135 pr_info("%s: cover is closed, "
b62f6228
AH		 1136 "card is now accessible\n",
1137 mmc_hostname(host->mmc));
1138 host->protect_card = 0;
1139 }
1140 } else {
1141 if (!host->protect_card) {
3f8ddb03 1142 pr_info("%s: cover is open, "
b62f6228
AH		 1143 "card is now inaccessible\n",
1144 mmc_hostname(host->mmc));
1145 host->protect_card = 1;
1146 }
1147 }
1148}
1149
a45c6cb8 1150/*
7efab4f3 1151 * irq handler to notify the core about card insertion/removal
a45c6cb8 1152 */
7efab4f3 1153static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1154{
7efab4f3 1155 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1156 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1157 int carddetect;
1158
1159 if (host->suspended)
7efab4f3 1160 return IRQ_HANDLED;
a6b2240d
AH		 1161
1162 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1163
191d1f1d 1164 if (slot->card_detect)
db0fefc5 1165 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1166 else {
1167 omap_hsmmc_protect_card(host);
a6b2240d 1168 carddetect = -ENOSYS;
b62f6228 1169 }
a45c6cb8 1170
cdeebadd 1171 if (carddetect)
a45c6cb8 1172 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1173 else
a45c6cb8 1174 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1175 return IRQ_HANDLED;
1176}
1177
70a3341a 1178static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1179 struct mmc_data *data)
1180{
1181 int sync_dev;
1182
f3e2f1dd
GI		 1183 if (data->flags & MMC_DATA_WRITE)
1184 sync_dev = host->dma_line_tx;
1185 else
1186 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1187 return sync_dev;
1188}
1189
70a3341a 1190static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1191 struct mmc_data *data,
1192 struct scatterlist *sgl)
1193{
1194 int blksz, nblk, dma_ch;
1195
1196 dma_ch = host->dma_ch;
1197 if (data->flags & MMC_DATA_WRITE) {
1198 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1199 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1200 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1201 sg_dma_address(sgl), 0, 0);
1202 } else {
1203 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1204 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1205 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1206 sg_dma_address(sgl), 0, 0);
1207 }
1208
1209 blksz = host->data->blksz;
1210 nblk = sg_dma_len(sgl) / blksz;
1211
1212 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1213 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1214 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1215 !(data->flags & MMC_DATA_WRITE));
1216
1217 omap_start_dma(dma_ch);
1218}
1219
a45c6cb8
MC		 1220/*
1221 * DMA call back function
1222 */
b417577d 1223static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1224{
b417577d 1225 struct omap_hsmmc_host *host = cb_data;
770d7432 1226 struct mmc_data *data;
b417577d 1227 int dma_ch, req_in_progress;
a45c6cb8 1228
f3584e5e
V		 1229 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1230 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1231 ch_status);
1232 return;
1233 }
a45c6cb8 1234
b417577d
AH		 1235 spin_lock(&host->irq_lock);
1236 if (host->dma_ch < 0) {
1237 spin_unlock(&host->irq_lock);
a45c6cb8 1238 return;
b417577d 1239 }
a45c6cb8 1240
770d7432 1241 data = host->mrq->data;
0ccd76d4
JY		 1242 host->dma_sg_idx++;
1243 if (host->dma_sg_idx < host->dma_len) {
1244 /* Fire up the next transfer. */
b417577d
AH		 1245 omap_hsmmc_config_dma_params(host, data,
1246 data->sg + host->dma_sg_idx);
1247 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1248 return;
1249 }
1250
9782aff8
PF		 1251 if (!data->host_cookie)
1252 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1253 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1254
1255 req_in_progress = host->req_in_progress;
1256 dma_ch = host->dma_ch;
a45c6cb8 1257 host->dma_ch = -1;
b417577d
AH		 1258 spin_unlock(&host->irq_lock);
1259
1260 omap_free_dma(dma_ch);
1261
1262 /* If DMA has finished after TC, complete the request */
1263 if (!req_in_progress) {
1264 struct mmc_request *mrq = host->mrq;
1265
1266 host->mrq = NULL;
1267 mmc_request_done(host->mmc, mrq);
1268 }
a45c6cb8
MC		 1269}
1270
9782aff8
PF		 1271static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1272 struct mmc_data *data,
1273 struct omap_hsmmc_next *next)
1274{
1275 int dma_len;
1276
1277 if (!next && data->host_cookie &&
1278 data->host_cookie != host->next_data.cookie) {
a3c76eb9 1279 pr_warning("[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1280 " host->next_data.cookie %d\n",
1281 __func__, data->host_cookie, host->next_data.cookie);
1282 data->host_cookie = 0;
1283 }
1284
1285 /* Check if next job is already prepared */
1286 if (next ||
1287 (!next && data->host_cookie != host->next_data.cookie)) {
1288 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1289 data->sg_len,
1290 omap_hsmmc_get_dma_dir(host, data));
1291
1292 } else {
1293 dma_len = host->next_data.dma_len;
1294 host->next_data.dma_len = 0;
1295 }
1296
1297
1298 if (dma_len == 0)
1299 return -EINVAL;
1300
1301 if (next) {
1302 next->dma_len = dma_len;
1303 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1304 } else
1305 host->dma_len = dma_len;
1306
1307 return 0;
1308}
1309
a45c6cb8
MC		 1310/*
1311 * Routine to configure and start DMA for the MMC card
1312 */
70a3341a
DK		 1313static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1314 struct mmc_request *req)
a45c6cb8 1315{
b417577d 1316 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1317 struct mmc_data *data = req->data;
1318
0ccd76d4 1319 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1320 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1321 struct scatterlist *sgl;
1322
1323 sgl = data->sg + i;
1324 if (sgl->length % data->blksz)
1325 return -EINVAL;
1326 }
1327 if ((data->blksz % 4) != 0)
1328 /* REVISIT: The MMC buffer increments only when MSB is written.
1329 * Return error for blksz which is non multiple of four.
1330 */
1331 return -EINVAL;
1332
b417577d 1333 BUG_ON(host->dma_ch != -1);
a45c6cb8 1334
70a3341a
DK		 1335 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1336 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1337 if (ret != 0) {
0ccd76d4 1338 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1339 "%s: omap_request_dma() failed with %d\n",
1340 mmc_hostname(host->mmc), ret);
1341 return ret;
1342 }
9782aff8
PF		 1343 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1344 if (ret)
1345 return ret;
a45c6cb8 1346
a45c6cb8 1347 host->dma_ch = dma_ch;
0ccd76d4 1348 host->dma_sg_idx = 0;
a45c6cb8 1349
70a3341a 1350 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1351
a45c6cb8
MC		 1352 return 0;
1353}
1354
70a3341a 1355static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1356 unsigned int timeout_ns,
1357 unsigned int timeout_clks)
a45c6cb8
MC		 1358{
1359 unsigned int timeout, cycle_ns;
1360 uint32_t reg, clkd, dto = 0;
1361
1362 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1363 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1364 if (clkd == 0)
1365 clkd = 1;
1366
1367 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1368 timeout = timeout_ns / cycle_ns;
1369 timeout += timeout_clks;
a45c6cb8
MC		 1370 if (timeout) {
1371 while ((timeout & 0x80000000) == 0) {
1372 dto += 1;
1373 timeout <<= 1;
1374 }
1375 dto = 31 - dto;
1376 timeout <<= 1;
1377 if (timeout && dto)
1378 dto += 1;
1379 if (dto >= 13)
1380 dto -= 13;
1381 else
1382 dto = 0;
1383 if (dto > 14)
1384 dto = 14;
1385 }
1386
1387 reg &= ~DTO_MASK;
1388 reg |= dto << DTO_SHIFT;
1389 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1390}
1391
1392/*
1393 * Configure block length for MMC/SD cards and initiate the transfer.
1394 */
1395static int
70a3341a 1396omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1397{
1398 int ret;
1399 host->data = req->data;
1400
1401 if (req->data == NULL) {
a45c6cb8 1402 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1403 /*
1404 * Set an arbitrary 100ms data timeout for commands with
1405 * busy signal.
1406 */
1407 if (req->cmd->flags & MMC_RSP_BUSY)
1408 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1409 return 0;
1410 }
1411
1412 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1413 | (req->data->blocks << 16));
e2bf08d6 1414 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1415
a45c6cb8 1416 if (host->use_dma) {
70a3341a 1417 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1418 if (ret != 0) {
1419 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1420 return ret;
1421 }
1422 }
1423 return 0;
1424}
1425
9782aff8
PF		 1426static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1427 int err)
1428{
1429 struct omap_hsmmc_host *host = mmc_priv(mmc);
1430 struct mmc_data *data = mrq->data;
1431
1432 if (host->use_dma) {
053bf34f
PF		 1433 if (data->host_cookie)
1434 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1435 data->sg_len,
1436 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1437 data->host_cookie = 0;
1438 }
1439}
1440
1441static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1442 bool is_first_req)
1443{
1444 struct omap_hsmmc_host *host = mmc_priv(mmc);
1445
1446 if (mrq->data->host_cookie) {
1447 mrq->data->host_cookie = 0;
1448 return ;
1449 }
1450
1451 if (host->use_dma)
1452 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1453 &host->next_data))
1454 mrq->data->host_cookie = 0;
1455}
1456
a45c6cb8
MC		 1457/*
1458 * Request function. for read/write operation
1459 */
70a3341a 1460static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1461{
70a3341a 1462 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1463 int err;
a45c6cb8 1464
b417577d
AH		 1465 BUG_ON(host->req_in_progress);
1466 BUG_ON(host->dma_ch != -1);
1467 if (host->protect_card) {
1468 if (host->reqs_blocked < 3) {
1469 /*
1470 * Ensure the controller is left in a consistent
1471 * state by resetting the command and data state
1472 * machines.
1473 */
1474 omap_hsmmc_reset_controller_fsm(host, SRD);
1475 omap_hsmmc_reset_controller_fsm(host, SRC);
1476 host->reqs_blocked += 1;
1477 }
1478 req->cmd->error = -EBADF;
1479 if (req->data)
1480 req->data->error = -EBADF;
1481 req->cmd->retries = 0;
1482 mmc_request_done(mmc, req);
1483 return;
1484 } else if (host->reqs_blocked)
1485 host->reqs_blocked = 0;
a45c6cb8
MC		 1486 WARN_ON(host->mrq != NULL);
1487 host->mrq = req;
70a3341a 1488 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1489 if (err) {
1490 req->cmd->error = err;
1491 if (req->data)
1492 req->data->error = err;
1493 host->mrq = NULL;
1494 mmc_request_done(mmc, req);
1495 return;
1496 }
1497
70a3341a 1498 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1499}
1500
a45c6cb8 1501/* Routine to configure clock values. Exposed API to core */
70a3341a 1502static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1503{
70a3341a 1504 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1505 int do_send_init_stream = 0;
a45c6cb8 1506
fa4aa2d4 1507 pm_runtime_get_sync(host->dev);
5e2ea617 1508
a3621465
AH		 1509 if (ios->power_mode != host->power_mode) {
1510 switch (ios->power_mode) {
1511 case MMC_POWER_OFF:
1512 mmc_slot(host).set_power(host->dev, host->slot_id,
1513 0, 0);
623821f7 1514 host->vdd = 0;
a3621465
AH		 1515 break;
1516 case MMC_POWER_UP:
1517 mmc_slot(host).set_power(host->dev, host->slot_id,
1518 1, ios->vdd);
623821f7 1519 host->vdd = ios->vdd;
a3621465
AH		 1520 break;
1521 case MMC_POWER_ON:
1522 do_send_init_stream = 1;
1523 break;
1524 }
1525 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1526 }
1527
dd498eff
DK		 1528 /* FIXME: set registers based only on changes to ios */
1529
3796fb8a 1530 omap_hsmmc_set_bus_width(host);
a45c6cb8 1531
4621d5f8 1532 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1533 /* Only MMC1 can interface at 3V without some flavor
1534 * of external transceiver; but they all handle 1.8V.
1535 */
a45c6cb8
MC		 1536 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1537 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1538 /*
1539 * The mmc_select_voltage fn of the core does
1540 * not seem to set the power_mode to
1541 * MMC_POWER_UP upon recalculating the voltage.
1542 * vdd 1.8v.
1543 */
70a3341a
DK		 1544 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1545 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1546 "Switch operation failed\n");
1547 }
1548 }
1549
5934df2f 1550 omap_hsmmc_set_clock(host);
a45c6cb8 1551
a3621465 1552 if (do_send_init_stream)
a45c6cb8
MC		 1553 send_init_stream(host);
1554
3796fb8a 1555 omap_hsmmc_set_bus_mode(host);
5e2ea617 1556
fa4aa2d4 1557 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1558}
1559
1560static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1561{
70a3341a 1562 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1563
191d1f1d 1564 if (!mmc_slot(host).card_detect)
a45c6cb8 1565 return -ENOSYS;
db0fefc5 1566 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1567}
1568
1569static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1570{
70a3341a 1571 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1572
191d1f1d 1573 if (!mmc_slot(host).get_ro)
a45c6cb8 1574 return -ENOSYS;
191d1f1d 1575 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1576}
1577
4816858c
GI		 1578static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1579{
1580 struct omap_hsmmc_host *host = mmc_priv(mmc);
1581
1582 if (mmc_slot(host).init_card)
1583 mmc_slot(host).init_card(card);
1584}
1585
70a3341a 1586static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1587{
1588 u32 hctl, capa, value;
1589
1590 /* Only MMC1 supports 3.0V */
4621d5f8 1591 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1592 hctl = SDVS30;
1593 capa = VS30 | VS18;
1594 } else {
1595 hctl = SDVS18;
1596 capa = VS18;
1597 }
1598
1599 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1600 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1601
1602 value = OMAP_HSMMC_READ(host->base, CAPA);
1603 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1604
1605 /* Set the controller to AUTO IDLE mode */
1606 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1607 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1608
1609 /* Set SD bus power bit */
e13bb300 1610 set_sd_bus_power(host);
1b331e69
KK		 1611}
1612
70a3341a 1613static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1614{
70a3341a 1615 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1616
fa4aa2d4
B		 1617 pm_runtime_get_sync(host->dev);
1618
dd498eff
DK		 1619 return 0;
1620}
1621
70a3341a 1622static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1623{
70a3341a 1624 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1625
fa4aa2d4
B		 1626 pm_runtime_mark_last_busy(host->dev);
1627 pm_runtime_put_autosuspend(host->dev);
1628
dd498eff
DK		 1629 return 0;
1630}
1631
70a3341a
DK		 1632static const struct mmc_host_ops omap_hsmmc_ops = {
1633 .enable = omap_hsmmc_enable_fclk,
1634 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1635 .post_req = omap_hsmmc_post_req,
1636 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1637 .request = omap_hsmmc_request,
1638 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1639 .get_cd = omap_hsmmc_get_cd,
1640 .get_ro = omap_hsmmc_get_ro,
4816858c 1641 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1642 /* NYET -- enable_sdio_irq */
1643};
1644
d900f712
DK		 1645#ifdef CONFIG_DEBUG_FS
1646
70a3341a 1647static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1648{
1649 struct mmc_host *mmc = s->private;
70a3341a 1650 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1651 int context_loss = 0;
1652
70a3341a
DK		 1653 if (host->pdata->get_context_loss_count)
1654 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1655
5e2ea617
AH		 1656 seq_printf(s, "mmc%d:\n"
1657 " enabled:\t%d\n"
dd498eff 1658 " dpm_state:\t%d\n"
5e2ea617 1659 " nesting_cnt:\t%d\n"
11dd62a7 1660 " ctx_loss:\t%d:%d\n"
5e2ea617 1661 "\nregs:\n",
dd498eff
DK		 1662 mmc->index, mmc->enabled ? 1 : 0,
1663 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1664 host->context_loss, context_loss);
5e2ea617 1665
7a8c2cef 1666 if (host->suspended) {
dd498eff
DK		 1667 seq_printf(s, "host suspended, can't read registers\n");
1668 return 0;
1669 }
1670
fa4aa2d4 1671 pm_runtime_get_sync(host->dev);
d900f712
DK		 1672
1673 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1674 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1675 seq_printf(s, "CON:\t\t0x%08x\n",
1676 OMAP_HSMMC_READ(host->base, CON));
1677 seq_printf(s, "HCTL:\t\t0x%08x\n",
1678 OMAP_HSMMC_READ(host->base, HCTL));
1679 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1680 OMAP_HSMMC_READ(host->base, SYSCTL));
1681 seq_printf(s, "IE:\t\t0x%08x\n",
1682 OMAP_HSMMC_READ(host->base, IE));
1683 seq_printf(s, "ISE:\t\t0x%08x\n",
1684 OMAP_HSMMC_READ(host->base, ISE));
1685 seq_printf(s, "CAPA:\t\t0x%08x\n",
1686 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1687
fa4aa2d4
B		 1688 pm_runtime_mark_last_busy(host->dev);
1689 pm_runtime_put_autosuspend(host->dev);
dd498eff 1690
d900f712
DK		 1691 return 0;
1692}
1693
70a3341a 1694static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1695{
70a3341a 1696 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1697}
1698
1699static const struct file_operations mmc_regs_fops = {
70a3341a 1700 .open = omap_hsmmc_regs_open,
d900f712
DK		 1701 .read = seq_read,
1702 .llseek = seq_lseek,
1703 .release = single_release,
1704};
1705
70a3341a 1706static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1707{
1708 if (mmc->debugfs_root)
1709 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1710 mmc, &mmc_regs_fops);
1711}
1712
1713#else
1714
70a3341a 1715static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1716{
1717}
1718
1719#endif
1720
70a3341a 1721static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1722{
1723 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1724 struct mmc_host *mmc;
70a3341a 1725 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1726 struct resource *res;
db0fefc5 1727 int ret, irq;
a45c6cb8
MC		 1728
1729 if (pdata == NULL) {
1730 dev_err(&pdev->dev, "Platform Data is missing\n");
1731 return -ENXIO;
1732 }
1733
1734 if (pdata->nr_slots == 0) {
1735 dev_err(&pdev->dev, "No Slots\n");
1736 return -ENXIO;
1737 }
1738
1739 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1740 irq = platform_get_irq(pdev, 0);
1741 if (res == NULL || irq < 0)
1742 return -ENXIO;
1743
91a0b089 1744 res->start += pdata->reg_offset;
1745 res->end += pdata->reg_offset;
984b203a 1746 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1747 if (res == NULL)
1748 return -EBUSY;
1749
db0fefc5
AH		 1750 ret = omap_hsmmc_gpio_init(pdata);
1751 if (ret)
1752 goto err;
1753
70a3341a 1754 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1755 if (!mmc) {
1756 ret = -ENOMEM;
db0fefc5 1757 goto err_alloc;
a45c6cb8
MC		 1758 }
1759
1760 host = mmc_priv(mmc);
1761 host->mmc = mmc;
1762 host->pdata = pdata;
1763 host->dev = &pdev->dev;
1764 host->use_dma = 1;
1765 host->dev->dma_mask = &pdata->dma_mask;
1766 host->dma_ch = -1;
1767 host->irq = irq;
a45c6cb8
MC		 1768 host->slot_id = 0;
1769 host->mapbase = res->start;
1770 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1771 host->power_mode = MMC_POWER_OFF;
9782aff8 1772 host->next_data.cookie = 1;
a45c6cb8
MC		 1773
1774 platform_set_drvdata(pdev, host);
a45c6cb8 1775
7a8c2cef 1776 mmc->ops = &omap_hsmmc_ops;
dd498eff 1777
e0eb2424
AH		 1778 /*
1779 * If regulator_disable can only put vcc_aux to sleep then there is
1780 * no off state.
1781 */
1782 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1783 mmc_slot(host).no_off = 1;
1784
d418ed87
DM		 1785 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1786
1787 if (pdata->max_freq > 0)
1788 mmc->f_max = pdata->max_freq;
1789 else
1790 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1791
4dffd7a2 1792 spin_lock_init(&host->irq_lock);
a45c6cb8 1793
6f7607cc 1794 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1795 if (IS_ERR(host->fclk)) {
1796 ret = PTR_ERR(host->fclk);
1797 host->fclk = NULL;
a45c6cb8
MC		 1798 goto err1;
1799 }
1800
70a3341a 1801 omap_hsmmc_context_save(host);
11dd62a7 1802
5e2ea617 1803 mmc->caps |= MMC_CAP_DISABLE;
9b68256c
PW		 1804 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1805 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1806 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1807 }
dd498eff 1808
fa4aa2d4
B		 1809 pm_runtime_enable(host->dev);
1810 pm_runtime_get_sync(host->dev);
1811 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1812 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1813
2bec0893
AH		 1814 if (cpu_is_omap2430()) {
1815 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1816 /*
1817 * MMC can still work without debounce clock.
1818 */
1819 if (IS_ERR(host->dbclk))
1820 dev_warn(mmc_dev(host->mmc),
1821 "Failed to get debounce clock\n");
a45c6cb8 1822 else
2bec0893
AH		 1823 host->got_dbclk = 1;
1824
1825 if (host->got_dbclk)
1826 if (clk_enable(host->dbclk) != 0)
1827 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1828 " clk failed\n");
1829 }
a45c6cb8 1830
0ccd76d4
JY		 1831 /* Since we do only SG emulation, we can have as many segs
1832 * as we want. */
a36274e0 1833 mmc->max_segs = 1024;
0ccd76d4 1834
a45c6cb8
MC		 1835 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1836 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1837 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1838 mmc->max_seg_size = mmc->max_req_size;
1839
13189e78 1840 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1841 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1842
3a63833e
SG		 1843 mmc->caps |= mmc_slot(host).caps;
1844 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1845 mmc->caps |= MMC_CAP_4_BIT_DATA;
1846
191d1f1d 1847 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1848 mmc->caps |= MMC_CAP_NONREMOVABLE;
1849
6fdc75de
EP		 1850 mmc->pm_caps = mmc_slot(host).pm_caps;
1851
70a3341a 1852 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1853
b7bf773b
B		 1854 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1855 if (!res) {
1856 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1857 goto err_irq;
1858 }
1859 host->dma_line_tx = res->start;
1860
1861 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1862 if (!res) {
1863 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
f3e2f1dd
GI		 1864 goto err_irq;
1865 }
b7bf773b 1866 host->dma_line_rx = res->start;
a45c6cb8
MC		 1867
1868 /* Request IRQ for MMC operations */
d9618e9f 1869 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1870 mmc_hostname(mmc), host);
1871 if (ret) {
1872 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1873 goto err_irq;
1874 }
1875
1876 if (pdata->init != NULL) {
1877 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 1878 dev_dbg(mmc_dev(host->mmc),
1879 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1880 goto err_irq_cd_init;
1881 }
1882 }
db0fefc5 1883
b702b106 1884 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1885 ret = omap_hsmmc_reg_get(host);
1886 if (ret)
1887 goto err_reg;
1888 host->use_reg = 1;
1889 }
1890
b583f26d 1891 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1892
1893 /* Request IRQ for card detect */
e1a55f5e 1894 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1895 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1896 NULL,
1897 omap_hsmmc_detect,
1898 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1899 mmc_hostname(mmc), host);
a45c6cb8
MC		 1900 if (ret) {
1901 dev_dbg(mmc_dev(host->mmc),
1902 "Unable to grab MMC CD IRQ\n");
1903 goto err_irq_cd;
1904 }
72f2e2c7 1905 pdata->suspend = omap_hsmmc_suspend_cdirq;
1906 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 1907 }
1908
b417577d 1909 omap_hsmmc_disable_irq(host);
a45c6cb8 1910
b62f6228
AH		 1911 omap_hsmmc_protect_card(host);
1912
a45c6cb8
MC		 1913 mmc_add_host(mmc);
1914
191d1f1d 1915 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 1916 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1917 if (ret < 0)
1918 goto err_slot_name;
1919 }
191d1f1d 1920 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 1921 ret = device_create_file(&mmc->class_dev,
1922 &dev_attr_cover_switch);
1923 if (ret < 0)
db0fefc5 1924 goto err_slot_name;
a45c6cb8
MC		 1925 }
1926
70a3341a 1927 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 1928 pm_runtime_mark_last_busy(host->dev);
1929 pm_runtime_put_autosuspend(host->dev);
d900f712 1930
a45c6cb8
MC		 1931 return 0;
1932
a45c6cb8
MC		 1933err_slot_name:
1934 mmc_remove_host(mmc);
a45c6cb8 1935 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 1936err_irq_cd:
1937 if (host->use_reg)
1938 omap_hsmmc_reg_put(host);
1939err_reg:
1940 if (host->pdata->cleanup)
1941 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 1942err_irq_cd_init:
1943 free_irq(host->irq, host);
1944err_irq:
fa4aa2d4
B		 1945 pm_runtime_mark_last_busy(host->dev);
1946 pm_runtime_put_autosuspend(host->dev);
a45c6cb8 1947 clk_put(host->fclk);
2bec0893 1948 if (host->got_dbclk) {
a45c6cb8
MC		 1949 clk_disable(host->dbclk);
1950 clk_put(host->dbclk);
1951 }
a45c6cb8
MC		 1952err1:
1953 iounmap(host->base);
db0fefc5
AH		 1954 platform_set_drvdata(pdev, NULL);
1955 mmc_free_host(mmc);
1956err_alloc:
1957 omap_hsmmc_gpio_free(pdata);
a45c6cb8 1958err:
984b203a 1959 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 1960 return ret;
1961}
1962
70a3341a 1963static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 1964{
70a3341a 1965 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 1966 struct resource *res;
1967
1968 if (host) {
fa4aa2d4 1969 pm_runtime_get_sync(host->dev);
a45c6cb8 1970 mmc_remove_host(host->mmc);
db0fefc5
AH		 1971 if (host->use_reg)
1972 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 1973 if (host->pdata->cleanup)
1974 host->pdata->cleanup(&pdev->dev);
1975 free_irq(host->irq, host);
1976 if (mmc_slot(host).card_detect_irq)
1977 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 1978
fa4aa2d4
B		 1979 pm_runtime_put_sync(host->dev);
1980 pm_runtime_disable(host->dev);
a45c6cb8 1981 clk_put(host->fclk);
2bec0893 1982 if (host->got_dbclk) {
a45c6cb8
MC		 1983 clk_disable(host->dbclk);
1984 clk_put(host->dbclk);
1985 }
1986
1987 mmc_free_host(host->mmc);
1988 iounmap(host->base);
db0fefc5 1989 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 1990 }
1991
1992 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1993 if (res)
984b203a 1994 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 1995 platform_set_drvdata(pdev, NULL);
1996
1997 return 0;
1998}
1999
2000#ifdef CONFIG_PM
a791daa1 2001static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2002{
2003 int ret = 0;
a791daa1 2004 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2005 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2006
2007 if (host && host->suspended)
2008 return 0;
2009
2010 if (host) {
fa4aa2d4 2011 pm_runtime_get_sync(host->dev);
a6b2240d
AH		 2012 host->suspended = 1;
2013 if (host->pdata->suspend) {
2014 ret = host->pdata->suspend(&pdev->dev,
2015 host->slot_id);
2016 if (ret) {
2017 dev_dbg(mmc_dev(host->mmc),
2018 "Unable to handle MMC board"
2019 " level suspend\n");
2020 host->suspended = 0;
2021 return ret;
2022 }
2023 }
1a13f8fa 2024 ret = mmc_suspend_host(host->mmc);
fa4aa2d4 2025
31f9d463 2026 if (ret) {
a6b2240d
AH		 2027 host->suspended = 0;
2028 if (host->pdata->resume) {
2029 ret = host->pdata->resume(&pdev->dev,
2030 host->slot_id);
2031 if (ret)
2032 dev_dbg(mmc_dev(host->mmc),
2033 "Unmask interrupt failed\n");
2034 }
31f9d463 2035 goto err;
a6b2240d 2036 }
31f9d463
EP		 2037
2038 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2039 omap_hsmmc_disable_irq(host);
2040 OMAP_HSMMC_WRITE(host->base, HCTL,
2041 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2042 }
2043 if (host->got_dbclk)
2044 clk_disable(host->dbclk);
2045
a45c6cb8 2046 }
31f9d463
EP		 2047err:
2048 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2049 return ret;
2050}
2051
2052/* Routine to resume the MMC device */
a791daa1 2053static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2054{
2055 int ret = 0;
a791daa1 2056 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2057 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2058
2059 if (host && !host->suspended)
2060 return 0;
2061
2062 if (host) {
fa4aa2d4 2063 pm_runtime_get_sync(host->dev);
11dd62a7 2064
2bec0893
AH		 2065 if (host->got_dbclk)
2066 clk_enable(host->dbclk);
2067
31f9d463
EP		 2068 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2069 omap_hsmmc_conf_bus_power(host);
1b331e69 2070
a45c6cb8
MC		 2071 if (host->pdata->resume) {
2072 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2073 if (ret)
2074 dev_dbg(mmc_dev(host->mmc),
2075 "Unmask interrupt failed\n");
2076 }
2077
b62f6228
AH		 2078 omap_hsmmc_protect_card(host);
2079
a45c6cb8
MC		 2080 /* Notify the core to resume the host */
2081 ret = mmc_resume_host(host->mmc);
2082 if (ret == 0)
2083 host->suspended = 0;
fa4aa2d4
B		 2084
2085 pm_runtime_mark_last_busy(host->dev);
2086 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2087 }
2088
2089 return ret;
2090
a45c6cb8
MC		 2091}
2092
2093#else
70a3341a
DK		 2094#define omap_hsmmc_suspend NULL
2095#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2096#endif
2097
fa4aa2d4
B		 2098static int omap_hsmmc_runtime_suspend(struct device *dev)
2099{
2100 struct omap_hsmmc_host *host;
2101
2102 host = platform_get_drvdata(to_platform_device(dev));
2103 omap_hsmmc_context_save(host);
2104 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2105
2106 return 0;
2107}
2108
2109static int omap_hsmmc_runtime_resume(struct device *dev)
2110{
2111 struct omap_hsmmc_host *host;
2112
2113 host = platform_get_drvdata(to_platform_device(dev));
2114 omap_hsmmc_context_restore(host);
2115 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2116
2117 return 0;
2118}
2119
a791daa1 2120static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2121 .suspend = omap_hsmmc_suspend,
2122 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2123 .runtime_suspend = omap_hsmmc_runtime_suspend,
2124 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2125};
2126
2127static struct platform_driver omap_hsmmc_driver = {
2128 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2129 .driver = {
2130 .name = DRIVER_NAME,
2131 .owner = THIS_MODULE,
a791daa1 2132 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2133 },
2134};
2135
70a3341a 2136static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2137{
2138 /* Register the MMC driver */
8753298a 2139 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2140}
2141
70a3341a 2142static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2143{
2144 /* Unregister MMC driver */
70a3341a 2145 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2146}
2147
70a3341a
DK		 2148module_init(omap_hsmmc_init);
2149module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2150
2151MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2152MODULE_LICENSE("GPL");
2153MODULE_ALIAS("platform:" DRIVER_NAME);
2154MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)