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mmc: omap_hsmmc: remove pbias workaround
[linux-2.6-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712 21#include <linux/debugfs.h>
c5c98927 22#include <linux/dmaengine.h>
d900f712 23#include <linux/seq_file.h>
031cd037 24#include <linux/sizes.h>
a45c6cb8
MC		 25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
a45c6cb8
MC		 29#include <linux/timer.h>
30#include <linux/clk.h>
46856a68
RN		 31#include <linux/of.h>
32#include <linux/of_gpio.h>
33#include <linux/of_device.h>
3451c067 34#include <linux/omap-dma.h>
a45c6cb8 35#include <linux/mmc/host.h>
13189e78 36#include <linux/mmc/core.h>
93caf8e6 37#include <linux/mmc/mmc.h>
a45c6cb8 38#include <linux/io.h>
db0fefc5
AH		 39#include <linux/gpio.h>
40#include <linux/regulator/consumer.h>
46b76035 41#include <linux/pinctrl/consumer.h>
fa4aa2d4 42#include <linux/pm_runtime.h>
68f39e74 43#include <linux/platform_data/mmc-omap.h>
a45c6cb8
MC		 44
45/* OMAP HSMMC Host Controller Registers */
11dd62a7 46#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 47#define OMAP_HSMMC_CON 0x002C
48#define OMAP_HSMMC_BLK 0x0104
49#define OMAP_HSMMC_ARG 0x0108
50#define OMAP_HSMMC_CMD 0x010C
51#define OMAP_HSMMC_RSP10 0x0110
52#define OMAP_HSMMC_RSP32 0x0114
53#define OMAP_HSMMC_RSP54 0x0118
54#define OMAP_HSMMC_RSP76 0x011C
55#define OMAP_HSMMC_DATA 0x0120
56#define OMAP_HSMMC_HCTL 0x0128
57#define OMAP_HSMMC_SYSCTL 0x012C
58#define OMAP_HSMMC_STAT 0x0130
59#define OMAP_HSMMC_IE 0x0134
60#define OMAP_HSMMC_ISE 0x0138
61#define OMAP_HSMMC_CAPA 0x0140
62
63#define VS18 (1 << 26)
64#define VS30 (1 << 25)
cd587096 65#define HSS (1 << 21)
a45c6cb8
MC		 66#define SDVS18 (0x5 << 9)
67#define SDVS30 (0x6 << 9)
eb250826 68#define SDVS33 (0x7 << 9)
1b331e69 69#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 70#define SDVSCLR 0xFFFFF1FF
71#define SDVSDET 0x00000400
72#define AUTOIDLE 0x1
73#define SDBP (1 << 8)
74#define DTO 0xe
75#define ICE 0x1
76#define ICS 0x2
77#define CEN (1 << 2)
ed164182 78#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
a45c6cb8
MC		 79#define CLKD_MASK 0x0000FFC0
80#define CLKD_SHIFT 6
81#define DTO_MASK 0x000F0000
82#define DTO_SHIFT 16
a45c6cb8
MC		 83#define INIT_STREAM (1 << 1)
84#define DP_SELECT (1 << 21)
85#define DDIR (1 << 4)
a7e96879 86#define DMAE 0x1
a45c6cb8
MC		 87#define MSBS (1 << 5)
88#define BCE (1 << 1)
89#define FOUR_BIT (1 << 1)
cd587096 90#define HSPE (1 << 2)
03b5d924 91#define DDR (1 << 19)
73153010 92#define DW8 (1 << 5)
a45c6cb8 93#define OD 0x1
a45c6cb8
MC		 94#define STAT_CLEAR 0xFFFFFFFF
95#define INIT_STREAM_CMD 0x00000000
96#define DUAL_VOLT_OCR_BIT 7
97#define SRC (1 << 25)
98#define SRD (1 << 26)
11dd62a7
DK		 99#define SOFTRESET (1 << 1)
100#define RESETDONE (1 << 0)
a45c6cb8 101
a7e96879
V		 102/* Interrupt masks for IE and ISE register */
103#define CC_EN (1 << 0)
104#define TC_EN (1 << 1)
105#define BWR_EN (1 << 4)
106#define BRR_EN (1 << 5)
107#define ERR_EN (1 << 15)
108#define CTO_EN (1 << 16)
109#define CCRC_EN (1 << 17)
110#define CEB_EN (1 << 18)
111#define CIE_EN (1 << 19)
112#define DTO_EN (1 << 20)
113#define DCRC_EN (1 << 21)
114#define DEB_EN (1 << 22)
115#define CERR_EN (1 << 28)
116#define BADA_EN (1 << 29)
117
118#define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
119 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
120 BRR_EN | BWR_EN | TC_EN | CC_EN)
121
fa4aa2d4 122#define MMC_AUTOSUSPEND_DELAY 100
1e881786
JM		 123#define MMC_TIMEOUT_MS 20 /* 20 mSec */
124#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
6b206efe
AS		 125#define OMAP_MMC_MIN_CLOCK 400000
126#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 127#define DRIVER_NAME "omap_hsmmc"
a45c6cb8 128
e99448ff
B		 129#define VDD_1V8 1800000 /* 180000 uV */
130#define VDD_3V0 3000000 /* 300000 uV */
131#define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
132
a45c6cb8
MC		 133/*
134 * One controller can have multiple slots, like on some omap boards using
135 * omap.c controller driver. Luckily this is not currently done on any known
136 * omap_hsmmc.c device.
137 */
138#define mmc_slot(host) (host->pdata->slots[host->slot_id])
139
140/*
141 * MMC Host controller read/write API's
142 */
143#define OMAP_HSMMC_READ(base, reg) \
144 __raw_readl((base) + OMAP_HSMMC_##reg)
145
146#define OMAP_HSMMC_WRITE(base, reg, val) \
147 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
148
9782aff8
PF		 149struct omap_hsmmc_next {
150 unsigned int dma_len;
151 s32 cookie;
152};
153
70a3341a 154struct omap_hsmmc_host {
a45c6cb8
MC		 155 struct device *dev;
156 struct mmc_host *mmc;
157 struct mmc_request *mrq;
158 struct mmc_command *cmd;
159 struct mmc_data *data;
160 struct clk *fclk;
a45c6cb8 161 struct clk *dbclk;
db0fefc5
AH		 162 /*
163 * vcc == configured supply
164 * vcc_aux == optional
165 * - MMC1, supply for DAT4..DAT7
166 * - MMC2/MMC2, external level shifter voltage supply, for
167 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
168 */
169 struct regulator *vcc;
170 struct regulator *vcc_aux;
e99448ff
B		 171 struct regulator *pbias;
172 bool pbias_enabled;
a45c6cb8
MC		 173 void __iomem *base;
174 resource_size_t mapbase;
4dffd7a2 175 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 176 unsigned int dma_len;
0ccd76d4 177 unsigned int dma_sg_idx;
a45c6cb8 178 unsigned char bus_mode;
a3621465 179 unsigned char power_mode;
a45c6cb8 180 int suspended;
0a82e06e
TL		 181 u32 con;
182 u32 hctl;
183 u32 sysctl;
184 u32 capa;
a45c6cb8 185 int irq;
a45c6cb8 186 int use_dma, dma_ch;
c5c98927
RK		 187 struct dma_chan *tx_chan;
188 struct dma_chan *rx_chan;
a45c6cb8 189 int slot_id;
4a694dc9 190 int response_busy;
11dd62a7 191 int context_loss;
b62f6228
AH		 192 int protect_card;
193 int reqs_blocked;
db0fefc5 194 int use_reg;
b417577d 195 int req_in_progress;
9782aff8 196 struct omap_hsmmc_next next_data;
a45c6cb8
MC		 197 struct omap_mmc_platform_data *pdata;
198};
199
59445b10
NM		 200struct omap_mmc_of_data {
201 u32 reg_offset;
202 u8 controller_flags;
203};
204
db0fefc5
AH		 205static int omap_hsmmc_card_detect(struct device *dev, int slot)
206{
9ea28ecb
B		 207 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
208 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 209
210 /* NOTE: assumes card detect signal is active-low */
211 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
212}
213
214static int omap_hsmmc_get_wp(struct device *dev, int slot)
215{
9ea28ecb
B		 216 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
217 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 218
219 /* NOTE: assumes write protect signal is active-high */
220 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
221}
222
223static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
224{
9ea28ecb
B		 225 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
226 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 227
228 /* NOTE: assumes card detect signal is active-low */
229 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
230}
231
232#ifdef CONFIG_PM
233
234static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
235{
9ea28ecb
B		 236 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
237 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 238
239 disable_irq(mmc->slots[0].card_detect_irq);
240 return 0;
241}
242
243static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
244{
9ea28ecb
B		 245 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
246 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 247
248 enable_irq(mmc->slots[0].card_detect_irq);
249 return 0;
250}
251
252#else
253
254#define omap_hsmmc_suspend_cdirq NULL
255#define omap_hsmmc_resume_cdirq NULL
256
257#endif
258
b702b106
AH		 259#ifdef CONFIG_REGULATOR
260
69b07ece 261static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 262 int vdd)
263{
264 struct omap_hsmmc_host *host =
265 platform_get_drvdata(to_platform_device(dev));
266 int ret = 0;
267
268 /*
269 * If we don't see a Vcc regulator, assume it's a fixed
270 * voltage always-on regulator.
271 */
272 if (!host->vcc)
273 return 0;
274
275 if (mmc_slot(host).before_set_reg)
276 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
277
e99448ff
B		 278 if (host->pbias) {
279 if (host->pbias_enabled == 1) {
280 ret = regulator_disable(host->pbias);
281 if (!ret)
282 host->pbias_enabled = 0;
283 }
284 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
285 }
286
db0fefc5
AH		 287 /*
288 * Assume Vcc regulator is used only to power the card ... OMAP
289 * VDDS is used to power the pins, optionally with a transceiver to
290 * support cards using voltages other than VDDS (1.8V nominal). When a
291 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
292 *
293 * In some cases this regulator won't support enable/disable;
294 * e.g. it's a fixed rail for a WLAN chip.
295 *
296 * In other cases vcc_aux switches interface power. Example, for
297 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
298 * chips/cards need an interface voltage rail too.
299 */
300 if (power_on) {
987fd49b
B		 301 if (host->vcc)
302 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 303 /* Enable interface voltage rail, if needed */
304 if (ret == 0 && host->vcc_aux) {
305 ret = regulator_enable(host->vcc_aux);
987fd49b 306 if (ret < 0 && host->vcc)
99fc5131
LW		 307 ret = mmc_regulator_set_ocr(host->mmc,
308 host->vcc, 0);
db0fefc5
AH		 309 }
310 } else {
99fc5131 311 /* Shut down the rail */
6da20c89
AH		 312 if (host->vcc_aux)
313 ret = regulator_disable(host->vcc_aux);
987fd49b 314 if (host->vcc) {
99fc5131
LW		 315 /* Then proceed to shut down the local regulator */
316 ret = mmc_regulator_set_ocr(host->mmc,
317 host->vcc, 0);
318 }
db0fefc5
AH		 319 }
320
e99448ff
B		 321 if (host->pbias) {
322 if (vdd <= VDD_165_195)
323 ret = regulator_set_voltage(host->pbias, VDD_1V8,
324 VDD_1V8);
325 else
326 ret = regulator_set_voltage(host->pbias, VDD_3V0,
327 VDD_3V0);
328 if (ret < 0)
329 goto error_set_power;
330
331 if (host->pbias_enabled == 0) {
332 ret = regulator_enable(host->pbias);
333 if (!ret)
334 host->pbias_enabled = 1;
335 }
336 }
337
db0fefc5
AH		 338 if (mmc_slot(host).after_set_reg)
339 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
340
e99448ff 341error_set_power:
db0fefc5
AH		 342 return ret;
343}
344
db0fefc5
AH		 345static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
346{
347 struct regulator *reg;
64be9782 348 int ocr_value = 0;
db0fefc5 349
f2ddc1da 350 reg = devm_regulator_get(host->dev, "vmmc");
db0fefc5 351 if (IS_ERR(reg)) {
987fd49b
B		 352 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
353 PTR_ERR(reg));
1fdc90fb 354 return PTR_ERR(reg);
db0fefc5
AH		 355 } else {
356 host->vcc = reg;
64be9782 357 ocr_value = mmc_regulator_get_ocrmask(reg);
358 if (!mmc_slot(host).ocr_mask) {
359 mmc_slot(host).ocr_mask = ocr_value;
360 } else {
361 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
2cecdf00 362 dev_err(host->dev, "ocrmask %x is not supported\n",
e3f1adb6 363 mmc_slot(host).ocr_mask);
64be9782 364 mmc_slot(host).ocr_mask = 0;
365 return -EINVAL;
366 }
367 }
987fd49b
B		 368 }
369 mmc_slot(host).set_power = omap_hsmmc_set_power;
db0fefc5 370
987fd49b
B		 371 /* Allow an aux regulator */
372 reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
373 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
374
e99448ff
B		 375 reg = devm_regulator_get_optional(host->dev, "pbias");
376 host->pbias = IS_ERR(reg) ? NULL : reg;
377
987fd49b
B		 378 /* For eMMC do not power off when not in sleep state */
379 if (mmc_slot(host).no_regulator_off_init)
380 return 0;
381 /*
382 * To disable boot_on regulator, enable regulator
383 * to increase usecount and then disable it.
384 */
385 if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
386 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
387 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
388
389 mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
390 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
db0fefc5
AH		 391 }
392
393 return 0;
db0fefc5
AH		 394}
395
396static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
397{
db0fefc5 398 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 399}
400
b702b106
AH		 401static inline int omap_hsmmc_have_reg(void)
402{
403 return 1;
404}
405
406#else
407
408static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
409{
410 return -EINVAL;
411}
412
413static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
414{
415}
416
417static inline int omap_hsmmc_have_reg(void)
418{
419 return 0;
420}
421
422#endif
423
424static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
425{
426 int ret;
427
428 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 429 if (pdata->slots[0].cover)
430 pdata->slots[0].get_cover_state =
431 omap_hsmmc_get_cover_state;
432 else
433 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
434 pdata->slots[0].card_detect_irq =
435 gpio_to_irq(pdata->slots[0].switch_pin);
436 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
437 if (ret)
438 return ret;
439 ret = gpio_direction_input(pdata->slots[0].switch_pin);
440 if (ret)
441 goto err_free_sp;
442 } else
443 pdata->slots[0].switch_pin = -EINVAL;
444
445 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
446 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
447 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
448 if (ret)
449 goto err_free_cd;
450 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
451 if (ret)
452 goto err_free_wp;
453 } else
454 pdata->slots[0].gpio_wp = -EINVAL;
455
456 return 0;
457
458err_free_wp:
459 gpio_free(pdata->slots[0].gpio_wp);
460err_free_cd:
461 if (gpio_is_valid(pdata->slots[0].switch_pin))
462err_free_sp:
463 gpio_free(pdata->slots[0].switch_pin);
464 return ret;
465}
466
467static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
468{
469 if (gpio_is_valid(pdata->slots[0].gpio_wp))
470 gpio_free(pdata->slots[0].gpio_wp);
471 if (gpio_is_valid(pdata->slots[0].switch_pin))
472 gpio_free(pdata->slots[0].switch_pin);
473}
474
e0c7f99b
AS		 475/*
476 * Start clock to the card
477 */
478static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
479{
480 OMAP_HSMMC_WRITE(host->base, SYSCTL,
481 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
482}
483
a45c6cb8
MC		 484/*
485 * Stop clock to the card
486 */
70a3341a 487static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 488{
489 OMAP_HSMMC_WRITE(host->base, SYSCTL,
490 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
491 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
7122bbb0 492 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
a45c6cb8
MC		 493}
494
93caf8e6
AH		 495static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
496 struct mmc_command *cmd)
b417577d
AH		 497{
498 unsigned int irq_mask;
499
500 if (host->use_dma)
a7e96879 501 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
b417577d
AH		 502 else
503 irq_mask = INT_EN_MASK;
504
93caf8e6
AH		 505 /* Disable timeout for erases */
506 if (cmd->opcode == MMC_ERASE)
a7e96879 507 irq_mask &= ~DTO_EN;
93caf8e6 508
b417577d
AH		 509 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
510 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
511 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
512}
513
514static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
515{
516 OMAP_HSMMC_WRITE(host->base, ISE, 0);
517 OMAP_HSMMC_WRITE(host->base, IE, 0);
518 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
519}
520
ac330f44 521/* Calculate divisor for the given clock frequency */
d83b6e03 522static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 523{
524 u16 dsor = 0;
525
526 if (ios->clock) {
d83b6e03 527 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ed164182
B		 528 if (dsor > CLKD_MAX)
529 dsor = CLKD_MAX;
ac330f44
AS		 530 }
531
532 return dsor;
533}
534
5934df2f
AS		 535static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
536{
537 struct mmc_ios *ios = &host->mmc->ios;
538 unsigned long regval;
539 unsigned long timeout;
cd587096 540 unsigned long clkdiv;
5934df2f 541
8986d31b 542 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
5934df2f
AS		 543
544 omap_hsmmc_stop_clock(host);
545
546 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
547 regval = regval & ~(CLKD_MASK | DTO_MASK);
cd587096
HG		 548 clkdiv = calc_divisor(host, ios);
549 regval = regval | (clkdiv << 6) | (DTO << 16);
5934df2f
AS		 550 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
551 OMAP_HSMMC_WRITE(host->base, SYSCTL,
552 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
553
554 /* Wait till the ICS bit is set */
555 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
556 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
557 && time_before(jiffies, timeout))
558 cpu_relax();
559
cd587096
HG		 560 /*
561 * Enable High-Speed Support
562 * Pre-Requisites
563 * - Controller should support High-Speed-Enable Bit
564 * - Controller should not be using DDR Mode
565 * - Controller should advertise that it supports High Speed
566 * in capabilities register
567 * - MMC/SD clock coming out of controller > 25MHz
568 */
569 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
570 (ios->timing != MMC_TIMING_UHS_DDR50) &&
571 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
572 regval = OMAP_HSMMC_READ(host->base, HCTL);
573 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
574 regval |= HSPE;
575 else
576 regval &= ~HSPE;
577
578 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
579 }
580
5934df2f
AS		 581 omap_hsmmc_start_clock(host);
582}
583
3796fb8a
AS		 584static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
585{
586 struct mmc_ios *ios = &host->mmc->ios;
587 u32 con;
588
589 con = OMAP_HSMMC_READ(host->base, CON);
03b5d924
B		 590 if (ios->timing == MMC_TIMING_UHS_DDR50)
591 con |= DDR; /* configure in DDR mode */
592 else
593 con &= ~DDR;
3796fb8a
AS		 594 switch (ios->bus_width) {
595 case MMC_BUS_WIDTH_8:
596 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
597 break;
598 case MMC_BUS_WIDTH_4:
599 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
600 OMAP_HSMMC_WRITE(host->base, HCTL,
601 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
602 break;
603 case MMC_BUS_WIDTH_1:
604 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
605 OMAP_HSMMC_WRITE(host->base, HCTL,
606 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
607 break;
608 }
609}
610
611static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
612{
613 struct mmc_ios *ios = &host->mmc->ios;
614 u32 con;
615
616 con = OMAP_HSMMC_READ(host->base, CON);
617 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
618 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
619 else
620 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
621}
622
11dd62a7
DK		 623#ifdef CONFIG_PM
624
625/*
626 * Restore the MMC host context, if it was lost as result of a
627 * power state change.
628 */
70a3341a 629static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 630{
631 struct mmc_ios *ios = &host->mmc->ios;
3796fb8a 632 u32 hctl, capa;
11dd62a7
DK		 633 unsigned long timeout;
634
6c31b215
V		 635 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
636 return 1;
11dd62a7 637
0a82e06e
TL		 638 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
639 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
640 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
641 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
642 return 0;
643
644 host->context_loss++;
645
c2200efb 646 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 647 if (host->power_mode != MMC_POWER_OFF &&
648 (1 << ios->vdd) <= MMC_VDD_23_24)
649 hctl = SDVS18;
650 else
651 hctl = SDVS30;
652 capa = VS30 | VS18;
653 } else {
654 hctl = SDVS18;
655 capa = VS18;
656 }
657
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
660
661 OMAP_HSMMC_WRITE(host->base, CAPA,
662 OMAP_HSMMC_READ(host->base, CAPA) | capa);
663
664 OMAP_HSMMC_WRITE(host->base, HCTL,
665 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
666
667 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
668 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
669 && time_before(jiffies, timeout))
670 ;
671
b417577d 672 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 673
674 /* Do not initialize card-specific things if the power is off */
675 if (host->power_mode == MMC_POWER_OFF)
676 goto out;
677
3796fb8a 678 omap_hsmmc_set_bus_width(host);
11dd62a7 679
5934df2f 680 omap_hsmmc_set_clock(host);
11dd62a7 681
3796fb8a
AS		 682 omap_hsmmc_set_bus_mode(host);
683
11dd62a7 684out:
0a82e06e
TL		 685 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
686 host->context_loss);
11dd62a7
DK		 687 return 0;
688}
689
690/*
691 * Save the MMC host context (store the number of power state changes so far).
692 */
70a3341a 693static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7 694{
0a82e06e
TL		 695 host->con = OMAP_HSMMC_READ(host->base, CON);
696 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
697 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
698 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
11dd62a7
DK		 699}
700
701#else
702
70a3341a 703static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 704{
705 return 0;
706}
707
70a3341a 708static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 709{
710}
711
712#endif
713
a45c6cb8
MC		 714/*
715 * Send init stream sequence to card
716 * before sending IDLE command
717 */
70a3341a 718static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 719{
720 int reg = 0;
721 unsigned long timeout;
722
b62f6228
AH		 723 if (host->protect_card)
724 return;
725
a45c6cb8 726 disable_irq(host->irq);
b417577d
AH		 727
728 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 729 OMAP_HSMMC_WRITE(host->base, CON,
730 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
731 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
732
733 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
a7e96879
V		 734 while ((reg != CC_EN) && time_before(jiffies, timeout))
735 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
a45c6cb8
MC		 736
737 OMAP_HSMMC_WRITE(host->base, CON,
738 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 739
740 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
741 OMAP_HSMMC_READ(host->base, STAT);
742
a45c6cb8
MC		 743 enable_irq(host->irq);
744}
745
746static inline
70a3341a 747int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 748{
749 int r = 1;
750
191d1f1d
DK		 751 if (mmc_slot(host).get_cover_state)
752 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 753 return r;
754}
755
756static ssize_t
70a3341a 757omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 758 char *buf)
759{
760 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 761 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 762
70a3341a
DK		 763 return sprintf(buf, "%s\n",
764 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 765}
766
70a3341a 767static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 768
769static ssize_t
70a3341a 770omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 771 char *buf)
772{
773 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 774 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 775
191d1f1d 776 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 777}
778
70a3341a 779static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 780
781/*
782 * Configure the response type and send the cmd.
783 */
784static void
70a3341a 785omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 786 struct mmc_data *data)
787{
788 int cmdreg = 0, resptype = 0, cmdtype = 0;
789
8986d31b 790 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
a45c6cb8
MC		 791 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
792 host->cmd = cmd;
793
93caf8e6 794 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 795
4a694dc9 796 host->response_busy = 0;
a45c6cb8
MC		 797 if (cmd->flags & MMC_RSP_PRESENT) {
798 if (cmd->flags & MMC_RSP_136)
799 resptype = 1;
4a694dc9
AH		 800 else if (cmd->flags & MMC_RSP_BUSY) {
801 resptype = 3;
802 host->response_busy = 1;
803 } else
a45c6cb8
MC		 804 resptype = 2;
805 }
806
807 /*
808 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
809 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
810 * a val of 0x3, rest 0x0.
811 */
812 if (cmd == host->mrq->stop)
813 cmdtype = 0x3;
814
815 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
816
817 if (data) {
818 cmdreg |= DP_SELECT | MSBS | BCE;
819 if (data->flags & MMC_DATA_READ)
820 cmdreg |= DDIR;
821 else
822 cmdreg &= ~(DDIR);
823 }
824
825 if (host->use_dma)
a7e96879 826 cmdreg |= DMAE;
a45c6cb8 827
b417577d 828 host->req_in_progress = 1;
4dffd7a2 829
a45c6cb8
MC		 830 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
831 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
832}
833
0ccd76d4 834static int
70a3341a 835omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 836{
837 if (data->flags & MMC_DATA_WRITE)
838 return DMA_TO_DEVICE;
839 else
840 return DMA_FROM_DEVICE;
841}
842
c5c98927
RK		 843static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
844 struct mmc_data *data)
845{
846 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
847}
848
b417577d
AH		 849static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
850{
851 int dma_ch;
31463b14 852 unsigned long flags;
b417577d 853
31463b14 854 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 855 host->req_in_progress = 0;
856 dma_ch = host->dma_ch;
31463b14 857 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 858
859 omap_hsmmc_disable_irq(host);
860 /* Do not complete the request if DMA is still in progress */
861 if (mrq->data && host->use_dma && dma_ch != -1)
862 return;
863 host->mrq = NULL;
864 mmc_request_done(host->mmc, mrq);
865}
866
a45c6cb8
MC		 867/*
868 * Notify the transfer complete to MMC core
869 */
870static void
70a3341a 871omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 872{
4a694dc9
AH		 873 if (!data) {
874 struct mmc_request *mrq = host->mrq;
875
23050103
AH		 876 /* TC before CC from CMD6 - don't know why, but it happens */
877 if (host->cmd && host->cmd->opcode == 6 &&
878 host->response_busy) {
879 host->response_busy = 0;
880 return;
881 }
882
b417577d 883 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 884 return;
885 }
886
a45c6cb8
MC		 887 host->data = NULL;
888
a45c6cb8
MC		 889 if (!data->error)
890 data->bytes_xfered += data->blocks * (data->blksz);
891 else
892 data->bytes_xfered = 0;
893
fe852273 894 if (!data->stop) {
b417577d 895 omap_hsmmc_request_done(host, data->mrq);
fe852273 896 return;
a45c6cb8 897 }
fe852273 898 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 899}
900
901/*
902 * Notify the core about command completion
903 */
904static void
70a3341a 905omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 906{
907 host->cmd = NULL;
908
909 if (cmd->flags & MMC_RSP_PRESENT) {
910 if (cmd->flags & MMC_RSP_136) {
911 /* response type 2 */
912 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
913 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
914 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
915 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
916 } else {
917 /* response types 1, 1b, 3, 4, 5, 6 */
918 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
919 }
920 }
b417577d
AH		 921 if ((host->data == NULL && !host->response_busy) || cmd->error)
922 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 923}
924
925/*
926 * DMA clean up for command errors
927 */
70a3341a 928static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 929{
b417577d 930 int dma_ch;
31463b14 931 unsigned long flags;
b417577d 932
82788ff5 933 host->data->error = errno;
a45c6cb8 934
31463b14 935 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 936 dma_ch = host->dma_ch;
937 host->dma_ch = -1;
31463b14 938 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 939
940 if (host->use_dma && dma_ch != -1) {
c5c98927
RK		 941 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
942
943 dmaengine_terminate_all(chan);
944 dma_unmap_sg(chan->device->dev,
945 host->data->sg, host->data->sg_len,
70a3341a 946 omap_hsmmc_get_dma_dir(host, host->data));
c5c98927 947
053bf34f 948 host->data->host_cookie = 0;
a45c6cb8
MC		 949 }
950 host->data = NULL;
a45c6cb8
MC		 951}
952
953/*
954 * Readable error output
955 */
956#ifdef CONFIG_MMC_DEBUG
699b958b 957static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 958{
959 /* --- means reserved bit without definition at documentation */
70a3341a 960 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 961 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
962 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
963 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
964 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 965 };
966 char res[256];
967 char *buf = res;
968 int len, i;
969
970 len = sprintf(buf, "MMC IRQ 0x%x :", status);
971 buf += len;
972
70a3341a 973 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 974 if (status & (1 << i)) {
70a3341a 975 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 976 buf += len;
977 }
978
8986d31b 979 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
a45c6cb8 980}
699b958b
AH		 981#else
982static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
983 u32 status)
984{
985}
a45c6cb8
MC		 986#endif /* CONFIG_MMC_DEBUG */
987
3ebf74b1
JP		 988/*
989 * MMC controller internal state machines reset
990 *
991 * Used to reset command or data internal state machines, using respectively
992 * SRC or SRD bit of SYSCTL register
993 * Can be called from interrupt context
994 */
70a3341a
DK		 995static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
996 unsigned long bit)
3ebf74b1
JP		 997{
998 unsigned long i = 0;
1e881786 999 unsigned long limit = MMC_TIMEOUT_US;
3ebf74b1
JP		 1000
1001 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1002 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1003
07ad64b6
MC		 1004 /*
1005 * OMAP4 ES2 and greater has an updated reset logic.
1006 * Monitor a 0->1 transition first
1007 */
1008 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1009 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6 1010 && (i++ < limit))
1e881786 1011 udelay(1);
07ad64b6
MC		 1012 }
1013 i = 0;
1014
3ebf74b1
JP		 1015 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1016 (i++ < limit))
1e881786 1017 udelay(1);
3ebf74b1
JP		 1018
1019 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1020 dev_err(mmc_dev(host->mmc),
1021 "Timeout waiting on controller reset in %s\n",
1022 __func__);
1023}
a45c6cb8 1024
25e1897b
B		 1025static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1026 int err, int end_cmd)
ae4bf788 1027{
25e1897b 1028 if (end_cmd) {
94d4f272 1029 omap_hsmmc_reset_controller_fsm(host, SRC);
25e1897b
B		 1030 if (host->cmd)
1031 host->cmd->error = err;
1032 }
ae4bf788
V		 1033
1034 if (host->data) {
1035 omap_hsmmc_reset_controller_fsm(host, SRD);
1036 omap_hsmmc_dma_cleanup(host, err);
dc7745bd
B		 1037 } else if (host->mrq && host->mrq->cmd)
1038 host->mrq->cmd->error = err;
ae4bf788
V		 1039}
1040
b417577d 1041static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1042{
a45c6cb8 1043 struct mmc_data *data;
b417577d
AH		 1044 int end_cmd = 0, end_trans = 0;
1045
a45c6cb8 1046 data = host->data;
8986d31b 1047 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
a45c6cb8 1048
a7e96879 1049 if (status & ERR_EN) {
699b958b 1050 omap_hsmmc_dbg_report_irq(host, status);
25e1897b 1051
a7e96879 1052 if (status & (CTO_EN | CCRC_EN))
25e1897b 1053 end_cmd = 1;
a7e96879 1054 if (status & (CTO_EN | DTO_EN))
25e1897b 1055 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
a7e96879 1056 else if (status & (CCRC_EN | DCRC_EN))
25e1897b 1057 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
ae4bf788 1058
ae4bf788 1059 if (host->data || host->response_busy) {
25e1897b 1060 end_trans = !end_cmd;
ae4bf788 1061 host->response_busy = 0;
a45c6cb8
MC		 1062 }
1063 }
1064
7472bab2 1065 OMAP_HSMMC_WRITE(host->base, STAT, status);
a7e96879 1066 if (end_cmd || ((status & CC_EN) && host->cmd))
70a3341a 1067 omap_hsmmc_cmd_done(host, host->cmd);
a7e96879 1068 if ((end_trans || (status & TC_EN)) && host->mrq)
70a3341a 1069 omap_hsmmc_xfer_done(host, data);
b417577d 1070}
a45c6cb8 1071
b417577d
AH		 1072/*
1073 * MMC controller IRQ handler
1074 */
1075static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1076{
1077 struct omap_hsmmc_host *host = dev_id;
1078 int status;
1079
1080 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1081 while (status & INT_EN_MASK && host->req_in_progress) {
b417577d 1082 omap_hsmmc_do_irq(host, status);
1f6b9fa4 1083
b417577d
AH		 1084 /* Flush posted write */
1085 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1086 }
4dffd7a2 1087
a45c6cb8
MC		 1088 return IRQ_HANDLED;
1089}
1090
70a3341a 1091static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1092{
1093 unsigned long i;
1094
1095 OMAP_HSMMC_WRITE(host->base, HCTL,
1096 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1097 for (i = 0; i < loops_per_jiffy; i++) {
1098 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1099 break;
1100 cpu_relax();
1101 }
1102}
1103
a45c6cb8 1104/*
eb250826
DB		 1105 * Switch MMC interface voltage ... only relevant for MMC1.
1106 *
1107 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1108 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1109 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1110 */
70a3341a 1111static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1112{
1113 u32 reg_val = 0;
1114 int ret;
1115
1116 /* Disable the clocks */
fa4aa2d4 1117 pm_runtime_put_sync(host->dev);
cd03d9a8 1118 if (host->dbclk)
94c18149 1119 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1120
1121 /* Turn the power off */
1122 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1123
1124 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1125 if (!ret)
1126 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1127 vdd);
fa4aa2d4 1128 pm_runtime_get_sync(host->dev);
cd03d9a8 1129 if (host->dbclk)
94c18149 1130 clk_prepare_enable(host->dbclk);
2bec0893 1131
a45c6cb8
MC		 1132 if (ret != 0)
1133 goto err;
1134
a45c6cb8
MC		 1135 OMAP_HSMMC_WRITE(host->base, HCTL,
1136 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1137 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1138
a45c6cb8
MC		 1139 /*
1140 * If a MMC dual voltage card is detected, the set_ios fn calls
1141 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1142 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1143 *
eb250826
DB		 1144 * Cope with a bit of slop in the range ... per data sheets:
1145 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1146 * but recommended values are 1.71V to 1.89V
1147 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1148 * but recommended values are 2.7V to 3.3V
1149 *
1150 * Board setup code shouldn't permit anything very out-of-range.
1151 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1152 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1153 */
eb250826 1154 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1155 reg_val |= SDVS18;
eb250826
DB		 1156 else
1157 reg_val |= SDVS30;
a45c6cb8
MC		 1158
1159 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1160 set_sd_bus_power(host);
a45c6cb8
MC		 1161
1162 return 0;
1163err:
b1e056ae 1164 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
a45c6cb8
MC		 1165 return ret;
1166}
1167
b62f6228
AH		 1168/* Protect the card while the cover is open */
1169static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1170{
1171 if (!mmc_slot(host).get_cover_state)
1172 return;
1173
1174 host->reqs_blocked = 0;
1175 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1176 if (host->protect_card) {
2cecdf00 1177 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1178 "card is now accessible\n",
1179 mmc_hostname(host->mmc));
1180 host->protect_card = 0;
1181 }
1182 } else {
1183 if (!host->protect_card) {
2cecdf00 1184 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1185 "card is now inaccessible\n",
1186 mmc_hostname(host->mmc));
1187 host->protect_card = 1;
1188 }
1189 }
1190}
1191
a45c6cb8 1192/*
7efab4f3 1193 * irq handler to notify the core about card insertion/removal
a45c6cb8 1194 */
7efab4f3 1195static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1196{
7efab4f3 1197 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1198 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1199 int carddetect;
1200
a6b2240d 1201 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1202
191d1f1d 1203 if (slot->card_detect)
db0fefc5 1204 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1205 else {
1206 omap_hsmmc_protect_card(host);
a6b2240d 1207 carddetect = -ENOSYS;
b62f6228 1208 }
a45c6cb8 1209
cdeebadd 1210 if (carddetect)
a45c6cb8 1211 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1212 else
a45c6cb8 1213 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1214 return IRQ_HANDLED;
1215}
1216
c5c98927 1217static void omap_hsmmc_dma_callback(void *param)
a45c6cb8 1218{
c5c98927
RK		 1219 struct omap_hsmmc_host *host = param;
1220 struct dma_chan *chan;
770d7432 1221 struct mmc_data *data;
c5c98927 1222 int req_in_progress;
a45c6cb8 1223
c5c98927 1224 spin_lock_irq(&host->irq_lock);
b417577d 1225 if (host->dma_ch < 0) {
c5c98927 1226 spin_unlock_irq(&host->irq_lock);
a45c6cb8 1227 return;
b417577d 1228 }
a45c6cb8 1229
770d7432 1230 data = host->mrq->data;
c5c98927 1231 chan = omap_hsmmc_get_dma_chan(host, data);
9782aff8 1232 if (!data->host_cookie)
c5c98927
RK		 1233 dma_unmap_sg(chan->device->dev,
1234 data->sg, data->sg_len,
9782aff8 1235 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1236
1237 req_in_progress = host->req_in_progress;
a45c6cb8 1238 host->dma_ch = -1;
c5c98927 1239 spin_unlock_irq(&host->irq_lock);
b417577d
AH		 1240
1241 /* If DMA has finished after TC, complete the request */
1242 if (!req_in_progress) {
1243 struct mmc_request *mrq = host->mrq;
1244
1245 host->mrq = NULL;
1246 mmc_request_done(host->mmc, mrq);
1247 }
a45c6cb8
MC		 1248}
1249
9782aff8
PF		 1250static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1251 struct mmc_data *data,
c5c98927 1252 struct omap_hsmmc_next *next,
26b88520 1253 struct dma_chan *chan)
9782aff8
PF		 1254{
1255 int dma_len;
1256
1257 if (!next && data->host_cookie &&
1258 data->host_cookie != host->next_data.cookie) {
2cecdf00 1259 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1260 " host->next_data.cookie %d\n",
1261 __func__, data->host_cookie, host->next_data.cookie);
1262 data->host_cookie = 0;
1263 }
1264
1265 /* Check if next job is already prepared */
b38313d6 1266 if (next || data->host_cookie != host->next_data.cookie) {
26b88520 1267 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
9782aff8
PF		 1268 omap_hsmmc_get_dma_dir(host, data));
1269
1270 } else {
1271 dma_len = host->next_data.dma_len;
1272 host->next_data.dma_len = 0;
1273 }
1274
1275
1276 if (dma_len == 0)
1277 return -EINVAL;
1278
1279 if (next) {
1280 next->dma_len = dma_len;
1281 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1282 } else
1283 host->dma_len = dma_len;
1284
1285 return 0;
1286}
1287
a45c6cb8
MC		 1288/*
1289 * Routine to configure and start DMA for the MMC card
1290 */
70a3341a
DK		 1291static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1292 struct mmc_request *req)
a45c6cb8 1293{
26b88520
RK		 1294 struct dma_slave_config cfg;
1295 struct dma_async_tx_descriptor *tx;
1296 int ret = 0, i;
a45c6cb8 1297 struct mmc_data *data = req->data;
c5c98927 1298 struct dma_chan *chan;
a45c6cb8 1299
0ccd76d4 1300 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1301 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1302 struct scatterlist *sgl;
1303
1304 sgl = data->sg + i;
1305 if (sgl->length % data->blksz)
1306 return -EINVAL;
1307 }
1308 if ((data->blksz % 4) != 0)
1309 /* REVISIT: The MMC buffer increments only when MSB is written.
1310 * Return error for blksz which is non multiple of four.
1311 */
1312 return -EINVAL;
1313
b417577d 1314 BUG_ON(host->dma_ch != -1);
a45c6cb8 1315
c5c98927 1316 chan = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1317
26b88520
RK		 1318 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1319 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1320 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1321 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1322 cfg.src_maxburst = data->blksz / 4;
1323 cfg.dst_maxburst = data->blksz / 4;
c5c98927 1324
26b88520
RK		 1325 ret = dmaengine_slave_config(chan, &cfg);
1326 if (ret)
a45c6cb8 1327 return ret;
c5c98927 1328
26b88520 1329 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
9782aff8
PF		 1330 if (ret)
1331 return ret;
a45c6cb8 1332
26b88520
RK		 1333 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1334 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1335 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1336 if (!tx) {
1337 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1338 /* FIXME: cleanup */
1339 return -1;
1340 }
a45c6cb8 1341
26b88520
RK		 1342 tx->callback = omap_hsmmc_dma_callback;
1343 tx->callback_param = host;
a45c6cb8 1344
26b88520
RK		 1345 /* Does not fail */
1346 dmaengine_submit(tx);
c5c98927 1347
26b88520 1348 host->dma_ch = 1;
c5c98927 1349
26b88520 1350 dma_async_issue_pending(chan);
a45c6cb8 1351
a45c6cb8
MC		 1352 return 0;
1353}
1354
70a3341a 1355static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1356 unsigned int timeout_ns,
1357 unsigned int timeout_clks)
a45c6cb8
MC		 1358{
1359 unsigned int timeout, cycle_ns;
1360 uint32_t reg, clkd, dto = 0;
1361
1362 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1363 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1364 if (clkd == 0)
1365 clkd = 1;
1366
1367 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1368 timeout = timeout_ns / cycle_ns;
1369 timeout += timeout_clks;
a45c6cb8
MC		 1370 if (timeout) {
1371 while ((timeout & 0x80000000) == 0) {
1372 dto += 1;
1373 timeout <<= 1;
1374 }
1375 dto = 31 - dto;
1376 timeout <<= 1;
1377 if (timeout && dto)
1378 dto += 1;
1379 if (dto >= 13)
1380 dto -= 13;
1381 else
1382 dto = 0;
1383 if (dto > 14)
1384 dto = 14;
1385 }
1386
1387 reg &= ~DTO_MASK;
1388 reg |= dto << DTO_SHIFT;
1389 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1390}
1391
1392/*
1393 * Configure block length for MMC/SD cards and initiate the transfer.
1394 */
1395static int
70a3341a 1396omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1397{
1398 int ret;
1399 host->data = req->data;
1400
1401 if (req->data == NULL) {
a45c6cb8 1402 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1403 /*
1404 * Set an arbitrary 100ms data timeout for commands with
1405 * busy signal.
1406 */
1407 if (req->cmd->flags & MMC_RSP_BUSY)
1408 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1409 return 0;
1410 }
1411
1412 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1413 | (req->data->blocks << 16));
e2bf08d6 1414 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1415
a45c6cb8 1416 if (host->use_dma) {
70a3341a 1417 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8 1418 if (ret != 0) {
b1e056ae 1419 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
a45c6cb8
MC		 1420 return ret;
1421 }
1422 }
1423 return 0;
1424}
1425
9782aff8
PF		 1426static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1427 int err)
1428{
1429 struct omap_hsmmc_host *host = mmc_priv(mmc);
1430 struct mmc_data *data = mrq->data;
1431
26b88520 1432 if (host->use_dma && data->host_cookie) {
c5c98927 1433 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1434
26b88520
RK		 1435 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1436 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1437 data->host_cookie = 0;
1438 }
1439}
1440
1441static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1442 bool is_first_req)
1443{
1444 struct omap_hsmmc_host *host = mmc_priv(mmc);
1445
1446 if (mrq->data->host_cookie) {
1447 mrq->data->host_cookie = 0;
1448 return ;
1449 }
1450
c5c98927
RK		 1451 if (host->use_dma) {
1452 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
c5c98927 1453
9782aff8 1454 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
26b88520 1455 &host->next_data, c))
9782aff8 1456 mrq->data->host_cookie = 0;
c5c98927 1457 }
9782aff8
PF		 1458}
1459
a45c6cb8
MC		 1460/*
1461 * Request function. for read/write operation
1462 */
70a3341a 1463static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1464{
70a3341a 1465 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1466 int err;
a45c6cb8 1467
b417577d
AH		 1468 BUG_ON(host->req_in_progress);
1469 BUG_ON(host->dma_ch != -1);
1470 if (host->protect_card) {
1471 if (host->reqs_blocked < 3) {
1472 /*
1473 * Ensure the controller is left in a consistent
1474 * state by resetting the command and data state
1475 * machines.
1476 */
1477 omap_hsmmc_reset_controller_fsm(host, SRD);
1478 omap_hsmmc_reset_controller_fsm(host, SRC);
1479 host->reqs_blocked += 1;
1480 }
1481 req->cmd->error = -EBADF;
1482 if (req->data)
1483 req->data->error = -EBADF;
1484 req->cmd->retries = 0;
1485 mmc_request_done(mmc, req);
1486 return;
1487 } else if (host->reqs_blocked)
1488 host->reqs_blocked = 0;
a45c6cb8
MC		 1489 WARN_ON(host->mrq != NULL);
1490 host->mrq = req;
70a3341a 1491 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1492 if (err) {
1493 req->cmd->error = err;
1494 if (req->data)
1495 req->data->error = err;
1496 host->mrq = NULL;
1497 mmc_request_done(mmc, req);
1498 return;
1499 }
1500
70a3341a 1501 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1502}
1503
a45c6cb8 1504/* Routine to configure clock values. Exposed API to core */
70a3341a 1505static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1506{
70a3341a 1507 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1508 int do_send_init_stream = 0;
a45c6cb8 1509
fa4aa2d4 1510 pm_runtime_get_sync(host->dev);
5e2ea617 1511
a3621465
AH		 1512 if (ios->power_mode != host->power_mode) {
1513 switch (ios->power_mode) {
1514 case MMC_POWER_OFF:
1515 mmc_slot(host).set_power(host->dev, host->slot_id,
1516 0, 0);
1517 break;
1518 case MMC_POWER_UP:
1519 mmc_slot(host).set_power(host->dev, host->slot_id,
1520 1, ios->vdd);
1521 break;
1522 case MMC_POWER_ON:
1523 do_send_init_stream = 1;
1524 break;
1525 }
1526 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1527 }
1528
dd498eff
DK		 1529 /* FIXME: set registers based only on changes to ios */
1530
3796fb8a 1531 omap_hsmmc_set_bus_width(host);
a45c6cb8 1532
4621d5f8 1533 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1534 /* Only MMC1 can interface at 3V without some flavor
1535 * of external transceiver; but they all handle 1.8V.
1536 */
a45c6cb8 1537 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
2cf171cb 1538 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
a45c6cb8
MC		 1539 /*
1540 * The mmc_select_voltage fn of the core does
1541 * not seem to set the power_mode to
1542 * MMC_POWER_UP upon recalculating the voltage.
1543 * vdd 1.8v.
1544 */
70a3341a
DK		 1545 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1546 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1547 "Switch operation failed\n");
1548 }
1549 }
1550
5934df2f 1551 omap_hsmmc_set_clock(host);
a45c6cb8 1552
a3621465 1553 if (do_send_init_stream)
a45c6cb8
MC		 1554 send_init_stream(host);
1555
3796fb8a 1556 omap_hsmmc_set_bus_mode(host);
5e2ea617 1557
fa4aa2d4 1558 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1559}
1560
1561static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1562{
70a3341a 1563 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1564
191d1f1d 1565 if (!mmc_slot(host).card_detect)
a45c6cb8 1566 return -ENOSYS;
db0fefc5 1567 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1568}
1569
1570static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1571{
70a3341a 1572 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1573
191d1f1d 1574 if (!mmc_slot(host).get_ro)
a45c6cb8 1575 return -ENOSYS;
191d1f1d 1576 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1577}
1578
4816858c
GI		 1579static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1580{
1581 struct omap_hsmmc_host *host = mmc_priv(mmc);
1582
1583 if (mmc_slot(host).init_card)
1584 mmc_slot(host).init_card(card);
1585}
1586
70a3341a 1587static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1588{
1589 u32 hctl, capa, value;
1590
1591 /* Only MMC1 supports 3.0V */
4621d5f8 1592 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1593 hctl = SDVS30;
1594 capa = VS30 | VS18;
1595 } else {
1596 hctl = SDVS18;
1597 capa = VS18;
1598 }
1599
1600 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1601 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1602
1603 value = OMAP_HSMMC_READ(host->base, CAPA);
1604 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1605
1b331e69 1606 /* Set SD bus power bit */
e13bb300 1607 set_sd_bus_power(host);
1b331e69
KK		 1608}
1609
70a3341a 1610static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1611{
70a3341a 1612 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1613
fa4aa2d4
B		 1614 pm_runtime_get_sync(host->dev);
1615
dd498eff
DK		 1616 return 0;
1617}
1618
907d2e7c 1619static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
dd498eff 1620{
70a3341a 1621 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1622
fa4aa2d4
B		 1623 pm_runtime_mark_last_busy(host->dev);
1624 pm_runtime_put_autosuspend(host->dev);
1625
dd498eff
DK		 1626 return 0;
1627}
1628
70a3341a
DK		 1629static const struct mmc_host_ops omap_hsmmc_ops = {
1630 .enable = omap_hsmmc_enable_fclk,
1631 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1632 .post_req = omap_hsmmc_post_req,
1633 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1634 .request = omap_hsmmc_request,
1635 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1636 .get_cd = omap_hsmmc_get_cd,
1637 .get_ro = omap_hsmmc_get_ro,
4816858c 1638 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1639 /* NYET -- enable_sdio_irq */
1640};
1641
d900f712
DK		 1642#ifdef CONFIG_DEBUG_FS
1643
70a3341a 1644static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1645{
1646 struct mmc_host *mmc = s->private;
70a3341a 1647 struct omap_hsmmc_host *host = mmc_priv(mmc);
d900f712 1648
0a82e06e
TL		 1649 seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n",
1650 mmc->index, host->context_loss);
5e2ea617 1651
fa4aa2d4 1652 pm_runtime_get_sync(host->dev);
d900f712 1653
d900f712
DK		 1654 seq_printf(s, "CON:\t\t0x%08x\n",
1655 OMAP_HSMMC_READ(host->base, CON));
1656 seq_printf(s, "HCTL:\t\t0x%08x\n",
1657 OMAP_HSMMC_READ(host->base, HCTL));
1658 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1659 OMAP_HSMMC_READ(host->base, SYSCTL));
1660 seq_printf(s, "IE:\t\t0x%08x\n",
1661 OMAP_HSMMC_READ(host->base, IE));
1662 seq_printf(s, "ISE:\t\t0x%08x\n",
1663 OMAP_HSMMC_READ(host->base, ISE));
1664 seq_printf(s, "CAPA:\t\t0x%08x\n",
1665 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1666
fa4aa2d4
B		 1667 pm_runtime_mark_last_busy(host->dev);
1668 pm_runtime_put_autosuspend(host->dev);
dd498eff 1669
d900f712
DK		 1670 return 0;
1671}
1672
70a3341a 1673static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1674{
70a3341a 1675 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1676}
1677
1678static const struct file_operations mmc_regs_fops = {
70a3341a 1679 .open = omap_hsmmc_regs_open,
d900f712
DK		 1680 .read = seq_read,
1681 .llseek = seq_lseek,
1682 .release = single_release,
1683};
1684
70a3341a 1685static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1686{
1687 if (mmc->debugfs_root)
1688 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1689 mmc, &mmc_regs_fops);
1690}
1691
1692#else
1693
70a3341a 1694static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1695{
1696}
1697
1698#endif
1699
46856a68 1700#ifdef CONFIG_OF
59445b10
NM		 1701static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1702 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1703 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1704};
1705
1706static const struct omap_mmc_of_data omap4_mmc_of_data = {
1707 .reg_offset = 0x100,
1708};
46856a68
RN		 1709
1710static const struct of_device_id omap_mmc_of_match[] = {
1711 {
1712 .compatible = "ti,omap2-hsmmc",
1713 },
59445b10
NM		 1714 {
1715 .compatible = "ti,omap3-pre-es3-hsmmc",
1716 .data = &omap3_pre_es3_mmc_of_data,
1717 },
46856a68
RN		 1718 {
1719 .compatible = "ti,omap3-hsmmc",
1720 },
1721 {
1722 .compatible = "ti,omap4-hsmmc",
59445b10 1723 .data = &omap4_mmc_of_data,
46856a68
RN		 1724 },
1725 {},
b6d085f6 1726};
46856a68
RN		 1727MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1728
1729static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1730{
1731 struct omap_mmc_platform_data *pdata;
1732 struct device_node *np = dev->of_node;
d8714e87 1733 u32 bus_width, max_freq;
dc642c28
JL		 1734 int cd_gpio, wp_gpio;
1735
1736 cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1737 wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1738 if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1739 return ERR_PTR(-EPROBE_DEFER);
46856a68
RN		 1740
1741 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1742 if (!pdata)
1743 return NULL; /* out of memory */
1744
1745 if (of_find_property(np, "ti,dual-volt", NULL))
1746 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1747
1748 /* This driver only supports 1 slot */
1749 pdata->nr_slots = 1;
dc642c28
JL		 1750 pdata->slots[0].switch_pin = cd_gpio;
1751 pdata->slots[0].gpio_wp = wp_gpio;
46856a68
RN		 1752
1753 if (of_find_property(np, "ti,non-removable", NULL)) {
1754 pdata->slots[0].nonremovable = true;
1755 pdata->slots[0].no_regulator_off_init = true;
1756 }
7f217794 1757 of_property_read_u32(np, "bus-width", &bus_width);
46856a68
RN		 1758 if (bus_width == 4)
1759 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1760 else if (bus_width == 8)
1761 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1762
1763 if (of_find_property(np, "ti,needs-special-reset", NULL))
1764 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1765
d8714e87
DM		 1766 if (!of_property_read_u32(np, "max-frequency", &max_freq))
1767 pdata->max_freq = max_freq;
1768
cd587096
HG		 1769 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1770 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1771
c9ae64db
DM		 1772 if (of_find_property(np, "keep-power-in-suspend", NULL))
1773 pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER;
1774
1775 if (of_find_property(np, "enable-sdio-wakeup", NULL))
1776 pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1777
46856a68
RN		 1778 return pdata;
1779}
1780#else
1781static inline struct omap_mmc_platform_data
1782 *of_get_hsmmc_pdata(struct device *dev)
1783{
1784 return NULL;
1785}
1786#endif
1787
c3be1efd 1788static int omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1789{
1790 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1791 struct mmc_host *mmc;
70a3341a 1792 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1793 struct resource *res;
db0fefc5 1794 int ret, irq;
46856a68 1795 const struct of_device_id *match;
26b88520
RK		 1796 dma_cap_mask_t mask;
1797 unsigned tx_req, rx_req;
46b76035 1798 struct pinctrl *pinctrl;
59445b10 1799 const struct omap_mmc_of_data *data;
46856a68
RN		 1800
1801 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1802 if (match) {
1803 pdata = of_get_hsmmc_pdata(&pdev->dev);
dc642c28
JL		 1804
1805 if (IS_ERR(pdata))
1806 return PTR_ERR(pdata);
1807
46856a68 1808 if (match->data) {
59445b10
NM		 1809 data = match->data;
1810 pdata->reg_offset = data->reg_offset;
1811 pdata->controller_flags |= data->controller_flags;
46856a68
RN		 1812 }
1813 }
a45c6cb8
MC		 1814
1815 if (pdata == NULL) {
1816 dev_err(&pdev->dev, "Platform Data is missing\n");
1817 return -ENXIO;
1818 }
1819
1820 if (pdata->nr_slots == 0) {
1821 dev_err(&pdev->dev, "No Slots\n");
1822 return -ENXIO;
1823 }
1824
1825 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1826 irq = platform_get_irq(pdev, 0);
1827 if (res == NULL || irq < 0)
1828 return -ENXIO;
1829
984b203a 1830 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1831 if (res == NULL)
1832 return -EBUSY;
1833
db0fefc5
AH		 1834 ret = omap_hsmmc_gpio_init(pdata);
1835 if (ret)
1836 goto err;
1837
70a3341a 1838 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1839 if (!mmc) {
1840 ret = -ENOMEM;
db0fefc5 1841 goto err_alloc;
a45c6cb8
MC		 1842 }
1843
1844 host = mmc_priv(mmc);
1845 host->mmc = mmc;
1846 host->pdata = pdata;
1847 host->dev = &pdev->dev;
1848 host->use_dma = 1;
a45c6cb8
MC		 1849 host->dma_ch = -1;
1850 host->irq = irq;
a45c6cb8 1851 host->slot_id = 0;
fc307df8 1852 host->mapbase = res->start + pdata->reg_offset;
a45c6cb8 1853 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1854 host->power_mode = MMC_POWER_OFF;
9782aff8 1855 host->next_data.cookie = 1;
e99448ff 1856 host->pbias_enabled = 0;
a45c6cb8
MC		 1857
1858 platform_set_drvdata(pdev, host);
a45c6cb8 1859
7a8c2cef 1860 mmc->ops = &omap_hsmmc_ops;
dd498eff 1861
d418ed87
DM		 1862 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1863
1864 if (pdata->max_freq > 0)
1865 mmc->f_max = pdata->max_freq;
1866 else
1867 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1868
4dffd7a2 1869 spin_lock_init(&host->irq_lock);
a45c6cb8 1870
6f7607cc 1871 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1872 if (IS_ERR(host->fclk)) {
1873 ret = PTR_ERR(host->fclk);
1874 host->fclk = NULL;
a45c6cb8
MC		 1875 goto err1;
1876 }
1877
9b68256c
PW		 1878 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1879 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1880 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1881 }
dd498eff 1882
fa4aa2d4
B		 1883 pm_runtime_enable(host->dev);
1884 pm_runtime_get_sync(host->dev);
1885 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1886 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1887
92a3aebf
B		 1888 omap_hsmmc_context_save(host);
1889
cd03d9a8
RN		 1890 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1891 /*
1892 * MMC can still work without debounce clock.
1893 */
1894 if (IS_ERR(host->dbclk)) {
cd03d9a8 1895 host->dbclk = NULL;
94c18149 1896 } else if (clk_prepare_enable(host->dbclk) != 0) {
cd03d9a8
RN		 1897 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1898 clk_put(host->dbclk);
1899 host->dbclk = NULL;
2bec0893 1900 }
a45c6cb8 1901
0ccd76d4
JY		 1902 /* Since we do only SG emulation, we can have as many segs
1903 * as we want. */
a36274e0 1904 mmc->max_segs = 1024;
0ccd76d4 1905
a45c6cb8
MC		 1906 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1907 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1908 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1909 mmc->max_seg_size = mmc->max_req_size;
1910
13189e78 1911 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1912 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1913
3a63833e
SG		 1914 mmc->caps |= mmc_slot(host).caps;
1915 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1916 mmc->caps |= MMC_CAP_4_BIT_DATA;
1917
191d1f1d 1918 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1919 mmc->caps |= MMC_CAP_NONREMOVABLE;
1920
6fdc75de
EP		 1921 mmc->pm_caps = mmc_slot(host).pm_caps;
1922
70a3341a 1923 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1924
4a29b559
SS		 1925 if (!pdev->dev.of_node) {
1926 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1927 if (!res) {
1928 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1929 ret = -ENXIO;
1930 goto err_irq;
1931 }
1932 tx_req = res->start;
b7bf773b 1933
4a29b559
SS		 1934 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1935 if (!res) {
1936 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1937 ret = -ENXIO;
1938 goto err_irq;
1939 }
1940 rx_req = res->start;
f3e2f1dd 1941 }
a45c6cb8 1942
26b88520
RK		 1943 dma_cap_zero(mask);
1944 dma_cap_set(DMA_SLAVE, mask);
1945
d272fbf0
MP		 1946 host->rx_chan =
1947 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1948 &rx_req, &pdev->dev, "rx");
1949
26b88520
RK		 1950 if (!host->rx_chan) {
1951 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
04e8c7bc 1952 ret = -ENXIO;
26b88520
RK		 1953 goto err_irq;
1954 }
1955
d272fbf0
MP		 1956 host->tx_chan =
1957 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1958 &tx_req, &pdev->dev, "tx");
1959
26b88520
RK		 1960 if (!host->tx_chan) {
1961 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
04e8c7bc 1962 ret = -ENXIO;
26b88520 1963 goto err_irq;
c5c98927 1964 }
a45c6cb8
MC		 1965
1966 /* Request IRQ for MMC operations */
d9618e9f 1967 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1968 mmc_hostname(mmc), host);
1969 if (ret) {
b1e056ae 1970 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
a45c6cb8
MC		 1971 goto err_irq;
1972 }
1973
1974 if (pdata->init != NULL) {
1975 if (pdata->init(&pdev->dev) != 0) {
b1e056ae 1976 dev_err(mmc_dev(host->mmc),
70a3341a 1977 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1978 goto err_irq_cd_init;
1979 }
1980 }
db0fefc5 1981
b702b106 1982 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1983 ret = omap_hsmmc_reg_get(host);
1984 if (ret)
1985 goto err_reg;
1986 host->use_reg = 1;
1987 }
1988
b583f26d 1989 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1990
1991 /* Request IRQ for card detect */
e1a55f5e 1992 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1993 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1994 NULL,
1995 omap_hsmmc_detect,
db35f83e 1996 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
7efab4f3 1997 mmc_hostname(mmc), host);
a45c6cb8 1998 if (ret) {
b1e056ae 1999 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 2000 "Unable to grab MMC CD IRQ\n");
2001 goto err_irq_cd;
2002 }
72f2e2c7 2003 pdata->suspend = omap_hsmmc_suspend_cdirq;
2004 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 2005 }
2006
b417577d 2007 omap_hsmmc_disable_irq(host);
a45c6cb8 2008
46b76035
DM		 2009 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
2010 if (IS_ERR(pinctrl))
2011 dev_warn(&pdev->dev,
2012 "pins are not configured from the driver\n");
2013
b62f6228
AH		 2014 omap_hsmmc_protect_card(host);
2015
a45c6cb8
MC		 2016 mmc_add_host(mmc);
2017
191d1f1d 2018 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2019 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2020 if (ret < 0)
2021 goto err_slot_name;
2022 }
191d1f1d 2023 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2024 ret = device_create_file(&mmc->class_dev,
2025 &dev_attr_cover_switch);
2026 if (ret < 0)
db0fefc5 2027 goto err_slot_name;
a45c6cb8
MC		 2028 }
2029
70a3341a 2030 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2031 pm_runtime_mark_last_busy(host->dev);
2032 pm_runtime_put_autosuspend(host->dev);
d900f712 2033
a45c6cb8
MC		 2034 return 0;
2035
a45c6cb8
MC		 2036err_slot_name:
2037 mmc_remove_host(mmc);
a45c6cb8 2038 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2039err_irq_cd:
2040 if (host->use_reg)
2041 omap_hsmmc_reg_put(host);
2042err_reg:
2043 if (host->pdata->cleanup)
2044 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2045err_irq_cd_init:
2046 free_irq(host->irq, host);
2047err_irq:
c5c98927
RK		 2048 if (host->tx_chan)
2049 dma_release_channel(host->tx_chan);
2050 if (host->rx_chan)
2051 dma_release_channel(host->rx_chan);
d59d77ed 2052 pm_runtime_put_sync(host->dev);
37f6190d 2053 pm_runtime_disable(host->dev);
a45c6cb8 2054 clk_put(host->fclk);
cd03d9a8 2055 if (host->dbclk) {
94c18149 2056 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 2057 clk_put(host->dbclk);
2058 }
a45c6cb8
MC		 2059err1:
2060 iounmap(host->base);
db0fefc5
AH		 2061 mmc_free_host(mmc);
2062err_alloc:
2063 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2064err:
48b332f9
RK		 2065 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2066 if (res)
2067 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2068 return ret;
2069}
2070
6e0ee714 2071static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2072{
70a3341a 2073 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2074 struct resource *res;
2075
927ce944
FB		 2076 pm_runtime_get_sync(host->dev);
2077 mmc_remove_host(host->mmc);
2078 if (host->use_reg)
2079 omap_hsmmc_reg_put(host);
2080 if (host->pdata->cleanup)
2081 host->pdata->cleanup(&pdev->dev);
2082 free_irq(host->irq, host);
2083 if (mmc_slot(host).card_detect_irq)
2084 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 2085
c5c98927
RK		 2086 if (host->tx_chan)
2087 dma_release_channel(host->tx_chan);
2088 if (host->rx_chan)
2089 dma_release_channel(host->rx_chan);
2090
927ce944
FB		 2091 pm_runtime_put_sync(host->dev);
2092 pm_runtime_disable(host->dev);
2093 clk_put(host->fclk);
cd03d9a8 2094 if (host->dbclk) {
94c18149 2095 clk_disable_unprepare(host->dbclk);
927ce944 2096 clk_put(host->dbclk);
a45c6cb8
MC		 2097 }
2098
9ea28ecb 2099 omap_hsmmc_gpio_free(host->pdata);
927ce944 2100 iounmap(host->base);
9d1f0286 2101 mmc_free_host(host->mmc);
927ce944 2102
a45c6cb8
MC		 2103 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2104 if (res)
984b203a 2105 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2106
2107 return 0;
2108}
2109
2110#ifdef CONFIG_PM
a48ce884
FB		 2111static int omap_hsmmc_prepare(struct device *dev)
2112{
2113 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2114
2115 if (host->pdata->suspend)
2116 return host->pdata->suspend(dev, host->slot_id);
2117
2118 return 0;
2119}
2120
2121static void omap_hsmmc_complete(struct device *dev)
2122{
2123 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2124
2125 if (host->pdata->resume)
2126 host->pdata->resume(dev, host->slot_id);
2127
2128}
2129
a791daa1 2130static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8 2131{
927ce944 2132 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2133
927ce944 2134 if (!host)
a45c6cb8
MC		 2135 return 0;
2136
927ce944 2137 pm_runtime_get_sync(host->dev);
31f9d463 2138
927ce944
FB		 2139 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2140 omap_hsmmc_disable_irq(host);
2141 OMAP_HSMMC_WRITE(host->base, HCTL,
2142 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2143 }
927ce944 2144
cd03d9a8 2145 if (host->dbclk)
94c18149 2146 clk_disable_unprepare(host->dbclk);
3932afd5 2147
31f9d463 2148 pm_runtime_put_sync(host->dev);
3932afd5 2149 return 0;
a45c6cb8
MC		 2150}
2151
2152/* Routine to resume the MMC device */
a791daa1 2153static int omap_hsmmc_resume(struct device *dev)
a45c6cb8 2154{
927ce944
FB		 2155 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2156
2157 if (!host)
2158 return 0;
a45c6cb8 2159
927ce944 2160 pm_runtime_get_sync(host->dev);
11dd62a7 2161
cd03d9a8 2162 if (host->dbclk)
94c18149 2163 clk_prepare_enable(host->dbclk);
2bec0893 2164
927ce944
FB		 2165 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2166 omap_hsmmc_conf_bus_power(host);
1b331e69 2167
927ce944 2168 omap_hsmmc_protect_card(host);
b62f6228 2169
927ce944
FB		 2170 pm_runtime_mark_last_busy(host->dev);
2171 pm_runtime_put_autosuspend(host->dev);
3932afd5 2172 return 0;
a45c6cb8
MC		 2173}
2174
2175#else
a48ce884
FB		 2176#define omap_hsmmc_prepare NULL
2177#define omap_hsmmc_complete NULL
70a3341a 2178#define omap_hsmmc_suspend NULL
a48ce884 2179#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2180#endif
2181
fa4aa2d4
B		 2182static int omap_hsmmc_runtime_suspend(struct device *dev)
2183{
2184 struct omap_hsmmc_host *host;
2185
2186 host = platform_get_drvdata(to_platform_device(dev));
2187 omap_hsmmc_context_save(host);
927ce944 2188 dev_dbg(dev, "disabled\n");
fa4aa2d4
B		 2189
2190 return 0;
2191}
2192
2193static int omap_hsmmc_runtime_resume(struct device *dev)
2194{
2195 struct omap_hsmmc_host *host;
2196
2197 host = platform_get_drvdata(to_platform_device(dev));
2198 omap_hsmmc_context_restore(host);
927ce944 2199 dev_dbg(dev, "enabled\n");
fa4aa2d4
B		 2200
2201 return 0;
2202}
2203
a791daa1 2204static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2205 .suspend = omap_hsmmc_suspend,
2206 .resume = omap_hsmmc_resume,
a48ce884
FB		 2207 .prepare = omap_hsmmc_prepare,
2208 .complete = omap_hsmmc_complete,
fa4aa2d4
B		 2209 .runtime_suspend = omap_hsmmc_runtime_suspend,
2210 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2211};
2212
2213static struct platform_driver omap_hsmmc_driver = {
efa25fd3 2214 .probe = omap_hsmmc_probe,
0433c143 2215 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2216 .driver = {
2217 .name = DRIVER_NAME,
2218 .owner = THIS_MODULE,
a791daa1 2219 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2220 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2221 },
2222};
2223
b796450b 2224module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2225MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2226MODULE_LICENSE("GPL");
2227MODULE_ALIAS("platform:" DRIVER_NAME);
2228MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)