projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
omap_hsmmc: cater for weird CMD6 behaviour
[linux-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
a45c6cb8
MC		 31#include <linux/io.h>
32#include <linux/semaphore.h>
33#include <mach/dma.h>
34#include <mach/hardware.h>
35#include <mach/board.h>
36#include <mach/mmc.h>
37#include <mach/cpu.h>
38
39/* OMAP HSMMC Host Controller Registers */
40#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 41#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 42#define OMAP_HSMMC_CON 0x002C
43#define OMAP_HSMMC_BLK 0x0104
44#define OMAP_HSMMC_ARG 0x0108
45#define OMAP_HSMMC_CMD 0x010C
46#define OMAP_HSMMC_RSP10 0x0110
47#define OMAP_HSMMC_RSP32 0x0114
48#define OMAP_HSMMC_RSP54 0x0118
49#define OMAP_HSMMC_RSP76 0x011C
50#define OMAP_HSMMC_DATA 0x0120
51#define OMAP_HSMMC_HCTL 0x0128
52#define OMAP_HSMMC_SYSCTL 0x012C
53#define OMAP_HSMMC_STAT 0x0130
54#define OMAP_HSMMC_IE 0x0134
55#define OMAP_HSMMC_ISE 0x0138
56#define OMAP_HSMMC_CAPA 0x0140
57
58#define VS18 (1 << 26)
59#define VS30 (1 << 25)
60#define SDVS18 (0x5 << 9)
61#define SDVS30 (0x6 << 9)
eb250826 62#define SDVS33 (0x7 << 9)
1b331e69 63#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 64#define SDVSCLR 0xFFFFF1FF
65#define SDVSDET 0x00000400
66#define AUTOIDLE 0x1
67#define SDBP (1 << 8)
68#define DTO 0xe
69#define ICE 0x1
70#define ICS 0x2
71#define CEN (1 << 2)
72#define CLKD_MASK 0x0000FFC0
73#define CLKD_SHIFT 6
74#define DTO_MASK 0x000F0000
75#define DTO_SHIFT 16
76#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 77#define BWR_ENABLE (1 << 4)
78#define BRR_ENABLE (1 << 5)
a45c6cb8
MC		 79#define INIT_STREAM (1 << 1)
80#define DP_SELECT (1 << 21)
81#define DDIR (1 << 4)
82#define DMA_EN 0x1
83#define MSBS (1 << 5)
84#define BCE (1 << 1)
85#define FOUR_BIT (1 << 1)
73153010 86#define DW8 (1 << 5)
a45c6cb8
MC		 87#define CC 0x1
88#define TC 0x02
89#define OD 0x1
90#define ERR (1 << 15)
91#define CMD_TIMEOUT (1 << 16)
92#define DATA_TIMEOUT (1 << 20)
93#define CMD_CRC (1 << 17)
94#define DATA_CRC (1 << 21)
95#define CARD_ERR (1 << 28)
96#define STAT_CLEAR 0xFFFFFFFF
97#define INIT_STREAM_CMD 0x00000000
98#define DUAL_VOLT_OCR_BIT 7
99#define SRC (1 << 25)
100#define SRD (1 << 26)
11dd62a7
DK		 101#define SOFTRESET (1 << 1)
102#define RESETDONE (1 << 0)
a45c6cb8
MC		 103
104/*
105 * FIXME: Most likely all the data using these _DEVID defines should come
106 * from the platform_data, or implemented in controller and slot specific
107 * functions.
108 */
109#define OMAP_MMC1_DEVID 0
110#define OMAP_MMC2_DEVID 1
f3e2f1dd 111#define OMAP_MMC3_DEVID 2
a45c6cb8 112
a45c6cb8
MC		 113#define MMC_TIMEOUT_MS 20
114#define OMAP_MMC_MASTER_CLOCK 96000000
115#define DRIVER_NAME "mmci-omap-hs"
116
dd498eff
DK		 117/* Timeouts for entering power saving states on inactivity, msec */
118#define OMAP_MMC_DISABLED_TIMEOUT 100
13189e78
JL		 119#define OMAP_MMC_SLEEP_TIMEOUT 1000
120#define OMAP_MMC_OFF_TIMEOUT 8000
dd498eff 121
a45c6cb8
MC		 122/*
123 * One controller can have multiple slots, like on some omap boards using
124 * omap.c controller driver. Luckily this is not currently done on any known
125 * omap_hsmmc.c device.
126 */
127#define mmc_slot(host) (host->pdata->slots[host->slot_id])
128
129/*
130 * MMC Host controller read/write API's
131 */
132#define OMAP_HSMMC_READ(base, reg) \
133 __raw_readl((base) + OMAP_HSMMC_##reg)
134
135#define OMAP_HSMMC_WRITE(base, reg, val) \
136 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
137
138struct mmc_omap_host {
139 struct device *dev;
140 struct mmc_host *mmc;
141 struct mmc_request *mrq;
142 struct mmc_command *cmd;
143 struct mmc_data *data;
144 struct clk *fclk;
145 struct clk *iclk;
146 struct clk *dbclk;
147 struct semaphore sem;
148 struct work_struct mmc_carddetect_work;
149 void __iomem *base;
150 resource_size_t mapbase;
151 unsigned int id;
152 unsigned int dma_len;
0ccd76d4 153 unsigned int dma_sg_idx;
a45c6cb8 154 unsigned char bus_mode;
a3621465 155 unsigned char power_mode;
a45c6cb8
MC		 156 u32 *buffer;
157 u32 bytesleft;
158 int suspended;
159 int irq;
a45c6cb8 160 int use_dma, dma_ch;
f3e2f1dd 161 int dma_line_tx, dma_line_rx;
a45c6cb8
MC		 162 int slot_id;
163 int dbclk_enabled;
4a694dc9 164 int response_busy;
11dd62a7 165 int context_loss;
dd498eff 166 int dpm_state;
623821f7 167 int vdd;
11dd62a7 168
a45c6cb8
MC		 169 struct omap_mmc_platform_data *pdata;
170};
171
172/*
173 * Stop clock to the card
174 */
175static void omap_mmc_stop_clock(struct mmc_omap_host *host)
176{
177 OMAP_HSMMC_WRITE(host->base, SYSCTL,
178 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
179 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
180 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
181}
182
11dd62a7
DK		 183#ifdef CONFIG_PM
184
185/*
186 * Restore the MMC host context, if it was lost as result of a
187 * power state change.
188 */
189static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
190{
191 struct mmc_ios *ios = &host->mmc->ios;
192 struct omap_mmc_platform_data *pdata = host->pdata;
193 int context_loss = 0;
194 u32 hctl, capa, con;
195 u16 dsor = 0;
196 unsigned long timeout;
197
198 if (pdata->get_context_loss_count) {
199 context_loss = pdata->get_context_loss_count(host->dev);
200 if (context_loss < 0)
201 return 1;
202 }
203
204 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
205 context_loss == host->context_loss ? "not " : "");
206 if (host->context_loss == context_loss)
207 return 1;
208
209 /* Wait for hardware reset */
210 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
211 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
212 && time_before(jiffies, timeout))
213 ;
214
215 /* Do software reset */
216 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
217 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
218 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
219 && time_before(jiffies, timeout))
220 ;
221
222 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
223 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
224
225 if (host->id == OMAP_MMC1_DEVID) {
226 if (host->power_mode != MMC_POWER_OFF &&
227 (1 << ios->vdd) <= MMC_VDD_23_24)
228 hctl = SDVS18;
229 else
230 hctl = SDVS30;
231 capa = VS30 | VS18;
232 } else {
233 hctl = SDVS18;
234 capa = VS18;
235 }
236
237 OMAP_HSMMC_WRITE(host->base, HCTL,
238 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
239
240 OMAP_HSMMC_WRITE(host->base, CAPA,
241 OMAP_HSMMC_READ(host->base, CAPA) | capa);
242
243 OMAP_HSMMC_WRITE(host->base, HCTL,
244 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
245
246 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
247 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
248 && time_before(jiffies, timeout))
249 ;
250
251 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
252 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
253 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
254
255 /* Do not initialize card-specific things if the power is off */
256 if (host->power_mode == MMC_POWER_OFF)
257 goto out;
258
259 con = OMAP_HSMMC_READ(host->base, CON);
260 switch (ios->bus_width) {
261 case MMC_BUS_WIDTH_8:
262 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
263 break;
264 case MMC_BUS_WIDTH_4:
265 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
266 OMAP_HSMMC_WRITE(host->base, HCTL,
267 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
268 break;
269 case MMC_BUS_WIDTH_1:
270 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
271 OMAP_HSMMC_WRITE(host->base, HCTL,
272 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
273 break;
274 }
275
276 if (ios->clock) {
277 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
278 if (dsor < 1)
279 dsor = 1;
280
281 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
282 dsor++;
283
284 if (dsor > 250)
285 dsor = 250;
286 }
287
288 OMAP_HSMMC_WRITE(host->base, SYSCTL,
289 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
290 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
291 OMAP_HSMMC_WRITE(host->base, SYSCTL,
292 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
293
294 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
295 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
296 && time_before(jiffies, timeout))
297 ;
298
299 OMAP_HSMMC_WRITE(host->base, SYSCTL,
300 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
301
302 con = OMAP_HSMMC_READ(host->base, CON);
303 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
304 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
305 else
306 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
307out:
308 host->context_loss = context_loss;
309
310 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
311 return 0;
312}
313
314/*
315 * Save the MMC host context (store the number of power state changes so far).
316 */
317static void omap_mmc_save_ctx(struct mmc_omap_host *host)
318{
319 struct omap_mmc_platform_data *pdata = host->pdata;
320 int context_loss;
321
322 if (pdata->get_context_loss_count) {
323 context_loss = pdata->get_context_loss_count(host->dev);
324 if (context_loss < 0)
325 return;
326 host->context_loss = context_loss;
327 }
328}
329
330#else
331
332static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
333{
334 return 0;
335}
336
337static void omap_mmc_save_ctx(struct mmc_omap_host *host)
338{
339}
340
341#endif
342
a45c6cb8
MC		 343/*
344 * Send init stream sequence to card
345 * before sending IDLE command
346 */
347static void send_init_stream(struct mmc_omap_host *host)
348{
349 int reg = 0;
350 unsigned long timeout;
351
352 disable_irq(host->irq);
353 OMAP_HSMMC_WRITE(host->base, CON,
354 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
355 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
356
357 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
358 while ((reg != CC) && time_before(jiffies, timeout))
359 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
360
361 OMAP_HSMMC_WRITE(host->base, CON,
362 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 363
364 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
365 OMAP_HSMMC_READ(host->base, STAT);
366
a45c6cb8
MC		 367 enable_irq(host->irq);
368}
369
370static inline
371int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
372{
373 int r = 1;
374
191d1f1d
DK		 375 if (mmc_slot(host).get_cover_state)
376 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 377 return r;
378}
379
380static ssize_t
381mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
382 char *buf)
383{
384 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
385 struct mmc_omap_host *host = mmc_priv(mmc);
386
387 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
388 "open");
389}
390
391static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
392
393static ssize_t
394mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
395 char *buf)
396{
397 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
398 struct mmc_omap_host *host = mmc_priv(mmc);
a45c6cb8 399
191d1f1d 400 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 401}
402
403static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
404
405/*
406 * Configure the response type and send the cmd.
407 */
408static void
409mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
410 struct mmc_data *data)
411{
412 int cmdreg = 0, resptype = 0, cmdtype = 0;
413
414 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
415 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
416 host->cmd = cmd;
417
418 /*
419 * Clear status bits and enable interrupts
420 */
421 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
422 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
ccdfe3a6
AG		 423
424 if (host->use_dma)
425 OMAP_HSMMC_WRITE(host->base, IE,
426 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
427 else
428 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8 429
4a694dc9 430 host->response_busy = 0;
a45c6cb8
MC		 431 if (cmd->flags & MMC_RSP_PRESENT) {
432 if (cmd->flags & MMC_RSP_136)
433 resptype = 1;
4a694dc9
AH		 434 else if (cmd->flags & MMC_RSP_BUSY) {
435 resptype = 3;
436 host->response_busy = 1;
437 } else
a45c6cb8
MC		 438 resptype = 2;
439 }
440
441 /*
442 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
443 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
444 * a val of 0x3, rest 0x0.
445 */
446 if (cmd == host->mrq->stop)
447 cmdtype = 0x3;
448
449 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
450
451 if (data) {
452 cmdreg |= DP_SELECT | MSBS | BCE;
453 if (data->flags & MMC_DATA_READ)
454 cmdreg |= DDIR;
455 else
456 cmdreg &= ~(DDIR);
457 }
458
459 if (host->use_dma)
460 cmdreg |= DMA_EN;
461
462 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
463 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
464}
465
0ccd76d4
JY		 466static int
467mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
468{
469 if (data->flags & MMC_DATA_WRITE)
470 return DMA_TO_DEVICE;
471 else
472 return DMA_FROM_DEVICE;
473}
474
a45c6cb8
MC		 475/*
476 * Notify the transfer complete to MMC core
477 */
478static void
479mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
480{
4a694dc9
AH		 481 if (!data) {
482 struct mmc_request *mrq = host->mrq;
483
23050103
AH		 484 /* TC before CC from CMD6 - don't know why, but it happens */
485 if (host->cmd && host->cmd->opcode == 6 &&
486 host->response_busy) {
487 host->response_busy = 0;
488 return;
489 }
490
4a694dc9 491 host->mrq = NULL;
4a694dc9
AH		 492 mmc_request_done(host->mmc, mrq);
493 return;
494 }
495
a45c6cb8
MC		 496 host->data = NULL;
497
498 if (host->use_dma && host->dma_ch != -1)
499 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
0ccd76d4 500 mmc_omap_get_dma_dir(host, data));
a45c6cb8
MC		 501
502 if (!data->error)
503 data->bytes_xfered += data->blocks * (data->blksz);
504 else
505 data->bytes_xfered = 0;
506
507 if (!data->stop) {
508 host->mrq = NULL;
509 mmc_request_done(host->mmc, data->mrq);
510 return;
511 }
512 mmc_omap_start_command(host, data->stop, NULL);
513}
514
515/*
516 * Notify the core about command completion
517 */
518static void
519mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
520{
521 host->cmd = NULL;
522
523 if (cmd->flags & MMC_RSP_PRESENT) {
524 if (cmd->flags & MMC_RSP_136) {
525 /* response type 2 */
526 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
527 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
528 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
529 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
530 } else {
531 /* response types 1, 1b, 3, 4, 5, 6 */
532 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
533 }
534 }
4a694dc9 535 if ((host->data == NULL && !host->response_busy) || cmd->error) {
a45c6cb8
MC		 536 host->mrq = NULL;
537 mmc_request_done(host->mmc, cmd->mrq);
538 }
539}
540
541/*
542 * DMA clean up for command errors
543 */
82788ff5 544static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
a45c6cb8 545{
82788ff5 546 host->data->error = errno;
a45c6cb8
MC		 547
548 if (host->use_dma && host->dma_ch != -1) {
549 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
0ccd76d4 550 mmc_omap_get_dma_dir(host, host->data));
a45c6cb8
MC		 551 omap_free_dma(host->dma_ch);
552 host->dma_ch = -1;
553 up(&host->sem);
554 }
555 host->data = NULL;
a45c6cb8
MC		 556}
557
558/*
559 * Readable error output
560 */
561#ifdef CONFIG_MMC_DEBUG
562static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
563{
564 /* --- means reserved bit without definition at documentation */
565 static const char *mmc_omap_status_bits[] = {
566 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
567 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
568 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
569 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
570 };
571 char res[256];
572 char *buf = res;
573 int len, i;
574
575 len = sprintf(buf, "MMC IRQ 0x%x :", status);
576 buf += len;
577
578 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
579 if (status & (1 << i)) {
580 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
581 buf += len;
582 }
583
584 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
585}
586#endif /* CONFIG_MMC_DEBUG */
587
3ebf74b1
JP		 588/*
589 * MMC controller internal state machines reset
590 *
591 * Used to reset command or data internal state machines, using respectively
592 * SRC or SRD bit of SYSCTL register
593 * Can be called from interrupt context
594 */
595static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
596 unsigned long bit)
597{
598 unsigned long i = 0;
599 unsigned long limit = (loops_per_jiffy *
600 msecs_to_jiffies(MMC_TIMEOUT_MS));
601
602 OMAP_HSMMC_WRITE(host->base, SYSCTL,
603 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
604
605 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
606 (i++ < limit))
607 cpu_relax();
608
609 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
610 dev_err(mmc_dev(host->mmc),
611 "Timeout waiting on controller reset in %s\n",
612 __func__);
613}
a45c6cb8
MC		 614
615/*
616 * MMC controller IRQ handler
617 */
618static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
619{
620 struct mmc_omap_host *host = dev_id;
621 struct mmc_data *data;
622 int end_cmd = 0, end_trans = 0, status;
623
4a694dc9 624 if (host->mrq == NULL) {
a45c6cb8
MC		 625 OMAP_HSMMC_WRITE(host->base, STAT,
626 OMAP_HSMMC_READ(host->base, STAT));
00adadc1
KH		 627 /* Flush posted write */
628 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8
MC		 629 return IRQ_HANDLED;
630 }
631
632 data = host->data;
633 status = OMAP_HSMMC_READ(host->base, STAT);
634 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
635
636 if (status & ERR) {
637#ifdef CONFIG_MMC_DEBUG
638 mmc_omap_report_irq(host, status);
639#endif
640 if ((status & CMD_TIMEOUT) ||
641 (status & CMD_CRC)) {
642 if (host->cmd) {
643 if (status & CMD_TIMEOUT) {
191d1f1d
DK		 644 mmc_omap_reset_controller_fsm(host,
645 SRC);
a45c6cb8
MC		 646 host->cmd->error = -ETIMEDOUT;
647 } else {
648 host->cmd->error = -EILSEQ;
649 }
650 end_cmd = 1;
651 }
4a694dc9
AH		 652 if (host->data || host->response_busy) {
653 if (host->data)
654 mmc_dma_cleanup(host, -ETIMEDOUT);
655 host->response_busy = 0;
3ebf74b1 656 mmc_omap_reset_controller_fsm(host, SRD);
c232f457 657 }
a45c6cb8
MC		 658 }
659 if ((status & DATA_TIMEOUT) ||
660 (status & DATA_CRC)) {
4a694dc9
AH		 661 if (host->data || host->response_busy) {
662 int err = (status & DATA_TIMEOUT) ?
663 -ETIMEDOUT : -EILSEQ;
664
665 if (host->data)
666 mmc_dma_cleanup(host, err);
a45c6cb8 667 else
4a694dc9
AH		 668 host->mrq->cmd->error = err;
669 host->response_busy = 0;
3ebf74b1 670 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 671 end_trans = 1;
672 }
673 }
674 if (status & CARD_ERR) {
675 dev_dbg(mmc_dev(host->mmc),
676 "Ignoring card err CMD%d\n", host->cmd->opcode);
677 if (host->cmd)
678 end_cmd = 1;
679 if (host->data)
680 end_trans = 1;
681 }
682 }
683
684 OMAP_HSMMC_WRITE(host->base, STAT, status);
00adadc1
KH		 685 /* Flush posted write */
686 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8 687
a8fe29d8 688 if (end_cmd || ((status & CC) && host->cmd))
a45c6cb8 689 mmc_omap_cmd_done(host, host->cmd);
0a40e647 690 if ((end_trans || (status & TC)) && host->mrq)
a45c6cb8
MC		 691 mmc_omap_xfer_done(host, data);
692
693 return IRQ_HANDLED;
694}
695
e13bb300
AH		 696static void set_sd_bus_power(struct mmc_omap_host *host)
697{
698 unsigned long i;
699
700 OMAP_HSMMC_WRITE(host->base, HCTL,
701 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
702 for (i = 0; i < loops_per_jiffy; i++) {
703 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
704 break;
705 cpu_relax();
706 }
707}
708
a45c6cb8 709/*
eb250826
DB		 710 * Switch MMC interface voltage ... only relevant for MMC1.
711 *
712 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
713 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
714 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8
MC		 715 */
716static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
717{
718 u32 reg_val = 0;
719 int ret;
720
721 /* Disable the clocks */
722 clk_disable(host->fclk);
723 clk_disable(host->iclk);
724 clk_disable(host->dbclk);
725
726 /* Turn the power off */
727 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
728 if (ret != 0)
729 goto err;
730
731 /* Turn the power ON with given VDD 1.8 or 3.0v */
732 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
733 if (ret != 0)
734 goto err;
735
736 clk_enable(host->fclk);
737 clk_enable(host->iclk);
738 clk_enable(host->dbclk);
739
740 OMAP_HSMMC_WRITE(host->base, HCTL,
741 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
742 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 743
a45c6cb8
MC		 744 /*
745 * If a MMC dual voltage card is detected, the set_ios fn calls
746 * this fn with VDD bit set for 1.8V. Upon card removal from the
747 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
748 *
eb250826
DB		 749 * Cope with a bit of slop in the range ... per data sheets:
750 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
751 * but recommended values are 1.71V to 1.89V
752 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
753 * but recommended values are 2.7V to 3.3V
754 *
755 * Board setup code shouldn't permit anything very out-of-range.
756 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
757 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 758 */
eb250826 759 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 760 reg_val |= SDVS18;
eb250826
DB		 761 else
762 reg_val |= SDVS30;
a45c6cb8
MC		 763
764 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 765 set_sd_bus_power(host);
a45c6cb8
MC		 766
767 return 0;
768err:
769 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
770 return ret;
771}
772
773/*
774 * Work Item to notify the core about card insertion/removal
775 */
776static void mmc_omap_detect(struct work_struct *work)
777{
778 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
779 mmc_carddetect_work);
249d0fa9 780 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 781 int carddetect;
782
783 if (host->suspended)
784 return;
785
786 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 787
191d1f1d 788 if (slot->card_detect)
a6b2240d 789 carddetect = slot->card_detect(slot->card_detect_irq);
e1a55f5e 790 else
a6b2240d 791 carddetect = -ENOSYS;
a45c6cb8 792
a6b2240d 793 if (carddetect) {
a45c6cb8
MC		 794 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
795 } else {
5e2ea617 796 mmc_host_enable(host->mmc);
3ebf74b1 797 mmc_omap_reset_controller_fsm(host, SRD);
5e2ea617 798 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 799 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
800 }
801}
802
803/*
804 * ISR for handling card insertion and removal
805 */
806static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
807{
808 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
809
a6b2240d
AH		 810 if (host->suspended)
811 return IRQ_HANDLED;
a45c6cb8
MC		 812 schedule_work(&host->mmc_carddetect_work);
813
814 return IRQ_HANDLED;
815}
816
0ccd76d4
JY		 817static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
818 struct mmc_data *data)
819{
820 int sync_dev;
821
f3e2f1dd
GI		 822 if (data->flags & MMC_DATA_WRITE)
823 sync_dev = host->dma_line_tx;
824 else
825 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 826 return sync_dev;
827}
828
829static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
830 struct mmc_data *data,
831 struct scatterlist *sgl)
832{
833 int blksz, nblk, dma_ch;
834
835 dma_ch = host->dma_ch;
836 if (data->flags & MMC_DATA_WRITE) {
837 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
838 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
839 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
840 sg_dma_address(sgl), 0, 0);
841 } else {
842 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 843 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 844 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
845 sg_dma_address(sgl), 0, 0);
846 }
847
848 blksz = host->data->blksz;
849 nblk = sg_dma_len(sgl) / blksz;
850
851 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
852 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
853 mmc_omap_get_dma_sync_dev(host, data),
854 !(data->flags & MMC_DATA_WRITE));
855
856 omap_start_dma(dma_ch);
857}
858
a45c6cb8
MC		 859/*
860 * DMA call back function
861 */
862static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
863{
864 struct mmc_omap_host *host = data;
865
866 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
867 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
868
869 if (host->dma_ch < 0)
870 return;
871
0ccd76d4
JY		 872 host->dma_sg_idx++;
873 if (host->dma_sg_idx < host->dma_len) {
874 /* Fire up the next transfer. */
875 mmc_omap_config_dma_params(host, host->data,
876 host->data->sg + host->dma_sg_idx);
877 return;
878 }
879
a45c6cb8
MC		 880 omap_free_dma(host->dma_ch);
881 host->dma_ch = -1;
882 /*
883 * DMA Callback: run in interrupt context.
85b84322 884 * mutex_unlock will throw a kernel warning if used.
a45c6cb8
MC		 885 */
886 up(&host->sem);
887}
888
a45c6cb8
MC		 889/*
890 * Routine to configure and start DMA for the MMC card
891 */
892static int
893mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
894{
0ccd76d4 895 int dma_ch = 0, ret = 0, err = 1, i;
a45c6cb8
MC		 896 struct mmc_data *data = req->data;
897
0ccd76d4 898 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 899 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 900 struct scatterlist *sgl;
901
902 sgl = data->sg + i;
903 if (sgl->length % data->blksz)
904 return -EINVAL;
905 }
906 if ((data->blksz % 4) != 0)
907 /* REVISIT: The MMC buffer increments only when MSB is written.
908 * Return error for blksz which is non multiple of four.
909 */
910 return -EINVAL;
911
a45c6cb8
MC		 912 /*
913 * If for some reason the DMA transfer is still active,
914 * we wait for timeout period and free the dma
915 */
916 if (host->dma_ch != -1) {
917 set_current_state(TASK_UNINTERRUPTIBLE);
918 schedule_timeout(100);
919 if (down_trylock(&host->sem)) {
920 omap_free_dma(host->dma_ch);
921 host->dma_ch = -1;
922 up(&host->sem);
923 return err;
924 }
925 } else {
926 if (down_trylock(&host->sem))
927 return err;
928 }
929
0ccd76d4 930 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
191d1f1d 931 mmc_omap_dma_cb, host, &dma_ch);
a45c6cb8 932 if (ret != 0) {
0ccd76d4 933 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 934 "%s: omap_request_dma() failed with %d\n",
935 mmc_hostname(host->mmc), ret);
936 return ret;
937 }
938
939 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
0ccd76d4 940 data->sg_len, mmc_omap_get_dma_dir(host, data));
a45c6cb8 941 host->dma_ch = dma_ch;
0ccd76d4 942 host->dma_sg_idx = 0;
a45c6cb8 943
0ccd76d4 944 mmc_omap_config_dma_params(host, data, data->sg);
a45c6cb8 945
a45c6cb8
MC		 946 return 0;
947}
948
949static void set_data_timeout(struct mmc_omap_host *host,
950 struct mmc_request *req)
951{
952 unsigned int timeout, cycle_ns;
953 uint32_t reg, clkd, dto = 0;
954
955 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
956 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
957 if (clkd == 0)
958 clkd = 1;
959
960 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
961 timeout = req->data->timeout_ns / cycle_ns;
962 timeout += req->data->timeout_clks;
963 if (timeout) {
964 while ((timeout & 0x80000000) == 0) {
965 dto += 1;
966 timeout <<= 1;
967 }
968 dto = 31 - dto;
969 timeout <<= 1;
970 if (timeout && dto)
971 dto += 1;
972 if (dto >= 13)
973 dto -= 13;
974 else
975 dto = 0;
976 if (dto > 14)
977 dto = 14;
978 }
979
980 reg &= ~DTO_MASK;
981 reg |= dto << DTO_SHIFT;
982 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
983}
984
985/*
986 * Configure block length for MMC/SD cards and initiate the transfer.
987 */
988static int
989mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
990{
991 int ret;
992 host->data = req->data;
993
994 if (req->data == NULL) {
a45c6cb8
MC		 995 OMAP_HSMMC_WRITE(host->base, BLK, 0);
996 return 0;
997 }
998
999 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1000 | (req->data->blocks << 16));
1001 set_data_timeout(host, req);
1002
a45c6cb8
MC		 1003 if (host->use_dma) {
1004 ret = mmc_omap_start_dma_transfer(host, req);
1005 if (ret != 0) {
1006 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1007 return ret;
1008 }
1009 }
1010 return 0;
1011}
1012
1013/*
1014 * Request function. for read/write operation
1015 */
1016static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
1017{
1018 struct mmc_omap_host *host = mmc_priv(mmc);
a3f406f8 1019 int err;
a45c6cb8
MC		 1020
1021 WARN_ON(host->mrq != NULL);
1022 host->mrq = req;
a3f406f8
JL		 1023 err = mmc_omap_prepare_data(host, req);
1024 if (err) {
1025 req->cmd->error = err;
1026 if (req->data)
1027 req->data->error = err;
1028 host->mrq = NULL;
1029 mmc_request_done(mmc, req);
1030 return;
1031 }
1032
a45c6cb8
MC		 1033 mmc_omap_start_command(host, req->cmd, req->data);
1034}
1035
1036
1037/* Routine to configure clock values. Exposed API to core */
1038static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1039{
1040 struct mmc_omap_host *host = mmc_priv(mmc);
1041 u16 dsor = 0;
1042 unsigned long regval;
1043 unsigned long timeout;
73153010 1044 u32 con;
a3621465 1045 int do_send_init_stream = 0;
a45c6cb8 1046
5e2ea617
AH		 1047 mmc_host_enable(host->mmc);
1048
a3621465
AH		 1049 if (ios->power_mode != host->power_mode) {
1050 switch (ios->power_mode) {
1051 case MMC_POWER_OFF:
1052 mmc_slot(host).set_power(host->dev, host->slot_id,
1053 0, 0);
623821f7 1054 host->vdd = 0;
a3621465
AH		 1055 break;
1056 case MMC_POWER_UP:
1057 mmc_slot(host).set_power(host->dev, host->slot_id,
1058 1, ios->vdd);
623821f7 1059 host->vdd = ios->vdd;
a3621465
AH		 1060 break;
1061 case MMC_POWER_ON:
1062 do_send_init_stream = 1;
1063 break;
1064 }
1065 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1066 }
1067
dd498eff
DK		 1068 /* FIXME: set registers based only on changes to ios */
1069
73153010 1070 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1071 switch (mmc->ios.bus_width) {
73153010
JL		 1072 case MMC_BUS_WIDTH_8:
1073 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1074 break;
a45c6cb8 1075 case MMC_BUS_WIDTH_4:
73153010 1076 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1077 OMAP_HSMMC_WRITE(host->base, HCTL,
1078 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1079 break;
1080 case MMC_BUS_WIDTH_1:
73153010 1081 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1082 OMAP_HSMMC_WRITE(host->base, HCTL,
1083 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1084 break;
1085 }
1086
1087 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 1088 /* Only MMC1 can interface at 3V without some flavor
1089 * of external transceiver; but they all handle 1.8V.
1090 */
a45c6cb8
MC		 1091 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1092 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1093 /*
1094 * The mmc_select_voltage fn of the core does
1095 * not seem to set the power_mode to
1096 * MMC_POWER_UP upon recalculating the voltage.
1097 * vdd 1.8v.
1098 */
1099 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
1100 dev_dbg(mmc_dev(host->mmc),
1101 "Switch operation failed\n");
1102 }
1103 }
1104
1105 if (ios->clock) {
1106 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1107 if (dsor < 1)
1108 dsor = 1;
1109
1110 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1111 dsor++;
1112
1113 if (dsor > 250)
1114 dsor = 250;
1115 }
1116 omap_mmc_stop_clock(host);
1117 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1118 regval = regval & ~(CLKD_MASK);
1119 regval = regval | (dsor << 6) | (DTO << 16);
1120 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1121 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1122 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1123
1124 /* Wait till the ICS bit is set */
1125 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1126 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1127 && time_before(jiffies, timeout))
1128 msleep(1);
1129
1130 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1131 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1132
a3621465 1133 if (do_send_init_stream)
a45c6cb8
MC		 1134 send_init_stream(host);
1135
abb28e73 1136 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1137 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1138 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1139 else
1140 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1141
dd498eff
DK		 1142 if (host->power_mode == MMC_POWER_OFF)
1143 mmc_host_disable(host->mmc);
1144 else
1145 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1146}
1147
1148static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1149{
1150 struct mmc_omap_host *host = mmc_priv(mmc);
a45c6cb8 1151
191d1f1d 1152 if (!mmc_slot(host).card_detect)
a45c6cb8 1153 return -ENOSYS;
191d1f1d 1154 return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq);
a45c6cb8
MC		 1155}
1156
1157static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1158{
1159 struct mmc_omap_host *host = mmc_priv(mmc);
a45c6cb8 1160
191d1f1d 1161 if (!mmc_slot(host).get_ro)
a45c6cb8 1162 return -ENOSYS;
191d1f1d 1163 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1164}
1165
1b331e69
KK		 1166static void omap_hsmmc_init(struct mmc_omap_host *host)
1167{
1168 u32 hctl, capa, value;
1169
1170 /* Only MMC1 supports 3.0V */
1171 if (host->id == OMAP_MMC1_DEVID) {
1172 hctl = SDVS30;
1173 capa = VS30 | VS18;
1174 } else {
1175 hctl = SDVS18;
1176 capa = VS18;
1177 }
1178
1179 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1180 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1181
1182 value = OMAP_HSMMC_READ(host->base, CAPA);
1183 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1184
1185 /* Set the controller to AUTO IDLE mode */
1186 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1187 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1188
1189 /* Set SD bus power bit */
e13bb300 1190 set_sd_bus_power(host);
1b331e69
KK		 1191}
1192
dd498eff
DK		 1193/*
1194 * Dynamic power saving handling, FSM:
13189e78
JL		 1195 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1196 * ^___________| | |
1197 * |______________________|______________________|
dd498eff
DK		 1198 *
1199 * ENABLED: mmc host is fully functional
1200 * DISABLED: fclk is off
13189e78
JL		 1201 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1202 * REGSLEEP: fclk is off, voltage regulator is asleep
1203 * OFF: fclk is off, voltage regulator is off
dd498eff
DK		 1204 *
1205 * Transition handlers return the timeout for the next state transition
1206 * or negative error.
1207 */
1208
13189e78 1209enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
dd498eff
DK		 1210
1211/* Handler for [ENABLED -> DISABLED] transition */
1212static int omap_mmc_enabled_to_disabled(struct mmc_omap_host *host)
1213{
1214 omap_mmc_save_ctx(host);
1215 clk_disable(host->fclk);
1216 host->dpm_state = DISABLED;
1217
1218 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1219
1220 if (host->power_mode == MMC_POWER_OFF)
1221 return 0;
1222
13189e78 1223 return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
dd498eff
DK		 1224}
1225
13189e78
JL		 1226/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1227static int omap_mmc_disabled_to_sleep(struct mmc_omap_host *host)
dd498eff 1228{
13189e78 1229 int err, new_state;
dd498eff
DK		 1230
1231 if (!mmc_try_claim_host(host->mmc))
1232 return 0;
1233
1234 clk_enable(host->fclk);
dd498eff 1235 omap_mmc_restore_ctx(host);
13189e78
JL		 1236 if (mmc_card_can_sleep(host->mmc)) {
1237 err = mmc_card_sleep(host->mmc);
1238 if (err < 0) {
1239 clk_disable(host->fclk);
1240 mmc_release_host(host->mmc);
1241 return err;
1242 }
1243 new_state = CARDSLEEP;
1244 } else
1245 new_state = REGSLEEP;
1246 if (mmc_slot(host).set_sleep)
1247 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1248 new_state == CARDSLEEP);
1249 /* FIXME: turn off bus power and perhaps interrupts too */
1250 clk_disable(host->fclk);
1251 host->dpm_state = new_state;
1252
1253 mmc_release_host(host->mmc);
1254
1255 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1256 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1257
1258 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1259 mmc_slot(host).card_detect ||
1260 (mmc_slot(host).get_cover_state &&
13189e78
JL		 1261 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1262 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1263
1264 return 0;
1265}
1266
1267/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1268static int omap_mmc_sleep_to_off(struct mmc_omap_host *host)
1269{
1270 if (!mmc_try_claim_host(host->mmc))
1271 return 0;
1272
1273 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1274 mmc_slot(host).card_detect ||
1275 (mmc_slot(host).get_cover_state &&
1276 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1277 mmc_release_host(host->mmc);
1278 return 0;
623821f7 1279 }
dd498eff 1280
13189e78
JL		 1281 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1282 host->vdd = 0;
1283 host->power_mode = MMC_POWER_OFF;
dd498eff 1284
13189e78
JL		 1285 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1286 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1287
13189e78 1288 host->dpm_state = OFF;
dd498eff
DK		 1289
1290 mmc_release_host(host->mmc);
1291
1292 return 0;
1293}
1294
1295/* Handler for [DISABLED -> ENABLED] transition */
1296static int omap_mmc_disabled_to_enabled(struct mmc_omap_host *host)
1297{
1298 int err;
1299
1300 err = clk_enable(host->fclk);
1301 if (err < 0)
1302 return err;
1303
1304 omap_mmc_restore_ctx(host);
1305
1306 host->dpm_state = ENABLED;
1307
1308 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1309
1310 return 0;
1311}
1312
13189e78
JL		 1313/* Handler for [SLEEP -> ENABLED] transition */
1314static int omap_mmc_sleep_to_enabled(struct mmc_omap_host *host)
dd498eff 1315{
13189e78
JL		 1316 if (!mmc_try_claim_host(host->mmc))
1317 return 0;
dd498eff 1318
13189e78 1319 clk_enable(host->fclk);
dd498eff 1320 omap_mmc_restore_ctx(host);
13189e78
JL		 1321 if (mmc_slot(host).set_sleep)
1322 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1323 host->vdd, host->dpm_state == CARDSLEEP);
1324 if (mmc_card_can_sleep(host->mmc))
1325 mmc_card_awake(host->mmc);
1326
1327 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1328 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1329
1330 host->dpm_state = ENABLED;
1331
13189e78 1332 mmc_release_host(host->mmc);
dd498eff
DK		 1333
1334 return 0;
1335}
1336
13189e78
JL		 1337/* Handler for [OFF -> ENABLED] transition */
1338static int omap_mmc_off_to_enabled(struct mmc_omap_host *host)
623821f7 1339{
623821f7 1340 clk_enable(host->fclk);
623821f7
AH		 1341
1342 omap_mmc_restore_ctx(host);
13189e78
JL		 1343 omap_hsmmc_init(host);
1344 mmc_power_restore_host(host->mmc);
623821f7
AH		 1345
1346 host->dpm_state = ENABLED;
1347
13189e78
JL		 1348 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1349
623821f7
AH		 1350 return 0;
1351}
1352
dd498eff
DK		 1353/*
1354 * Bring MMC host to ENABLED from any other PM state.
1355 */
1356static int omap_mmc_enable(struct mmc_host *mmc)
1357{
1358 struct mmc_omap_host *host = mmc_priv(mmc);
1359
1360 switch (host->dpm_state) {
1361 case DISABLED:
1362 return omap_mmc_disabled_to_enabled(host);
13189e78 1363 case CARDSLEEP:
623821f7 1364 case REGSLEEP:
13189e78 1365 return omap_mmc_sleep_to_enabled(host);
dd498eff
DK		 1366 case OFF:
1367 return omap_mmc_off_to_enabled(host);
1368 default:
1369 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1370 return -EINVAL;
1371 }
1372}
1373
1374/*
1375 * Bring MMC host in PM state (one level deeper).
1376 */
1377static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
1378{
1379 struct mmc_omap_host *host = mmc_priv(mmc);
1380
1381 switch (host->dpm_state) {
1382 case ENABLED: {
1383 int delay;
1384
1385 delay = omap_mmc_enabled_to_disabled(host);
1386 if (lazy || delay < 0)
1387 return delay;
1388 return 0;
1389 }
1390 case DISABLED:
13189e78
JL		 1391 return omap_mmc_disabled_to_sleep(host);
1392 case CARDSLEEP:
1393 case REGSLEEP:
1394 return omap_mmc_sleep_to_off(host);
dd498eff
DK		 1395 default:
1396 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1397 return -EINVAL;
1398 }
1399}
1400
1401static int omap_mmc_enable_fclk(struct mmc_host *mmc)
1402{
1403 struct mmc_omap_host *host = mmc_priv(mmc);
1404 int err;
1405
1406 err = clk_enable(host->fclk);
1407 if (err)
1408 return err;
1409 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1410 omap_mmc_restore_ctx(host);
1411 return 0;
1412}
1413
1414static int omap_mmc_disable_fclk(struct mmc_host *mmc, int lazy)
1415{
1416 struct mmc_omap_host *host = mmc_priv(mmc);
1417
1418 omap_mmc_save_ctx(host);
1419 clk_disable(host->fclk);
1420 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1421 return 0;
1422}
1423
1424static const struct mmc_host_ops mmc_omap_ops = {
1425 .enable = omap_mmc_enable_fclk,
1426 .disable = omap_mmc_disable_fclk,
1427 .request = omap_mmc_request,
1428 .set_ios = omap_mmc_set_ios,
1429 .get_cd = omap_hsmmc_get_cd,
1430 .get_ro = omap_hsmmc_get_ro,
1431 /* NYET -- enable_sdio_irq */
1432};
1433
1434static const struct mmc_host_ops mmc_omap_ps_ops = {
5e2ea617
AH		 1435 .enable = omap_mmc_enable,
1436 .disable = omap_mmc_disable,
a45c6cb8
MC		 1437 .request = omap_mmc_request,
1438 .set_ios = omap_mmc_set_ios,
1439 .get_cd = omap_hsmmc_get_cd,
1440 .get_ro = omap_hsmmc_get_ro,
1441 /* NYET -- enable_sdio_irq */
1442};
1443
d900f712
DK		 1444#ifdef CONFIG_DEBUG_FS
1445
1446static int mmc_regs_show(struct seq_file *s, void *data)
1447{
1448 struct mmc_host *mmc = s->private;
1449 struct mmc_omap_host *host = mmc_priv(mmc);
11dd62a7
DK		 1450 struct omap_mmc_platform_data *pdata = host->pdata;
1451 int context_loss = 0;
1452
1453 if (pdata->get_context_loss_count)
1454 context_loss = pdata->get_context_loss_count(host->dev);
d900f712 1455
5e2ea617
AH		 1456 seq_printf(s, "mmc%d:\n"
1457 " enabled:\t%d\n"
dd498eff 1458 " dpm_state:\t%d\n"
5e2ea617 1459 " nesting_cnt:\t%d\n"
11dd62a7 1460 " ctx_loss:\t%d:%d\n"
5e2ea617 1461 "\nregs:\n",
dd498eff
DK		 1462 mmc->index, mmc->enabled ? 1 : 0,
1463 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1464 host->context_loss, context_loss);
5e2ea617 1465
13189e78 1466 if (host->suspended || host->dpm_state == OFF) {
dd498eff
DK		 1467 seq_printf(s, "host suspended, can't read registers\n");
1468 return 0;
1469 }
1470
5e2ea617
AH		 1471 if (clk_enable(host->fclk) != 0) {
1472 seq_printf(s, "can't read the regs\n");
dd498eff 1473 return 0;
5e2ea617 1474 }
d900f712
DK		 1475
1476 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1477 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1478 seq_printf(s, "CON:\t\t0x%08x\n",
1479 OMAP_HSMMC_READ(host->base, CON));
1480 seq_printf(s, "HCTL:\t\t0x%08x\n",
1481 OMAP_HSMMC_READ(host->base, HCTL));
1482 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1483 OMAP_HSMMC_READ(host->base, SYSCTL));
1484 seq_printf(s, "IE:\t\t0x%08x\n",
1485 OMAP_HSMMC_READ(host->base, IE));
1486 seq_printf(s, "ISE:\t\t0x%08x\n",
1487 OMAP_HSMMC_READ(host->base, ISE));
1488 seq_printf(s, "CAPA:\t\t0x%08x\n",
1489 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1490
1491 clk_disable(host->fclk);
dd498eff 1492
d900f712
DK		 1493 return 0;
1494}
1495
1496static int mmc_regs_open(struct inode *inode, struct file *file)
1497{
1498 return single_open(file, mmc_regs_show, inode->i_private);
1499}
1500
1501static const struct file_operations mmc_regs_fops = {
1502 .open = mmc_regs_open,
1503 .read = seq_read,
1504 .llseek = seq_lseek,
1505 .release = single_release,
1506};
1507
1508static void omap_mmc_debugfs(struct mmc_host *mmc)
1509{
1510 if (mmc->debugfs_root)
1511 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1512 mmc, &mmc_regs_fops);
1513}
1514
1515#else
1516
1517static void omap_mmc_debugfs(struct mmc_host *mmc)
1518{
1519}
1520
1521#endif
1522
a45c6cb8
MC		 1523static int __init omap_mmc_probe(struct platform_device *pdev)
1524{
1525 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1526 struct mmc_host *mmc;
1527 struct mmc_omap_host *host = NULL;
1528 struct resource *res;
1529 int ret = 0, irq;
a45c6cb8
MC		 1530
1531 if (pdata == NULL) {
1532 dev_err(&pdev->dev, "Platform Data is missing\n");
1533 return -ENXIO;
1534 }
1535
1536 if (pdata->nr_slots == 0) {
1537 dev_err(&pdev->dev, "No Slots\n");
1538 return -ENXIO;
1539 }
1540
1541 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1542 irq = platform_get_irq(pdev, 0);
1543 if (res == NULL || irq < 0)
1544 return -ENXIO;
1545
1546 res = request_mem_region(res->start, res->end - res->start + 1,
1547 pdev->name);
1548 if (res == NULL)
1549 return -EBUSY;
1550
1551 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1552 if (!mmc) {
1553 ret = -ENOMEM;
1554 goto err;
1555 }
1556
1557 host = mmc_priv(mmc);
1558 host->mmc = mmc;
1559 host->pdata = pdata;
1560 host->dev = &pdev->dev;
1561 host->use_dma = 1;
1562 host->dev->dma_mask = &pdata->dma_mask;
1563 host->dma_ch = -1;
1564 host->irq = irq;
1565 host->id = pdev->id;
1566 host->slot_id = 0;
1567 host->mapbase = res->start;
1568 host->base = ioremap(host->mapbase, SZ_4K);
a3621465 1569 host->power_mode = -1;
a45c6cb8
MC		 1570
1571 platform_set_drvdata(pdev, host);
1572 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1573
191d1f1d 1574 if (mmc_slot(host).power_saving)
dd498eff
DK		 1575 mmc->ops = &mmc_omap_ps_ops;
1576 else
1577 mmc->ops = &mmc_omap_ops;
1578
a45c6cb8
MC		 1579 mmc->f_min = 400000;
1580 mmc->f_max = 52000000;
1581
1582 sema_init(&host->sem, 1);
1583
6f7607cc 1584 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 1585 if (IS_ERR(host->iclk)) {
1586 ret = PTR_ERR(host->iclk);
1587 host->iclk = NULL;
1588 goto err1;
1589 }
6f7607cc 1590 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1591 if (IS_ERR(host->fclk)) {
1592 ret = PTR_ERR(host->fclk);
1593 host->fclk = NULL;
1594 clk_put(host->iclk);
1595 goto err1;
1596 }
1597
11dd62a7
DK		 1598 omap_mmc_save_ctx(host);
1599
5e2ea617 1600 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 1601 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
1602 /* we start off in DISABLED state */
1603 host->dpm_state = DISABLED;
1604
5e2ea617 1605 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 1606 clk_put(host->iclk);
1607 clk_put(host->fclk);
1608 goto err1;
1609 }
1610
1611 if (clk_enable(host->iclk) != 0) {
5e2ea617 1612 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1613 clk_put(host->iclk);
1614 clk_put(host->fclk);
1615 goto err1;
1616 }
1617
1618 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1619 /*
1620 * MMC can still work without debounce clock.
1621 */
1622 if (IS_ERR(host->dbclk))
1623 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1624 else
1625 if (clk_enable(host->dbclk) != 0)
1626 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1627 " clk failed\n");
1628 else
1629 host->dbclk_enabled = 1;
1630
0ccd76d4
JY		 1631 /* Since we do only SG emulation, we can have as many segs
1632 * as we want. */
1633 mmc->max_phys_segs = 1024;
1634 mmc->max_hw_segs = 1024;
1635
a45c6cb8
MC		 1636 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1637 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1638 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1639 mmc->max_seg_size = mmc->max_req_size;
1640
13189e78
JL		 1641 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1642 MMC_CAP_WAIT_WHILE_BUSY;
a45c6cb8 1643
191d1f1d 1644 if (mmc_slot(host).wires >= 8)
73153010 1645 mmc->caps |= MMC_CAP_8_BIT_DATA;
191d1f1d 1646 else if (mmc_slot(host).wires >= 4)
a45c6cb8
MC		 1647 mmc->caps |= MMC_CAP_4_BIT_DATA;
1648
191d1f1d 1649 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1650 mmc->caps |= MMC_CAP_NONREMOVABLE;
1651
1b331e69 1652 omap_hsmmc_init(host);
a45c6cb8 1653
f3e2f1dd
GI		 1654 /* Select DMA lines */
1655 switch (host->id) {
1656 case OMAP_MMC1_DEVID:
1657 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1658 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1659 break;
1660 case OMAP_MMC2_DEVID:
1661 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1662 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1663 break;
1664 case OMAP_MMC3_DEVID:
1665 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1666 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1667 break;
1668 default:
1669 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1670 goto err_irq;
1671 }
a45c6cb8
MC		 1672
1673 /* Request IRQ for MMC operations */
1674 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1675 mmc_hostname(mmc), host);
1676 if (ret) {
1677 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1678 goto err_irq;
1679 }
1680
b583f26d 1681 /* initialize power supplies, gpios, etc */
a45c6cb8
MC		 1682 if (pdata->init != NULL) {
1683 if (pdata->init(&pdev->dev) != 0) {
b583f26d 1684 dev_dbg(mmc_dev(host->mmc), "late init error\n");
a45c6cb8
MC		 1685 goto err_irq_cd_init;
1686 }
1687 }
b583f26d 1688 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1689
1690 /* Request IRQ for card detect */
e1a55f5e 1691 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8
MC		 1692 ret = request_irq(mmc_slot(host).card_detect_irq,
1693 omap_mmc_cd_handler,
1694 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1695 | IRQF_DISABLED,
1696 mmc_hostname(mmc), host);
1697 if (ret) {
1698 dev_dbg(mmc_dev(host->mmc),
1699 "Unable to grab MMC CD IRQ\n");
1700 goto err_irq_cd;
1701 }
1702 }
1703
1704 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1705 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1706
5e2ea617
AH		 1707 mmc_host_lazy_disable(host->mmc);
1708
a45c6cb8
MC		 1709 mmc_add_host(mmc);
1710
191d1f1d 1711 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 1712 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1713 if (ret < 0)
1714 goto err_slot_name;
1715 }
191d1f1d 1716 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 1717 ret = device_create_file(&mmc->class_dev,
1718 &dev_attr_cover_switch);
1719 if (ret < 0)
1720 goto err_cover_switch;
1721 }
1722
d900f712
DK		 1723 omap_mmc_debugfs(mmc);
1724
a45c6cb8
MC		 1725 return 0;
1726
1727err_cover_switch:
1728 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1729err_slot_name:
1730 mmc_remove_host(mmc);
1731err_irq_cd:
1732 free_irq(mmc_slot(host).card_detect_irq, host);
1733err_irq_cd_init:
1734 free_irq(host->irq, host);
1735err_irq:
5e2ea617 1736 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1737 clk_disable(host->iclk);
1738 clk_put(host->fclk);
1739 clk_put(host->iclk);
1740 if (host->dbclk_enabled) {
1741 clk_disable(host->dbclk);
1742 clk_put(host->dbclk);
1743 }
1744
1745err1:
1746 iounmap(host->base);
1747err:
1748 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1749 release_mem_region(res->start, res->end - res->start + 1);
1750 if (host)
1751 mmc_free_host(mmc);
1752 return ret;
1753}
1754
1755static int omap_mmc_remove(struct platform_device *pdev)
1756{
1757 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1758 struct resource *res;
1759
1760 if (host) {
5e2ea617 1761 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1762 mmc_remove_host(host->mmc);
1763 if (host->pdata->cleanup)
1764 host->pdata->cleanup(&pdev->dev);
1765 free_irq(host->irq, host);
1766 if (mmc_slot(host).card_detect_irq)
1767 free_irq(mmc_slot(host).card_detect_irq, host);
1768 flush_scheduled_work();
1769
5e2ea617 1770 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1771 clk_disable(host->iclk);
1772 clk_put(host->fclk);
1773 clk_put(host->iclk);
1774 if (host->dbclk_enabled) {
1775 clk_disable(host->dbclk);
1776 clk_put(host->dbclk);
1777 }
1778
1779 mmc_free_host(host->mmc);
1780 iounmap(host->base);
1781 }
1782
1783 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1784 if (res)
1785 release_mem_region(res->start, res->end - res->start + 1);
1786 platform_set_drvdata(pdev, NULL);
1787
1788 return 0;
1789}
1790
1791#ifdef CONFIG_PM
1792static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1793{
1794 int ret = 0;
1795 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1796
1797 if (host && host->suspended)
1798 return 0;
1799
1800 if (host) {
a6b2240d
AH		 1801 host->suspended = 1;
1802 if (host->pdata->suspend) {
1803 ret = host->pdata->suspend(&pdev->dev,
1804 host->slot_id);
1805 if (ret) {
1806 dev_dbg(mmc_dev(host->mmc),
1807 "Unable to handle MMC board"
1808 " level suspend\n");
1809 host->suspended = 0;
1810 return ret;
1811 }
1812 }
1813 cancel_work_sync(&host->mmc_carddetect_work);
5e2ea617 1814 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1815 ret = mmc_suspend_host(host->mmc, state);
1816 if (ret == 0) {
a45c6cb8
MC		 1817 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1818 OMAP_HSMMC_WRITE(host->base, IE, 0);
1819
a45c6cb8 1820
0683af48 1821 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 1822 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 1823 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1824 clk_disable(host->iclk);
1825 clk_disable(host->dbclk);
a6b2240d
AH		 1826 } else {
1827 host->suspended = 0;
1828 if (host->pdata->resume) {
1829 ret = host->pdata->resume(&pdev->dev,
1830 host->slot_id);
1831 if (ret)
1832 dev_dbg(mmc_dev(host->mmc),
1833 "Unmask interrupt failed\n");
1834 }
5e2ea617 1835 mmc_host_disable(host->mmc);
a6b2240d 1836 }
a45c6cb8
MC		 1837
1838 }
1839 return ret;
1840}
1841
1842/* Routine to resume the MMC device */
1843static int omap_mmc_resume(struct platform_device *pdev)
1844{
1845 int ret = 0;
1846 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1847
1848 if (host && !host->suspended)
1849 return 0;
1850
1851 if (host) {
a45c6cb8 1852 ret = clk_enable(host->iclk);
11dd62a7 1853 if (ret)
a45c6cb8 1854 goto clk_en_err;
a45c6cb8
MC		 1855
1856 if (clk_enable(host->dbclk) != 0)
1857 dev_dbg(mmc_dev(host->mmc),
1858 "Enabling debounce clk failed\n");
1859
11dd62a7
DK		 1860 if (mmc_host_enable(host->mmc) != 0) {
1861 clk_disable(host->iclk);
1862 goto clk_en_err;
1863 }
1864
1b331e69
KK		 1865 omap_hsmmc_init(host);
1866
a45c6cb8
MC		 1867 if (host->pdata->resume) {
1868 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1869 if (ret)
1870 dev_dbg(mmc_dev(host->mmc),
1871 "Unmask interrupt failed\n");
1872 }
1873
1874 /* Notify the core to resume the host */
1875 ret = mmc_resume_host(host->mmc);
1876 if (ret == 0)
1877 host->suspended = 0;
5e2ea617 1878 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1879 }
1880
1881 return ret;
1882
1883clk_en_err:
1884 dev_dbg(mmc_dev(host->mmc),
1885 "Failed to enable MMC clocks during resume\n");
1886 return ret;
1887}
1888
1889#else
1890#define omap_mmc_suspend NULL
1891#define omap_mmc_resume NULL
1892#endif
1893
1894static struct platform_driver omap_mmc_driver = {
a45c6cb8
MC		 1895 .remove = omap_mmc_remove,
1896 .suspend = omap_mmc_suspend,
1897 .resume = omap_mmc_resume,
1898 .driver = {
1899 .name = DRIVER_NAME,
1900 .owner = THIS_MODULE,
1901 },
1902};
1903
1904static int __init omap_mmc_init(void)
1905{
1906 /* Register the MMC driver */
f400cd8c 1907 return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
a45c6cb8
MC		 1908}
1909
1910static void __exit omap_mmc_cleanup(void)
1911{
1912 /* Unregister MMC driver */
1913 platform_driver_unregister(&omap_mmc_driver);
1914}
1915
1916module_init(omap_mmc_init);
1917module_exit(omap_mmc_cleanup);
1918
1919MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1920MODULE_LICENSE("GPL");
1921MODULE_ALIAS("platform:" DRIVER_NAME);
1922MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)