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Merge tag 'platform-drivers-x86-v4.17-1' of git://git.infradead.org/linux-platform...
[linux-2.6-block.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712 21#include <linux/debugfs.h>
c5c98927 22#include <linux/dmaengine.h>
d900f712 23#include <linux/seq_file.h>
031cd037 24#include <linux/sizes.h>
a45c6cb8
MC		 25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
a45c6cb8
MC		 29#include <linux/timer.h>
30#include <linux/clk.h>
46856a68 31#include <linux/of.h>
2cd3a2a5 32#include <linux/of_irq.h>
46856a68
RN		 33#include <linux/of_gpio.h>
34#include <linux/of_device.h>
a45c6cb8 35#include <linux/mmc/host.h>
13189e78 36#include <linux/mmc/core.h>
93caf8e6 37#include <linux/mmc/mmc.h>
41afa314 38#include <linux/mmc/slot-gpio.h>
a45c6cb8 39#include <linux/io.h>
2cd3a2a5 40#include <linux/irq.h>
db0fefc5
AH		 41#include <linux/gpio.h>
42#include <linux/regulator/consumer.h>
46b76035 43#include <linux/pinctrl/consumer.h>
fa4aa2d4 44#include <linux/pm_runtime.h>
5b83b223 45#include <linux/pm_wakeirq.h>
55143438 46#include <linux/platform_data/hsmmc-omap.h>
a45c6cb8
MC		 47
48/* OMAP HSMMC Host Controller Registers */
11dd62a7 49#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8 50#define OMAP_HSMMC_CON 0x002C
a2e77152 51#define OMAP_HSMMC_SDMASA 0x0100
a45c6cb8
MC		 52#define OMAP_HSMMC_BLK 0x0104
53#define OMAP_HSMMC_ARG 0x0108
54#define OMAP_HSMMC_CMD 0x010C
55#define OMAP_HSMMC_RSP10 0x0110
56#define OMAP_HSMMC_RSP32 0x0114
57#define OMAP_HSMMC_RSP54 0x0118
58#define OMAP_HSMMC_RSP76 0x011C
59#define OMAP_HSMMC_DATA 0x0120
bb0635f0 60#define OMAP_HSMMC_PSTATE 0x0124
a45c6cb8
MC		 61#define OMAP_HSMMC_HCTL 0x0128
62#define OMAP_HSMMC_SYSCTL 0x012C
63#define OMAP_HSMMC_STAT 0x0130
64#define OMAP_HSMMC_IE 0x0134
65#define OMAP_HSMMC_ISE 0x0138
a2e77152 66#define OMAP_HSMMC_AC12 0x013C
a45c6cb8
MC		 67#define OMAP_HSMMC_CAPA 0x0140
68
69#define VS18 (1 << 26)
70#define VS30 (1 << 25)
cd587096 71#define HSS (1 << 21)
a45c6cb8
MC		 72#define SDVS18 (0x5 << 9)
73#define SDVS30 (0x6 << 9)
eb250826 74#define SDVS33 (0x7 << 9)
1b331e69 75#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 76#define SDVSCLR 0xFFFFF1FF
77#define SDVSDET 0x00000400
78#define AUTOIDLE 0x1
79#define SDBP (1 << 8)
80#define DTO 0xe
81#define ICE 0x1
82#define ICS 0x2
83#define CEN (1 << 2)
ed164182 84#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
a45c6cb8
MC		 85#define CLKD_MASK 0x0000FFC0
86#define CLKD_SHIFT 6
87#define DTO_MASK 0x000F0000
88#define DTO_SHIFT 16
a45c6cb8 89#define INIT_STREAM (1 << 1)
a2e77152 90#define ACEN_ACMD23 (2 << 2)
a45c6cb8
MC		 91#define DP_SELECT (1 << 21)
92#define DDIR (1 << 4)
a7e96879 93#define DMAE 0x1
a45c6cb8
MC		 94#define MSBS (1 << 5)
95#define BCE (1 << 1)
96#define FOUR_BIT (1 << 1)
cd587096 97#define HSPE (1 << 2)
5a52b08b 98#define IWE (1 << 24)
03b5d924 99#define DDR (1 << 19)
5a52b08b
B		 100#define CLKEXTFREE (1 << 16)
101#define CTPL (1 << 11)
73153010 102#define DW8 (1 << 5)
a45c6cb8 103#define OD 0x1
a45c6cb8
MC		 104#define STAT_CLEAR 0xFFFFFFFF
105#define INIT_STREAM_CMD 0x00000000
106#define DUAL_VOLT_OCR_BIT 7
107#define SRC (1 << 25)
108#define SRD (1 << 26)
11dd62a7 109#define SOFTRESET (1 << 1)
a45c6cb8 110
f945901f
AF		 111/* PSTATE */
112#define DLEV_DAT(x) (1 << (20 + (x)))
113
a7e96879
V		 114/* Interrupt masks for IE and ISE register */
115#define CC_EN (1 << 0)
116#define TC_EN (1 << 1)
117#define BWR_EN (1 << 4)
118#define BRR_EN (1 << 5)
2cd3a2a5 119#define CIRQ_EN (1 << 8)
a7e96879
V		 120#define ERR_EN (1 << 15)
121#define CTO_EN (1 << 16)
122#define CCRC_EN (1 << 17)
123#define CEB_EN (1 << 18)
124#define CIE_EN (1 << 19)
125#define DTO_EN (1 << 20)
126#define DCRC_EN (1 << 21)
127#define DEB_EN (1 << 22)
a2e77152 128#define ACE_EN (1 << 24)
a7e96879
V		 129#define CERR_EN (1 << 28)
130#define BADA_EN (1 << 29)
131
a2e77152 132#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
a7e96879
V		 133 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
134 BRR_EN | BWR_EN | TC_EN | CC_EN)
135
a2e77152
B		 136#define CNI (1 << 7)
137#define ACIE (1 << 4)
138#define ACEB (1 << 3)
139#define ACCE (1 << 2)
140#define ACTO (1 << 1)
141#define ACNE (1 << 0)
142
fa4aa2d4 143#define MMC_AUTOSUSPEND_DELAY 100
1e881786
JM		 144#define MMC_TIMEOUT_MS 20 /* 20 mSec */
145#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
6b206efe
AS		 146#define OMAP_MMC_MIN_CLOCK 400000
147#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 148#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 149
150/*
151 * One controller can have multiple slots, like on some omap boards using
152 * omap.c controller driver. Luckily this is not currently done on any known
153 * omap_hsmmc.c device.
154 */
326119c9 155#define mmc_pdata(host) host->pdata
a45c6cb8
MC		 156
157/*
158 * MMC Host controller read/write API's
159 */
160#define OMAP_HSMMC_READ(base, reg) \
161 __raw_readl((base) + OMAP_HSMMC_##reg)
162
163#define OMAP_HSMMC_WRITE(base, reg, val) \
164 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
165
9782aff8
PF		 166struct omap_hsmmc_next {
167 unsigned int dma_len;
168 s32 cookie;
169};
170
70a3341a 171struct omap_hsmmc_host {
a45c6cb8
MC		 172 struct device *dev;
173 struct mmc_host *mmc;
174 struct mmc_request *mrq;
175 struct mmc_command *cmd;
176 struct mmc_data *data;
177 struct clk *fclk;
a45c6cb8 178 struct clk *dbclk;
e99448ff 179 struct regulator *pbias;
bb2726b5 180 bool pbias_enabled;
a45c6cb8 181 void __iomem *base;
3f77f702 182 int vqmmc_enabled;
a45c6cb8 183 resource_size_t mapbase;
4dffd7a2 184 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 185 unsigned int dma_len;
0ccd76d4 186 unsigned int dma_sg_idx;
a45c6cb8 187 unsigned char bus_mode;
a3621465 188 unsigned char power_mode;
a45c6cb8 189 int suspended;
0a82e06e
TL		 190 u32 con;
191 u32 hctl;
192 u32 sysctl;
193 u32 capa;
a45c6cb8 194 int irq;
2cd3a2a5 195 int wake_irq;
a45c6cb8 196 int use_dma, dma_ch;
c5c98927
RK		 197 struct dma_chan *tx_chan;
198 struct dma_chan *rx_chan;
4a694dc9 199 int response_busy;
11dd62a7 200 int context_loss;
b62f6228
AH		 201 int protect_card;
202 int reqs_blocked;
b417577d 203 int req_in_progress;
6e3076c2 204 unsigned long clk_rate;
a2e77152 205 unsigned int flags;
2cd3a2a5
AF		 206#define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
207#define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
9782aff8 208 struct omap_hsmmc_next next_data;
55143438 209 struct omap_hsmmc_platform_data *pdata;
b5cd43f0 210
b5cd43f0
AF		 211 /* return MMC cover switch state, can be NULL if not supported.
212 *
213 * possible return values:
214 * 0 - closed
215 * 1 - open
216 */
80412ca8 217 int (*get_cover_state)(struct device *dev);
b5cd43f0 218
80412ca8 219 int (*card_detect)(struct device *dev);
a45c6cb8
MC		 220};
221
59445b10
NM		 222struct omap_mmc_of_data {
223 u32 reg_offset;
224 u8 controller_flags;
225};
226
bf129e1c
B		 227static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
228
80412ca8 229static int omap_hsmmc_card_detect(struct device *dev)
db0fefc5 230{
9ea28ecb 231 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
db0fefc5 232
41afa314 233 return mmc_gpio_get_cd(host->mmc);
db0fefc5
AH		 234}
235
80412ca8 236static int omap_hsmmc_get_cover_state(struct device *dev)
db0fefc5 237{
9ea28ecb 238 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
db0fefc5 239
41afa314 240 return mmc_gpio_get_cd(host->mmc);
db0fefc5
AH		 241}
242
1d17f30b 243static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
2a17f844
KVA		 244{
245 int ret;
3f77f702 246 struct omap_hsmmc_host *host = mmc_priv(mmc);
1d17f30b 247 struct mmc_ios *ios = &mmc->ios;
2a17f844 248
86d79da0 249 if (!IS_ERR(mmc->supply.vmmc)) {
1d17f30b 250 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
2a17f844
KVA		 251 if (ret)
252 return ret;
253 }
254
255 /* Enable interface voltage rail, if needed */
86d79da0 256 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
2a17f844
KVA		 257 ret = regulator_enable(mmc->supply.vqmmc);
258 if (ret) {
259 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
260 goto err_vqmmc;
261 }
3f77f702 262 host->vqmmc_enabled = 1;
2a17f844
KVA		 263 }
264
265 return 0;
266
267err_vqmmc:
86d79da0 268 if (!IS_ERR(mmc->supply.vmmc))
2a17f844
KVA		 269 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
270
271 return ret;
272}
273
274static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
275{
276 int ret;
277 int status;
3f77f702 278 struct omap_hsmmc_host *host = mmc_priv(mmc);
2a17f844 279
86d79da0 280 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
2a17f844
KVA		 281 ret = regulator_disable(mmc->supply.vqmmc);
282 if (ret) {
283 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
284 return ret;
285 }
3f77f702 286 host->vqmmc_enabled = 0;
2a17f844
KVA		 287 }
288
86d79da0 289 if (!IS_ERR(mmc->supply.vmmc)) {
2a17f844
KVA		 290 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
291 if (ret)
292 goto err_set_ocr;
293 }
294
295 return 0;
296
297err_set_ocr:
86d79da0 298 if (!IS_ERR(mmc->supply.vqmmc)) {
2a17f844
KVA		 299 status = regulator_enable(mmc->supply.vqmmc);
300 if (status)
301 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
302 }
303
304 return ret;
305}
306
66162bec 307static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
ec85c95e
KVA		 308{
309 int ret;
310
86d79da0 311 if (IS_ERR(host->pbias))
ec85c95e
KVA		 312 return 0;
313
314 if (power_on) {
bb2726b5 315 if (host->pbias_enabled == 0) {
ec85c95e
KVA		 316 ret = regulator_enable(host->pbias);
317 if (ret) {
318 dev_err(host->dev, "pbias reg enable fail\n");
319 return ret;
320 }
bb2726b5 321 host->pbias_enabled = 1;
ec85c95e
KVA		 322 }
323 } else {
bb2726b5 324 if (host->pbias_enabled == 1) {
ec85c95e
KVA		 325 ret = regulator_disable(host->pbias);
326 if (ret) {
327 dev_err(host->dev, "pbias reg disable fail\n");
328 return ret;
329 }
bb2726b5 330 host->pbias_enabled = 0;
ec85c95e
KVA		 331 }
332 }
333
334 return 0;
335}
336
66162bec 337static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
db0fefc5 338{
aa9a6801 339 struct mmc_host *mmc = host->mmc;
db0fefc5
AH		 340 int ret = 0;
341
342 /*
343 * If we don't see a Vcc regulator, assume it's a fixed
344 * voltage always-on regulator.
345 */
86d79da0 346 if (IS_ERR(mmc->supply.vmmc))
db0fefc5
AH		 347 return 0;
348
66162bec 349 ret = omap_hsmmc_set_pbias(host, false);
ec85c95e
KVA		 350 if (ret)
351 return ret;
e99448ff 352
db0fefc5
AH		 353 /*
354 * Assume Vcc regulator is used only to power the card ... OMAP
355 * VDDS is used to power the pins, optionally with a transceiver to
356 * support cards using voltages other than VDDS (1.8V nominal). When a
357 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
358 *
359 * In some cases this regulator won't support enable/disable;
360 * e.g. it's a fixed rail for a WLAN chip.
361 *
362 * In other cases vcc_aux switches interface power. Example, for
363 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
364 * chips/cards need an interface voltage rail too.
365 */
366 if (power_on) {
1d17f30b 367 ret = omap_hsmmc_enable_supply(mmc);
2a17f844
KVA		 368 if (ret)
369 return ret;
97fe7e5a 370
66162bec 371 ret = omap_hsmmc_set_pbias(host, true);
97fe7e5a
KVA		 372 if (ret)
373 goto err_set_voltage;
db0fefc5 374 } else {
2a17f844
KVA		 375 ret = omap_hsmmc_disable_supply(mmc);
376 if (ret)
377 return ret;
db0fefc5
AH		 378 }
379
229f3292
KVA		 380 return 0;
381
382err_set_voltage:
2a17f844 383 omap_hsmmc_disable_supply(mmc);
229f3292 384
db0fefc5
AH		 385 return ret;
386}
387
c8518efa
KVA		 388static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
389{
390 int ret;
391
86d79da0 392 if (IS_ERR(reg))
c8518efa
KVA		 393 return 0;
394
395 if (regulator_is_enabled(reg)) {
396 ret = regulator_enable(reg);
397 if (ret)
398 return ret;
399
400 ret = regulator_disable(reg);
401 if (ret)
402 return ret;
403 }
404
405 return 0;
406}
407
408static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
409{
410 struct mmc_host *mmc = host->mmc;
411 int ret;
412
413 /*
414 * disable regulators enabled during boot and get the usecount
415 * right so that regulators can be enabled/disabled by checking
416 * the return value of regulator_is_enabled
417 */
418 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
419 if (ret) {
420 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
421 return ret;
422 }
423
424 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
425 if (ret) {
426 dev_err(host->dev,
427 "fail to disable boot enabled vmmc_aux reg\n");
428 return ret;
429 }
430
431 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
432 if (ret) {
433 dev_err(host->dev,
434 "failed to disable boot enabled pbias reg\n");
435 return ret;
436 }
437
438 return 0;
439}
440
db0fefc5
AH		 441static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
442{
7d607f91 443 int ret;
aa9a6801 444 struct mmc_host *mmc = host->mmc;
db0fefc5 445
f7f0f035 446
13ab2a66 447 ret = mmc_regulator_get_supply(mmc);
3b649a73 448 if (ret)
13ab2a66 449 return ret;
db0fefc5 450
987fd49b 451 /* Allow an aux regulator */
aa9a6801 452 if (IS_ERR(mmc->supply.vqmmc)) {
13ab2a66
KVA		 453 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
454 "vmmc_aux");
455 if (IS_ERR(mmc->supply.vqmmc)) {
456 ret = PTR_ERR(mmc->supply.vqmmc);
457 if ((ret != -ENODEV) && host->dev->of_node)
458 return ret;
459 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
460 PTR_ERR(mmc->supply.vqmmc));
461 }
6a9b2ff0 462 }
987fd49b 463
c299dc39
KVA		 464 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
465 if (IS_ERR(host->pbias)) {
466 ret = PTR_ERR(host->pbias);
9143757b
KVA		 467 if ((ret != -ENODEV) && host->dev->of_node) {
468 dev_err(host->dev,
469 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
6a9b2ff0 470 return ret;
9143757b 471 }
6a9b2ff0 472 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
c299dc39 473 PTR_ERR(host->pbias));
6a9b2ff0 474 }
e99448ff 475
987fd49b 476 /* For eMMC do not power off when not in sleep state */
326119c9 477 if (mmc_pdata(host)->no_regulator_off_init)
987fd49b 478 return 0;
987fd49b 479
c8518efa
KVA		 480 ret = omap_hsmmc_disable_boot_regulators(host);
481 if (ret)
482 return ret;
db0fefc5
AH		 483
484 return 0;
db0fefc5
AH		 485}
486
cde592cb 487static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
41afa314
N		 488
489static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
490 struct omap_hsmmc_host *host,
1e363e3b 491 struct omap_hsmmc_platform_data *pdata)
b702b106
AH		 492{
493 int ret;
494
b7a5646f
AF		 495 if (gpio_is_valid(pdata->gpio_cod)) {
496 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
b702b106
AH		 497 if (ret)
498 return ret;
cde592cb
AF		 499
500 host->get_cover_state = omap_hsmmc_get_cover_state;
501 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
b7a5646f
AF		 502 } else if (gpio_is_valid(pdata->gpio_cd)) {
503 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
cde592cb
AF		 504 if (ret)
505 return ret;
506
507 host->card_detect = omap_hsmmc_card_detect;
326119c9 508 }
b702b106 509
326119c9 510 if (gpio_is_valid(pdata->gpio_wp)) {
41afa314 511 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
b702b106 512 if (ret)
41afa314 513 return ret;
326119c9 514 }
b702b106
AH		 515
516 return 0;
b702b106
AH		 517}
518
e0c7f99b
AS		 519/*
520 * Start clock to the card
521 */
522static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
523{
524 OMAP_HSMMC_WRITE(host->base, SYSCTL,
525 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
526}
527
a45c6cb8
MC		 528/*
529 * Stop clock to the card
530 */
70a3341a 531static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 532{
533 OMAP_HSMMC_WRITE(host->base, SYSCTL,
534 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
535 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
7122bbb0 536 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
a45c6cb8
MC		 537}
538
93caf8e6
AH		 539static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
540 struct mmc_command *cmd)
b417577d 541{
2cd3a2a5
AF		 542 u32 irq_mask = INT_EN_MASK;
543 unsigned long flags;
b417577d
AH		 544
545 if (host->use_dma)
2cd3a2a5 546 irq_mask &= ~(BRR_EN | BWR_EN);
b417577d 547
93caf8e6
AH		 548 /* Disable timeout for erases */
549 if (cmd->opcode == MMC_ERASE)
a7e96879 550 irq_mask &= ~DTO_EN;
93caf8e6 551
2cd3a2a5 552 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 553 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
554 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
2cd3a2a5
AF		 555
556 /* latch pending CIRQ, but don't signal MMC core */
557 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
558 irq_mask |= CIRQ_EN;
b417577d 559 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
2cd3a2a5 560 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 561}
562
563static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
564{
2cd3a2a5
AF		 565 u32 irq_mask = 0;
566 unsigned long flags;
567
568 spin_lock_irqsave(&host->irq_lock, flags);
569 /* no transfer running but need to keep cirq if enabled */
570 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
571 irq_mask |= CIRQ_EN;
572 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
573 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
b417577d 574 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2cd3a2a5 575 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 576}
577
ac330f44 578/* Calculate divisor for the given clock frequency */
d83b6e03 579static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 580{
581 u16 dsor = 0;
582
583 if (ios->clock) {
d83b6e03 584 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ed164182
B		 585 if (dsor > CLKD_MAX)
586 dsor = CLKD_MAX;
ac330f44
AS		 587 }
588
589 return dsor;
590}
591
5934df2f
AS		 592static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
593{
594 struct mmc_ios *ios = &host->mmc->ios;
595 unsigned long regval;
596 unsigned long timeout;
cd587096 597 unsigned long clkdiv;
5934df2f 598
8986d31b 599 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
5934df2f
AS		 600
601 omap_hsmmc_stop_clock(host);
602
603 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
604 regval = regval & ~(CLKD_MASK | DTO_MASK);
cd587096
HG		 605 clkdiv = calc_divisor(host, ios);
606 regval = regval | (clkdiv << 6) | (DTO << 16);
5934df2f
AS		 607 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
608 OMAP_HSMMC_WRITE(host->base, SYSCTL,
609 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
610
611 /* Wait till the ICS bit is set */
612 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
613 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
614 && time_before(jiffies, timeout))
615 cpu_relax();
616
cd587096
HG		 617 /*
618 * Enable High-Speed Support
619 * Pre-Requisites
620 * - Controller should support High-Speed-Enable Bit
621 * - Controller should not be using DDR Mode
622 * - Controller should advertise that it supports High Speed
623 * in capabilities register
624 * - MMC/SD clock coming out of controller > 25MHz
625 */
326119c9 626 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
5438ad95 627 (ios->timing != MMC_TIMING_MMC_DDR52) &&
903101a8 628 (ios->timing != MMC_TIMING_UHS_DDR50) &&
cd587096
HG		 629 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
630 regval = OMAP_HSMMC_READ(host->base, HCTL);
631 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
632 regval |= HSPE;
633 else
634 regval &= ~HSPE;
635
636 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
637 }
638
5934df2f
AS		 639 omap_hsmmc_start_clock(host);
640}
641
3796fb8a
AS		 642static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
643{
644 struct mmc_ios *ios = &host->mmc->ios;
645 u32 con;
646
647 con = OMAP_HSMMC_READ(host->base, CON);
903101a8
UH		 648 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
649 ios->timing == MMC_TIMING_UHS_DDR50)
03b5d924
B		 650 con |= DDR; /* configure in DDR mode */
651 else
652 con &= ~DDR;
3796fb8a
AS		 653 switch (ios->bus_width) {
654 case MMC_BUS_WIDTH_8:
655 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
656 break;
657 case MMC_BUS_WIDTH_4:
658 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
659 OMAP_HSMMC_WRITE(host->base, HCTL,
660 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
661 break;
662 case MMC_BUS_WIDTH_1:
663 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
664 OMAP_HSMMC_WRITE(host->base, HCTL,
665 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
666 break;
667 }
668}
669
670static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
671{
672 struct mmc_ios *ios = &host->mmc->ios;
673 u32 con;
674
675 con = OMAP_HSMMC_READ(host->base, CON);
676 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
677 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
678 else
679 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
680}
681
11dd62a7
DK		 682#ifdef CONFIG_PM
683
684/*
685 * Restore the MMC host context, if it was lost as result of a
686 * power state change.
687 */
70a3341a 688static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 689{
690 struct mmc_ios *ios = &host->mmc->ios;
3796fb8a 691 u32 hctl, capa;
11dd62a7
DK		 692 unsigned long timeout;
693
0a82e06e
TL		 694 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
695 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
696 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
697 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
698 return 0;
699
700 host->context_loss++;
701
c2200efb 702 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 703 if (host->power_mode != MMC_POWER_OFF &&
704 (1 << ios->vdd) <= MMC_VDD_23_24)
705 hctl = SDVS18;
706 else
707 hctl = SDVS30;
708 capa = VS30 | VS18;
709 } else {
710 hctl = SDVS18;
711 capa = VS18;
712 }
713
5a52b08b
B		 714 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
715 hctl |= IWE;
716
11dd62a7
DK		 717 OMAP_HSMMC_WRITE(host->base, HCTL,
718 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
719
720 OMAP_HSMMC_WRITE(host->base, CAPA,
721 OMAP_HSMMC_READ(host->base, CAPA) | capa);
722
723 OMAP_HSMMC_WRITE(host->base, HCTL,
724 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
725
726 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
727 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
728 && time_before(jiffies, timeout))
729 ;
730
2cd3a2a5
AF		 731 OMAP_HSMMC_WRITE(host->base, ISE, 0);
732 OMAP_HSMMC_WRITE(host->base, IE, 0);
733 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
11dd62a7
DK		 734
735 /* Do not initialize card-specific things if the power is off */
736 if (host->power_mode == MMC_POWER_OFF)
737 goto out;
738
3796fb8a 739 omap_hsmmc_set_bus_width(host);
11dd62a7 740
5934df2f 741 omap_hsmmc_set_clock(host);
11dd62a7 742
3796fb8a
AS		 743 omap_hsmmc_set_bus_mode(host);
744
11dd62a7 745out:
0a82e06e
TL		 746 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
747 host->context_loss);
11dd62a7
DK		 748 return 0;
749}
750
751/*
752 * Save the MMC host context (store the number of power state changes so far).
753 */
70a3341a 754static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7 755{
0a82e06e
TL		 756 host->con = OMAP_HSMMC_READ(host->base, CON);
757 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
758 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
759 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
11dd62a7
DK		 760}
761
762#else
763
70a3341a 764static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 765{
766 return 0;
767}
768
70a3341a 769static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 770{
771}
772
773#endif
774
a45c6cb8
MC		 775/*
776 * Send init stream sequence to card
777 * before sending IDLE command
778 */
70a3341a 779static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 780{
781 int reg = 0;
782 unsigned long timeout;
783
b62f6228
AH		 784 if (host->protect_card)
785 return;
786
a45c6cb8 787 disable_irq(host->irq);
b417577d
AH		 788
789 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 790 OMAP_HSMMC_WRITE(host->base, CON,
791 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
792 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
793
794 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
a7e96879
V		 795 while ((reg != CC_EN) && time_before(jiffies, timeout))
796 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
a45c6cb8
MC		 797
798 OMAP_HSMMC_WRITE(host->base, CON,
799 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 800
801 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
802 OMAP_HSMMC_READ(host->base, STAT);
803
a45c6cb8
MC		 804 enable_irq(host->irq);
805}
806
807static inline
70a3341a 808int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 809{
810 int r = 1;
811
b5cd43f0 812 if (host->get_cover_state)
80412ca8 813 r = host->get_cover_state(host->dev);
a45c6cb8
MC		 814 return r;
815}
816
817static ssize_t
70a3341a 818omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 819 char *buf)
820{
821 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 822 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 823
70a3341a
DK		 824 return sprintf(buf, "%s\n",
825 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 826}
827
70a3341a 828static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 829
830static ssize_t
70a3341a 831omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 832 char *buf)
833{
834 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 835 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 836
326119c9 837 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
a45c6cb8
MC		 838}
839
70a3341a 840static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 841
842/*
843 * Configure the response type and send the cmd.
844 */
845static void
70a3341a 846omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 847 struct mmc_data *data)
848{
849 int cmdreg = 0, resptype = 0, cmdtype = 0;
850
8986d31b 851 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
a45c6cb8
MC		 852 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
853 host->cmd = cmd;
854
93caf8e6 855 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 856
4a694dc9 857 host->response_busy = 0;
a45c6cb8
MC		 858 if (cmd->flags & MMC_RSP_PRESENT) {
859 if (cmd->flags & MMC_RSP_136)
860 resptype = 1;
4a694dc9
AH		 861 else if (cmd->flags & MMC_RSP_BUSY) {
862 resptype = 3;
863 host->response_busy = 1;
864 } else
a45c6cb8
MC		 865 resptype = 2;
866 }
867
868 /*
869 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
870 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
871 * a val of 0x3, rest 0x0.
872 */
873 if (cmd == host->mrq->stop)
874 cmdtype = 0x3;
875
876 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
877
a2e77152
B		 878 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
879 host->mrq->sbc) {
880 cmdreg |= ACEN_ACMD23;
881 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
882 }
a45c6cb8
MC		 883 if (data) {
884 cmdreg |= DP_SELECT | MSBS | BCE;
885 if (data->flags & MMC_DATA_READ)
886 cmdreg |= DDIR;
887 else
888 cmdreg &= ~(DDIR);
889 }
890
891 if (host->use_dma)
a7e96879 892 cmdreg |= DMAE;
a45c6cb8 893
b417577d 894 host->req_in_progress = 1;
4dffd7a2 895
a45c6cb8
MC		 896 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
897 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
898}
899
c5c98927
RK		 900static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
901 struct mmc_data *data)
902{
903 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
904}
905
b417577d
AH		 906static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
907{
908 int dma_ch;
31463b14 909 unsigned long flags;
b417577d 910
31463b14 911 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 912 host->req_in_progress = 0;
913 dma_ch = host->dma_ch;
31463b14 914 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 915
916 omap_hsmmc_disable_irq(host);
917 /* Do not complete the request if DMA is still in progress */
918 if (mrq->data && host->use_dma && dma_ch != -1)
919 return;
920 host->mrq = NULL;
921 mmc_request_done(host->mmc, mrq);
922}
923
a45c6cb8
MC		 924/*
925 * Notify the transfer complete to MMC core
926 */
927static void
70a3341a 928omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 929{
4a694dc9
AH		 930 if (!data) {
931 struct mmc_request *mrq = host->mrq;
932
23050103
AH		 933 /* TC before CC from CMD6 - don't know why, but it happens */
934 if (host->cmd && host->cmd->opcode == 6 &&
935 host->response_busy) {
936 host->response_busy = 0;
937 return;
938 }
939
b417577d 940 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 941 return;
942 }
943
a45c6cb8
MC		 944 host->data = NULL;
945
a45c6cb8
MC		 946 if (!data->error)
947 data->bytes_xfered += data->blocks * (data->blksz);
948 else
949 data->bytes_xfered = 0;
950
bf129e1c
B		 951 if (data->stop && (data->error || !host->mrq->sbc))
952 omap_hsmmc_start_command(host, data->stop, NULL);
953 else
b417577d 954 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 955}
956
957/*
958 * Notify the core about command completion
959 */
960static void
70a3341a 961omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8 962{
bf129e1c 963 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
a2e77152 964 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
2177fa94 965 host->cmd = NULL;
bf129e1c
B		 966 omap_hsmmc_start_dma_transfer(host);
967 omap_hsmmc_start_command(host, host->mrq->cmd,
968 host->mrq->data);
969 return;
970 }
971
2177fa94
B		 972 host->cmd = NULL;
973
a45c6cb8
MC		 974 if (cmd->flags & MMC_RSP_PRESENT) {
975 if (cmd->flags & MMC_RSP_136) {
976 /* response type 2 */
977 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
978 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
979 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
980 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
981 } else {
982 /* response types 1, 1b, 3, 4, 5, 6 */
983 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
984 }
985 }
b417577d 986 if ((host->data == NULL && !host->response_busy) || cmd->error)
d4b2c375 987 omap_hsmmc_request_done(host, host->mrq);
a45c6cb8
MC		 988}
989
990/*
991 * DMA clean up for command errors
992 */
70a3341a 993static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 994{
b417577d 995 int dma_ch;
31463b14 996 unsigned long flags;
b417577d 997
82788ff5 998 host->data->error = errno;
a45c6cb8 999
31463b14 1000 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 1001 dma_ch = host->dma_ch;
1002 host->dma_ch = -1;
31463b14 1003 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 1004
1005 if (host->use_dma && dma_ch != -1) {
c5c98927
RK		 1006 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1007
1008 dmaengine_terminate_all(chan);
1009 dma_unmap_sg(chan->device->dev,
1010 host->data->sg, host->data->sg_len,
feeef096 1011 mmc_get_dma_dir(host->data));
c5c98927 1012
053bf34f 1013 host->data->host_cookie = 0;
a45c6cb8
MC		 1014 }
1015 host->data = NULL;
a45c6cb8
MC		 1016}
1017
1018/*
1019 * Readable error output
1020 */
1021#ifdef CONFIG_MMC_DEBUG
699b958b 1022static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 1023{
1024 /* --- means reserved bit without definition at documentation */
70a3341a 1025 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 1026 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1027 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1028 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1029 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 1030 };
1031 char res[256];
1032 char *buf = res;
1033 int len, i;
1034
1035 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1036 buf += len;
1037
70a3341a 1038 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 1039 if (status & (1 << i)) {
70a3341a 1040 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 1041 buf += len;
1042 }
1043
8986d31b 1044 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
a45c6cb8 1045}
699b958b
AH		 1046#else
1047static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1048 u32 status)
1049{
1050}
a45c6cb8
MC		 1051#endif /* CONFIG_MMC_DEBUG */
1052
3ebf74b1
JP		 1053/*
1054 * MMC controller internal state machines reset
1055 *
1056 * Used to reset command or data internal state machines, using respectively
1057 * SRC or SRD bit of SYSCTL register
1058 * Can be called from interrupt context
1059 */
70a3341a
DK		 1060static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1061 unsigned long bit)
3ebf74b1
JP		 1062{
1063 unsigned long i = 0;
1e881786 1064 unsigned long limit = MMC_TIMEOUT_US;
3ebf74b1
JP		 1065
1066 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1067 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1068
07ad64b6
MC		 1069 /*
1070 * OMAP4 ES2 and greater has an updated reset logic.
1071 * Monitor a 0->1 transition first
1072 */
326119c9 1073 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1074 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6 1075 && (i++ < limit))
1e881786 1076 udelay(1);
07ad64b6
MC		 1077 }
1078 i = 0;
1079
3ebf74b1
JP		 1080 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1081 (i++ < limit))
1e881786 1082 udelay(1);
3ebf74b1
JP		 1083
1084 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1085 dev_err(mmc_dev(host->mmc),
1086 "Timeout waiting on controller reset in %s\n",
1087 __func__);
1088}
a45c6cb8 1089
25e1897b
B		 1090static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1091 int err, int end_cmd)
ae4bf788 1092{
25e1897b 1093 if (end_cmd) {
94d4f272 1094 omap_hsmmc_reset_controller_fsm(host, SRC);
25e1897b
B		 1095 if (host->cmd)
1096 host->cmd->error = err;
1097 }
ae4bf788
V		 1098
1099 if (host->data) {
1100 omap_hsmmc_reset_controller_fsm(host, SRD);
1101 omap_hsmmc_dma_cleanup(host, err);
dc7745bd
B		 1102 } else if (host->mrq && host->mrq->cmd)
1103 host->mrq->cmd->error = err;
ae4bf788
V		 1104}
1105
b417577d 1106static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1107{
a45c6cb8 1108 struct mmc_data *data;
b417577d 1109 int end_cmd = 0, end_trans = 0;
a2e77152 1110 int error = 0;
b417577d 1111
a45c6cb8 1112 data = host->data;
8986d31b 1113 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
a45c6cb8 1114
a7e96879 1115 if (status & ERR_EN) {
699b958b 1116 omap_hsmmc_dbg_report_irq(host, status);
25e1897b 1117
24380dd4 1118 if (status & (CTO_EN | CCRC_EN | CEB_EN))
25e1897b 1119 end_cmd = 1;
408806f7
KVA		 1120 if (host->data || host->response_busy) {
1121 end_trans = !end_cmd;
1122 host->response_busy = 0;
1123 }
a7e96879 1124 if (status & (CTO_EN | DTO_EN))
25e1897b 1125 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
5027cd1e
V		 1126 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1127 BADA_EN))
25e1897b 1128 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
ae4bf788 1129
a2e77152
B		 1130 if (status & ACE_EN) {
1131 u32 ac12;
1132 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1133 if (!(ac12 & ACNE) && host->mrq->sbc) {
1134 end_cmd = 1;
1135 if (ac12 & ACTO)
1136 error = -ETIMEDOUT;
1137 else if (ac12 & (ACCE | ACEB | ACIE))
1138 error = -EILSEQ;
1139 host->mrq->sbc->error = error;
1140 hsmmc_command_incomplete(host, error, end_cmd);
1141 }
1142 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1143 }
a45c6cb8
MC		 1144 }
1145
7472bab2 1146 OMAP_HSMMC_WRITE(host->base, STAT, status);
a7e96879 1147 if (end_cmd || ((status & CC_EN) && host->cmd))
70a3341a 1148 omap_hsmmc_cmd_done(host, host->cmd);
a7e96879 1149 if ((end_trans || (status & TC_EN)) && host->mrq)
70a3341a 1150 omap_hsmmc_xfer_done(host, data);
b417577d 1151}
a45c6cb8 1152
b417577d
AH		 1153/*
1154 * MMC controller IRQ handler
1155 */
1156static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1157{
1158 struct omap_hsmmc_host *host = dev_id;
1159 int status;
1160
1161 status = OMAP_HSMMC_READ(host->base, STAT);
2cd3a2a5
AF		 1162 while (status & (INT_EN_MASK | CIRQ_EN)) {
1163 if (host->req_in_progress)
1164 omap_hsmmc_do_irq(host, status);
1165
1166 if (status & CIRQ_EN)
1167 mmc_signal_sdio_irq(host->mmc);
1f6b9fa4 1168
b417577d
AH		 1169 /* Flush posted write */
1170 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1171 }
4dffd7a2 1172
a45c6cb8
MC		 1173 return IRQ_HANDLED;
1174}
1175
70a3341a 1176static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1177{
1178 unsigned long i;
1179
1180 OMAP_HSMMC_WRITE(host->base, HCTL,
1181 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1182 for (i = 0; i < loops_per_jiffy; i++) {
1183 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1184 break;
1185 cpu_relax();
1186 }
1187}
1188
a45c6cb8 1189/*
eb250826
DB		 1190 * Switch MMC interface voltage ... only relevant for MMC1.
1191 *
1192 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1193 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1194 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1195 */
70a3341a 1196static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1197{
1198 u32 reg_val = 0;
1199 int ret;
1200
1201 /* Disable the clocks */
cd03d9a8 1202 if (host->dbclk)
94c18149 1203 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1204
1205 /* Turn the power off */
66162bec 1206 ret = omap_hsmmc_set_power(host, 0);
a45c6cb8
MC		 1207
1208 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893 1209 if (!ret)
66162bec 1210 ret = omap_hsmmc_set_power(host, 1);
cd03d9a8 1211 if (host->dbclk)
94c18149 1212 clk_prepare_enable(host->dbclk);
2bec0893 1213
a45c6cb8
MC		 1214 if (ret != 0)
1215 goto err;
1216
a45c6cb8
MC		 1217 OMAP_HSMMC_WRITE(host->base, HCTL,
1218 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1219 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1220
a45c6cb8
MC		 1221 /*
1222 * If a MMC dual voltage card is detected, the set_ios fn calls
1223 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1224 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1225 *
eb250826
DB		 1226 * Cope with a bit of slop in the range ... per data sheets:
1227 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1228 * but recommended values are 1.71V to 1.89V
1229 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1230 * but recommended values are 2.7V to 3.3V
1231 *
1232 * Board setup code shouldn't permit anything very out-of-range.
1233 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1234 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1235 */
eb250826 1236 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1237 reg_val |= SDVS18;
eb250826
DB		 1238 else
1239 reg_val |= SDVS30;
a45c6cb8
MC		 1240
1241 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1242 set_sd_bus_power(host);
a45c6cb8
MC		 1243
1244 return 0;
1245err:
b1e056ae 1246 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
a45c6cb8
MC		 1247 return ret;
1248}
1249
b62f6228
AH		 1250/* Protect the card while the cover is open */
1251static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1252{
b5cd43f0 1253 if (!host->get_cover_state)
b62f6228
AH		 1254 return;
1255
1256 host->reqs_blocked = 0;
80412ca8 1257 if (host->get_cover_state(host->dev)) {
b62f6228 1258 if (host->protect_card) {
2cecdf00 1259 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1260 "card is now accessible\n",
1261 mmc_hostname(host->mmc));
1262 host->protect_card = 0;
1263 }
1264 } else {
1265 if (!host->protect_card) {
2cecdf00 1266 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1267 "card is now inaccessible\n",
1268 mmc_hostname(host->mmc));
1269 host->protect_card = 1;
1270 }
1271 }
1272}
1273
a45c6cb8 1274/*
cde592cb 1275 * irq handler when (cell-phone) cover is mounted/removed
a45c6cb8 1276 */
cde592cb 1277static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
a45c6cb8 1278{
7efab4f3 1279 struct omap_hsmmc_host *host = dev_id;
a6b2240d 1280
a6b2240d 1281 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1282
11227d12
AF		 1283 omap_hsmmc_protect_card(host);
1284 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cde592cb
AF		 1285 return IRQ_HANDLED;
1286}
1287
c5c98927 1288static void omap_hsmmc_dma_callback(void *param)
a45c6cb8 1289{
c5c98927
RK		 1290 struct omap_hsmmc_host *host = param;
1291 struct dma_chan *chan;
770d7432 1292 struct mmc_data *data;
c5c98927 1293 int req_in_progress;
a45c6cb8 1294
c5c98927 1295 spin_lock_irq(&host->irq_lock);
b417577d 1296 if (host->dma_ch < 0) {
c5c98927 1297 spin_unlock_irq(&host->irq_lock);
a45c6cb8 1298 return;
b417577d 1299 }
a45c6cb8 1300
770d7432 1301 data = host->mrq->data;
c5c98927 1302 chan = omap_hsmmc_get_dma_chan(host, data);
9782aff8 1303 if (!data->host_cookie)
c5c98927
RK		 1304 dma_unmap_sg(chan->device->dev,
1305 data->sg, data->sg_len,
feeef096 1306 mmc_get_dma_dir(data));
b417577d
AH		 1307
1308 req_in_progress = host->req_in_progress;
a45c6cb8 1309 host->dma_ch = -1;
c5c98927 1310 spin_unlock_irq(&host->irq_lock);
b417577d
AH		 1311
1312 /* If DMA has finished after TC, complete the request */
1313 if (!req_in_progress) {
1314 struct mmc_request *mrq = host->mrq;
1315
1316 host->mrq = NULL;
1317 mmc_request_done(host->mmc, mrq);
1318 }
a45c6cb8
MC		 1319}
1320
9782aff8
PF		 1321static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1322 struct mmc_data *data,
c5c98927 1323 struct omap_hsmmc_next *next,
26b88520 1324 struct dma_chan *chan)
9782aff8
PF		 1325{
1326 int dma_len;
1327
1328 if (!next && data->host_cookie &&
1329 data->host_cookie != host->next_data.cookie) {
2cecdf00 1330 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1331 " host->next_data.cookie %d\n",
1332 __func__, data->host_cookie, host->next_data.cookie);
1333 data->host_cookie = 0;
1334 }
1335
1336 /* Check if next job is already prepared */
b38313d6 1337 if (next || data->host_cookie != host->next_data.cookie) {
26b88520 1338 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
feeef096 1339 mmc_get_dma_dir(data));
9782aff8
PF		 1340
1341 } else {
1342 dma_len = host->next_data.dma_len;
1343 host->next_data.dma_len = 0;
1344 }
1345
1346
1347 if (dma_len == 0)
1348 return -EINVAL;
1349
1350 if (next) {
1351 next->dma_len = dma_len;
1352 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1353 } else
1354 host->dma_len = dma_len;
1355
1356 return 0;
1357}
1358
a45c6cb8
MC		 1359/*
1360 * Routine to configure and start DMA for the MMC card
1361 */
9d025334 1362static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
70a3341a 1363 struct mmc_request *req)
a45c6cb8 1364{
26b88520
RK		 1365 struct dma_async_tx_descriptor *tx;
1366 int ret = 0, i;
a45c6cb8 1367 struct mmc_data *data = req->data;
c5c98927 1368 struct dma_chan *chan;
e5789608
PU		 1369 struct dma_slave_config cfg = {
1370 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1371 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1372 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1373 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1374 .src_maxburst = data->blksz / 4,
1375 .dst_maxburst = data->blksz / 4,
1376 };
a45c6cb8 1377
0ccd76d4 1378 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1379 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1380 struct scatterlist *sgl;
1381
1382 sgl = data->sg + i;
1383 if (sgl->length % data->blksz)
1384 return -EINVAL;
1385 }
1386 if ((data->blksz % 4) != 0)
1387 /* REVISIT: The MMC buffer increments only when MSB is written.
1388 * Return error for blksz which is non multiple of four.
1389 */
1390 return -EINVAL;
1391
b417577d 1392 BUG_ON(host->dma_ch != -1);
a45c6cb8 1393
c5c98927 1394 chan = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1395
26b88520
RK		 1396 ret = dmaengine_slave_config(chan, &cfg);
1397 if (ret)
a45c6cb8 1398 return ret;
c5c98927 1399
26b88520 1400 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
9782aff8
PF		 1401 if (ret)
1402 return ret;
a45c6cb8 1403
26b88520
RK		 1404 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1405 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1406 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1407 if (!tx) {
1408 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1409 /* FIXME: cleanup */
1410 return -1;
1411 }
a45c6cb8 1412
26b88520
RK		 1413 tx->callback = omap_hsmmc_dma_callback;
1414 tx->callback_param = host;
a45c6cb8 1415
26b88520
RK		 1416 /* Does not fail */
1417 dmaengine_submit(tx);
c5c98927 1418
26b88520 1419 host->dma_ch = 1;
c5c98927 1420
a45c6cb8
MC		 1421 return 0;
1422}
1423
70a3341a 1424static void set_data_timeout(struct omap_hsmmc_host *host,
a53210f5 1425 unsigned long long timeout_ns,
e2bf08d6 1426 unsigned int timeout_clks)
a45c6cb8 1427{
a53210f5
RK		 1428 unsigned long long timeout = timeout_ns;
1429 unsigned int cycle_ns;
a45c6cb8
MC		 1430 uint32_t reg, clkd, dto = 0;
1431
1432 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1433 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1434 if (clkd == 0)
1435 clkd = 1;
1436
6e3076c2 1437 cycle_ns = 1000000000 / (host->clk_rate / clkd);
a53210f5 1438 do_div(timeout, cycle_ns);
e2bf08d6 1439 timeout += timeout_clks;
a45c6cb8
MC		 1440 if (timeout) {
1441 while ((timeout & 0x80000000) == 0) {
1442 dto += 1;
1443 timeout <<= 1;
1444 }
1445 dto = 31 - dto;
1446 timeout <<= 1;
1447 if (timeout && dto)
1448 dto += 1;
1449 if (dto >= 13)
1450 dto -= 13;
1451 else
1452 dto = 0;
1453 if (dto > 14)
1454 dto = 14;
1455 }
1456
1457 reg &= ~DTO_MASK;
1458 reg |= dto << DTO_SHIFT;
1459 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1460}
1461
9d025334
B		 1462static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1463{
1464 struct mmc_request *req = host->mrq;
1465 struct dma_chan *chan;
1466
1467 if (!req->data)
1468 return;
1469 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1470 | (req->data->blocks << 16));
1471 set_data_timeout(host, req->data->timeout_ns,
1472 req->data->timeout_clks);
1473 chan = omap_hsmmc_get_dma_chan(host, req->data);
1474 dma_async_issue_pending(chan);
1475}
1476
a45c6cb8
MC		 1477/*
1478 * Configure block length for MMC/SD cards and initiate the transfer.
1479 */
1480static int
70a3341a 1481omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1482{
1483 int ret;
a53210f5 1484 unsigned long long timeout;
8cc9a3e7 1485
a45c6cb8
MC		 1486 host->data = req->data;
1487
1488 if (req->data == NULL) {
a45c6cb8 1489 OMAP_HSMMC_WRITE(host->base, BLK, 0);
8cc9a3e7
KVA		 1490 if (req->cmd->flags & MMC_RSP_BUSY) {
1491 timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
1492
1493 /*
1494 * Set an arbitrary 100ms data timeout for commands with
1495 * busy signal and no indication of busy_timeout.
1496 */
1497 if (!timeout)
1498 timeout = 100000000U;
1499
1500 set_data_timeout(host, timeout, 0);
1501 }
a45c6cb8
MC		 1502 return 0;
1503 }
1504
a45c6cb8 1505 if (host->use_dma) {
9d025334 1506 ret = omap_hsmmc_setup_dma_transfer(host, req);
a45c6cb8 1507 if (ret != 0) {
b1e056ae 1508 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
a45c6cb8
MC		 1509 return ret;
1510 }
1511 }
1512 return 0;
1513}
1514
9782aff8
PF		 1515static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1516 int err)
1517{
1518 struct omap_hsmmc_host *host = mmc_priv(mmc);
1519 struct mmc_data *data = mrq->data;
1520
26b88520 1521 if (host->use_dma && data->host_cookie) {
c5c98927 1522 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1523
26b88520 1524 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
feeef096 1525 mmc_get_dma_dir(data));
9782aff8
PF		 1526 data->host_cookie = 0;
1527 }
1528}
1529
d3c6aac3 1530static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
9782aff8
PF		 1531{
1532 struct omap_hsmmc_host *host = mmc_priv(mmc);
1533
1534 if (mrq->data->host_cookie) {
1535 mrq->data->host_cookie = 0;
1536 return ;
1537 }
1538
c5c98927
RK		 1539 if (host->use_dma) {
1540 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
c5c98927 1541
9782aff8 1542 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
26b88520 1543 &host->next_data, c))
9782aff8 1544 mrq->data->host_cookie = 0;
c5c98927 1545 }
9782aff8
PF		 1546}
1547
a45c6cb8
MC		 1548/*
1549 * Request function. for read/write operation
1550 */
70a3341a 1551static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1552{
70a3341a 1553 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1554 int err;
a45c6cb8 1555
b417577d
AH		 1556 BUG_ON(host->req_in_progress);
1557 BUG_ON(host->dma_ch != -1);
1558 if (host->protect_card) {
1559 if (host->reqs_blocked < 3) {
1560 /*
1561 * Ensure the controller is left in a consistent
1562 * state by resetting the command and data state
1563 * machines.
1564 */
1565 omap_hsmmc_reset_controller_fsm(host, SRD);
1566 omap_hsmmc_reset_controller_fsm(host, SRC);
1567 host->reqs_blocked += 1;
1568 }
1569 req->cmd->error = -EBADF;
1570 if (req->data)
1571 req->data->error = -EBADF;
1572 req->cmd->retries = 0;
1573 mmc_request_done(mmc, req);
1574 return;
1575 } else if (host->reqs_blocked)
1576 host->reqs_blocked = 0;
a45c6cb8
MC		 1577 WARN_ON(host->mrq != NULL);
1578 host->mrq = req;
6e3076c2 1579 host->clk_rate = clk_get_rate(host->fclk);
70a3341a 1580 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1581 if (err) {
1582 req->cmd->error = err;
1583 if (req->data)
1584 req->data->error = err;
1585 host->mrq = NULL;
1586 mmc_request_done(mmc, req);
1587 return;
1588 }
a2e77152 1589 if (req->sbc && !(host->flags & AUTO_CMD23)) {
bf129e1c
B		 1590 omap_hsmmc_start_command(host, req->sbc, NULL);
1591 return;
1592 }
a3f406f8 1593
9d025334 1594 omap_hsmmc_start_dma_transfer(host);
70a3341a 1595 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1596}
1597
a45c6cb8 1598/* Routine to configure clock values. Exposed API to core */
70a3341a 1599static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1600{
70a3341a 1601 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1602 int do_send_init_stream = 0;
a45c6cb8 1603
a3621465
AH		 1604 if (ios->power_mode != host->power_mode) {
1605 switch (ios->power_mode) {
1606 case MMC_POWER_OFF:
66162bec 1607 omap_hsmmc_set_power(host, 0);
a3621465
AH		 1608 break;
1609 case MMC_POWER_UP:
66162bec 1610 omap_hsmmc_set_power(host, 1);
a3621465
AH		 1611 break;
1612 case MMC_POWER_ON:
1613 do_send_init_stream = 1;
1614 break;
1615 }
1616 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1617 }
1618
dd498eff
DK		 1619 /* FIXME: set registers based only on changes to ios */
1620
3796fb8a 1621 omap_hsmmc_set_bus_width(host);
a45c6cb8 1622
4621d5f8 1623 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1624 /* Only MMC1 can interface at 3V without some flavor
1625 * of external transceiver; but they all handle 1.8V.
1626 */
a45c6cb8 1627 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
2cf171cb 1628 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
a45c6cb8
MC		 1629 /*
1630 * The mmc_select_voltage fn of the core does
1631 * not seem to set the power_mode to
1632 * MMC_POWER_UP upon recalculating the voltage.
1633 * vdd 1.8v.
1634 */
70a3341a
DK		 1635 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1636 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1637 "Switch operation failed\n");
1638 }
1639 }
1640
5934df2f 1641 omap_hsmmc_set_clock(host);
a45c6cb8 1642
a3621465 1643 if (do_send_init_stream)
a45c6cb8
MC		 1644 send_init_stream(host);
1645
3796fb8a 1646 omap_hsmmc_set_bus_mode(host);
a45c6cb8
MC		 1647}
1648
1649static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1650{
70a3341a 1651 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1652
b5cd43f0 1653 if (!host->card_detect)
a45c6cb8 1654 return -ENOSYS;
80412ca8 1655 return host->card_detect(host->dev);
a45c6cb8
MC		 1656}
1657
4816858c
GI		 1658static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1659{
1660 struct omap_hsmmc_host *host = mmc_priv(mmc);
1661
326119c9
AF		 1662 if (mmc_pdata(host)->init_card)
1663 mmc_pdata(host)->init_card(card);
4816858c
GI		 1664}
1665
2cd3a2a5
AF		 1666static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1667{
1668 struct omap_hsmmc_host *host = mmc_priv(mmc);
5a52b08b 1669 u32 irq_mask, con;
2cd3a2a5
AF		 1670 unsigned long flags;
1671
1672 spin_lock_irqsave(&host->irq_lock, flags);
1673
5a52b08b 1674 con = OMAP_HSMMC_READ(host->base, CON);
2cd3a2a5
AF		 1675 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1676 if (enable) {
1677 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1678 irq_mask |= CIRQ_EN;
5a52b08b 1679 con |= CTPL | CLKEXTFREE;
2cd3a2a5
AF		 1680 } else {
1681 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1682 irq_mask &= ~CIRQ_EN;
5a52b08b 1683 con &= ~(CTPL | CLKEXTFREE);
2cd3a2a5 1684 }
5a52b08b 1685 OMAP_HSMMC_WRITE(host->base, CON, con);
2cd3a2a5
AF		 1686 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1687
1688 /*
1689 * if enable, piggy back detection on current request
1690 * but always disable immediately
1691 */
1692 if (!host->req_in_progress || !enable)
1693 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1694
1695 /* flush posted write */
1696 OMAP_HSMMC_READ(host->base, IE);
1697
1698 spin_unlock_irqrestore(&host->irq_lock, flags);
1699}
1700
1701static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1702{
2cd3a2a5
AF		 1703 int ret;
1704
1705 /*
1706 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1707 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1708 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1709 * with functional clock disabled.
1710 */
1711 if (!host->dev->of_node || !host->wake_irq)
1712 return -ENODEV;
1713
5b83b223 1714 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
2cd3a2a5
AF		 1715 if (ret) {
1716 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1717 goto err;
1718 }
1719
1720 /*
1721 * Some omaps don't have wake-up path from deeper idle states
1722 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1723 */
1724 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
455e5cd6 1725 struct pinctrl *p = devm_pinctrl_get(host->dev);
ec5ab893
DC		 1726 if (IS_ERR(p)) {
1727 ret = PTR_ERR(p);
455e5cd6
AF		 1728 goto err_free_irq;
1729 }
1730 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1731 dev_info(host->dev, "missing default pinctrl state\n");
1732 devm_pinctrl_put(p);
1733 ret = -EINVAL;
1734 goto err_free_irq;
1735 }
1736
1737 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1738 dev_info(host->dev, "missing idle pinctrl state\n");
1739 devm_pinctrl_put(p);
1740 ret = -EINVAL;
1741 goto err_free_irq;
1742 }
1743 devm_pinctrl_put(p);
2cd3a2a5
AF		 1744 }
1745
5a52b08b
B		 1746 OMAP_HSMMC_WRITE(host->base, HCTL,
1747 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
2cd3a2a5
AF		 1748 return 0;
1749
455e5cd6 1750err_free_irq:
5b83b223 1751 dev_pm_clear_wake_irq(host->dev);
2cd3a2a5
AF		 1752err:
1753 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1754 host->wake_irq = 0;
1755 return ret;
1756}
1757
70a3341a 1758static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1759{
1760 u32 hctl, capa, value;
1761
1762 /* Only MMC1 supports 3.0V */
4621d5f8 1763 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1764 hctl = SDVS30;
1765 capa = VS30 | VS18;
1766 } else {
1767 hctl = SDVS18;
1768 capa = VS18;
1769 }
1770
1771 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1772 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1773
1774 value = OMAP_HSMMC_READ(host->base, CAPA);
1775 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1776
1b331e69 1777 /* Set SD bus power bit */
e13bb300 1778 set_sd_bus_power(host);
1b331e69
KK		 1779}
1780
afd8c29d
KM		 1781static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1782 unsigned int direction, int blk_size)
1783{
1784 /* This controller can't do multiblock reads due to hw bugs */
1785 if (direction == MMC_DATA_READ)
1786 return 1;
1787
1788 return blk_size;
1789}
1790
1791static struct mmc_host_ops omap_hsmmc_ops = {
9782aff8
PF		 1792 .post_req = omap_hsmmc_post_req,
1793 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1794 .request = omap_hsmmc_request,
1795 .set_ios = omap_hsmmc_set_ios,
dd498eff 1796 .get_cd = omap_hsmmc_get_cd,
a49d8353 1797 .get_ro = mmc_gpio_get_ro,
4816858c 1798 .init_card = omap_hsmmc_init_card,
2cd3a2a5 1799 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
dd498eff
DK		 1800};
1801
d900f712
DK		 1802#ifdef CONFIG_DEBUG_FS
1803
70a3341a 1804static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1805{
1806 struct mmc_host *mmc = s->private;
70a3341a 1807 struct omap_hsmmc_host *host = mmc_priv(mmc);
d900f712 1808
bb0635f0
AF		 1809 seq_printf(s, "mmc%d:\n", mmc->index);
1810 seq_printf(s, "sdio irq mode\t%s\n",
1811 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
5e2ea617 1812
bb0635f0
AF		 1813 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1814 seq_printf(s, "sdio irq \t%s\n",
1815 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1816 : "disabled");
1817 }
1818 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
d900f712 1819
bb0635f0
AF		 1820 pm_runtime_get_sync(host->dev);
1821 seq_puts(s, "\nregs:\n");
d900f712
DK		 1822 seq_printf(s, "CON:\t\t0x%08x\n",
1823 OMAP_HSMMC_READ(host->base, CON));
bb0635f0
AF		 1824 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1825 OMAP_HSMMC_READ(host->base, PSTATE));
d900f712
DK		 1826 seq_printf(s, "HCTL:\t\t0x%08x\n",
1827 OMAP_HSMMC_READ(host->base, HCTL));
1828 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1829 OMAP_HSMMC_READ(host->base, SYSCTL));
1830 seq_printf(s, "IE:\t\t0x%08x\n",
1831 OMAP_HSMMC_READ(host->base, IE));
1832 seq_printf(s, "ISE:\t\t0x%08x\n",
1833 OMAP_HSMMC_READ(host->base, ISE));
1834 seq_printf(s, "CAPA:\t\t0x%08x\n",
1835 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1836
fa4aa2d4
B		 1837 pm_runtime_mark_last_busy(host->dev);
1838 pm_runtime_put_autosuspend(host->dev);
dd498eff 1839
d900f712
DK		 1840 return 0;
1841}
1842
70a3341a 1843static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1844{
70a3341a 1845 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1846}
1847
1848static const struct file_operations mmc_regs_fops = {
70a3341a 1849 .open = omap_hsmmc_regs_open,
d900f712
DK		 1850 .read = seq_read,
1851 .llseek = seq_lseek,
1852 .release = single_release,
1853};
1854
70a3341a 1855static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1856{
1857 if (mmc->debugfs_root)
1858 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1859 mmc, &mmc_regs_fops);
1860}
1861
1862#else
1863
70a3341a 1864static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1865{
1866}
1867
1868#endif
1869
46856a68 1870#ifdef CONFIG_OF
59445b10
NM		 1871static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1872 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1873 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1874};
1875
1876static const struct omap_mmc_of_data omap4_mmc_of_data = {
1877 .reg_offset = 0x100,
1878};
2cd3a2a5
AF		 1879static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1880 .reg_offset = 0x100,
1881 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1882};
46856a68
RN		 1883
1884static const struct of_device_id omap_mmc_of_match[] = {
1885 {
1886 .compatible = "ti,omap2-hsmmc",
1887 },
59445b10
NM		 1888 {
1889 .compatible = "ti,omap3-pre-es3-hsmmc",
1890 .data = &omap3_pre_es3_mmc_of_data,
1891 },
46856a68
RN		 1892 {
1893 .compatible = "ti,omap3-hsmmc",
1894 },
1895 {
1896 .compatible = "ti,omap4-hsmmc",
59445b10 1897 .data = &omap4_mmc_of_data,
46856a68 1898 },
2cd3a2a5
AF		 1899 {
1900 .compatible = "ti,am33xx-hsmmc",
1901 .data = &am33xx_mmc_of_data,
1902 },
46856a68 1903 {},
b6d085f6 1904};
46856a68
RN		 1905MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1906
55143438 1907static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
46856a68 1908{
db863d89 1909 struct omap_hsmmc_platform_data *pdata, *legacy;
46856a68 1910 struct device_node *np = dev->of_node;
46856a68
RN		 1911
1912 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1913 if (!pdata)
19df45bc 1914 return ERR_PTR(-ENOMEM); /* out of memory */
46856a68 1915
db863d89
TL		 1916 legacy = dev_get_platdata(dev);
1917 if (legacy && legacy->name)
1918 pdata->name = legacy->name;
1919
46856a68
RN		 1920 if (of_find_property(np, "ti,dual-volt", NULL))
1921 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1922
b7a5646f
AF		 1923 pdata->gpio_cd = -EINVAL;
1924 pdata->gpio_cod = -EINVAL;
fdb9de12 1925 pdata->gpio_wp = -EINVAL;
46856a68
RN		 1926
1927 if (of_find_property(np, "ti,non-removable", NULL)) {
326119c9
AF		 1928 pdata->nonremovable = true;
1929 pdata->no_regulator_off_init = true;
46856a68 1930 }
46856a68
RN		 1931
1932 if (of_find_property(np, "ti,needs-special-reset", NULL))
326119c9 1933 pdata->features |= HSMMC_HAS_UPDATED_RESET;
46856a68 1934
cd587096 1935 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
326119c9 1936 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
cd587096 1937
46856a68
RN		 1938 return pdata;
1939}
1940#else
55143438 1941static inline struct omap_hsmmc_platform_data
46856a68
RN		 1942 *of_get_hsmmc_pdata(struct device *dev)
1943{
19df45bc 1944 return ERR_PTR(-EINVAL);
46856a68
RN		 1945}
1946#endif
1947
c3be1efd 1948static int omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8 1949{
55143438 1950 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
a45c6cb8 1951 struct mmc_host *mmc;
70a3341a 1952 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1953 struct resource *res;
db0fefc5 1954 int ret, irq;
46856a68 1955 const struct of_device_id *match;
59445b10 1956 const struct omap_mmc_of_data *data;
77fae219 1957 void __iomem *base;
46856a68
RN		 1958
1959 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1960 if (match) {
1961 pdata = of_get_hsmmc_pdata(&pdev->dev);
dc642c28
JL		 1962
1963 if (IS_ERR(pdata))
1964 return PTR_ERR(pdata);
1965
46856a68 1966 if (match->data) {
59445b10
NM		 1967 data = match->data;
1968 pdata->reg_offset = data->reg_offset;
1969 pdata->controller_flags |= data->controller_flags;
46856a68
RN		 1970 }
1971 }
a45c6cb8
MC		 1972
1973 if (pdata == NULL) {
1974 dev_err(&pdev->dev, "Platform Data is missing\n");
1975 return -ENXIO;
1976 }
1977
a45c6cb8
MC		 1978 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1979 irq = platform_get_irq(pdev, 0);
1980 if (res == NULL || irq < 0)
1981 return -ENXIO;
1982
77fae219
B		 1983 base = devm_ioremap_resource(&pdev->dev, res);
1984 if (IS_ERR(base))
1985 return PTR_ERR(base);
a45c6cb8 1986
70a3341a 1987 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1988 if (!mmc) {
1989 ret = -ENOMEM;
1e363e3b 1990 goto err;
a45c6cb8
MC		 1991 }
1992
fdb9de12
N		 1993 ret = mmc_of_parse(mmc);
1994 if (ret)
1995 goto err1;
1996
a45c6cb8
MC		 1997 host = mmc_priv(mmc);
1998 host->mmc = mmc;
1999 host->pdata = pdata;
2000 host->dev = &pdev->dev;
2001 host->use_dma = 1;
a45c6cb8
MC		 2002 host->dma_ch = -1;
2003 host->irq = irq;
fc307df8 2004 host->mapbase = res->start + pdata->reg_offset;
77fae219 2005 host->base = base + pdata->reg_offset;
6da20c89 2006 host->power_mode = MMC_POWER_OFF;
9782aff8 2007 host->next_data.cookie = 1;
bb2726b5 2008 host->pbias_enabled = 0;
3f77f702 2009 host->vqmmc_enabled = 0;
a45c6cb8 2010
41afa314 2011 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
1e363e3b
AF		 2012 if (ret)
2013 goto err_gpio;
2014
a45c6cb8 2015 platform_set_drvdata(pdev, host);
a45c6cb8 2016
2cd3a2a5
AF		 2017 if (pdev->dev.of_node)
2018 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2019
7a8c2cef 2020 mmc->ops = &omap_hsmmc_ops;
dd498eff 2021
d418ed87
DM		 2022 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2023
2024 if (pdata->max_freq > 0)
2025 mmc->f_max = pdata->max_freq;
fdb9de12 2026 else if (mmc->f_max == 0)
d418ed87 2027 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 2028
4dffd7a2 2029 spin_lock_init(&host->irq_lock);
a45c6cb8 2030
9618195e 2031 host->fclk = devm_clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 2032 if (IS_ERR(host->fclk)) {
2033 ret = PTR_ERR(host->fclk);
2034 host->fclk = NULL;
a45c6cb8
MC		 2035 goto err1;
2036 }
2037
9b68256c
PW		 2038 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2039 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
afd8c29d 2040 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
9b68256c 2041 }
dd498eff 2042
5b83b223 2043 device_init_wakeup(&pdev->dev, true);
fa4aa2d4
B		 2044 pm_runtime_enable(host->dev);
2045 pm_runtime_get_sync(host->dev);
2046 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2047 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 2048
92a3aebf
B		 2049 omap_hsmmc_context_save(host);
2050
9618195e 2051 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
cd03d9a8
RN		 2052 /*
2053 * MMC can still work without debounce clock.
2054 */
2055 if (IS_ERR(host->dbclk)) {
cd03d9a8 2056 host->dbclk = NULL;
94c18149 2057 } else if (clk_prepare_enable(host->dbclk) != 0) {
cd03d9a8 2058 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
cd03d9a8 2059 host->dbclk = NULL;
2bec0893 2060 }
a45c6cb8 2061
94424004
WN		 2062 /* Set this to a value that allows allocating an entire descriptor
2063 * list within a page (zero order allocation). */
2064 mmc->max_segs = 64;
0ccd76d4 2065
a45c6cb8
MC		 2066 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2067 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2068 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2069 mmc->max_seg_size = mmc->max_req_size;
2070
13189e78 2071 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
ac2b2115 2072 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23;
a45c6cb8 2073
326119c9 2074 mmc->caps |= mmc_pdata(host)->caps;
3a63833e 2075 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 2076 mmc->caps |= MMC_CAP_4_BIT_DATA;
2077
326119c9 2078 if (mmc_pdata(host)->nonremovable)
23d99bb9
AH		 2079 mmc->caps |= MMC_CAP_NONREMOVABLE;
2080
fdb9de12 2081 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
6fdc75de 2082
70a3341a 2083 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2084
81eef6ca
PU		 2085 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
2086 if (IS_ERR(host->rx_chan)) {
2087 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
2088 ret = PTR_ERR(host->rx_chan);
26b88520
RK		 2089 goto err_irq;
2090 }
2091
81eef6ca
PU		 2092 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
2093 if (IS_ERR(host->tx_chan)) {
2094 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
2095 ret = PTR_ERR(host->tx_chan);
26b88520 2096 goto err_irq;
c5c98927 2097 }
a45c6cb8
MC		 2098
2099 /* Request IRQ for MMC operations */
e1538ed7 2100 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 2101 mmc_hostname(mmc), host);
2102 if (ret) {
b1e056ae 2103 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
a45c6cb8
MC		 2104 goto err_irq;
2105 }
2106
987e05c9
KVA		 2107 ret = omap_hsmmc_reg_get(host);
2108 if (ret)
2109 goto err_irq;
db0fefc5 2110
13ab2a66
KVA		 2111 if (!mmc->ocr_avail)
2112 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
a45c6cb8 2113
b417577d 2114 omap_hsmmc_disable_irq(host);
a45c6cb8 2115
2cd3a2a5
AF		 2116 /*
2117 * For now, only support SDIO interrupt if we have a separate
2118 * wake-up interrupt configured from device tree. This is because
2119 * the wake-up interrupt is needed for idle state and some
2120 * platforms need special quirks. And we don't want to add new
2121 * legacy mux platform init code callbacks any longer as we
2122 * are moving to DT based booting anyways.
2123 */
2124 ret = omap_hsmmc_configure_wake_irq(host);
2125 if (!ret)
2126 mmc->caps |= MMC_CAP_SDIO_IRQ;
2127
b62f6228
AH		 2128 omap_hsmmc_protect_card(host);
2129
a45c6cb8
MC		 2130 mmc_add_host(mmc);
2131
326119c9 2132 if (mmc_pdata(host)->name != NULL) {
a45c6cb8
MC		 2133 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2134 if (ret < 0)
2135 goto err_slot_name;
2136 }
cde592cb 2137 if (host->get_cover_state) {
a45c6cb8 2138 ret = device_create_file(&mmc->class_dev,
cde592cb 2139 &dev_attr_cover_switch);
a45c6cb8 2140 if (ret < 0)
db0fefc5 2141 goto err_slot_name;
a45c6cb8
MC		 2142 }
2143
70a3341a 2144 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2145 pm_runtime_mark_last_busy(host->dev);
2146 pm_runtime_put_autosuspend(host->dev);
d900f712 2147
a45c6cb8
MC		 2148 return 0;
2149
a45c6cb8
MC		 2150err_slot_name:
2151 mmc_remove_host(mmc);
a45c6cb8 2152err_irq:
5b83b223 2153 device_init_wakeup(&pdev->dev, false);
81eef6ca 2154 if (!IS_ERR_OR_NULL(host->tx_chan))
c5c98927 2155 dma_release_channel(host->tx_chan);
81eef6ca 2156 if (!IS_ERR_OR_NULL(host->rx_chan))
c5c98927 2157 dma_release_channel(host->rx_chan);
814a3c0c 2158 pm_runtime_dont_use_autosuspend(host->dev);
d59d77ed 2159 pm_runtime_put_sync(host->dev);
37f6190d 2160 pm_runtime_disable(host->dev);
9618195e 2161 if (host->dbclk)
94c18149 2162 clk_disable_unprepare(host->dbclk);
a45c6cb8 2163err1:
1e363e3b 2164err_gpio:
db0fefc5 2165 mmc_free_host(mmc);
a45c6cb8 2166err:
a45c6cb8
MC		 2167 return ret;
2168}
2169
6e0ee714 2170static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2171{
70a3341a 2172 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8 2173
927ce944
FB		 2174 pm_runtime_get_sync(host->dev);
2175 mmc_remove_host(host->mmc);
a45c6cb8 2176
dc28562b
PU		 2177 dma_release_channel(host->tx_chan);
2178 dma_release_channel(host->rx_chan);
c5c98927 2179
814a3c0c 2180 pm_runtime_dont_use_autosuspend(host->dev);
927ce944
FB		 2181 pm_runtime_put_sync(host->dev);
2182 pm_runtime_disable(host->dev);
5b83b223 2183 device_init_wakeup(&pdev->dev, false);
9618195e 2184 if (host->dbclk)
94c18149 2185 clk_disable_unprepare(host->dbclk);
a45c6cb8 2186
9d1f0286 2187 mmc_free_host(host->mmc);
927ce944 2188
a45c6cb8
MC		 2189 return 0;
2190}
2191
3d3bbfbd 2192#ifdef CONFIG_PM_SLEEP
a791daa1 2193static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8 2194{
927ce944 2195 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2196
927ce944 2197 if (!host)
a45c6cb8
MC		 2198 return 0;
2199
927ce944 2200 pm_runtime_get_sync(host->dev);
31f9d463 2201
927ce944 2202 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2cd3a2a5
AF		 2203 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2204 OMAP_HSMMC_WRITE(host->base, IE, 0);
2205 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
927ce944
FB		 2206 OMAP_HSMMC_WRITE(host->base, HCTL,
2207 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2208 }
927ce944 2209
cd03d9a8 2210 if (host->dbclk)
94c18149 2211 clk_disable_unprepare(host->dbclk);
3932afd5 2212
31f9d463 2213 pm_runtime_put_sync(host->dev);
3932afd5 2214 return 0;
a45c6cb8
MC		 2215}
2216
2217/* Routine to resume the MMC device */
a791daa1 2218static int omap_hsmmc_resume(struct device *dev)
a45c6cb8 2219{
927ce944
FB		 2220 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2221
2222 if (!host)
2223 return 0;
a45c6cb8 2224
927ce944 2225 pm_runtime_get_sync(host->dev);
11dd62a7 2226
cd03d9a8 2227 if (host->dbclk)
94c18149 2228 clk_prepare_enable(host->dbclk);
2bec0893 2229
927ce944
FB		 2230 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2231 omap_hsmmc_conf_bus_power(host);
1b331e69 2232
927ce944 2233 omap_hsmmc_protect_card(host);
927ce944
FB		 2234 pm_runtime_mark_last_busy(host->dev);
2235 pm_runtime_put_autosuspend(host->dev);
3932afd5 2236 return 0;
a45c6cb8 2237}
a45c6cb8
MC		 2238#endif
2239
fa4aa2d4
B		 2240static int omap_hsmmc_runtime_suspend(struct device *dev)
2241{
2242 struct omap_hsmmc_host *host;
2cd3a2a5 2243 unsigned long flags;
f945901f 2244 int ret = 0;
fa4aa2d4
B		 2245
2246 host = platform_get_drvdata(to_platform_device(dev));
2247 omap_hsmmc_context_save(host);
927ce944 2248 dev_dbg(dev, "disabled\n");
fa4aa2d4 2249
2cd3a2a5
AF		 2250 spin_lock_irqsave(&host->irq_lock, flags);
2251 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2252 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2253 /* disable sdio irq handling to prevent race */
2254 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2255 OMAP_HSMMC_WRITE(host->base, IE, 0);
f945901f
AF		 2256
2257 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2258 /*
2259 * dat1 line low, pending sdio irq
2260 * race condition: possible irq handler running on
2261 * multi-core, abort
2262 */
2263 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2264 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2265 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2266 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2267 pm_runtime_mark_last_busy(dev);
2268 ret = -EBUSY;
2269 goto abort;
2270 }
2cd3a2a5 2271
97978a44 2272 pinctrl_pm_select_idle_state(dev);
97978a44
AF		 2273 } else {
2274 pinctrl_pm_select_idle_state(dev);
2cd3a2a5 2275 }
97978a44 2276
f945901f 2277abort:
2cd3a2a5 2278 spin_unlock_irqrestore(&host->irq_lock, flags);
f945901f 2279 return ret;
fa4aa2d4
B		 2280}
2281
2282static int omap_hsmmc_runtime_resume(struct device *dev)
2283{
2284 struct omap_hsmmc_host *host;
2cd3a2a5 2285 unsigned long flags;
fa4aa2d4
B		 2286
2287 host = platform_get_drvdata(to_platform_device(dev));
2288 omap_hsmmc_context_restore(host);
927ce944 2289 dev_dbg(dev, "enabled\n");
fa4aa2d4 2290
2cd3a2a5
AF		 2291 spin_lock_irqsave(&host->irq_lock, flags);
2292 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2293 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2cd3a2a5 2294
97978a44
AF		 2295 pinctrl_pm_select_default_state(host->dev);
2296
2297 /* irq lost, if pinmux incorrect */
2cd3a2a5
AF		 2298 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2299 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2300 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
97978a44
AF		 2301 } else {
2302 pinctrl_pm_select_default_state(host->dev);
2cd3a2a5
AF		 2303 }
2304 spin_unlock_irqrestore(&host->irq_lock, flags);
fa4aa2d4
B		 2305 return 0;
2306}
2307
6bba4064 2308static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
3d3bbfbd 2309 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
fa4aa2d4
B		 2310 .runtime_suspend = omap_hsmmc_runtime_suspend,
2311 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2312};
2313
2314static struct platform_driver omap_hsmmc_driver = {
efa25fd3 2315 .probe = omap_hsmmc_probe,
0433c143 2316 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2317 .driver = {
2318 .name = DRIVER_NAME,
a791daa1 2319 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2320 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2321 },
2322};
2323
b796450b 2324module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2325MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2326MODULE_LICENSE("GPL");
2327MODULE_ALIAS("platform:" DRIVER_NAME);
2328MODULE_AUTHOR("Texas Instruments Inc");
Linux 6.x block layer and io_uring tree(s)