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mmc: mxcmmc: DT support
[linux-2.6-block.git] / drivers / mmc / host / mxcmmc.c
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d96be879
SH		 1/*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
3ad2f3fb 7 * not need all the quirks found in imxmmc.c, hence the separate driver.
d96be879
SH		 8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/blkdev.h>
27#include <linux/dma-mapping.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
74b66954 34#include <linux/regulator/consumer.h>
f53fbde4 35#include <linux/dmaengine.h>
258aea76 36#include <linux/types.h>
7ff747c4
MP		 37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_dma.h>
40#include <linux/of_gpio.h>
d96be879
SH		 41
42#include <asm/dma.h>
43#include <asm/irq.h>
44#include <asm/sizes.h>
82906b13 45#include <linux/platform_data/mmc-mxcmmc.h>
d96be879 46
82906b13 47#include <linux/platform_data/dma-imx.h>
d96be879 48
9563b1db 49#define DRIVER_NAME "mxc-mmc"
f6ad0a48 50#define MXCMCI_TIMEOUT_MS 10000
d96be879
SH		 51
52#define MMC_REG_STR_STP_CLK 0x00
53#define MMC_REG_STATUS 0x04
54#define MMC_REG_CLK_RATE 0x08
55#define MMC_REG_CMD_DAT_CONT 0x0C
56#define MMC_REG_RES_TO 0x10
57#define MMC_REG_READ_TO 0x14
58#define MMC_REG_BLK_LEN 0x18
59#define MMC_REG_NOB 0x1C
60#define MMC_REG_REV_NO 0x20
61#define MMC_REG_INT_CNTR 0x24
62#define MMC_REG_CMD 0x28
63#define MMC_REG_ARG 0x2C
64#define MMC_REG_RES_FIFO 0x34
65#define MMC_REG_BUFFER_ACCESS 0x38
66
67#define STR_STP_CLK_RESET (1 << 3)
68#define STR_STP_CLK_START_CLK (1 << 1)
69#define STR_STP_CLK_STOP_CLK (1 << 0)
70
71#define STATUS_CARD_INSERTION (1 << 31)
72#define STATUS_CARD_REMOVAL (1 << 30)
73#define STATUS_YBUF_EMPTY (1 << 29)
74#define STATUS_XBUF_EMPTY (1 << 28)
75#define STATUS_YBUF_FULL (1 << 27)
76#define STATUS_XBUF_FULL (1 << 26)
77#define STATUS_BUF_UND_RUN (1 << 25)
78#define STATUS_BUF_OVFL (1 << 24)
79#define STATUS_SDIO_INT_ACTIVE (1 << 14)
80#define STATUS_END_CMD_RESP (1 << 13)
81#define STATUS_WRITE_OP_DONE (1 << 12)
82#define STATUS_DATA_TRANS_DONE (1 << 11)
83#define STATUS_READ_OP_DONE (1 << 11)
84#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
85#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
86#define STATUS_BUF_READ_RDY (1 << 7)
87#define STATUS_BUF_WRITE_RDY (1 << 6)
88#define STATUS_RESP_CRC_ERR (1 << 5)
89#define STATUS_CRC_READ_ERR (1 << 3)
90#define STATUS_CRC_WRITE_ERR (1 << 2)
91#define STATUS_TIME_OUT_RESP (1 << 1)
92#define STATUS_TIME_OUT_READ (1 << 0)
93#define STATUS_ERR_MASK 0x2f
94
95#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
96#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
97#define CMD_DAT_CONT_START_READWAIT (1 << 10)
98#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
99#define CMD_DAT_CONT_INIT (1 << 7)
100#define CMD_DAT_CONT_WRITE (1 << 4)
101#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
102#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
103#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
104#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
105
106#define INT_SDIO_INT_WKP_EN (1 << 18)
107#define INT_CARD_INSERTION_WKP_EN (1 << 17)
108#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
109#define INT_CARD_INSERTION_EN (1 << 15)
110#define INT_CARD_REMOVAL_EN (1 << 14)
111#define INT_SDIO_IRQ_EN (1 << 13)
112#define INT_DAT0_EN (1 << 12)
113#define INT_BUF_READ_EN (1 << 4)
114#define INT_BUF_WRITE_EN (1 << 3)
115#define INT_END_CMD_RES_EN (1 << 2)
116#define INT_WRITE_OP_DONE_EN (1 << 1)
117#define INT_READ_OP_EN (1 << 0)
118
7f917a8d
SG		 119enum mxcmci_type {
120 IMX21_MMC,
121 IMX31_MMC,
122};
123
d96be879
SH		 124struct mxcmci_host {
125 struct mmc_host *mmc;
126 struct resource *res;
127 void __iomem *base;
128 int irq;
129 int detect_irq;
f53fbde4
SH		 130 struct dma_chan *dma;
131 struct dma_async_tx_descriptor *desc;
d96be879 132 int do_dma;
16b3bf8c 133 int default_irq_mask;
f441b993 134 int use_sdio;
d96be879
SH		 135 unsigned int power_mode;
136 struct imxmmc_platform_data *pdata;
137
138 struct mmc_request *req;
139 struct mmc_command *cmd;
140 struct mmc_data *data;
141
d96be879
SH		 142 unsigned int datasize;
143 unsigned int dma_dir;
144
145 u16 rev_no;
146 unsigned int cmdat;
147
529aa29e
SH		 148 struct clk *clk_ipg;
149 struct clk *clk_per;
d96be879
SH		 150
151 int clock;
152
153 struct work_struct datawork;
f441b993 154 spinlock_t lock;
74b66954
AP		 155
156 struct regulator *vcc;
f53fbde4
SH		 157
158 int burstlen;
159 int dmareq;
160 struct dma_slave_config dma_slave_config;
161 struct imx_dma_data dma_data;
f6ad0a48
JM		 162
163 struct timer_list watchdog;
7f917a8d
SG		 164 enum mxcmci_type devtype;
165};
166
167static struct platform_device_id mxcmci_devtype[] = {
168 {
169 .name = "imx21-mmc",
170 .driver_data = IMX21_MMC,
171 }, {
172 .name = "imx31-mmc",
173 .driver_data = IMX31_MMC,
174 }, {
175 /* sentinel */
176 }
d96be879 177};
7f917a8d
SG		 178MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
179
7ff747c4
MP		 180static const struct of_device_id mxcmci_of_match[] = {
181 {
182 .compatible = "fsl,imx21-mmc",
183 .data = &mxcmci_devtype[IMX21_MMC],
184 }, {
185 .compatible = "fsl,imx31-mmc",
186 .data = &mxcmci_devtype[IMX31_MMC],
187 }, {
188 /* sentinel */
189 }
190};
191MODULE_DEVICE_TABLE(of, mxcmci_of_match);
192
7f917a8d
SG		 193static inline int is_imx31_mmc(struct mxcmci_host *host)
194{
195 return host->devtype == IMX31_MMC;
196}
d96be879 197
18489fa2
MF		 198static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
199
74b66954
AP		 200static inline void mxcmci_init_ocr(struct mxcmci_host *host)
201{
74b66954
AP		 202 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
203
204 if (IS_ERR(host->vcc)) {
205 host->vcc = NULL;
206 } else {
207 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
208 if (host->pdata && host->pdata->ocr_avail)
209 dev_warn(mmc_dev(host->mmc),
210 "pdata->ocr_avail will not be used\n");
211 }
d078d242 212
74b66954
AP		 213 if (host->vcc == NULL) {
214 /* fall-back to platform data */
215 if (host->pdata && host->pdata->ocr_avail)
216 host->mmc->ocr_avail = host->pdata->ocr_avail;
217 else
218 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
219 }
220}
221
d078d242
AP		 222static inline void mxcmci_set_power(struct mxcmci_host *host,
223 unsigned char power_mode,
224 unsigned int vdd)
74b66954 225{
d078d242
AP		 226 if (host->vcc) {
227 if (power_mode == MMC_POWER_UP)
228 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
229 else if (power_mode == MMC_POWER_OFF)
230 mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
231 }
232
74b66954
AP		 233 if (host->pdata && host->pdata->setpower)
234 host->pdata->setpower(mmc_dev(host->mmc), vdd);
235}
236
d96be879
SH		 237static inline int mxcmci_use_dma(struct mxcmci_host *host)
238{
239 return host->do_dma;
240}
241
242static void mxcmci_softreset(struct mxcmci_host *host)
243{
244 int i;
245
4725f6f1
DM		 246 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
247
d96be879
SH		 248 /* reset sequence */
249 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
250 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
251 host->base + MMC_REG_STR_STP_CLK);
252
253 for (i = 0; i < 8; i++)
254 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
255
256 writew(0xff, host->base + MMC_REG_RES_TO);
257}
f53fbde4 258static int mxcmci_setup_dma(struct mmc_host *mmc);
d96be879 259
656217d2 260static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
d96be879
SH		 261{
262 unsigned int nob = data->blocks;
263 unsigned int blksz = data->blksz;
264 unsigned int datasize = nob * blksz;
d96be879 265 struct scatterlist *sg;
05f5799c 266 enum dma_transfer_direction slave_dirn;
f53fbde4
SH		 267 int i, nents;
268
d96be879
SH		 269 if (data->flags & MMC_DATA_STREAM)
270 nob = 0xffff;
271
272 host->data = data;
273 data->bytes_xfered = 0;
274
275 writew(nob, host->base + MMC_REG_NOB);
276 writew(blksz, host->base + MMC_REG_BLK_LEN);
277 host->datasize = datasize;
278
f53fbde4
SH		 279 if (!mxcmci_use_dma(host))
280 return 0;
281
d96be879 282 for_each_sg(data->sg, sg, data->sg_len, i) {
2cb53552 283 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
d96be879 284 host->do_dma = 0;
656217d2 285 return 0;
d96be879
SH		 286 }
287 }
288
05f5799c 289 if (data->flags & MMC_DATA_READ) {
d96be879 290 host->dma_dir = DMA_FROM_DEVICE;
05f5799c
VK		 291 slave_dirn = DMA_DEV_TO_MEM;
292 } else {
d96be879 293 host->dma_dir = DMA_TO_DEVICE;
05f5799c
VK		 294 slave_dirn = DMA_MEM_TO_DEV;
295 }
d96be879 296
f53fbde4
SH		 297 nents = dma_map_sg(host->dma->device->dev, data->sg,
298 data->sg_len, host->dma_dir);
299 if (nents != data->sg_len)
300 return -EINVAL;
301
16052827 302 host->desc = dmaengine_prep_slave_sg(host->dma,
05f5799c 303 data->sg, data->sg_len, slave_dirn,
f53fbde4 304 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
d96be879 305
f53fbde4
SH		 306 if (!host->desc) {
307 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
308 host->dma_dir);
309 host->do_dma = 0;
310 return 0; /* Fall back to PIO */
656217d2 311 }
d96be879
SH		 312 wmb();
313
f53fbde4 314 dmaengine_submit(host->desc);
439aa0ef 315 dma_async_issue_pending(host->dma);
f53fbde4 316
f6ad0a48
JM		 317 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
318
656217d2 319 return 0;
d96be879
SH		 320}
321
f6ad0a48
JM		 322static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
323static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
324
325static void mxcmci_dma_callback(void *data)
326{
327 struct mxcmci_host *host = data;
328 u32 stat;
329
330 del_timer(&host->watchdog);
331
332 stat = readl(host->base + MMC_REG_STATUS);
333 writel(stat & ~STATUS_DATA_TRANS_DONE, host->base + MMC_REG_STATUS);
334
335 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
336
337 if (stat & STATUS_READ_OP_DONE)
338 writel(STATUS_READ_OP_DONE, host->base + MMC_REG_STATUS);
339
340 mxcmci_data_done(host, stat);
341}
342
d96be879
SH		 343static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
344 unsigned int cmdat)
345{
16b3bf8c 346 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 347 unsigned long flags;
348
d96be879
SH		 349 WARN_ON(host->cmd != NULL);
350 host->cmd = cmd;
351
352 switch (mmc_resp_type(cmd)) {
353 case MMC_RSP_R1: /* short CRC, OPCODE */
354 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
355 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
356 break;
357 case MMC_RSP_R2: /* long 136 bit + CRC */
358 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
359 break;
360 case MMC_RSP_R3: /* short */
361 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
362 break;
363 case MMC_RSP_NONE:
364 break;
365 default:
366 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
367 mmc_resp_type(cmd));
368 cmd->error = -EINVAL;
369 return -EINVAL;
370 }
371
f441b993
DM		 372 int_cntr = INT_END_CMD_RES_EN;
373
f6ad0a48
JM		 374 if (mxcmci_use_dma(host)) {
375 if (host->dma_dir == DMA_FROM_DEVICE) {
376 host->desc->callback = mxcmci_dma_callback;
377 host->desc->callback_param = host;
378 } else {
379 int_cntr |= INT_WRITE_OP_DONE_EN;
380 }
381 }
f441b993
DM		 382
383 spin_lock_irqsave(&host->lock, flags);
384 if (host->use_sdio)
385 int_cntr |= INT_SDIO_IRQ_EN;
386 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
387 spin_unlock_irqrestore(&host->lock, flags);
d96be879
SH		 388
389 writew(cmd->opcode, host->base + MMC_REG_CMD);
390 writel(cmd->arg, host->base + MMC_REG_ARG);
391 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
392
393 return 0;
394}
395
396static void mxcmci_finish_request(struct mxcmci_host *host,
397 struct mmc_request *req)
398{
16b3bf8c 399 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 400 unsigned long flags;
401
402 spin_lock_irqsave(&host->lock, flags);
403 if (host->use_sdio)
404 int_cntr |= INT_SDIO_IRQ_EN;
405 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
406 spin_unlock_irqrestore(&host->lock, flags);
d96be879
SH		 407
408 host->req = NULL;
409 host->cmd = NULL;
410 host->data = NULL;
411
412 mmc_request_done(host->mmc, req);
413}
414
415static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
416{
417 struct mmc_data *data = host->data;
418 int data_error;
419
f6ad0a48 420 if (mxcmci_use_dma(host))
f53fbde4 421 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
d96be879 422 host->dma_dir);
d96be879
SH		 423
424 if (stat & STATUS_ERR_MASK) {
425 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
426 stat);
427 if (stat & STATUS_CRC_READ_ERR) {
4725f6f1 428 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
d96be879
SH		 429 data->error = -EILSEQ;
430 } else if (stat & STATUS_CRC_WRITE_ERR) {
431 u32 err_code = (stat >> 9) & 0x3;
4725f6f1
DM		 432 if (err_code == 2) { /* No CRC response */
433 dev_err(mmc_dev(host->mmc),
434 "%s: No CRC -ETIMEDOUT\n", __func__);
d96be879 435 data->error = -ETIMEDOUT;
4725f6f1
DM		 436 } else {
437 dev_err(mmc_dev(host->mmc),
438 "%s: -EILSEQ\n", __func__);
d96be879 439 data->error = -EILSEQ;
4725f6f1 440 }
d96be879 441 } else if (stat & STATUS_TIME_OUT_READ) {
4725f6f1
DM		 442 dev_err(mmc_dev(host->mmc),
443 "%s: read -ETIMEDOUT\n", __func__);
d96be879
SH		 444 data->error = -ETIMEDOUT;
445 } else {
4725f6f1 446 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
d96be879
SH		 447 data->error = -EIO;
448 }
449 } else {
450 data->bytes_xfered = host->datasize;
451 }
452
453 data_error = data->error;
454
455 host->data = NULL;
456
457 return data_error;
458}
459
460static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
461{
462 struct mmc_command *cmd = host->cmd;
463 int i;
464 u32 a, b, c;
465
466 if (!cmd)
467 return;
468
469 if (stat & STATUS_TIME_OUT_RESP) {
470 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
471 cmd->error = -ETIMEDOUT;
472 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
473 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
474 cmd->error = -EILSEQ;
475 }
476
477 if (cmd->flags & MMC_RSP_PRESENT) {
478 if (cmd->flags & MMC_RSP_136) {
479 for (i = 0; i < 4; i++) {
480 a = readw(host->base + MMC_REG_RES_FIFO);
481 b = readw(host->base + MMC_REG_RES_FIFO);
482 cmd->resp[i] = a << 16 | b;
483 }
484 } else {
485 a = readw(host->base + MMC_REG_RES_FIFO);
486 b = readw(host->base + MMC_REG_RES_FIFO);
487 c = readw(host->base + MMC_REG_RES_FIFO);
488 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
489 }
490 }
491}
492
493static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
494{
495 u32 stat;
496 unsigned long timeout = jiffies + HZ;
497
498 do {
499 stat = readl(host->base + MMC_REG_STATUS);
500 if (stat & STATUS_ERR_MASK)
501 return stat;
18489fa2
MF		 502 if (time_after(jiffies, timeout)) {
503 mxcmci_softreset(host);
504 mxcmci_set_clk_rate(host, host->clock);
d96be879 505 return STATUS_TIME_OUT_READ;
18489fa2 506 }
d96be879
SH		 507 if (stat & mask)
508 return 0;
509 cpu_relax();
510 } while (1);
511}
512
513static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
514{
515 unsigned int stat;
516 u32 *buf = _buf;
517
518 while (bytes > 3) {
519 stat = mxcmci_poll_status(host,
520 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
521 if (stat)
522 return stat;
523 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
524 bytes -= 4;
525 }
526
527 if (bytes) {
528 u8 *b = (u8 *)buf;
529 u32 tmp;
530
531 stat = mxcmci_poll_status(host,
532 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
533 if (stat)
534 return stat;
535 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
536 memcpy(b, &tmp, bytes);
537 }
538
539 return 0;
540}
541
542static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
543{
544 unsigned int stat;
545 u32 *buf = _buf;
546
547 while (bytes > 3) {
548 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
549 if (stat)
550 return stat;
551 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
552 bytes -= 4;
553 }
554
555 if (bytes) {
556 u8 *b = (u8 *)buf;
557 u32 tmp;
558
559 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
560 if (stat)
561 return stat;
562
563 memcpy(&tmp, b, bytes);
564 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
565 }
566
567 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
568 if (stat)
569 return stat;
570
571 return 0;
572}
573
574static int mxcmci_transfer_data(struct mxcmci_host *host)
575{
576 struct mmc_data *data = host->req->data;
577 struct scatterlist *sg;
578 int stat, i;
579
d96be879
SH		 580 host->data = data;
581 host->datasize = 0;
582
583 if (data->flags & MMC_DATA_READ) {
584 for_each_sg(data->sg, sg, data->sg_len, i) {
585 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
586 if (stat)
587 return stat;
588 host->datasize += sg->length;
589 }
590 } else {
591 for_each_sg(data->sg, sg, data->sg_len, i) {
592 stat = mxcmci_push(host, sg_virt(sg), sg->length);
593 if (stat)
594 return stat;
595 host->datasize += sg->length;
596 }
597 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
598 if (stat)
599 return stat;
600 }
601 return 0;
602}
603
604static void mxcmci_datawork(struct work_struct *work)
605{
606 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
607 datawork);
608 int datastat = mxcmci_transfer_data(host);
4a31f2ef
DM		 609
610 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
611 host->base + MMC_REG_STATUS);
d96be879
SH		 612 mxcmci_finish_data(host, datastat);
613
614 if (host->req->stop) {
615 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
616 mxcmci_finish_request(host, host->req);
617 return;
618 }
619 } else {
620 mxcmci_finish_request(host, host->req);
621 }
622}
623
d96be879
SH		 624static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
625{
626 struct mmc_data *data = host->data;
627 int data_error;
628
629 if (!data)
630 return;
631
632 data_error = mxcmci_finish_data(host, stat);
633
634 mxcmci_read_response(host, stat);
635 host->cmd = NULL;
636
637 if (host->req->stop) {
638 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
639 mxcmci_finish_request(host, host->req);
640 return;
641 }
642 } else {
643 mxcmci_finish_request(host, host->req);
644 }
645}
d96be879
SH		 646
647static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
648{
649 mxcmci_read_response(host, stat);
650 host->cmd = NULL;
651
652 if (!host->data && host->req) {
653 mxcmci_finish_request(host, host->req);
654 return;
655 }
656
657 /* For the DMA case the DMA engine handles the data transfer
fd589a8f 658 * automatically. For non DMA we have to do it ourselves.
d96be879
SH		 659 * Don't do it in interrupt context though.
660 */
661 if (!mxcmci_use_dma(host) && host->data)
662 schedule_work(&host->datawork);
663
664}
665
666static irqreturn_t mxcmci_irq(int irq, void *devid)
667{
668 struct mxcmci_host *host = devid;
f441b993
DM		 669 unsigned long flags;
670 bool sdio_irq;
d96be879
SH		 671 u32 stat;
672
673 stat = readl(host->base + MMC_REG_STATUS);
4a31f2ef
DM		 674 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
675 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
d96be879
SH		 676
677 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
678
f441b993
DM		 679 spin_lock_irqsave(&host->lock, flags);
680 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
681 spin_unlock_irqrestore(&host->lock, flags);
682
4a31f2ef
DM		 683 if (mxcmci_use_dma(host) &&
684 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
685 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
686 host->base + MMC_REG_STATUS);
4a31f2ef 687
f441b993
DM		 688 if (sdio_irq) {
689 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
690 mmc_signal_sdio_irq(host->mmc);
691 }
692
d96be879
SH		 693 if (stat & STATUS_END_CMD_RESP)
694 mxcmci_cmd_done(host, stat);
f441b993 695
d96be879 696 if (mxcmci_use_dma(host) &&
f6ad0a48
JM		 697 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) {
698 del_timer(&host->watchdog);
d96be879 699 mxcmci_data_done(host, stat);
f6ad0a48 700 }
f53fbde4 701
16b3bf8c
EB		 702 if (host->default_irq_mask &&
703 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
704 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
f53fbde4 705
d96be879
SH		 706 return IRQ_HANDLED;
707}
708
709static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
710{
711 struct mxcmci_host *host = mmc_priv(mmc);
712 unsigned int cmdat = host->cmdat;
656217d2 713 int error;
d96be879
SH		 714
715 WARN_ON(host->req != NULL);
716
717 host->req = req;
718 host->cmdat &= ~CMD_DAT_CONT_INIT;
f53fbde4
SH		 719
720 if (host->dma)
721 host->do_dma = 1;
722
d96be879 723 if (req->data) {
656217d2
MF		 724 error = mxcmci_setup_data(host, req->data);
725 if (error) {
726 req->cmd->error = error;
727 goto out;
728 }
729
d96be879
SH		 730
731 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
732
733 if (req->data->flags & MMC_DATA_WRITE)
734 cmdat |= CMD_DAT_CONT_WRITE;
735 }
736
656217d2 737 error = mxcmci_start_cmd(host, req->cmd, cmdat);
f53fbde4 738
656217d2
MF		 739out:
740 if (error)
d96be879
SH		 741 mxcmci_finish_request(host, req);
742}
743
744static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
745{
746 unsigned int divider;
747 int prescaler = 0;
529aa29e 748 unsigned int clk_in = clk_get_rate(host->clk_per);
d96be879
SH		 749
750 while (prescaler <= 0x800) {
751 for (divider = 1; divider <= 0xF; divider++) {
752 int x;
753
754 x = (clk_in / (divider + 1));
755
756 if (prescaler)
757 x /= (prescaler * 2);
758
759 if (x <= clk_ios)
760 break;
761 }
762 if (divider < 0x10)
763 break;
764
765 if (prescaler == 0)
766 prescaler = 1;
767 else
768 prescaler <<= 1;
769 }
770
771 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
772
773 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
774 prescaler, divider, clk_in, clk_ios);
775}
776
f53fbde4
SH		 777static int mxcmci_setup_dma(struct mmc_host *mmc)
778{
779 struct mxcmci_host *host = mmc_priv(mmc);
780 struct dma_slave_config *config = &host->dma_slave_config;
781
782 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
783 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
784 config->dst_addr_width = 4;
785 config->src_addr_width = 4;
786 config->dst_maxburst = host->burstlen;
787 config->src_maxburst = host->burstlen;
258aea76 788 config->device_fc = false;
f53fbde4
SH		 789
790 return dmaengine_slave_config(host->dma, config);
791}
792
d96be879
SH		 793static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
794{
795 struct mxcmci_host *host = mmc_priv(mmc);
f53fbde4
SH		 796 int burstlen, ret;
797
d96be879 798 /*
6584cb88
SH		 799 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
800 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
d96be879
SH		 801 */
802 if (ios->bus_width == MMC_BUS_WIDTH_4)
f53fbde4 803 burstlen = 16;
6584cb88
SH		 804 else
805 burstlen = 4;
f53fbde4
SH		 806
807 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
808 host->burstlen = burstlen;
809 ret = mxcmci_setup_dma(mmc);
810 if (ret) {
811 dev_err(mmc_dev(host->mmc),
812 "failed to config DMA channel. Falling back to PIO\n");
813 dma_release_channel(host->dma);
814 host->do_dma = 0;
e58f516f 815 host->dma = NULL;
f53fbde4
SH		 816 }
817 }
d96be879 818
d96be879
SH		 819 if (ios->bus_width == MMC_BUS_WIDTH_4)
820 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
821 else
822 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
823
824 if (host->power_mode != ios->power_mode) {
d078d242 825 mxcmci_set_power(host, ios->power_mode, ios->vdd);
d96be879 826 host->power_mode = ios->power_mode;
74b66954 827
d96be879
SH		 828 if (ios->power_mode == MMC_POWER_ON)
829 host->cmdat |= CMD_DAT_CONT_INIT;
830 }
831
832 if (ios->clock) {
833 mxcmci_set_clk_rate(host, ios->clock);
834 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
835 } else {
836 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
837 }
838
839 host->clock = ios->clock;
840}
841
842static irqreturn_t mxcmci_detect_irq(int irq, void *data)
843{
844 struct mmc_host *mmc = data;
845
846 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
847
848 mmc_detect_change(mmc, msecs_to_jiffies(250));
849 return IRQ_HANDLED;
850}
851
852static int mxcmci_get_ro(struct mmc_host *mmc)
853{
854 struct mxcmci_host *host = mmc_priv(mmc);
855
856 if (host->pdata && host->pdata->get_ro)
857 return !!host->pdata->get_ro(mmc_dev(mmc));
858 /*
859 * Board doesn't support read only detection; let the mmc core
860 * decide what to do.
861 */
862 return -ENOSYS;
863}
864
f441b993
DM		 865static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
866{
867 struct mxcmci_host *host = mmc_priv(mmc);
868 unsigned long flags;
869 u32 int_cntr;
870
871 spin_lock_irqsave(&host->lock, flags);
872 host->use_sdio = enable;
873 int_cntr = readl(host->base + MMC_REG_INT_CNTR);
874
875 if (enable)
876 int_cntr |= INT_SDIO_IRQ_EN;
877 else
878 int_cntr &= ~INT_SDIO_IRQ_EN;
879
880 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
881 spin_unlock_irqrestore(&host->lock, flags);
882}
d96be879 883
3fcb027d
DM		 884static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
885{
7f917a8d
SG		 886 struct mxcmci_host *mxcmci = mmc_priv(host);
887
3fcb027d
DM		 888 /*
889 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
890 * multi-block transfers when connected SDIO peripheral doesn't
891 * drive the BUSY line as required by the specs.
892 * One way to prevent this is to only allow 1-bit transfers.
893 */
894
7f917a8d 895 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
3fcb027d
DM		 896 host->caps &= ~MMC_CAP_4_BIT_DATA;
897 else
898 host->caps |= MMC_CAP_4_BIT_DATA;
899}
900
f53fbde4
SH		 901static bool filter(struct dma_chan *chan, void *param)
902{
903 struct mxcmci_host *host = param;
904
905 if (!imx_dma_is_general_purpose(chan))
906 return false;
907
908 chan->private = &host->dma_data;
909
910 return true;
911}
912
f6ad0a48
JM		 913static void mxcmci_watchdog(unsigned long data)
914{
915 struct mmc_host *mmc = (struct mmc_host *)data;
916 struct mxcmci_host *host = mmc_priv(mmc);
917 struct mmc_request *req = host->req;
918 unsigned int stat = readl(host->base + MMC_REG_STATUS);
919
920 if (host->dma_dir == DMA_FROM_DEVICE) {
921 dmaengine_terminate_all(host->dma);
922 dev_err(mmc_dev(host->mmc),
923 "%s: read time out (status = 0x%08x)\n",
924 __func__, stat);
925 } else {
926 dev_err(mmc_dev(host->mmc),
927 "%s: write time out (status = 0x%08x)\n",
928 __func__, stat);
929 mxcmci_softreset(host);
930 }
931
932 /* Mark transfer as erroneus and inform the upper layers */
933
934 host->data->error = -ETIMEDOUT;
935 host->req = NULL;
936 host->cmd = NULL;
937 host->data = NULL;
938 mmc_request_done(host->mmc, req);
939}
940
d96be879 941static const struct mmc_host_ops mxcmci_ops = {
f441b993
DM		 942 .request = mxcmci_request,
943 .set_ios = mxcmci_set_ios,
944 .get_ro = mxcmci_get_ro,
945 .enable_sdio_irq = mxcmci_enable_sdio_irq,
3fcb027d 946 .init_card = mxcmci_init_card,
d96be879
SH		 947};
948
949static int mxcmci_probe(struct platform_device *pdev)
950{
951 struct mmc_host *mmc;
952 struct mxcmci_host *host = NULL;
c0521baf 953 struct resource *iores, *r;
d96be879 954 int ret = 0, irq;
7ff747c4 955 bool dat3_card_detect = false;
f53fbde4 956 dma_cap_mask_t mask;
7ff747c4
MP		 957 const struct of_device_id *of_id;
958 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
d96be879 959
a3c76eb9 960 pr_info("i.MX SDHC driver\n");
d96be879 961
7ff747c4
MP		 962 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
963
c0521baf 964 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d96be879 965 irq = platform_get_irq(pdev, 0);
c0521baf 966 if (!iores || irq < 0)
d96be879
SH		 967 return -EINVAL;
968
c0521baf 969 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
d96be879
SH		 970 if (!r)
971 return -EBUSY;
972
973 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
974 if (!mmc) {
975 ret = -ENOMEM;
976 goto out_release_mem;
977 }
978
7ff747c4 979 mmc_of_parse(mmc);
d96be879 980 mmc->ops = &mxcmci_ops;
7ff747c4
MP		 981
982 /* For devicetree parsing, the bus width is read from devicetree */
983 if (pdata)
984 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
985 else
986 mmc->caps |= MMC_CAP_SDIO_IRQ;
d96be879
SH		 987
988 /* MMC core transfer sizes tunable parameters */
a36274e0 989 mmc->max_segs = 64;
d96be879
SH		 990 mmc->max_blk_size = 2048;
991 mmc->max_blk_count = 65535;
992 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
d759c374 993 mmc->max_seg_size = mmc->max_req_size;
d96be879
SH		 994
995 host = mmc_priv(mmc);
996 host->base = ioremap(r->start, resource_size(r));
997 if (!host->base) {
998 ret = -ENOMEM;
999 goto out_free;
1000 }
1001
7ff747c4
MP		 1002 if (of_id) {
1003 const struct platform_device_id *id_entry = of_id->data;
1004 host->devtype = id_entry->driver_data;
1005 } else {
1006 host->devtype = pdev->id_entry->driver_data;
1007 }
d96be879 1008 host->mmc = mmc;
7ff747c4 1009 host->pdata = pdata;
f441b993 1010 spin_lock_init(&host->lock);
d96be879 1011
7ff747c4
MP		 1012 if (pdata)
1013 dat3_card_detect = pdata->dat3_card_detect;
1014 else if (!(mmc->caps & MMC_CAP_NONREMOVABLE)
1015 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1016 dat3_card_detect = true;
1017
74b66954 1018 mxcmci_init_ocr(host);
d96be879 1019
7ff747c4 1020 if (dat3_card_detect)
16b3bf8c
EB		 1021 host->default_irq_mask =
1022 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1023 else
1024 host->default_irq_mask = 0;
1025
d96be879
SH		 1026 host->res = r;
1027 host->irq = irq;
1028
529aa29e
SH		 1029 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1030 if (IS_ERR(host->clk_ipg)) {
1031 ret = PTR_ERR(host->clk_ipg);
d96be879
SH		 1032 goto out_iounmap;
1033 }
529aa29e
SH		 1034
1035 host->clk_per = devm_clk_get(&pdev->dev, "per");
1036 if (IS_ERR(host->clk_per)) {
1037 ret = PTR_ERR(host->clk_per);
1038 goto out_iounmap;
1039 }
1040
1041 clk_prepare_enable(host->clk_per);
1042 clk_prepare_enable(host->clk_ipg);
d96be879
SH		 1043
1044 mxcmci_softreset(host);
1045
1046 host->rev_no = readw(host->base + MMC_REG_REV_NO);
1047 if (host->rev_no != 0x400) {
1048 ret = -ENODEV;
1049 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1050 host->rev_no);
1051 goto out_clk_put;
1052 }
1053
529aa29e
SH		 1054 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1055 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
d96be879
SH		 1056
1057 /* recommended in data sheet */
1058 writew(0x2db4, host->base + MMC_REG_READ_TO);
1059
16b3bf8c 1060 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
d96be879 1061
7ff747c4
MP		 1062 if (!host->pdata) {
1063 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx");
1064 } else {
1065 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1066 if (r) {
1067 host->dmareq = r->start;
1068 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1069 host->dma_data.priority = DMA_PRIO_LOW;
1070 host->dma_data.dma_request = host->dmareq;
1071 dma_cap_zero(mask);
1072 dma_cap_set(DMA_SLAVE, mask);
1073 host->dma = dma_request_channel(mask, filter, host);
1074 }
f53fbde4 1075 }
7ff747c4
MP		 1076 if (host->dma)
1077 mmc->max_seg_size = dma_get_max_seg_size(
1078 host->dma->device->dev);
1079 else
f53fbde4 1080 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
d96be879 1081
d96be879
SH		 1082 INIT_WORK(&host->datawork, mxcmci_datawork);
1083
1084 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
1085 if (ret)
1086 goto out_free_dma;
1087
1088 platform_set_drvdata(pdev, mmc);
1089
1090 if (host->pdata && host->pdata->init) {
1091 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1092 host->mmc);
1093 if (ret)
1094 goto out_free_irq;
1095 }
1096
f6ad0a48
JM		 1097 init_timer(&host->watchdog);
1098 host->watchdog.function = &mxcmci_watchdog;
1099 host->watchdog.data = (unsigned long)mmc;
1100
abd4190f
AS		 1101 mmc_add_host(mmc);
1102
d96be879
SH		 1103 return 0;
1104
1105out_free_irq:
1106 free_irq(host->irq, host);
1107out_free_dma:
f53fbde4
SH		 1108 if (host->dma)
1109 dma_release_channel(host->dma);
d96be879 1110out_clk_put:
529aa29e
SH		 1111 clk_disable_unprepare(host->clk_per);
1112 clk_disable_unprepare(host->clk_ipg);
d96be879
SH		 1113out_iounmap:
1114 iounmap(host->base);
1115out_free:
1116 mmc_free_host(mmc);
1117out_release_mem:
c0521baf 1118 release_mem_region(iores->start, resource_size(iores));
d96be879
SH		 1119 return ret;
1120}
1121
1122static int mxcmci_remove(struct platform_device *pdev)
1123{
1124 struct mmc_host *mmc = platform_get_drvdata(pdev);
1125 struct mxcmci_host *host = mmc_priv(mmc);
1126
1127 platform_set_drvdata(pdev, NULL);
1128
1129 mmc_remove_host(mmc);
1130
74b66954
AP		 1131 if (host->vcc)
1132 regulator_put(host->vcc);
1133
d96be879
SH		 1134 if (host->pdata && host->pdata->exit)
1135 host->pdata->exit(&pdev->dev, mmc);
1136
1137 free_irq(host->irq, host);
1138 iounmap(host->base);
f53fbde4
SH		 1139
1140 if (host->dma)
1141 dma_release_channel(host->dma);
1142
529aa29e
SH		 1143 clk_disable_unprepare(host->clk_per);
1144 clk_disable_unprepare(host->clk_ipg);
d96be879
SH		 1145
1146 release_mem_region(host->res->start, resource_size(host->res));
d96be879
SH		 1147
1148 mmc_free_host(mmc);
1149
1150 return 0;
1151}
1152
1153#ifdef CONFIG_PM
a7d403cf 1154static int mxcmci_suspend(struct device *dev)
d96be879 1155{
a7d403cf
EB		 1156 struct mmc_host *mmc = dev_get_drvdata(dev);
1157 struct mxcmci_host *host = mmc_priv(mmc);
d96be879
SH		 1158 int ret = 0;
1159
1160 if (mmc)
1a13f8fa 1161 ret = mmc_suspend_host(mmc);
529aa29e
SH		 1162 clk_disable_unprepare(host->clk_per);
1163 clk_disable_unprepare(host->clk_ipg);
d96be879
SH		 1164
1165 return ret;
1166}
1167
a7d403cf 1168static int mxcmci_resume(struct device *dev)
d96be879 1169{
a7d403cf
EB		 1170 struct mmc_host *mmc = dev_get_drvdata(dev);
1171 struct mxcmci_host *host = mmc_priv(mmc);
d96be879
SH		 1172 int ret = 0;
1173
529aa29e
SH		 1174 clk_prepare_enable(host->clk_per);
1175 clk_prepare_enable(host->clk_ipg);
a7d403cf 1176 if (mmc)
d96be879 1177 ret = mmc_resume_host(mmc);
d96be879
SH		 1178
1179 return ret;
1180}
a7d403cf
EB		 1181
1182static const struct dev_pm_ops mxcmci_pm_ops = {
1183 .suspend = mxcmci_suspend,
1184 .resume = mxcmci_resume,
1185};
1186#endif
d96be879
SH		 1187
1188static struct platform_driver mxcmci_driver = {
1189 .probe = mxcmci_probe,
1190 .remove = mxcmci_remove,
7f917a8d 1191 .id_table = mxcmci_devtype,
d96be879
SH		 1192 .driver = {
1193 .name = DRIVER_NAME,
1194 .owner = THIS_MODULE,
a7d403cf
EB		 1195#ifdef CONFIG_PM
1196 .pm = &mxcmci_pm_ops,
1197#endif
7ff747c4 1198 .of_match_table = mxcmci_of_match,
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SH		 1199 }
1200};
1201
d1f81a64 1202module_platform_driver(mxcmci_driver);
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SH		 1203
1204MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1205MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1206MODULE_LICENSE("GPL");
6eb30adf 1207MODULE_ALIAS("platform:mxc-mmc");
Linux 6.x block layer and io_uring tree(s)