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mxcmmc : Reset the SDHC hardware if software timeout occurs.
[linux-2.6-block.git] / drivers / mmc / host / mxcmmc.c
CommitLineData
d96be879
SH		 1/*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the seperate driver.
8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/blkdev.h>
27#include <linux/dma-mapping.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
34
35#include <asm/dma.h>
36#include <asm/irq.h>
37#include <asm/sizes.h>
38#include <mach/mmc.h>
39
40#ifdef CONFIG_ARCH_MX2
41#include <mach/dma-mx1-mx2.h>
42#define HAS_DMA
43#endif
44
9563b1db 45#define DRIVER_NAME "mxc-mmc"
d96be879
SH		 46
47#define MMC_REG_STR_STP_CLK 0x00
48#define MMC_REG_STATUS 0x04
49#define MMC_REG_CLK_RATE 0x08
50#define MMC_REG_CMD_DAT_CONT 0x0C
51#define MMC_REG_RES_TO 0x10
52#define MMC_REG_READ_TO 0x14
53#define MMC_REG_BLK_LEN 0x18
54#define MMC_REG_NOB 0x1C
55#define MMC_REG_REV_NO 0x20
56#define MMC_REG_INT_CNTR 0x24
57#define MMC_REG_CMD 0x28
58#define MMC_REG_ARG 0x2C
59#define MMC_REG_RES_FIFO 0x34
60#define MMC_REG_BUFFER_ACCESS 0x38
61
62#define STR_STP_CLK_RESET (1 << 3)
63#define STR_STP_CLK_START_CLK (1 << 1)
64#define STR_STP_CLK_STOP_CLK (1 << 0)
65
66#define STATUS_CARD_INSERTION (1 << 31)
67#define STATUS_CARD_REMOVAL (1 << 30)
68#define STATUS_YBUF_EMPTY (1 << 29)
69#define STATUS_XBUF_EMPTY (1 << 28)
70#define STATUS_YBUF_FULL (1 << 27)
71#define STATUS_XBUF_FULL (1 << 26)
72#define STATUS_BUF_UND_RUN (1 << 25)
73#define STATUS_BUF_OVFL (1 << 24)
74#define STATUS_SDIO_INT_ACTIVE (1 << 14)
75#define STATUS_END_CMD_RESP (1 << 13)
76#define STATUS_WRITE_OP_DONE (1 << 12)
77#define STATUS_DATA_TRANS_DONE (1 << 11)
78#define STATUS_READ_OP_DONE (1 << 11)
79#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81#define STATUS_BUF_READ_RDY (1 << 7)
82#define STATUS_BUF_WRITE_RDY (1 << 6)
83#define STATUS_RESP_CRC_ERR (1 << 5)
84#define STATUS_CRC_READ_ERR (1 << 3)
85#define STATUS_CRC_WRITE_ERR (1 << 2)
86#define STATUS_TIME_OUT_RESP (1 << 1)
87#define STATUS_TIME_OUT_READ (1 << 0)
88#define STATUS_ERR_MASK 0x2f
89
90#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92#define CMD_DAT_CONT_START_READWAIT (1 << 10)
93#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94#define CMD_DAT_CONT_INIT (1 << 7)
95#define CMD_DAT_CONT_WRITE (1 << 4)
96#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100
101#define INT_SDIO_INT_WKP_EN (1 << 18)
102#define INT_CARD_INSERTION_WKP_EN (1 << 17)
103#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104#define INT_CARD_INSERTION_EN (1 << 15)
105#define INT_CARD_REMOVAL_EN (1 << 14)
106#define INT_SDIO_IRQ_EN (1 << 13)
107#define INT_DAT0_EN (1 << 12)
108#define INT_BUF_READ_EN (1 << 4)
109#define INT_BUF_WRITE_EN (1 << 3)
110#define INT_END_CMD_RES_EN (1 << 2)
111#define INT_WRITE_OP_DONE_EN (1 << 1)
112#define INT_READ_OP_EN (1 << 0)
113
114struct mxcmci_host {
115 struct mmc_host *mmc;
116 struct resource *res;
117 void __iomem *base;
118 int irq;
119 int detect_irq;
120 int dma;
121 int do_dma;
122 unsigned int power_mode;
123 struct imxmmc_platform_data *pdata;
124
125 struct mmc_request *req;
126 struct mmc_command *cmd;
127 struct mmc_data *data;
128
129 unsigned int dma_nents;
130 unsigned int datasize;
131 unsigned int dma_dir;
132
133 u16 rev_no;
134 unsigned int cmdat;
135
136 struct clk *clk;
137
138 int clock;
139
140 struct work_struct datawork;
141};
142
18489fa2
MF		 143static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
144
d96be879
SH		 145static inline int mxcmci_use_dma(struct mxcmci_host *host)
146{
147 return host->do_dma;
148}
149
150static void mxcmci_softreset(struct mxcmci_host *host)
151{
152 int i;
153
154 /* reset sequence */
155 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
156 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
157 host->base + MMC_REG_STR_STP_CLK);
158
159 for (i = 0; i < 8; i++)
160 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
161
162 writew(0xff, host->base + MMC_REG_RES_TO);
163}
164
165static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
166{
167 unsigned int nob = data->blocks;
168 unsigned int blksz = data->blksz;
169 unsigned int datasize = nob * blksz;
170#ifdef HAS_DMA
171 struct scatterlist *sg;
172 int i;
173#endif
174 if (data->flags & MMC_DATA_STREAM)
175 nob = 0xffff;
176
177 host->data = data;
178 data->bytes_xfered = 0;
179
180 writew(nob, host->base + MMC_REG_NOB);
181 writew(blksz, host->base + MMC_REG_BLK_LEN);
182 host->datasize = datasize;
183
184#ifdef HAS_DMA
185 for_each_sg(data->sg, sg, data->sg_len, i) {
186 if (sg->offset & 3 || sg->length & 3) {
187 host->do_dma = 0;
188 return;
189 }
190 }
191
192 if (data->flags & MMC_DATA_READ) {
193 host->dma_dir = DMA_FROM_DEVICE;
194 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
195 data->sg_len, host->dma_dir);
196
197 imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, datasize,
198 host->res->start + MMC_REG_BUFFER_ACCESS,
199 DMA_MODE_READ);
200 } else {
201 host->dma_dir = DMA_TO_DEVICE;
202 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
203 data->sg_len, host->dma_dir);
204
205 imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, datasize,
206 host->res->start + MMC_REG_BUFFER_ACCESS,
207 DMA_MODE_WRITE);
208 }
209
210 wmb();
211
212 imx_dma_enable(host->dma);
213#endif /* HAS_DMA */
214}
215
216static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
217 unsigned int cmdat)
218{
219 WARN_ON(host->cmd != NULL);
220 host->cmd = cmd;
221
222 switch (mmc_resp_type(cmd)) {
223 case MMC_RSP_R1: /* short CRC, OPCODE */
224 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
225 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
226 break;
227 case MMC_RSP_R2: /* long 136 bit + CRC */
228 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
229 break;
230 case MMC_RSP_R3: /* short */
231 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
232 break;
233 case MMC_RSP_NONE:
234 break;
235 default:
236 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
237 mmc_resp_type(cmd));
238 cmd->error = -EINVAL;
239 return -EINVAL;
240 }
241
242 if (mxcmci_use_dma(host))
243 writel(INT_READ_OP_EN | INT_WRITE_OP_DONE_EN |
244 INT_END_CMD_RES_EN,
245 host->base + MMC_REG_INT_CNTR);
246 else
247 writel(INT_END_CMD_RES_EN, host->base + MMC_REG_INT_CNTR);
248
249 writew(cmd->opcode, host->base + MMC_REG_CMD);
250 writel(cmd->arg, host->base + MMC_REG_ARG);
251 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
252
253 return 0;
254}
255
256static void mxcmci_finish_request(struct mxcmci_host *host,
257 struct mmc_request *req)
258{
259 writel(0, host->base + MMC_REG_INT_CNTR);
260
261 host->req = NULL;
262 host->cmd = NULL;
263 host->data = NULL;
264
265 mmc_request_done(host->mmc, req);
266}
267
268static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
269{
270 struct mmc_data *data = host->data;
271 int data_error;
272
273#ifdef HAS_DMA
274 if (mxcmci_use_dma(host)) {
275 imx_dma_disable(host->dma);
276 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
277 host->dma_dir);
278 }
279#endif
280
281 if (stat & STATUS_ERR_MASK) {
282 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
283 stat);
284 if (stat & STATUS_CRC_READ_ERR) {
285 data->error = -EILSEQ;
286 } else if (stat & STATUS_CRC_WRITE_ERR) {
287 u32 err_code = (stat >> 9) & 0x3;
288 if (err_code == 2) /* No CRC response */
289 data->error = -ETIMEDOUT;
290 else
291 data->error = -EILSEQ;
292 } else if (stat & STATUS_TIME_OUT_READ) {
293 data->error = -ETIMEDOUT;
294 } else {
295 data->error = -EIO;
296 }
297 } else {
298 data->bytes_xfered = host->datasize;
299 }
300
301 data_error = data->error;
302
303 host->data = NULL;
304
305 return data_error;
306}
307
308static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
309{
310 struct mmc_command *cmd = host->cmd;
311 int i;
312 u32 a, b, c;
313
314 if (!cmd)
315 return;
316
317 if (stat & STATUS_TIME_OUT_RESP) {
318 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
319 cmd->error = -ETIMEDOUT;
320 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
321 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
322 cmd->error = -EILSEQ;
323 }
324
325 if (cmd->flags & MMC_RSP_PRESENT) {
326 if (cmd->flags & MMC_RSP_136) {
327 for (i = 0; i < 4; i++) {
328 a = readw(host->base + MMC_REG_RES_FIFO);
329 b = readw(host->base + MMC_REG_RES_FIFO);
330 cmd->resp[i] = a << 16 | b;
331 }
332 } else {
333 a = readw(host->base + MMC_REG_RES_FIFO);
334 b = readw(host->base + MMC_REG_RES_FIFO);
335 c = readw(host->base + MMC_REG_RES_FIFO);
336 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
337 }
338 }
339}
340
341static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
342{
343 u32 stat;
344 unsigned long timeout = jiffies + HZ;
345
346 do {
347 stat = readl(host->base + MMC_REG_STATUS);
348 if (stat & STATUS_ERR_MASK)
349 return stat;
18489fa2
MF		 350 if (time_after(jiffies, timeout)) {
351 mxcmci_softreset(host);
352 mxcmci_set_clk_rate(host, host->clock);
d96be879 353 return STATUS_TIME_OUT_READ;
18489fa2 354 }
d96be879
SH		 355 if (stat & mask)
356 return 0;
357 cpu_relax();
358 } while (1);
359}
360
361static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
362{
363 unsigned int stat;
364 u32 *buf = _buf;
365
366 while (bytes > 3) {
367 stat = mxcmci_poll_status(host,
368 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
369 if (stat)
370 return stat;
371 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
372 bytes -= 4;
373 }
374
375 if (bytes) {
376 u8 *b = (u8 *)buf;
377 u32 tmp;
378
379 stat = mxcmci_poll_status(host,
380 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
381 if (stat)
382 return stat;
383 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
384 memcpy(b, &tmp, bytes);
385 }
386
387 return 0;
388}
389
390static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
391{
392 unsigned int stat;
393 u32 *buf = _buf;
394
395 while (bytes > 3) {
396 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
397 if (stat)
398 return stat;
399 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
400 bytes -= 4;
401 }
402
403 if (bytes) {
404 u8 *b = (u8 *)buf;
405 u32 tmp;
406
407 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
408 if (stat)
409 return stat;
410
411 memcpy(&tmp, b, bytes);
412 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
413 }
414
415 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
416 if (stat)
417 return stat;
418
419 return 0;
420}
421
422static int mxcmci_transfer_data(struct mxcmci_host *host)
423{
424 struct mmc_data *data = host->req->data;
425 struct scatterlist *sg;
426 int stat, i;
427
428 host->datasize = 0;
429
430 host->data = data;
431 host->datasize = 0;
432
433 if (data->flags & MMC_DATA_READ) {
434 for_each_sg(data->sg, sg, data->sg_len, i) {
435 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
436 if (stat)
437 return stat;
438 host->datasize += sg->length;
439 }
440 } else {
441 for_each_sg(data->sg, sg, data->sg_len, i) {
442 stat = mxcmci_push(host, sg_virt(sg), sg->length);
443 if (stat)
444 return stat;
445 host->datasize += sg->length;
446 }
447 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
448 if (stat)
449 return stat;
450 }
451 return 0;
452}
453
454static void mxcmci_datawork(struct work_struct *work)
455{
456 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
457 datawork);
458 int datastat = mxcmci_transfer_data(host);
459 mxcmci_finish_data(host, datastat);
460
461 if (host->req->stop) {
462 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
463 mxcmci_finish_request(host, host->req);
464 return;
465 }
466 } else {
467 mxcmci_finish_request(host, host->req);
468 }
469}
470
471#ifdef HAS_DMA
472static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
473{
474 struct mmc_data *data = host->data;
475 int data_error;
476
477 if (!data)
478 return;
479
480 data_error = mxcmci_finish_data(host, stat);
481
482 mxcmci_read_response(host, stat);
483 host->cmd = NULL;
484
485 if (host->req->stop) {
486 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
487 mxcmci_finish_request(host, host->req);
488 return;
489 }
490 } else {
491 mxcmci_finish_request(host, host->req);
492 }
493}
494#endif /* HAS_DMA */
495
496static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
497{
498 mxcmci_read_response(host, stat);
499 host->cmd = NULL;
500
501 if (!host->data && host->req) {
502 mxcmci_finish_request(host, host->req);
503 return;
504 }
505
506 /* For the DMA case the DMA engine handles the data transfer
507 * automatically. For non DMA we have to to it ourselves.
508 * Don't do it in interrupt context though.
509 */
510 if (!mxcmci_use_dma(host) && host->data)
511 schedule_work(&host->datawork);
512
513}
514
515static irqreturn_t mxcmci_irq(int irq, void *devid)
516{
517 struct mxcmci_host *host = devid;
518 u32 stat;
519
520 stat = readl(host->base + MMC_REG_STATUS);
521 writel(stat, host->base + MMC_REG_STATUS);
522
523 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
524
525 if (stat & STATUS_END_CMD_RESP)
526 mxcmci_cmd_done(host, stat);
527#ifdef HAS_DMA
528 if (mxcmci_use_dma(host) &&
529 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
530 mxcmci_data_done(host, stat);
531#endif
532 return IRQ_HANDLED;
533}
534
535static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
536{
537 struct mxcmci_host *host = mmc_priv(mmc);
538 unsigned int cmdat = host->cmdat;
539
540 WARN_ON(host->req != NULL);
541
542 host->req = req;
543 host->cmdat &= ~CMD_DAT_CONT_INIT;
544#ifdef HAS_DMA
545 host->do_dma = 1;
546#endif
547 if (req->data) {
548 mxcmci_setup_data(host, req->data);
549
550 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
551
552 if (req->data->flags & MMC_DATA_WRITE)
553 cmdat |= CMD_DAT_CONT_WRITE;
554 }
555
556 if (mxcmci_start_cmd(host, req->cmd, cmdat))
557 mxcmci_finish_request(host, req);
558}
559
560static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
561{
562 unsigned int divider;
563 int prescaler = 0;
564 unsigned int clk_in = clk_get_rate(host->clk);
565
566 while (prescaler <= 0x800) {
567 for (divider = 1; divider <= 0xF; divider++) {
568 int x;
569
570 x = (clk_in / (divider + 1));
571
572 if (prescaler)
573 x /= (prescaler * 2);
574
575 if (x <= clk_ios)
576 break;
577 }
578 if (divider < 0x10)
579 break;
580
581 if (prescaler == 0)
582 prescaler = 1;
583 else
584 prescaler <<= 1;
585 }
586
587 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
588
589 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
590 prescaler, divider, clk_in, clk_ios);
591}
592
593static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
594{
595 struct mxcmci_host *host = mmc_priv(mmc);
596#ifdef HAS_DMA
597 unsigned int blen;
598 /*
599 * use burstlen of 64 in 4 bit mode (--> reg value 0)
600 * use burstlen of 16 in 1 bit mode (--> reg value 16)
601 */
602 if (ios->bus_width == MMC_BUS_WIDTH_4)
603 blen = 0;
604 else
605 blen = 16;
606
607 imx_dma_config_burstlen(host->dma, blen);
608#endif
609 if (ios->bus_width == MMC_BUS_WIDTH_4)
610 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
611 else
612 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
613
614 if (host->power_mode != ios->power_mode) {
615 if (host->pdata && host->pdata->setpower)
616 host->pdata->setpower(mmc_dev(mmc), ios->vdd);
617 host->power_mode = ios->power_mode;
618 if (ios->power_mode == MMC_POWER_ON)
619 host->cmdat |= CMD_DAT_CONT_INIT;
620 }
621
622 if (ios->clock) {
623 mxcmci_set_clk_rate(host, ios->clock);
624 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
625 } else {
626 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
627 }
628
629 host->clock = ios->clock;
630}
631
632static irqreturn_t mxcmci_detect_irq(int irq, void *data)
633{
634 struct mmc_host *mmc = data;
635
636 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
637
638 mmc_detect_change(mmc, msecs_to_jiffies(250));
639 return IRQ_HANDLED;
640}
641
642static int mxcmci_get_ro(struct mmc_host *mmc)
643{
644 struct mxcmci_host *host = mmc_priv(mmc);
645
646 if (host->pdata && host->pdata->get_ro)
647 return !!host->pdata->get_ro(mmc_dev(mmc));
648 /*
649 * Board doesn't support read only detection; let the mmc core
650 * decide what to do.
651 */
652 return -ENOSYS;
653}
654
655
656static const struct mmc_host_ops mxcmci_ops = {
657 .request = mxcmci_request,
658 .set_ios = mxcmci_set_ios,
659 .get_ro = mxcmci_get_ro,
660};
661
662static int mxcmci_probe(struct platform_device *pdev)
663{
664 struct mmc_host *mmc;
665 struct mxcmci_host *host = NULL;
666 struct resource *r;
667 int ret = 0, irq;
668
669 printk(KERN_INFO "i.MX SDHC driver\n");
670
671 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
672 irq = platform_get_irq(pdev, 0);
673 if (!r || irq < 0)
674 return -EINVAL;
675
676 r = request_mem_region(r->start, resource_size(r), pdev->name);
677 if (!r)
678 return -EBUSY;
679
680 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
681 if (!mmc) {
682 ret = -ENOMEM;
683 goto out_release_mem;
684 }
685
686 mmc->ops = &mxcmci_ops;
687 mmc->caps = MMC_CAP_4_BIT_DATA;
688
689 /* MMC core transfer sizes tunable parameters */
690 mmc->max_hw_segs = 64;
691 mmc->max_phys_segs = 64;
692 mmc->max_blk_size = 2048;
693 mmc->max_blk_count = 65535;
694 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
695 mmc->max_seg_size = mmc->max_seg_size;
696
697 host = mmc_priv(mmc);
698 host->base = ioremap(r->start, resource_size(r));
699 if (!host->base) {
700 ret = -ENOMEM;
701 goto out_free;
702 }
703
704 host->mmc = mmc;
705 host->pdata = pdev->dev.platform_data;
706
707 if (host->pdata && host->pdata->ocr_avail)
708 mmc->ocr_avail = host->pdata->ocr_avail;
709 else
710 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
711
712 host->res = r;
713 host->irq = irq;
714
06277b5c 715 host->clk = clk_get(&pdev->dev, NULL);
d96be879
SH		 716 if (IS_ERR(host->clk)) {
717 ret = PTR_ERR(host->clk);
718 goto out_iounmap;
719 }
720 clk_enable(host->clk);
721
722 mxcmci_softreset(host);
723
724 host->rev_no = readw(host->base + MMC_REG_REV_NO);
725 if (host->rev_no != 0x400) {
726 ret = -ENODEV;
727 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
728 host->rev_no);
729 goto out_clk_put;
730 }
731
c499b067
SH		 732 mmc->f_min = clk_get_rate(host->clk) >> 16;
733 if (mmc->f_min < 400000)
734 mmc->f_min = 400000;
d96be879
SH		 735 mmc->f_max = clk_get_rate(host->clk) >> 1;
736
737 /* recommended in data sheet */
738 writew(0x2db4, host->base + MMC_REG_READ_TO);
739
740 writel(0, host->base + MMC_REG_INT_CNTR);
741
742#ifdef HAS_DMA
743 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
744 if (host->dma < 0) {
745 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
746 ret = -EBUSY;
747 goto out_clk_put;
748 }
749
750 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
751 if (!r) {
752 ret = -EINVAL;
753 goto out_free_dma;
754 }
755
756 ret = imx_dma_config_channel(host->dma,
757 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
758 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
759 r->start, 0);
760 if (ret) {
761 dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n");
762 goto out_free_dma;
763 }
764#endif
765 INIT_WORK(&host->datawork, mxcmci_datawork);
766
767 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
768 if (ret)
769 goto out_free_dma;
770
771 platform_set_drvdata(pdev, mmc);
772
773 if (host->pdata && host->pdata->init) {
774 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
775 host->mmc);
776 if (ret)
777 goto out_free_irq;
778 }
779
780 mmc_add_host(mmc);
781
782 return 0;
783
784out_free_irq:
785 free_irq(host->irq, host);
786out_free_dma:
787#ifdef HAS_DMA
788 imx_dma_free(host->dma);
789#endif
790out_clk_put:
791 clk_disable(host->clk);
792 clk_put(host->clk);
793out_iounmap:
794 iounmap(host->base);
795out_free:
796 mmc_free_host(mmc);
797out_release_mem:
798 release_mem_region(host->res->start, resource_size(host->res));
799 return ret;
800}
801
802static int mxcmci_remove(struct platform_device *pdev)
803{
804 struct mmc_host *mmc = platform_get_drvdata(pdev);
805 struct mxcmci_host *host = mmc_priv(mmc);
806
807 platform_set_drvdata(pdev, NULL);
808
809 mmc_remove_host(mmc);
810
811 if (host->pdata && host->pdata->exit)
812 host->pdata->exit(&pdev->dev, mmc);
813
814 free_irq(host->irq, host);
815 iounmap(host->base);
816#ifdef HAS_DMA
817 imx_dma_free(host->dma);
818#endif
819 clk_disable(host->clk);
820 clk_put(host->clk);
821
822 release_mem_region(host->res->start, resource_size(host->res));
823 release_resource(host->res);
824
825 mmc_free_host(mmc);
826
827 return 0;
828}
829
830#ifdef CONFIG_PM
831static int mxcmci_suspend(struct platform_device *dev, pm_message_t state)
832{
833 struct mmc_host *mmc = platform_get_drvdata(dev);
834 int ret = 0;
835
836 if (mmc)
837 ret = mmc_suspend_host(mmc, state);
838
839 return ret;
840}
841
842static int mxcmci_resume(struct platform_device *dev)
843{
844 struct mmc_host *mmc = platform_get_drvdata(dev);
845 struct mxcmci_host *host;
846 int ret = 0;
847
848 if (mmc) {
849 host = mmc_priv(mmc);
850 ret = mmc_resume_host(mmc);
851 }
852
853 return ret;
854}
855#else
856#define mxcmci_suspend NULL
857#define mxcmci_resume NULL
858#endif /* CONFIG_PM */
859
860static struct platform_driver mxcmci_driver = {
861 .probe = mxcmci_probe,
862 .remove = mxcmci_remove,
863 .suspend = mxcmci_suspend,
864 .resume = mxcmci_resume,
865 .driver = {
866 .name = DRIVER_NAME,
867 .owner = THIS_MODULE,
868 }
869};
870
871static int __init mxcmci_init(void)
872{
873 return platform_driver_register(&mxcmci_driver);
874}
875
876static void __exit mxcmci_exit(void)
877{
878 platform_driver_unregister(&mxcmci_driver);
879}
880
881module_init(mxcmci_init);
882module_exit(mxcmci_exit);
883
884MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
885MODULE_AUTHOR("Sascha Hauer, Pengutronix");
886MODULE_LICENSE("GPL");
887MODULE_ALIAS("platform:imx-mmc");
Linux 6.x block layer and io_uring tree(s)