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Merge tag 'hwlock-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc...
[linux-2.6-block.git] / drivers / mmc / host / mxcmmc.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
d96be879
SH		 2/*
3 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 *
5 * This is a driver for the SDHC controller found in Freescale MX2/MX3
6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
7 * Unlike the hardware found on MX1, this hardware just works and does
3ad2f3fb 8 * not need all the quirks found in imxmmc.c, hence the separate driver.
d96be879
SH		 9 *
10 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
11 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 *
13 * derived from pxamci.c by Russell King
d96be879
SH		 14 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/ioport.h>
19#include <linux/platform_device.h>
a639bb72 20#include <linux/highmem.h>
d96be879
SH		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/blkdev.h>
24#include <linux/dma-mapping.h>
25#include <linux/mmc/host.h>
26#include <linux/mmc/card.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
29#include <linux/io.h>
74b66954 30#include <linux/regulator/consumer.h>
f53fbde4 31#include <linux/dmaengine.h>
258aea76 32#include <linux/types.h>
7ff747c4
MP		 33#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/of_dma.h>
bcf53524 36#include <linux/mmc/slot-gpio.h>
d96be879
SH		 37
38#include <asm/dma.h>
39#include <asm/irq.h>
82906b13 40#include <linux/platform_data/mmc-mxcmmc.h>
d96be879 41
c6547c2e 42#include <linux/dma/imx-dma.h>
d96be879 43
9563b1db 44#define DRIVER_NAME "mxc-mmc"
f6ad0a48 45#define MXCMCI_TIMEOUT_MS 10000
d96be879
SH		 46
47#define MMC_REG_STR_STP_CLK 0x00
48#define MMC_REG_STATUS 0x04
49#define MMC_REG_CLK_RATE 0x08
50#define MMC_REG_CMD_DAT_CONT 0x0C
51#define MMC_REG_RES_TO 0x10
52#define MMC_REG_READ_TO 0x14
53#define MMC_REG_BLK_LEN 0x18
54#define MMC_REG_NOB 0x1C
55#define MMC_REG_REV_NO 0x20
56#define MMC_REG_INT_CNTR 0x24
57#define MMC_REG_CMD 0x28
58#define MMC_REG_ARG 0x2C
59#define MMC_REG_RES_FIFO 0x34
60#define MMC_REG_BUFFER_ACCESS 0x38
61
62#define STR_STP_CLK_RESET (1 << 3)
63#define STR_STP_CLK_START_CLK (1 << 1)
64#define STR_STP_CLK_STOP_CLK (1 << 0)
65
66#define STATUS_CARD_INSERTION (1 << 31)
67#define STATUS_CARD_REMOVAL (1 << 30)
68#define STATUS_YBUF_EMPTY (1 << 29)
69#define STATUS_XBUF_EMPTY (1 << 28)
70#define STATUS_YBUF_FULL (1 << 27)
71#define STATUS_XBUF_FULL (1 << 26)
72#define STATUS_BUF_UND_RUN (1 << 25)
73#define STATUS_BUF_OVFL (1 << 24)
74#define STATUS_SDIO_INT_ACTIVE (1 << 14)
75#define STATUS_END_CMD_RESP (1 << 13)
76#define STATUS_WRITE_OP_DONE (1 << 12)
77#define STATUS_DATA_TRANS_DONE (1 << 11)
78#define STATUS_READ_OP_DONE (1 << 11)
79#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81#define STATUS_BUF_READ_RDY (1 << 7)
82#define STATUS_BUF_WRITE_RDY (1 << 6)
83#define STATUS_RESP_CRC_ERR (1 << 5)
84#define STATUS_CRC_READ_ERR (1 << 3)
85#define STATUS_CRC_WRITE_ERR (1 << 2)
86#define STATUS_TIME_OUT_RESP (1 << 1)
87#define STATUS_TIME_OUT_READ (1 << 0)
88#define STATUS_ERR_MASK 0x2f
89
90#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92#define CMD_DAT_CONT_START_READWAIT (1 << 10)
93#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94#define CMD_DAT_CONT_INIT (1 << 7)
95#define CMD_DAT_CONT_WRITE (1 << 4)
96#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100
101#define INT_SDIO_INT_WKP_EN (1 << 18)
102#define INT_CARD_INSERTION_WKP_EN (1 << 17)
103#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104#define INT_CARD_INSERTION_EN (1 << 15)
105#define INT_CARD_REMOVAL_EN (1 << 14)
106#define INT_SDIO_IRQ_EN (1 << 13)
107#define INT_DAT0_EN (1 << 12)
108#define INT_BUF_READ_EN (1 << 4)
109#define INT_BUF_WRITE_EN (1 << 3)
110#define INT_END_CMD_RES_EN (1 << 2)
111#define INT_WRITE_OP_DONE_EN (1 << 1)
112#define INT_READ_OP_EN (1 << 0)
113
7f917a8d
SG		 114enum mxcmci_type {
115 IMX21_MMC,
116 IMX31_MMC,
c7ceab02 117 MPC512X_MMC,
7f917a8d
SG		 118};
119
d96be879
SH		 120struct mxcmci_host {
121 struct mmc_host *mmc;
d96be879 122 void __iomem *base;
01e4f958 123 dma_addr_t phys_base;
d96be879 124 int detect_irq;
f53fbde4
SH		 125 struct dma_chan *dma;
126 struct dma_async_tx_descriptor *desc;
d96be879 127 int do_dma;
16b3bf8c 128 int default_irq_mask;
f441b993 129 int use_sdio;
d96be879
SH		 130 unsigned int power_mode;
131 struct imxmmc_platform_data *pdata;
132
133 struct mmc_request *req;
134 struct mmc_command *cmd;
135 struct mmc_data *data;
136
d96be879
SH		 137 unsigned int datasize;
138 unsigned int dma_dir;
139
140 u16 rev_no;
141 unsigned int cmdat;
142
529aa29e
SH		 143 struct clk *clk_ipg;
144 struct clk *clk_per;
d96be879
SH		 145
146 int clock;
147
148 struct work_struct datawork;
f441b993 149 spinlock_t lock;
74b66954 150
f53fbde4
SH		 151 int burstlen;
152 int dmareq;
153 struct dma_slave_config dma_slave_config;
154 struct imx_dma_data dma_data;
f6ad0a48
JM		 155
156 struct timer_list watchdog;
7f917a8d
SG		 157 enum mxcmci_type devtype;
158};
159
7ff747c4
MP		 160static const struct of_device_id mxcmci_of_match[] = {
161 {
162 .compatible = "fsl,imx21-mmc",
8223e885 163 .data = (void *) IMX21_MMC,
7ff747c4
MP		 164 }, {
165 .compatible = "fsl,imx31-mmc",
8223e885 166 .data = (void *) IMX31_MMC,
c7ceab02
AG		 167 }, {
168 .compatible = "fsl,mpc5121-sdhc",
8223e885 169 .data = (void *) MPC512X_MMC,
7ff747c4
MP		 170 }, {
171 /* sentinel */
172 }
173};
174MODULE_DEVICE_TABLE(of, mxcmci_of_match);
175
7f917a8d
SG		 176static inline int is_imx31_mmc(struct mxcmci_host *host)
177{
178 return host->devtype == IMX31_MMC;
179}
d96be879 180
c7ceab02
AG		 181static inline int is_mpc512x_mmc(struct mxcmci_host *host)
182{
183 return host->devtype == MPC512X_MMC;
184}
185
186static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
187{
188 if (IS_ENABLED(CONFIG_PPC_MPC512x))
189 return ioread32be(host->base + reg);
190 else
191 return readl(host->base + reg);
192}
193
194static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
195{
196 if (IS_ENABLED(CONFIG_PPC_MPC512x))
197 iowrite32be(val, host->base + reg);
198 else
199 writel(val, host->base + reg);
200}
201
202static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
203{
204 if (IS_ENABLED(CONFIG_PPC_MPC512x))
205 return ioread32be(host->base + reg);
206 else
207 return readw(host->base + reg);
208}
209
210static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
211{
212 if (IS_ENABLED(CONFIG_PPC_MPC512x))
213 iowrite32be(val, host->base + reg);
214 else
215 writew(val, host->base + reg);
216}
217
18489fa2
MF		 218static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
219
bc3c1771 220static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
74b66954 221{
bc3c1771
AS		 222 if (!IS_ERR(host->mmc->supply.vmmc)) {
223 if (host->power_mode == MMC_POWER_UP)
224 mmc_regulator_set_ocr(host->mmc,
225 host->mmc->supply.vmmc, vdd);
226 else if (host->power_mode == MMC_POWER_OFF)
227 mmc_regulator_set_ocr(host->mmc,
228 host->mmc->supply.vmmc, 0);
d078d242
AP		 229 }
230
74b66954
AP		 231 if (host->pdata && host->pdata->setpower)
232 host->pdata->setpower(mmc_dev(host->mmc), vdd);
233}
234
d96be879
SH		 235static inline int mxcmci_use_dma(struct mxcmci_host *host)
236{
237 return host->do_dma;
238}
239
240static void mxcmci_softreset(struct mxcmci_host *host)
241{
242 int i;
243
4725f6f1
DM		 244 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
245
d96be879 246 /* reset sequence */
c7ceab02
AG		 247 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
248 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
249 MMC_REG_STR_STP_CLK);
d96be879
SH		 250
251 for (i = 0; i < 8; i++)
c7ceab02 252 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
d96be879 253
c7ceab02 254 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
d96be879
SH		 255}
256
e48fc15a
AG		 257#if IS_ENABLED(CONFIG_PPC_MPC512x)
258static inline void buffer_swap32(u32 *buf, int len)
259{
260 int i;
261
262 for (i = 0; i < ((len + 3) / 4); i++) {
7a8bf874 263 *buf = swab32(*buf);
e48fc15a
AG		 264 buf++;
265 }
266}
267
268static void mxcmci_swap_buffers(struct mmc_data *data)
269{
270 struct scatterlist *sg;
271 int i;
272
2b77158f
AS		 273 for_each_sg(data->sg, sg, data->sg_len, i)
274 buffer_swap32(sg_virt(sg), sg->length);
e48fc15a
AG		 275}
276#else
277static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
278#endif
279
656217d2 280static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
d96be879
SH		 281{
282 unsigned int nob = data->blocks;
283 unsigned int blksz = data->blksz;
284 unsigned int datasize = nob * blksz;
d96be879 285 struct scatterlist *sg;
05f5799c 286 enum dma_transfer_direction slave_dirn;
f53fbde4
SH		 287 int i, nents;
288
d96be879
SH		 289 host->data = data;
290 data->bytes_xfered = 0;
291
c7ceab02
AG		 292 mxcmci_writew(host, nob, MMC_REG_NOB);
293 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
d96be879
SH		 294 host->datasize = datasize;
295
f53fbde4
SH		 296 if (!mxcmci_use_dma(host))
297 return 0;
298
d96be879 299 for_each_sg(data->sg, sg, data->sg_len, i) {
2cb53552 300 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
d96be879 301 host->do_dma = 0;
656217d2 302 return 0;
d96be879
SH		 303 }
304 }
305
05f5799c 306 if (data->flags & MMC_DATA_READ) {
d96be879 307 host->dma_dir = DMA_FROM_DEVICE;
05f5799c
VK		 308 slave_dirn = DMA_DEV_TO_MEM;
309 } else {
d96be879 310 host->dma_dir = DMA_TO_DEVICE;
05f5799c 311 slave_dirn = DMA_MEM_TO_DEV;
e48fc15a
AG		 312
313 mxcmci_swap_buffers(data);
05f5799c 314 }
d96be879 315
f53fbde4
SH		 316 nents = dma_map_sg(host->dma->device->dev, data->sg,
317 data->sg_len, host->dma_dir);
318 if (nents != data->sg_len)
319 return -EINVAL;
320
16052827 321 host->desc = dmaengine_prep_slave_sg(host->dma,
05f5799c 322 data->sg, data->sg_len, slave_dirn,
f53fbde4 323 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
d96be879 324
f53fbde4
SH		 325 if (!host->desc) {
326 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
327 host->dma_dir);
328 host->do_dma = 0;
329 return 0; /* Fall back to PIO */
656217d2 330 }
d96be879
SH		 331 wmb();
332
f53fbde4 333 dmaengine_submit(host->desc);
439aa0ef 334 dma_async_issue_pending(host->dma);
f53fbde4 335
f6ad0a48
JM		 336 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
337
656217d2 338 return 0;
d96be879
SH		 339}
340
f6ad0a48
JM		 341static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
342static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
343
344static void mxcmci_dma_callback(void *data)
345{
346 struct mxcmci_host *host = data;
347 u32 stat;
348
349 del_timer(&host->watchdog);
350
c7ceab02 351 stat = mxcmci_readl(host, MMC_REG_STATUS);
f6ad0a48
JM		 352
353 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
354
f6ad0a48
JM		 355 mxcmci_data_done(host, stat);
356}
357
d96be879
SH		 358static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
359 unsigned int cmdat)
360{
16b3bf8c 361 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 362 unsigned long flags;
363
d96be879
SH		 364 WARN_ON(host->cmd != NULL);
365 host->cmd = cmd;
366
367 switch (mmc_resp_type(cmd)) {
368 case MMC_RSP_R1: /* short CRC, OPCODE */
369 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
370 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
371 break;
372 case MMC_RSP_R2: /* long 136 bit + CRC */
373 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
374 break;
375 case MMC_RSP_R3: /* short */
376 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
377 break;
378 case MMC_RSP_NONE:
379 break;
380 default:
381 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
382 mmc_resp_type(cmd));
383 cmd->error = -EINVAL;
384 return -EINVAL;
385 }
386
f441b993
DM		 387 int_cntr = INT_END_CMD_RES_EN;
388
f6ad0a48
JM		 389 if (mxcmci_use_dma(host)) {
390 if (host->dma_dir == DMA_FROM_DEVICE) {
391 host->desc->callback = mxcmci_dma_callback;
392 host->desc->callback_param = host;
393 } else {
394 int_cntr |= INT_WRITE_OP_DONE_EN;
395 }
396 }
f441b993
DM		 397
398 spin_lock_irqsave(&host->lock, flags);
399 if (host->use_sdio)
400 int_cntr |= INT_SDIO_IRQ_EN;
c7ceab02 401 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993 402 spin_unlock_irqrestore(&host->lock, flags);
d96be879 403
c7ceab02
AG		 404 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
405 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
406 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
d96be879
SH		 407
408 return 0;
409}
410
411static void mxcmci_finish_request(struct mxcmci_host *host,
412 struct mmc_request *req)
413{
16b3bf8c 414 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 415 unsigned long flags;
416
417 spin_lock_irqsave(&host->lock, flags);
418 if (host->use_sdio)
419 int_cntr |= INT_SDIO_IRQ_EN;
c7ceab02 420 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993 421 spin_unlock_irqrestore(&host->lock, flags);
d96be879
SH		 422
423 host->req = NULL;
424 host->cmd = NULL;
425 host->data = NULL;
426
427 mmc_request_done(host->mmc, req);
428}
429
430static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
431{
432 struct mmc_data *data = host->data;
433 int data_error;
434
e48fc15a 435 if (mxcmci_use_dma(host)) {
f53fbde4 436 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
d96be879 437 host->dma_dir);
e48fc15a
AG		 438 mxcmci_swap_buffers(data);
439 }
d96be879
SH		 440
441 if (stat & STATUS_ERR_MASK) {
442 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
443 stat);
444 if (stat & STATUS_CRC_READ_ERR) {
4725f6f1 445 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
d96be879
SH		 446 data->error = -EILSEQ;
447 } else if (stat & STATUS_CRC_WRITE_ERR) {
448 u32 err_code = (stat >> 9) & 0x3;
4725f6f1
DM		 449 if (err_code == 2) { /* No CRC response */
450 dev_err(mmc_dev(host->mmc),
451 "%s: No CRC -ETIMEDOUT\n", __func__);
d96be879 452 data->error = -ETIMEDOUT;
4725f6f1
DM		 453 } else {
454 dev_err(mmc_dev(host->mmc),
455 "%s: -EILSEQ\n", __func__);
d96be879 456 data->error = -EILSEQ;
4725f6f1 457 }
d96be879 458 } else if (stat & STATUS_TIME_OUT_READ) {
4725f6f1
DM		 459 dev_err(mmc_dev(host->mmc),
460 "%s: read -ETIMEDOUT\n", __func__);
d96be879
SH		 461 data->error = -ETIMEDOUT;
462 } else {
4725f6f1 463 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
d96be879
SH		 464 data->error = -EIO;
465 }
466 } else {
467 data->bytes_xfered = host->datasize;
468 }
469
470 data_error = data->error;
471
472 host->data = NULL;
473
474 return data_error;
475}
476
477static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
478{
479 struct mmc_command *cmd = host->cmd;
480 int i;
481 u32 a, b, c;
482
483 if (!cmd)
484 return;
485
486 if (stat & STATUS_TIME_OUT_RESP) {
487 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
488 cmd->error = -ETIMEDOUT;
489 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
490 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
491 cmd->error = -EILSEQ;
492 }
493
494 if (cmd->flags & MMC_RSP_PRESENT) {
495 if (cmd->flags & MMC_RSP_136) {
496 for (i = 0; i < 4; i++) {
c7ceab02
AG		 497 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
498 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
d96be879
SH		 499 cmd->resp[i] = a << 16 | b;
500 }
501 } else {
c7ceab02
AG		 502 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
503 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
504 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
d96be879
SH		 505 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
506 }
507 }
508}
509
510static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
511{
512 u32 stat;
513 unsigned long timeout = jiffies + HZ;
514
515 do {
c7ceab02 516 stat = mxcmci_readl(host, MMC_REG_STATUS);
d96be879
SH		 517 if (stat & STATUS_ERR_MASK)
518 return stat;
18489fa2
MF		 519 if (time_after(jiffies, timeout)) {
520 mxcmci_softreset(host);
521 mxcmci_set_clk_rate(host, host->clock);
d96be879 522 return STATUS_TIME_OUT_READ;
18489fa2 523 }
d96be879
SH		 524 if (stat & mask)
525 return 0;
526 cpu_relax();
527 } while (1);
528}
529
530static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
531{
532 unsigned int stat;
533 u32 *buf = _buf;
534
535 while (bytes > 3) {
536 stat = mxcmci_poll_status(host,
537 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
538 if (stat)
539 return stat;
c7ceab02 540 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
d96be879
SH		 541 bytes -= 4;
542 }
543
544 if (bytes) {
545 u8 *b = (u8 *)buf;
546 u32 tmp;
547
548 stat = mxcmci_poll_status(host,
549 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
550 if (stat)
551 return stat;
c7ceab02 552 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
d96be879
SH		 553 memcpy(b, &tmp, bytes);
554 }
555
556 return 0;
557}
558
559static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
560{
561 unsigned int stat;
562 u32 *buf = _buf;
563
564 while (bytes > 3) {
565 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
566 if (stat)
567 return stat;
c7ceab02 568 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
d96be879
SH		 569 bytes -= 4;
570 }
571
572 if (bytes) {
573 u8 *b = (u8 *)buf;
574 u32 tmp;
575
576 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
577 if (stat)
578 return stat;
579
580 memcpy(&tmp, b, bytes);
c7ceab02 581 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
d96be879
SH		 582 }
583
6d916416 584 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
d96be879
SH		 585}
586
587static int mxcmci_transfer_data(struct mxcmci_host *host)
588{
589 struct mmc_data *data = host->req->data;
590 struct scatterlist *sg;
591 int stat, i;
592
d96be879
SH		 593 host->data = data;
594 host->datasize = 0;
595
596 if (data->flags & MMC_DATA_READ) {
597 for_each_sg(data->sg, sg, data->sg_len, i) {
2b77158f 598 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
d96be879
SH		 599 if (stat)
600 return stat;
601 host->datasize += sg->length;
602 }
603 } else {
604 for_each_sg(data->sg, sg, data->sg_len, i) {
2b77158f 605 stat = mxcmci_push(host, sg_virt(sg), sg->length);
d96be879
SH		 606 if (stat)
607 return stat;
608 host->datasize += sg->length;
609 }
610 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
611 if (stat)
612 return stat;
613 }
614 return 0;
615}
616
617static void mxcmci_datawork(struct work_struct *work)
618{
619 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
620 datawork);
621 int datastat = mxcmci_transfer_data(host);
4a31f2ef 622
c7ceab02
AG		 623 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
624 MMC_REG_STATUS);
d96be879
SH		 625 mxcmci_finish_data(host, datastat);
626
627 if (host->req->stop) {
628 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
629 mxcmci_finish_request(host, host->req);
630 return;
631 }
632 } else {
633 mxcmci_finish_request(host, host->req);
634 }
635}
636
d96be879
SH		 637static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
638{
70aa6109 639 struct mmc_request *req;
d96be879 640 int data_error;
70aa6109
AG		 641 unsigned long flags;
642
643 spin_lock_irqsave(&host->lock, flags);
d96be879 644
70aa6109
AG		 645 if (!host->data) {
646 spin_unlock_irqrestore(&host->lock, flags);
d96be879 647 return;
70aa6109
AG		 648 }
649
650 if (!host->req) {
651 spin_unlock_irqrestore(&host->lock, flags);
652 return;
653 }
654
655 req = host->req;
656 if (!req->stop)
657 host->req = NULL; /* we will handle finish req below */
d96be879
SH		 658
659 data_error = mxcmci_finish_data(host, stat);
660
70aa6109
AG		 661 spin_unlock_irqrestore(&host->lock, flags);
662
09954ea9
SL		 663 if (data_error)
664 return;
665
d96be879
SH		 666 mxcmci_read_response(host, stat);
667 host->cmd = NULL;
668
70aa6109
AG		 669 if (req->stop) {
670 if (mxcmci_start_cmd(host, req->stop, 0)) {
671 mxcmci_finish_request(host, req);
d96be879
SH		 672 return;
673 }
674 } else {
70aa6109 675 mxcmci_finish_request(host, req);
d96be879
SH		 676 }
677}
d96be879
SH		 678
679static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
680{
681 mxcmci_read_response(host, stat);
682 host->cmd = NULL;
683
684 if (!host->data && host->req) {
685 mxcmci_finish_request(host, host->req);
686 return;
687 }
688
689 /* For the DMA case the DMA engine handles the data transfer
fd589a8f 690 * automatically. For non DMA we have to do it ourselves.
d96be879
SH		 691 * Don't do it in interrupt context though.
692 */
693 if (!mxcmci_use_dma(host) && host->data)
694 schedule_work(&host->datawork);
695
696}
697
698static irqreturn_t mxcmci_irq(int irq, void *devid)
699{
700 struct mxcmci_host *host = devid;
f441b993 701 bool sdio_irq;
d96be879
SH		 702 u32 stat;
703
c7ceab02
AG		 704 stat = mxcmci_readl(host, MMC_REG_STATUS);
705 mxcmci_writel(host,
706 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
707 STATUS_WRITE_OP_DONE),
708 MMC_REG_STATUS);
d96be879
SH		 709
710 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
711
5a941898 712 spin_lock(&host->lock);
f441b993 713 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
5a941898 714 spin_unlock(&host->lock);
f441b993 715
adfa5703
MF		 716 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
717 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
4a31f2ef 718
f441b993 719 if (sdio_irq) {
c7ceab02 720 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
f441b993
DM		 721 mmc_signal_sdio_irq(host->mmc);
722 }
723
d96be879
SH		 724 if (stat & STATUS_END_CMD_RESP)
725 mxcmci_cmd_done(host, stat);
f441b993 726
adfa5703 727 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
f6ad0a48 728 del_timer(&host->watchdog);
d96be879 729 mxcmci_data_done(host, stat);
f6ad0a48 730 }
f53fbde4 731
16b3bf8c
EB		 732 if (host->default_irq_mask &&
733 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
734 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
f53fbde4 735
d96be879
SH		 736 return IRQ_HANDLED;
737}
738
739static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
740{
741 struct mxcmci_host *host = mmc_priv(mmc);
742 unsigned int cmdat = host->cmdat;
656217d2 743 int error;
d96be879
SH		 744
745 WARN_ON(host->req != NULL);
746
747 host->req = req;
748 host->cmdat &= ~CMD_DAT_CONT_INIT;
f53fbde4
SH		 749
750 if (host->dma)
751 host->do_dma = 1;
752
d96be879 753 if (req->data) {
656217d2
MF		 754 error = mxcmci_setup_data(host, req->data);
755 if (error) {
756 req->cmd->error = error;
757 goto out;
758 }
759
d96be879
SH		 760
761 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
762
763 if (req->data->flags & MMC_DATA_WRITE)
764 cmdat |= CMD_DAT_CONT_WRITE;
765 }
766
656217d2 767 error = mxcmci_start_cmd(host, req->cmd, cmdat);
f53fbde4 768
656217d2
MF		 769out:
770 if (error)
d96be879
SH		 771 mxcmci_finish_request(host, req);
772}
773
774static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
775{
776 unsigned int divider;
777 int prescaler = 0;
529aa29e 778 unsigned int clk_in = clk_get_rate(host->clk_per);
d96be879
SH		 779
780 while (prescaler <= 0x800) {
781 for (divider = 1; divider <= 0xF; divider++) {
782 int x;
783
784 x = (clk_in / (divider + 1));
785
786 if (prescaler)
787 x /= (prescaler * 2);
788
789 if (x <= clk_ios)
790 break;
791 }
792 if (divider < 0x10)
793 break;
794
795 if (prescaler == 0)
796 prescaler = 1;
797 else
798 prescaler <<= 1;
799 }
800
c7ceab02 801 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
d96be879
SH		 802
803 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
804 prescaler, divider, clk_in, clk_ios);
805}
806
f53fbde4
SH		 807static int mxcmci_setup_dma(struct mmc_host *mmc)
808{
809 struct mxcmci_host *host = mmc_priv(mmc);
810 struct dma_slave_config *config = &host->dma_slave_config;
811
01e4f958
AS		 812 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
813 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
f53fbde4
SH		 814 config->dst_addr_width = 4;
815 config->src_addr_width = 4;
816 config->dst_maxburst = host->burstlen;
817 config->src_maxburst = host->burstlen;
258aea76 818 config->device_fc = false;
f53fbde4
SH		 819
820 return dmaengine_slave_config(host->dma, config);
821}
822
d96be879
SH		 823static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
824{
825 struct mxcmci_host *host = mmc_priv(mmc);
f53fbde4
SH		 826 int burstlen, ret;
827
d96be879 828 /*
6584cb88
SH		 829 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
830 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
d96be879
SH		 831 */
832 if (ios->bus_width == MMC_BUS_WIDTH_4)
f53fbde4 833 burstlen = 16;
6584cb88
SH		 834 else
835 burstlen = 4;
f53fbde4
SH		 836
837 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
838 host->burstlen = burstlen;
839 ret = mxcmci_setup_dma(mmc);
840 if (ret) {
841 dev_err(mmc_dev(host->mmc),
842 "failed to config DMA channel. Falling back to PIO\n");
843 dma_release_channel(host->dma);
844 host->do_dma = 0;
e58f516f 845 host->dma = NULL;
f53fbde4
SH		 846 }
847 }
d96be879 848
d96be879
SH		 849 if (ios->bus_width == MMC_BUS_WIDTH_4)
850 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
851 else
852 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
853
854 if (host->power_mode != ios->power_mode) {
d96be879 855 host->power_mode = ios->power_mode;
bc3c1771 856 mxcmci_set_power(host, ios->vdd);
74b66954 857
d96be879
SH		 858 if (ios->power_mode == MMC_POWER_ON)
859 host->cmdat |= CMD_DAT_CONT_INIT;
860 }
861
862 if (ios->clock) {
863 mxcmci_set_clk_rate(host, ios->clock);
c7ceab02 864 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
d96be879 865 } else {
c7ceab02 866 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
d96be879
SH		 867 }
868
869 host->clock = ios->clock;
870}
871
872static irqreturn_t mxcmci_detect_irq(int irq, void *data)
873{
874 struct mmc_host *mmc = data;
875
876 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
877
878 mmc_detect_change(mmc, msecs_to_jiffies(250));
879 return IRQ_HANDLED;
880}
881
882static int mxcmci_get_ro(struct mmc_host *mmc)
883{
884 struct mxcmci_host *host = mmc_priv(mmc);
885
886 if (host->pdata && host->pdata->get_ro)
887 return !!host->pdata->get_ro(mmc_dev(mmc));
888 /*
bcf53524
AG		 889 * If board doesn't support read only detection (no mmc_gpio
890 * context or gpio is invalid), then let the mmc core decide
891 * what to do.
d96be879 892 */
bcf53524 893 return mmc_gpio_get_ro(mmc);
d96be879
SH		 894}
895
f441b993
DM		 896static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
897{
898 struct mxcmci_host *host = mmc_priv(mmc);
899 unsigned long flags;
900 u32 int_cntr;
901
902 spin_lock_irqsave(&host->lock, flags);
903 host->use_sdio = enable;
c7ceab02 904 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
f441b993
DM		 905
906 if (enable)
907 int_cntr |= INT_SDIO_IRQ_EN;
908 else
909 int_cntr &= ~INT_SDIO_IRQ_EN;
910
c7ceab02 911 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993
DM		 912 spin_unlock_irqrestore(&host->lock, flags);
913}
d96be879 914
3fcb027d
DM		 915static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
916{
7f917a8d
SG		 917 struct mxcmci_host *mxcmci = mmc_priv(host);
918
3fcb027d
DM		 919 /*
920 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
921 * multi-block transfers when connected SDIO peripheral doesn't
922 * drive the BUSY line as required by the specs.
923 * One way to prevent this is to only allow 1-bit transfers.
924 */
925
c095449e 926 if (is_imx31_mmc(mxcmci) && mmc_card_sdio(card))
3fcb027d
DM		 927 host->caps &= ~MMC_CAP_4_BIT_DATA;
928 else
929 host->caps |= MMC_CAP_4_BIT_DATA;
930}
931
f53fbde4
SH		 932static bool filter(struct dma_chan *chan, void *param)
933{
934 struct mxcmci_host *host = param;
935
936 if (!imx_dma_is_general_purpose(chan))
937 return false;
938
939 chan->private = &host->dma_data;
940
941 return true;
942}
943
2ee4f620 944static void mxcmci_watchdog(struct timer_list *t)
f6ad0a48 945{
2ee4f620 946 struct mxcmci_host *host = from_timer(host, t, watchdog);
f6ad0a48 947 struct mmc_request *req = host->req;
c7ceab02 948 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
f6ad0a48
JM		 949
950 if (host->dma_dir == DMA_FROM_DEVICE) {
951 dmaengine_terminate_all(host->dma);
952 dev_err(mmc_dev(host->mmc),
953 "%s: read time out (status = 0x%08x)\n",
954 __func__, stat);
955 } else {
956 dev_err(mmc_dev(host->mmc),
957 "%s: write time out (status = 0x%08x)\n",
958 __func__, stat);
959 mxcmci_softreset(host);
960 }
961
962 /* Mark transfer as erroneus and inform the upper layers */
963
70aa6109
AG		 964 if (host->data)
965 host->data->error = -ETIMEDOUT;
f6ad0a48
JM		 966 host->req = NULL;
967 host->cmd = NULL;
968 host->data = NULL;
969 mmc_request_done(host->mmc, req);
970}
971
d96be879 972static const struct mmc_host_ops mxcmci_ops = {
f441b993
DM		 973 .request = mxcmci_request,
974 .set_ios = mxcmci_set_ios,
975 .get_ro = mxcmci_get_ro,
976 .enable_sdio_irq = mxcmci_enable_sdio_irq,
3fcb027d 977 .init_card = mxcmci_init_card,
d96be879
SH		 978};
979
980static int mxcmci_probe(struct platform_device *pdev)
981{
982 struct mmc_host *mmc;
01e4f958
AS		 983 struct mxcmci_host *host;
984 struct resource *res;
d96be879 985 int ret = 0, irq;
7ff747c4 986 bool dat3_card_detect = false;
f53fbde4 987 dma_cap_mask_t mask;
7ff747c4 988 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
d96be879 989
c7ceab02 990 pr_info("i.MX/MPC512x SDHC driver\n");
d96be879 991
01e4f958 992 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d96be879 993 irq = platform_get_irq(pdev, 0);
9a7957d0 994 if (irq < 0)
f216c124 995 return irq;
d96be879 996
01e4f958
AS		 997 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
998 if (!mmc)
999 return -ENOMEM;
d96be879 1000
01e4f958
AS		 1001 host = mmc_priv(mmc);
1002
1003 host->base = devm_ioremap_resource(&pdev->dev, res);
1004 if (IS_ERR(host->base)) {
1005 ret = PTR_ERR(host->base);
1006 goto out_free;
d96be879
SH		 1007 }
1008
01e4f958
AS		 1009 host->phys_base = res->start;
1010
b8857696
SB		 1011 ret = mmc_of_parse(mmc);
1012 if (ret)
1013 goto out_free;
d96be879 1014 mmc->ops = &mxcmci_ops;
7ff747c4
MP		 1015
1016 /* For devicetree parsing, the bus width is read from devicetree */
1017 if (pdata)
1018 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1019 else
1020 mmc->caps |= MMC_CAP_SDIO_IRQ;
d96be879
SH		 1021
1022 /* MMC core transfer sizes tunable parameters */
d96be879
SH		 1023 mmc->max_blk_size = 2048;
1024 mmc->max_blk_count = 65535;
1025 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
d759c374 1026 mmc->max_seg_size = mmc->max_req_size;
d96be879 1027
7dc65e3c 1028 host->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev);
e48fc15a
AG		 1029
1030 /* adjust max_segs after devtype detection */
1031 if (!is_mpc512x_mmc(host))
1032 mmc->max_segs = 64;
1033
d96be879 1034 host->mmc = mmc;
7ff747c4 1035 host->pdata = pdata;
f441b993 1036 spin_lock_init(&host->lock);
d96be879 1037
7ff747c4
MP		 1038 if (pdata)
1039 dat3_card_detect = pdata->dat3_card_detect;
860951c5 1040 else if (mmc_card_is_removable(mmc)
7ff747c4
MP		 1041 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1042 dat3_card_detect = true;
1043
bc3c1771 1044 ret = mmc_regulator_get_supply(mmc);
337d7c8a 1045 if (ret)
18a09806
MF		 1046 goto out_free;
1047
1048 if (!mmc->ocr_avail) {
1049 if (pdata && pdata->ocr_avail)
1050 mmc->ocr_avail = pdata->ocr_avail;
bc3c1771 1051 else
18a09806 1052 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
bc3c1771 1053 }
d96be879 1054
7ff747c4 1055 if (dat3_card_detect)
16b3bf8c
EB		 1056 host->default_irq_mask =
1057 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1058 else
1059 host->default_irq_mask = 0;
1060
529aa29e
SH		 1061 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1062 if (IS_ERR(host->clk_ipg)) {
1063 ret = PTR_ERR(host->clk_ipg);
01e4f958 1064 goto out_free;
d96be879 1065 }
529aa29e
SH		 1066
1067 host->clk_per = devm_clk_get(&pdev->dev, "per");
1068 if (IS_ERR(host->clk_per)) {
1069 ret = PTR_ERR(host->clk_per);
01e4f958 1070 goto out_free;
529aa29e
SH		 1071 }
1072
a2bc74cf
AY		 1073 ret = clk_prepare_enable(host->clk_per);
1074 if (ret)
1075 goto out_free;
1076
1077 ret = clk_prepare_enable(host->clk_ipg);
1078 if (ret)
1079 goto out_clk_per_put;
d96be879
SH		 1080
1081 mxcmci_softreset(host);
1082
c7ceab02 1083 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
d96be879
SH		 1084 if (host->rev_no != 0x400) {
1085 ret = -ENODEV;
1086 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1087 host->rev_no);
1088 goto out_clk_put;
1089 }
1090
529aa29e
SH		 1091 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1092 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
d96be879
SH		 1093
1094 /* recommended in data sheet */
c7ceab02 1095 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
d96be879 1096
c7ceab02 1097 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
d96be879 1098
7ff747c4 1099 if (!host->pdata) {
c3b2a021
PU		 1100 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1101 if (IS_ERR(host->dma)) {
1102 if (PTR_ERR(host->dma) == -EPROBE_DEFER) {
1103 ret = -EPROBE_DEFER;
1104 goto out_clk_put;
1105 }
1106
1107 /* Ignore errors to fall back to PIO mode */
1108 host->dma = NULL;
1109 }
7ff747c4 1110 } else {
01e4f958
AS		 1111 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1112 if (res) {
1113 host->dmareq = res->start;
7ff747c4
MP		 1114 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1115 host->dma_data.priority = DMA_PRIO_LOW;
1116 host->dma_data.dma_request = host->dmareq;
1117 dma_cap_zero(mask);
1118 dma_cap_set(DMA_SLAVE, mask);
1119 host->dma = dma_request_channel(mask, filter, host);
1120 }
f53fbde4 1121 }
7ff747c4
MP		 1122 if (host->dma)
1123 mmc->max_seg_size = dma_get_max_seg_size(
1124 host->dma->device->dev);
1125 else
f53fbde4 1126 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
d96be879 1127
d96be879
SH		 1128 INIT_WORK(&host->datawork, mxcmci_datawork);
1129
01e4f958
AS		 1130 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1131 dev_name(&pdev->dev), host);
d96be879
SH		 1132 if (ret)
1133 goto out_free_dma;
1134
1135 platform_set_drvdata(pdev, mmc);
1136
1137 if (host->pdata && host->pdata->init) {
1138 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1139 host->mmc);
1140 if (ret)
01e4f958 1141 goto out_free_dma;
d96be879
SH		 1142 }
1143
2ee4f620 1144 timer_setup(&host->watchdog, mxcmci_watchdog, 0);
f6ad0a48 1145
cde600af
YY		 1146 ret = mmc_add_host(mmc);
1147 if (ret)
1148 goto out_free_dma;
abd4190f 1149
d96be879
SH		 1150 return 0;
1151
d96be879 1152out_free_dma:
f53fbde4
SH		 1153 if (host->dma)
1154 dma_release_channel(host->dma);
01e4f958 1155
d96be879 1156out_clk_put:
529aa29e 1157 clk_disable_unprepare(host->clk_ipg);
a2bc74cf
AY		 1158out_clk_per_put:
1159 clk_disable_unprepare(host->clk_per);
01e4f958 1160
d96be879
SH		 1161out_free:
1162 mmc_free_host(mmc);
01e4f958 1163
d96be879
SH		 1164 return ret;
1165}
1166
1167static int mxcmci_remove(struct platform_device *pdev)
1168{
1169 struct mmc_host *mmc = platform_get_drvdata(pdev);
1170 struct mxcmci_host *host = mmc_priv(mmc);
1171
d96be879
SH		 1172 mmc_remove_host(mmc);
1173
1174 if (host->pdata && host->pdata->exit)
1175 host->pdata->exit(&pdev->dev, mmc);
1176
f53fbde4
SH		 1177 if (host->dma)
1178 dma_release_channel(host->dma);
1179
529aa29e
SH		 1180 clk_disable_unprepare(host->clk_per);
1181 clk_disable_unprepare(host->clk_ipg);
d96be879 1182
d96be879
SH		 1183 mmc_free_host(mmc);
1184
1185 return 0;
1186}
1187
d8edfc4e 1188static int mxcmci_suspend(struct device *dev)
d96be879 1189{
a7d403cf
EB		 1190 struct mmc_host *mmc = dev_get_drvdata(dev);
1191 struct mxcmci_host *host = mmc_priv(mmc);
d96be879 1192
529aa29e
SH		 1193 clk_disable_unprepare(host->clk_per);
1194 clk_disable_unprepare(host->clk_ipg);
bd190f90 1195 return 0;
d96be879
SH		 1196}
1197
d8edfc4e 1198static int mxcmci_resume(struct device *dev)
d96be879 1199{
a7d403cf
EB		 1200 struct mmc_host *mmc = dev_get_drvdata(dev);
1201 struct mxcmci_host *host = mmc_priv(mmc);
a2bc74cf 1202 int ret;
d96be879 1203
a2bc74cf
AY		 1204 ret = clk_prepare_enable(host->clk_per);
1205 if (ret)
1206 return ret;
1207
1208 ret = clk_prepare_enable(host->clk_ipg);
1209 if (ret)
1210 clk_disable_unprepare(host->clk_per);
1211
1212 return ret;
d96be879 1213}
a7d403cf 1214
52cc1d7f 1215static DEFINE_SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
d96be879
SH		 1216
1217static struct platform_driver mxcmci_driver = {
1218 .probe = mxcmci_probe,
1219 .remove = mxcmci_remove,
d96be879
SH		 1220 .driver = {
1221 .name = DRIVER_NAME,
21b2cec6 1222 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2cdbd92c 1223 .pm = pm_sleep_ptr(&mxcmci_pm_ops),
7ff747c4 1224 .of_match_table = mxcmci_of_match,
d96be879
SH		 1225 }
1226};
1227
d1f81a64 1228module_platform_driver(mxcmci_driver);
d96be879
SH		 1229
1230MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1231MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1232MODULE_LICENSE("GPL");
6eb30adf 1233MODULE_ALIAS("platform:mxc-mmc");
Linux 6.x block layer and io_uring tree(s)