Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d96be879 SH |
2 | /* |
3 | * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver | |
4 | * | |
5 | * This is a driver for the SDHC controller found in Freescale MX2/MX3 | |
6 | * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). | |
7 | * Unlike the hardware found on MX1, this hardware just works and does | |
3ad2f3fb | 8 | * not need all the quirks found in imxmmc.c, hence the separate driver. |
d96be879 SH |
9 | * |
10 | * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
11 | * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> | |
12 | * | |
13 | * derived from pxamci.c by Russell King | |
d96be879 SH |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/platform_device.h> | |
a639bb72 | 20 | #include <linux/highmem.h> |
d96be879 SH |
21 | #include <linux/interrupt.h> |
22 | #include <linux/irq.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/mmc/host.h> | |
26 | #include <linux/mmc/card.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/io.h> | |
74b66954 | 30 | #include <linux/regulator/consumer.h> |
f53fbde4 | 31 | #include <linux/dmaengine.h> |
258aea76 | 32 | #include <linux/types.h> |
7ff747c4 | 33 | #include <linux/of.h> |
7ff747c4 | 34 | #include <linux/of_dma.h> |
bcf53524 | 35 | #include <linux/mmc/slot-gpio.h> |
d96be879 SH |
36 | |
37 | #include <asm/dma.h> | |
38 | #include <asm/irq.h> | |
82906b13 | 39 | #include <linux/platform_data/mmc-mxcmmc.h> |
d96be879 | 40 | |
c6547c2e | 41 | #include <linux/dma/imx-dma.h> |
d96be879 | 42 | |
9563b1db | 43 | #define DRIVER_NAME "mxc-mmc" |
f6ad0a48 | 44 | #define MXCMCI_TIMEOUT_MS 10000 |
d96be879 SH |
45 | |
46 | #define MMC_REG_STR_STP_CLK 0x00 | |
47 | #define MMC_REG_STATUS 0x04 | |
48 | #define MMC_REG_CLK_RATE 0x08 | |
49 | #define MMC_REG_CMD_DAT_CONT 0x0C | |
50 | #define MMC_REG_RES_TO 0x10 | |
51 | #define MMC_REG_READ_TO 0x14 | |
52 | #define MMC_REG_BLK_LEN 0x18 | |
53 | #define MMC_REG_NOB 0x1C | |
54 | #define MMC_REG_REV_NO 0x20 | |
55 | #define MMC_REG_INT_CNTR 0x24 | |
56 | #define MMC_REG_CMD 0x28 | |
57 | #define MMC_REG_ARG 0x2C | |
58 | #define MMC_REG_RES_FIFO 0x34 | |
59 | #define MMC_REG_BUFFER_ACCESS 0x38 | |
60 | ||
61 | #define STR_STP_CLK_RESET (1 << 3) | |
62 | #define STR_STP_CLK_START_CLK (1 << 1) | |
63 | #define STR_STP_CLK_STOP_CLK (1 << 0) | |
64 | ||
65 | #define STATUS_CARD_INSERTION (1 << 31) | |
66 | #define STATUS_CARD_REMOVAL (1 << 30) | |
67 | #define STATUS_YBUF_EMPTY (1 << 29) | |
68 | #define STATUS_XBUF_EMPTY (1 << 28) | |
69 | #define STATUS_YBUF_FULL (1 << 27) | |
70 | #define STATUS_XBUF_FULL (1 << 26) | |
71 | #define STATUS_BUF_UND_RUN (1 << 25) | |
72 | #define STATUS_BUF_OVFL (1 << 24) | |
73 | #define STATUS_SDIO_INT_ACTIVE (1 << 14) | |
74 | #define STATUS_END_CMD_RESP (1 << 13) | |
75 | #define STATUS_WRITE_OP_DONE (1 << 12) | |
76 | #define STATUS_DATA_TRANS_DONE (1 << 11) | |
77 | #define STATUS_READ_OP_DONE (1 << 11) | |
78 | #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) | |
79 | #define STATUS_CARD_BUS_CLK_RUN (1 << 8) | |
80 | #define STATUS_BUF_READ_RDY (1 << 7) | |
81 | #define STATUS_BUF_WRITE_RDY (1 << 6) | |
82 | #define STATUS_RESP_CRC_ERR (1 << 5) | |
83 | #define STATUS_CRC_READ_ERR (1 << 3) | |
84 | #define STATUS_CRC_WRITE_ERR (1 << 2) | |
85 | #define STATUS_TIME_OUT_RESP (1 << 1) | |
86 | #define STATUS_TIME_OUT_READ (1 << 0) | |
87 | #define STATUS_ERR_MASK 0x2f | |
88 | ||
89 | #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) | |
90 | #define CMD_DAT_CONT_STOP_READWAIT (1 << 11) | |
91 | #define CMD_DAT_CONT_START_READWAIT (1 << 10) | |
92 | #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) | |
93 | #define CMD_DAT_CONT_INIT (1 << 7) | |
94 | #define CMD_DAT_CONT_WRITE (1 << 4) | |
95 | #define CMD_DAT_CONT_DATA_ENABLE (1 << 3) | |
96 | #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) | |
97 | #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) | |
98 | #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) | |
99 | ||
100 | #define INT_SDIO_INT_WKP_EN (1 << 18) | |
101 | #define INT_CARD_INSERTION_WKP_EN (1 << 17) | |
102 | #define INT_CARD_REMOVAL_WKP_EN (1 << 16) | |
103 | #define INT_CARD_INSERTION_EN (1 << 15) | |
104 | #define INT_CARD_REMOVAL_EN (1 << 14) | |
105 | #define INT_SDIO_IRQ_EN (1 << 13) | |
106 | #define INT_DAT0_EN (1 << 12) | |
107 | #define INT_BUF_READ_EN (1 << 4) | |
108 | #define INT_BUF_WRITE_EN (1 << 3) | |
109 | #define INT_END_CMD_RES_EN (1 << 2) | |
110 | #define INT_WRITE_OP_DONE_EN (1 << 1) | |
111 | #define INT_READ_OP_EN (1 << 0) | |
112 | ||
7f917a8d SG |
113 | enum mxcmci_type { |
114 | IMX21_MMC, | |
115 | IMX31_MMC, | |
c7ceab02 | 116 | MPC512X_MMC, |
7f917a8d SG |
117 | }; |
118 | ||
d96be879 SH |
119 | struct mxcmci_host { |
120 | struct mmc_host *mmc; | |
d96be879 | 121 | void __iomem *base; |
01e4f958 | 122 | dma_addr_t phys_base; |
d96be879 | 123 | int detect_irq; |
f53fbde4 SH |
124 | struct dma_chan *dma; |
125 | struct dma_async_tx_descriptor *desc; | |
d96be879 | 126 | int do_dma; |
16b3bf8c | 127 | int default_irq_mask; |
f441b993 | 128 | int use_sdio; |
d96be879 SH |
129 | unsigned int power_mode; |
130 | struct imxmmc_platform_data *pdata; | |
131 | ||
132 | struct mmc_request *req; | |
133 | struct mmc_command *cmd; | |
134 | struct mmc_data *data; | |
135 | ||
d96be879 SH |
136 | unsigned int datasize; |
137 | unsigned int dma_dir; | |
138 | ||
139 | u16 rev_no; | |
140 | unsigned int cmdat; | |
141 | ||
529aa29e SH |
142 | struct clk *clk_ipg; |
143 | struct clk *clk_per; | |
d96be879 SH |
144 | |
145 | int clock; | |
146 | ||
147 | struct work_struct datawork; | |
f441b993 | 148 | spinlock_t lock; |
74b66954 | 149 | |
f53fbde4 SH |
150 | int burstlen; |
151 | int dmareq; | |
152 | struct dma_slave_config dma_slave_config; | |
153 | struct imx_dma_data dma_data; | |
f6ad0a48 JM |
154 | |
155 | struct timer_list watchdog; | |
7f917a8d SG |
156 | enum mxcmci_type devtype; |
157 | }; | |
158 | ||
7ff747c4 MP |
159 | static const struct of_device_id mxcmci_of_match[] = { |
160 | { | |
161 | .compatible = "fsl,imx21-mmc", | |
8223e885 | 162 | .data = (void *) IMX21_MMC, |
7ff747c4 MP |
163 | }, { |
164 | .compatible = "fsl,imx31-mmc", | |
8223e885 | 165 | .data = (void *) IMX31_MMC, |
c7ceab02 AG |
166 | }, { |
167 | .compatible = "fsl,mpc5121-sdhc", | |
8223e885 | 168 | .data = (void *) MPC512X_MMC, |
7ff747c4 MP |
169 | }, { |
170 | /* sentinel */ | |
171 | } | |
172 | }; | |
173 | MODULE_DEVICE_TABLE(of, mxcmci_of_match); | |
174 | ||
7f917a8d SG |
175 | static inline int is_imx31_mmc(struct mxcmci_host *host) |
176 | { | |
177 | return host->devtype == IMX31_MMC; | |
178 | } | |
d96be879 | 179 | |
c7ceab02 AG |
180 | static inline int is_mpc512x_mmc(struct mxcmci_host *host) |
181 | { | |
182 | return host->devtype == MPC512X_MMC; | |
183 | } | |
184 | ||
185 | static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg) | |
186 | { | |
187 | if (IS_ENABLED(CONFIG_PPC_MPC512x)) | |
188 | return ioread32be(host->base + reg); | |
189 | else | |
190 | return readl(host->base + reg); | |
191 | } | |
192 | ||
193 | static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg) | |
194 | { | |
195 | if (IS_ENABLED(CONFIG_PPC_MPC512x)) | |
196 | iowrite32be(val, host->base + reg); | |
197 | else | |
198 | writel(val, host->base + reg); | |
199 | } | |
200 | ||
201 | static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg) | |
202 | { | |
203 | if (IS_ENABLED(CONFIG_PPC_MPC512x)) | |
204 | return ioread32be(host->base + reg); | |
205 | else | |
206 | return readw(host->base + reg); | |
207 | } | |
208 | ||
209 | static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg) | |
210 | { | |
211 | if (IS_ENABLED(CONFIG_PPC_MPC512x)) | |
212 | iowrite32be(val, host->base + reg); | |
213 | else | |
214 | writew(val, host->base + reg); | |
215 | } | |
216 | ||
18489fa2 MF |
217 | static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); |
218 | ||
bc3c1771 | 219 | static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd) |
74b66954 | 220 | { |
bc3c1771 AS |
221 | if (!IS_ERR(host->mmc->supply.vmmc)) { |
222 | if (host->power_mode == MMC_POWER_UP) | |
223 | mmc_regulator_set_ocr(host->mmc, | |
224 | host->mmc->supply.vmmc, vdd); | |
225 | else if (host->power_mode == MMC_POWER_OFF) | |
226 | mmc_regulator_set_ocr(host->mmc, | |
227 | host->mmc->supply.vmmc, 0); | |
d078d242 AP |
228 | } |
229 | ||
74b66954 AP |
230 | if (host->pdata && host->pdata->setpower) |
231 | host->pdata->setpower(mmc_dev(host->mmc), vdd); | |
232 | } | |
233 | ||
d96be879 SH |
234 | static inline int mxcmci_use_dma(struct mxcmci_host *host) |
235 | { | |
236 | return host->do_dma; | |
237 | } | |
238 | ||
239 | static void mxcmci_softreset(struct mxcmci_host *host) | |
240 | { | |
241 | int i; | |
242 | ||
4725f6f1 DM |
243 | dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); |
244 | ||
d96be879 | 245 | /* reset sequence */ |
c7ceab02 AG |
246 | mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK); |
247 | mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, | |
248 | MMC_REG_STR_STP_CLK); | |
d96be879 SH |
249 | |
250 | for (i = 0; i < 8; i++) | |
c7ceab02 | 251 | mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); |
d96be879 | 252 | |
c7ceab02 | 253 | mxcmci_writew(host, 0xff, MMC_REG_RES_TO); |
d96be879 SH |
254 | } |
255 | ||
e48fc15a AG |
256 | #if IS_ENABLED(CONFIG_PPC_MPC512x) |
257 | static inline void buffer_swap32(u32 *buf, int len) | |
258 | { | |
259 | int i; | |
260 | ||
261 | for (i = 0; i < ((len + 3) / 4); i++) { | |
7a8bf874 | 262 | *buf = swab32(*buf); |
e48fc15a AG |
263 | buf++; |
264 | } | |
265 | } | |
266 | ||
267 | static void mxcmci_swap_buffers(struct mmc_data *data) | |
268 | { | |
12658af5 LW |
269 | struct sg_mapping_iter sgm; |
270 | u32 *buf; | |
271 | ||
272 | sg_miter_start(&sgm, data->sg, data->sg_len, | |
273 | SG_MITER_TO_SG | SG_MITER_FROM_SG); | |
274 | ||
275 | while (sg_miter_next(&sgm)) { | |
276 | buf = sgm.addr; | |
277 | buffer_swap32(buf, sgm.length); | |
278 | } | |
e48fc15a | 279 | |
12658af5 | 280 | sg_miter_stop(&sgm); |
e48fc15a AG |
281 | } |
282 | #else | |
283 | static inline void mxcmci_swap_buffers(struct mmc_data *data) {} | |
284 | #endif | |
285 | ||
656217d2 | 286 | static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) |
d96be879 SH |
287 | { |
288 | unsigned int nob = data->blocks; | |
289 | unsigned int blksz = data->blksz; | |
290 | unsigned int datasize = nob * blksz; | |
d96be879 | 291 | struct scatterlist *sg; |
05f5799c | 292 | enum dma_transfer_direction slave_dirn; |
f53fbde4 SH |
293 | int i, nents; |
294 | ||
d96be879 SH |
295 | host->data = data; |
296 | data->bytes_xfered = 0; | |
297 | ||
c7ceab02 AG |
298 | mxcmci_writew(host, nob, MMC_REG_NOB); |
299 | mxcmci_writew(host, blksz, MMC_REG_BLK_LEN); | |
d96be879 SH |
300 | host->datasize = datasize; |
301 | ||
f53fbde4 SH |
302 | if (!mxcmci_use_dma(host)) |
303 | return 0; | |
304 | ||
d96be879 | 305 | for_each_sg(data->sg, sg, data->sg_len, i) { |
2cb53552 | 306 | if (sg->offset & 3 || sg->length & 3 || sg->length < 512) { |
d96be879 | 307 | host->do_dma = 0; |
656217d2 | 308 | return 0; |
d96be879 SH |
309 | } |
310 | } | |
311 | ||
05f5799c | 312 | if (data->flags & MMC_DATA_READ) { |
d96be879 | 313 | host->dma_dir = DMA_FROM_DEVICE; |
05f5799c VK |
314 | slave_dirn = DMA_DEV_TO_MEM; |
315 | } else { | |
d96be879 | 316 | host->dma_dir = DMA_TO_DEVICE; |
05f5799c | 317 | slave_dirn = DMA_MEM_TO_DEV; |
e48fc15a AG |
318 | |
319 | mxcmci_swap_buffers(data); | |
05f5799c | 320 | } |
d96be879 | 321 | |
f53fbde4 SH |
322 | nents = dma_map_sg(host->dma->device->dev, data->sg, |
323 | data->sg_len, host->dma_dir); | |
324 | if (nents != data->sg_len) | |
325 | return -EINVAL; | |
326 | ||
16052827 | 327 | host->desc = dmaengine_prep_slave_sg(host->dma, |
05f5799c | 328 | data->sg, data->sg_len, slave_dirn, |
f53fbde4 | 329 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
d96be879 | 330 | |
f53fbde4 SH |
331 | if (!host->desc) { |
332 | dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, | |
333 | host->dma_dir); | |
334 | host->do_dma = 0; | |
335 | return 0; /* Fall back to PIO */ | |
656217d2 | 336 | } |
d96be879 SH |
337 | wmb(); |
338 | ||
f53fbde4 | 339 | dmaengine_submit(host->desc); |
439aa0ef | 340 | dma_async_issue_pending(host->dma); |
f53fbde4 | 341 | |
f6ad0a48 JM |
342 | mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS)); |
343 | ||
656217d2 | 344 | return 0; |
d96be879 SH |
345 | } |
346 | ||
f6ad0a48 JM |
347 | static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat); |
348 | static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat); | |
349 | ||
350 | static void mxcmci_dma_callback(void *data) | |
351 | { | |
352 | struct mxcmci_host *host = data; | |
353 | u32 stat; | |
354 | ||
355 | del_timer(&host->watchdog); | |
356 | ||
c7ceab02 | 357 | stat = mxcmci_readl(host, MMC_REG_STATUS); |
f6ad0a48 JM |
358 | |
359 | dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); | |
360 | ||
f6ad0a48 JM |
361 | mxcmci_data_done(host, stat); |
362 | } | |
363 | ||
d96be879 SH |
364 | static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, |
365 | unsigned int cmdat) | |
366 | { | |
16b3bf8c | 367 | u32 int_cntr = host->default_irq_mask; |
f441b993 DM |
368 | unsigned long flags; |
369 | ||
d96be879 SH |
370 | WARN_ON(host->cmd != NULL); |
371 | host->cmd = cmd; | |
372 | ||
373 | switch (mmc_resp_type(cmd)) { | |
374 | case MMC_RSP_R1: /* short CRC, OPCODE */ | |
375 | case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ | |
376 | cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; | |
377 | break; | |
378 | case MMC_RSP_R2: /* long 136 bit + CRC */ | |
379 | cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; | |
380 | break; | |
381 | case MMC_RSP_R3: /* short */ | |
382 | cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; | |
383 | break; | |
384 | case MMC_RSP_NONE: | |
385 | break; | |
386 | default: | |
387 | dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n", | |
388 | mmc_resp_type(cmd)); | |
389 | cmd->error = -EINVAL; | |
390 | return -EINVAL; | |
391 | } | |
392 | ||
f441b993 DM |
393 | int_cntr = INT_END_CMD_RES_EN; |
394 | ||
f6ad0a48 JM |
395 | if (mxcmci_use_dma(host)) { |
396 | if (host->dma_dir == DMA_FROM_DEVICE) { | |
397 | host->desc->callback = mxcmci_dma_callback; | |
398 | host->desc->callback_param = host; | |
399 | } else { | |
400 | int_cntr |= INT_WRITE_OP_DONE_EN; | |
401 | } | |
402 | } | |
f441b993 DM |
403 | |
404 | spin_lock_irqsave(&host->lock, flags); | |
405 | if (host->use_sdio) | |
406 | int_cntr |= INT_SDIO_IRQ_EN; | |
c7ceab02 | 407 | mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); |
f441b993 | 408 | spin_unlock_irqrestore(&host->lock, flags); |
d96be879 | 409 | |
c7ceab02 AG |
410 | mxcmci_writew(host, cmd->opcode, MMC_REG_CMD); |
411 | mxcmci_writel(host, cmd->arg, MMC_REG_ARG); | |
412 | mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT); | |
d96be879 SH |
413 | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static void mxcmci_finish_request(struct mxcmci_host *host, | |
418 | struct mmc_request *req) | |
419 | { | |
16b3bf8c | 420 | u32 int_cntr = host->default_irq_mask; |
f441b993 DM |
421 | unsigned long flags; |
422 | ||
423 | spin_lock_irqsave(&host->lock, flags); | |
424 | if (host->use_sdio) | |
425 | int_cntr |= INT_SDIO_IRQ_EN; | |
c7ceab02 | 426 | mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); |
f441b993 | 427 | spin_unlock_irqrestore(&host->lock, flags); |
d96be879 SH |
428 | |
429 | host->req = NULL; | |
430 | host->cmd = NULL; | |
431 | host->data = NULL; | |
432 | ||
433 | mmc_request_done(host->mmc, req); | |
434 | } | |
435 | ||
436 | static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) | |
437 | { | |
438 | struct mmc_data *data = host->data; | |
439 | int data_error; | |
440 | ||
e48fc15a | 441 | if (mxcmci_use_dma(host)) { |
f53fbde4 | 442 | dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, |
d96be879 | 443 | host->dma_dir); |
e48fc15a AG |
444 | mxcmci_swap_buffers(data); |
445 | } | |
d96be879 SH |
446 | |
447 | if (stat & STATUS_ERR_MASK) { | |
448 | dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", | |
449 | stat); | |
450 | if (stat & STATUS_CRC_READ_ERR) { | |
4725f6f1 | 451 | dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__); |
d96be879 SH |
452 | data->error = -EILSEQ; |
453 | } else if (stat & STATUS_CRC_WRITE_ERR) { | |
454 | u32 err_code = (stat >> 9) & 0x3; | |
4725f6f1 DM |
455 | if (err_code == 2) { /* No CRC response */ |
456 | dev_err(mmc_dev(host->mmc), | |
457 | "%s: No CRC -ETIMEDOUT\n", __func__); | |
d96be879 | 458 | data->error = -ETIMEDOUT; |
4725f6f1 DM |
459 | } else { |
460 | dev_err(mmc_dev(host->mmc), | |
461 | "%s: -EILSEQ\n", __func__); | |
d96be879 | 462 | data->error = -EILSEQ; |
4725f6f1 | 463 | } |
d96be879 | 464 | } else if (stat & STATUS_TIME_OUT_READ) { |
4725f6f1 DM |
465 | dev_err(mmc_dev(host->mmc), |
466 | "%s: read -ETIMEDOUT\n", __func__); | |
d96be879 SH |
467 | data->error = -ETIMEDOUT; |
468 | } else { | |
4725f6f1 | 469 | dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__); |
d96be879 SH |
470 | data->error = -EIO; |
471 | } | |
472 | } else { | |
473 | data->bytes_xfered = host->datasize; | |
474 | } | |
475 | ||
476 | data_error = data->error; | |
477 | ||
478 | host->data = NULL; | |
479 | ||
480 | return data_error; | |
481 | } | |
482 | ||
483 | static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) | |
484 | { | |
485 | struct mmc_command *cmd = host->cmd; | |
486 | int i; | |
487 | u32 a, b, c; | |
488 | ||
489 | if (!cmd) | |
490 | return; | |
491 | ||
492 | if (stat & STATUS_TIME_OUT_RESP) { | |
493 | dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); | |
494 | cmd->error = -ETIMEDOUT; | |
495 | } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { | |
496 | dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); | |
497 | cmd->error = -EILSEQ; | |
498 | } | |
499 | ||
500 | if (cmd->flags & MMC_RSP_PRESENT) { | |
501 | if (cmd->flags & MMC_RSP_136) { | |
502 | for (i = 0; i < 4; i++) { | |
c7ceab02 AG |
503 | a = mxcmci_readw(host, MMC_REG_RES_FIFO); |
504 | b = mxcmci_readw(host, MMC_REG_RES_FIFO); | |
d96be879 SH |
505 | cmd->resp[i] = a << 16 | b; |
506 | } | |
507 | } else { | |
c7ceab02 AG |
508 | a = mxcmci_readw(host, MMC_REG_RES_FIFO); |
509 | b = mxcmci_readw(host, MMC_REG_RES_FIFO); | |
510 | c = mxcmci_readw(host, MMC_REG_RES_FIFO); | |
d96be879 SH |
511 | cmd->resp[0] = a << 24 | b << 8 | c >> 8; |
512 | } | |
513 | } | |
514 | } | |
515 | ||
516 | static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) | |
517 | { | |
518 | u32 stat; | |
519 | unsigned long timeout = jiffies + HZ; | |
520 | ||
521 | do { | |
c7ceab02 | 522 | stat = mxcmci_readl(host, MMC_REG_STATUS); |
d96be879 SH |
523 | if (stat & STATUS_ERR_MASK) |
524 | return stat; | |
18489fa2 MF |
525 | if (time_after(jiffies, timeout)) { |
526 | mxcmci_softreset(host); | |
527 | mxcmci_set_clk_rate(host, host->clock); | |
d96be879 | 528 | return STATUS_TIME_OUT_READ; |
18489fa2 | 529 | } |
d96be879 SH |
530 | if (stat & mask) |
531 | return 0; | |
532 | cpu_relax(); | |
533 | } while (1); | |
534 | } | |
535 | ||
12658af5 | 536 | static int mxcmci_pull(struct mxcmci_host *host, u32 *buf, int bytes) |
d96be879 SH |
537 | { |
538 | unsigned int stat; | |
d96be879 SH |
539 | |
540 | while (bytes > 3) { | |
541 | stat = mxcmci_poll_status(host, | |
542 | STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); | |
543 | if (stat) | |
544 | return stat; | |
c7ceab02 | 545 | *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); |
d96be879 SH |
546 | bytes -= 4; |
547 | } | |
548 | ||
549 | if (bytes) { | |
550 | u8 *b = (u8 *)buf; | |
551 | u32 tmp; | |
552 | ||
553 | stat = mxcmci_poll_status(host, | |
554 | STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); | |
555 | if (stat) | |
556 | return stat; | |
c7ceab02 | 557 | tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); |
d96be879 SH |
558 | memcpy(b, &tmp, bytes); |
559 | } | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
12658af5 | 564 | static int mxcmci_push(struct mxcmci_host *host, u32 *buf, int bytes) |
d96be879 SH |
565 | { |
566 | unsigned int stat; | |
d96be879 SH |
567 | |
568 | while (bytes > 3) { | |
569 | stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); | |
570 | if (stat) | |
571 | return stat; | |
c7ceab02 | 572 | mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS); |
d96be879 SH |
573 | bytes -= 4; |
574 | } | |
575 | ||
576 | if (bytes) { | |
577 | u8 *b = (u8 *)buf; | |
578 | u32 tmp; | |
579 | ||
580 | stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); | |
581 | if (stat) | |
582 | return stat; | |
583 | ||
584 | memcpy(&tmp, b, bytes); | |
c7ceab02 | 585 | mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS); |
d96be879 SH |
586 | } |
587 | ||
6d916416 | 588 | return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); |
d96be879 SH |
589 | } |
590 | ||
591 | static int mxcmci_transfer_data(struct mxcmci_host *host) | |
592 | { | |
593 | struct mmc_data *data = host->req->data; | |
12658af5 LW |
594 | struct sg_mapping_iter sgm; |
595 | int stat; | |
596 | u32 *buf; | |
d96be879 | 597 | |
d96be879 SH |
598 | host->data = data; |
599 | host->datasize = 0; | |
12658af5 LW |
600 | sg_miter_start(&sgm, data->sg, data->sg_len, |
601 | (data->flags & MMC_DATA_READ) ? SG_MITER_TO_SG : SG_MITER_FROM_SG); | |
d96be879 SH |
602 | |
603 | if (data->flags & MMC_DATA_READ) { | |
12658af5 LW |
604 | while (sg_miter_next(&sgm)) { |
605 | buf = sgm.addr; | |
606 | stat = mxcmci_pull(host, buf, sgm.length); | |
d96be879 | 607 | if (stat) |
12658af5 LW |
608 | goto transfer_error; |
609 | host->datasize += sgm.length; | |
d96be879 SH |
610 | } |
611 | } else { | |
12658af5 LW |
612 | while (sg_miter_next(&sgm)) { |
613 | buf = sgm.addr; | |
614 | stat = mxcmci_push(host, buf, sgm.length); | |
d96be879 | 615 | if (stat) |
12658af5 LW |
616 | goto transfer_error; |
617 | host->datasize += sgm.length; | |
d96be879 SH |
618 | } |
619 | stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); | |
620 | if (stat) | |
12658af5 | 621 | goto transfer_error; |
d96be879 | 622 | } |
12658af5 LW |
623 | |
624 | transfer_error: | |
625 | sg_miter_stop(&sgm); | |
626 | return stat; | |
d96be879 SH |
627 | } |
628 | ||
629 | static void mxcmci_datawork(struct work_struct *work) | |
630 | { | |
631 | struct mxcmci_host *host = container_of(work, struct mxcmci_host, | |
632 | datawork); | |
633 | int datastat = mxcmci_transfer_data(host); | |
4a31f2ef | 634 | |
c7ceab02 AG |
635 | mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, |
636 | MMC_REG_STATUS); | |
d96be879 SH |
637 | mxcmci_finish_data(host, datastat); |
638 | ||
639 | if (host->req->stop) { | |
640 | if (mxcmci_start_cmd(host, host->req->stop, 0)) { | |
641 | mxcmci_finish_request(host, host->req); | |
642 | return; | |
643 | } | |
644 | } else { | |
645 | mxcmci_finish_request(host, host->req); | |
646 | } | |
647 | } | |
648 | ||
d96be879 SH |
649 | static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) |
650 | { | |
70aa6109 | 651 | struct mmc_request *req; |
d96be879 | 652 | int data_error; |
70aa6109 AG |
653 | unsigned long flags; |
654 | ||
655 | spin_lock_irqsave(&host->lock, flags); | |
d96be879 | 656 | |
70aa6109 AG |
657 | if (!host->data) { |
658 | spin_unlock_irqrestore(&host->lock, flags); | |
d96be879 | 659 | return; |
70aa6109 AG |
660 | } |
661 | ||
662 | if (!host->req) { | |
663 | spin_unlock_irqrestore(&host->lock, flags); | |
664 | return; | |
665 | } | |
666 | ||
667 | req = host->req; | |
668 | if (!req->stop) | |
669 | host->req = NULL; /* we will handle finish req below */ | |
d96be879 SH |
670 | |
671 | data_error = mxcmci_finish_data(host, stat); | |
672 | ||
70aa6109 AG |
673 | spin_unlock_irqrestore(&host->lock, flags); |
674 | ||
09954ea9 SL |
675 | if (data_error) |
676 | return; | |
677 | ||
d96be879 SH |
678 | mxcmci_read_response(host, stat); |
679 | host->cmd = NULL; | |
680 | ||
70aa6109 AG |
681 | if (req->stop) { |
682 | if (mxcmci_start_cmd(host, req->stop, 0)) { | |
683 | mxcmci_finish_request(host, req); | |
d96be879 SH |
684 | return; |
685 | } | |
686 | } else { | |
70aa6109 | 687 | mxcmci_finish_request(host, req); |
d96be879 SH |
688 | } |
689 | } | |
d96be879 SH |
690 | |
691 | static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) | |
692 | { | |
693 | mxcmci_read_response(host, stat); | |
694 | host->cmd = NULL; | |
695 | ||
696 | if (!host->data && host->req) { | |
697 | mxcmci_finish_request(host, host->req); | |
698 | return; | |
699 | } | |
700 | ||
701 | /* For the DMA case the DMA engine handles the data transfer | |
fd589a8f | 702 | * automatically. For non DMA we have to do it ourselves. |
d96be879 SH |
703 | * Don't do it in interrupt context though. |
704 | */ | |
705 | if (!mxcmci_use_dma(host) && host->data) | |
706 | schedule_work(&host->datawork); | |
707 | ||
708 | } | |
709 | ||
710 | static irqreturn_t mxcmci_irq(int irq, void *devid) | |
711 | { | |
712 | struct mxcmci_host *host = devid; | |
f441b993 | 713 | bool sdio_irq; |
d96be879 SH |
714 | u32 stat; |
715 | ||
c7ceab02 AG |
716 | stat = mxcmci_readl(host, MMC_REG_STATUS); |
717 | mxcmci_writel(host, | |
718 | stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | | |
719 | STATUS_WRITE_OP_DONE), | |
720 | MMC_REG_STATUS); | |
d96be879 SH |
721 | |
722 | dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); | |
723 | ||
5a941898 | 724 | spin_lock(&host->lock); |
f441b993 | 725 | sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; |
5a941898 | 726 | spin_unlock(&host->lock); |
f441b993 | 727 | |
adfa5703 MF |
728 | if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE))) |
729 | mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS); | |
4a31f2ef | 730 | |
f441b993 | 731 | if (sdio_irq) { |
c7ceab02 | 732 | mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS); |
f441b993 DM |
733 | mmc_signal_sdio_irq(host->mmc); |
734 | } | |
735 | ||
d96be879 SH |
736 | if (stat & STATUS_END_CMD_RESP) |
737 | mxcmci_cmd_done(host, stat); | |
f441b993 | 738 | |
adfa5703 | 739 | if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) { |
f6ad0a48 | 740 | del_timer(&host->watchdog); |
d96be879 | 741 | mxcmci_data_done(host, stat); |
f6ad0a48 | 742 | } |
f53fbde4 | 743 | |
16b3bf8c EB |
744 | if (host->default_irq_mask && |
745 | (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) | |
746 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
f53fbde4 | 747 | |
d96be879 SH |
748 | return IRQ_HANDLED; |
749 | } | |
750 | ||
751 | static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) | |
752 | { | |
753 | struct mxcmci_host *host = mmc_priv(mmc); | |
754 | unsigned int cmdat = host->cmdat; | |
656217d2 | 755 | int error; |
d96be879 SH |
756 | |
757 | WARN_ON(host->req != NULL); | |
758 | ||
759 | host->req = req; | |
760 | host->cmdat &= ~CMD_DAT_CONT_INIT; | |
f53fbde4 SH |
761 | |
762 | if (host->dma) | |
763 | host->do_dma = 1; | |
764 | ||
d96be879 | 765 | if (req->data) { |
656217d2 MF |
766 | error = mxcmci_setup_data(host, req->data); |
767 | if (error) { | |
768 | req->cmd->error = error; | |
769 | goto out; | |
770 | } | |
771 | ||
d96be879 SH |
772 | |
773 | cmdat |= CMD_DAT_CONT_DATA_ENABLE; | |
774 | ||
775 | if (req->data->flags & MMC_DATA_WRITE) | |
776 | cmdat |= CMD_DAT_CONT_WRITE; | |
777 | } | |
778 | ||
656217d2 | 779 | error = mxcmci_start_cmd(host, req->cmd, cmdat); |
f53fbde4 | 780 | |
656217d2 MF |
781 | out: |
782 | if (error) | |
d96be879 SH |
783 | mxcmci_finish_request(host, req); |
784 | } | |
785 | ||
786 | static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) | |
787 | { | |
788 | unsigned int divider; | |
789 | int prescaler = 0; | |
529aa29e | 790 | unsigned int clk_in = clk_get_rate(host->clk_per); |
d96be879 SH |
791 | |
792 | while (prescaler <= 0x800) { | |
793 | for (divider = 1; divider <= 0xF; divider++) { | |
794 | int x; | |
795 | ||
796 | x = (clk_in / (divider + 1)); | |
797 | ||
798 | if (prescaler) | |
799 | x /= (prescaler * 2); | |
800 | ||
801 | if (x <= clk_ios) | |
802 | break; | |
803 | } | |
804 | if (divider < 0x10) | |
805 | break; | |
806 | ||
807 | if (prescaler == 0) | |
808 | prescaler = 1; | |
809 | else | |
810 | prescaler <<= 1; | |
811 | } | |
812 | ||
c7ceab02 | 813 | mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE); |
d96be879 SH |
814 | |
815 | dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", | |
816 | prescaler, divider, clk_in, clk_ios); | |
817 | } | |
818 | ||
f53fbde4 SH |
819 | static int mxcmci_setup_dma(struct mmc_host *mmc) |
820 | { | |
821 | struct mxcmci_host *host = mmc_priv(mmc); | |
822 | struct dma_slave_config *config = &host->dma_slave_config; | |
823 | ||
01e4f958 AS |
824 | config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; |
825 | config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; | |
f53fbde4 SH |
826 | config->dst_addr_width = 4; |
827 | config->src_addr_width = 4; | |
828 | config->dst_maxburst = host->burstlen; | |
829 | config->src_maxburst = host->burstlen; | |
258aea76 | 830 | config->device_fc = false; |
f53fbde4 SH |
831 | |
832 | return dmaengine_slave_config(host->dma, config); | |
833 | } | |
834 | ||
d96be879 SH |
835 | static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
836 | { | |
837 | struct mxcmci_host *host = mmc_priv(mmc); | |
f53fbde4 SH |
838 | int burstlen, ret; |
839 | ||
d96be879 | 840 | /* |
6584cb88 SH |
841 | * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0) |
842 | * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16) | |
d96be879 SH |
843 | */ |
844 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
f53fbde4 | 845 | burstlen = 16; |
6584cb88 SH |
846 | else |
847 | burstlen = 4; | |
f53fbde4 SH |
848 | |
849 | if (mxcmci_use_dma(host) && burstlen != host->burstlen) { | |
850 | host->burstlen = burstlen; | |
851 | ret = mxcmci_setup_dma(mmc); | |
852 | if (ret) { | |
853 | dev_err(mmc_dev(host->mmc), | |
854 | "failed to config DMA channel. Falling back to PIO\n"); | |
855 | dma_release_channel(host->dma); | |
856 | host->do_dma = 0; | |
e58f516f | 857 | host->dma = NULL; |
f53fbde4 SH |
858 | } |
859 | } | |
d96be879 | 860 | |
d96be879 SH |
861 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
862 | host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; | |
863 | else | |
864 | host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; | |
865 | ||
866 | if (host->power_mode != ios->power_mode) { | |
d96be879 | 867 | host->power_mode = ios->power_mode; |
bc3c1771 | 868 | mxcmci_set_power(host, ios->vdd); |
74b66954 | 869 | |
d96be879 SH |
870 | if (ios->power_mode == MMC_POWER_ON) |
871 | host->cmdat |= CMD_DAT_CONT_INIT; | |
872 | } | |
873 | ||
874 | if (ios->clock) { | |
875 | mxcmci_set_clk_rate(host, ios->clock); | |
c7ceab02 | 876 | mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); |
d96be879 | 877 | } else { |
c7ceab02 | 878 | mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK); |
d96be879 SH |
879 | } |
880 | ||
881 | host->clock = ios->clock; | |
882 | } | |
883 | ||
884 | static irqreturn_t mxcmci_detect_irq(int irq, void *data) | |
885 | { | |
886 | struct mmc_host *mmc = data; | |
887 | ||
888 | dev_dbg(mmc_dev(mmc), "%s\n", __func__); | |
889 | ||
890 | mmc_detect_change(mmc, msecs_to_jiffies(250)); | |
891 | return IRQ_HANDLED; | |
892 | } | |
893 | ||
894 | static int mxcmci_get_ro(struct mmc_host *mmc) | |
895 | { | |
896 | struct mxcmci_host *host = mmc_priv(mmc); | |
897 | ||
898 | if (host->pdata && host->pdata->get_ro) | |
899 | return !!host->pdata->get_ro(mmc_dev(mmc)); | |
900 | /* | |
bcf53524 AG |
901 | * If board doesn't support read only detection (no mmc_gpio |
902 | * context or gpio is invalid), then let the mmc core decide | |
903 | * what to do. | |
d96be879 | 904 | */ |
bcf53524 | 905 | return mmc_gpio_get_ro(mmc); |
d96be879 SH |
906 | } |
907 | ||
f441b993 DM |
908 | static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
909 | { | |
910 | struct mxcmci_host *host = mmc_priv(mmc); | |
911 | unsigned long flags; | |
912 | u32 int_cntr; | |
913 | ||
914 | spin_lock_irqsave(&host->lock, flags); | |
915 | host->use_sdio = enable; | |
c7ceab02 | 916 | int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR); |
f441b993 DM |
917 | |
918 | if (enable) | |
919 | int_cntr |= INT_SDIO_IRQ_EN; | |
920 | else | |
921 | int_cntr &= ~INT_SDIO_IRQ_EN; | |
922 | ||
c7ceab02 | 923 | mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); |
f441b993 DM |
924 | spin_unlock_irqrestore(&host->lock, flags); |
925 | } | |
d96be879 | 926 | |
3fcb027d DM |
927 | static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) |
928 | { | |
7f917a8d SG |
929 | struct mxcmci_host *mxcmci = mmc_priv(host); |
930 | ||
3fcb027d DM |
931 | /* |
932 | * MX3 SoCs have a silicon bug which corrupts CRC calculation of | |
933 | * multi-block transfers when connected SDIO peripheral doesn't | |
934 | * drive the BUSY line as required by the specs. | |
935 | * One way to prevent this is to only allow 1-bit transfers. | |
936 | */ | |
937 | ||
c095449e | 938 | if (is_imx31_mmc(mxcmci) && mmc_card_sdio(card)) |
3fcb027d DM |
939 | host->caps &= ~MMC_CAP_4_BIT_DATA; |
940 | else | |
941 | host->caps |= MMC_CAP_4_BIT_DATA; | |
942 | } | |
943 | ||
f53fbde4 SH |
944 | static bool filter(struct dma_chan *chan, void *param) |
945 | { | |
946 | struct mxcmci_host *host = param; | |
947 | ||
948 | if (!imx_dma_is_general_purpose(chan)) | |
949 | return false; | |
950 | ||
951 | chan->private = &host->dma_data; | |
952 | ||
953 | return true; | |
954 | } | |
955 | ||
2ee4f620 | 956 | static void mxcmci_watchdog(struct timer_list *t) |
f6ad0a48 | 957 | { |
2ee4f620 | 958 | struct mxcmci_host *host = from_timer(host, t, watchdog); |
f6ad0a48 | 959 | struct mmc_request *req = host->req; |
c7ceab02 | 960 | unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS); |
f6ad0a48 JM |
961 | |
962 | if (host->dma_dir == DMA_FROM_DEVICE) { | |
963 | dmaengine_terminate_all(host->dma); | |
964 | dev_err(mmc_dev(host->mmc), | |
965 | "%s: read time out (status = 0x%08x)\n", | |
966 | __func__, stat); | |
967 | } else { | |
968 | dev_err(mmc_dev(host->mmc), | |
969 | "%s: write time out (status = 0x%08x)\n", | |
970 | __func__, stat); | |
971 | mxcmci_softreset(host); | |
972 | } | |
973 | ||
974 | /* Mark transfer as erroneus and inform the upper layers */ | |
975 | ||
70aa6109 AG |
976 | if (host->data) |
977 | host->data->error = -ETIMEDOUT; | |
f6ad0a48 JM |
978 | host->req = NULL; |
979 | host->cmd = NULL; | |
980 | host->data = NULL; | |
981 | mmc_request_done(host->mmc, req); | |
982 | } | |
983 | ||
d96be879 | 984 | static const struct mmc_host_ops mxcmci_ops = { |
f441b993 DM |
985 | .request = mxcmci_request, |
986 | .set_ios = mxcmci_set_ios, | |
987 | .get_ro = mxcmci_get_ro, | |
988 | .enable_sdio_irq = mxcmci_enable_sdio_irq, | |
3fcb027d | 989 | .init_card = mxcmci_init_card, |
d96be879 SH |
990 | }; |
991 | ||
992 | static int mxcmci_probe(struct platform_device *pdev) | |
993 | { | |
994 | struct mmc_host *mmc; | |
01e4f958 AS |
995 | struct mxcmci_host *host; |
996 | struct resource *res; | |
d96be879 | 997 | int ret = 0, irq; |
7ff747c4 | 998 | bool dat3_card_detect = false; |
f53fbde4 | 999 | dma_cap_mask_t mask; |
7ff747c4 | 1000 | struct imxmmc_platform_data *pdata = pdev->dev.platform_data; |
d96be879 | 1001 | |
c7ceab02 | 1002 | pr_info("i.MX/MPC512x SDHC driver\n"); |
d96be879 | 1003 | |
d96be879 | 1004 | irq = platform_get_irq(pdev, 0); |
9a7957d0 | 1005 | if (irq < 0) |
f216c124 | 1006 | return irq; |
d96be879 | 1007 | |
01e4f958 AS |
1008 | mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); |
1009 | if (!mmc) | |
1010 | return -ENOMEM; | |
d96be879 | 1011 | |
01e4f958 AS |
1012 | host = mmc_priv(mmc); |
1013 | ||
a1a28ac1 | 1014 | host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
01e4f958 AS |
1015 | if (IS_ERR(host->base)) { |
1016 | ret = PTR_ERR(host->base); | |
1017 | goto out_free; | |
d96be879 SH |
1018 | } |
1019 | ||
01e4f958 AS |
1020 | host->phys_base = res->start; |
1021 | ||
b8857696 SB |
1022 | ret = mmc_of_parse(mmc); |
1023 | if (ret) | |
1024 | goto out_free; | |
d96be879 | 1025 | mmc->ops = &mxcmci_ops; |
7ff747c4 MP |
1026 | |
1027 | /* For devicetree parsing, the bus width is read from devicetree */ | |
1028 | if (pdata) | |
1029 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; | |
1030 | else | |
1031 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
d96be879 SH |
1032 | |
1033 | /* MMC core transfer sizes tunable parameters */ | |
d96be879 SH |
1034 | mmc->max_blk_size = 2048; |
1035 | mmc->max_blk_count = 65535; | |
1036 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
d759c374 | 1037 | mmc->max_seg_size = mmc->max_req_size; |
d96be879 | 1038 | |
7dc65e3c | 1039 | host->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev); |
e48fc15a AG |
1040 | |
1041 | /* adjust max_segs after devtype detection */ | |
1042 | if (!is_mpc512x_mmc(host)) | |
1043 | mmc->max_segs = 64; | |
1044 | ||
d96be879 | 1045 | host->mmc = mmc; |
7ff747c4 | 1046 | host->pdata = pdata; |
f441b993 | 1047 | spin_lock_init(&host->lock); |
d96be879 | 1048 | |
7ff747c4 MP |
1049 | if (pdata) |
1050 | dat3_card_detect = pdata->dat3_card_detect; | |
860951c5 | 1051 | else if (mmc_card_is_removable(mmc) |
7ff747c4 MP |
1052 | && !of_property_read_bool(pdev->dev.of_node, "cd-gpios")) |
1053 | dat3_card_detect = true; | |
1054 | ||
bc3c1771 | 1055 | ret = mmc_regulator_get_supply(mmc); |
337d7c8a | 1056 | if (ret) |
18a09806 MF |
1057 | goto out_free; |
1058 | ||
1059 | if (!mmc->ocr_avail) { | |
1060 | if (pdata && pdata->ocr_avail) | |
1061 | mmc->ocr_avail = pdata->ocr_avail; | |
bc3c1771 | 1062 | else |
18a09806 | 1063 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
bc3c1771 | 1064 | } |
d96be879 | 1065 | |
7ff747c4 | 1066 | if (dat3_card_detect) |
16b3bf8c EB |
1067 | host->default_irq_mask = |
1068 | INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; | |
1069 | else | |
1070 | host->default_irq_mask = 0; | |
1071 | ||
529aa29e SH |
1072 | host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1073 | if (IS_ERR(host->clk_ipg)) { | |
1074 | ret = PTR_ERR(host->clk_ipg); | |
01e4f958 | 1075 | goto out_free; |
d96be879 | 1076 | } |
529aa29e SH |
1077 | |
1078 | host->clk_per = devm_clk_get(&pdev->dev, "per"); | |
1079 | if (IS_ERR(host->clk_per)) { | |
1080 | ret = PTR_ERR(host->clk_per); | |
01e4f958 | 1081 | goto out_free; |
529aa29e SH |
1082 | } |
1083 | ||
a2bc74cf AY |
1084 | ret = clk_prepare_enable(host->clk_per); |
1085 | if (ret) | |
1086 | goto out_free; | |
1087 | ||
1088 | ret = clk_prepare_enable(host->clk_ipg); | |
1089 | if (ret) | |
1090 | goto out_clk_per_put; | |
d96be879 SH |
1091 | |
1092 | mxcmci_softreset(host); | |
1093 | ||
c7ceab02 | 1094 | host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO); |
d96be879 SH |
1095 | if (host->rev_no != 0x400) { |
1096 | ret = -ENODEV; | |
1097 | dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", | |
1098 | host->rev_no); | |
1099 | goto out_clk_put; | |
1100 | } | |
1101 | ||
529aa29e SH |
1102 | mmc->f_min = clk_get_rate(host->clk_per) >> 16; |
1103 | mmc->f_max = clk_get_rate(host->clk_per) >> 1; | |
d96be879 SH |
1104 | |
1105 | /* recommended in data sheet */ | |
c7ceab02 | 1106 | mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO); |
d96be879 | 1107 | |
c7ceab02 | 1108 | mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR); |
d96be879 | 1109 | |
7ff747c4 | 1110 | if (!host->pdata) { |
c3b2a021 PU |
1111 | host->dma = dma_request_chan(&pdev->dev, "rx-tx"); |
1112 | if (IS_ERR(host->dma)) { | |
1113 | if (PTR_ERR(host->dma) == -EPROBE_DEFER) { | |
1114 | ret = -EPROBE_DEFER; | |
1115 | goto out_clk_put; | |
1116 | } | |
1117 | ||
1118 | /* Ignore errors to fall back to PIO mode */ | |
1119 | host->dma = NULL; | |
1120 | } | |
7ff747c4 | 1121 | } else { |
01e4f958 AS |
1122 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1123 | if (res) { | |
1124 | host->dmareq = res->start; | |
7ff747c4 MP |
1125 | host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; |
1126 | host->dma_data.priority = DMA_PRIO_LOW; | |
1127 | host->dma_data.dma_request = host->dmareq; | |
1128 | dma_cap_zero(mask); | |
1129 | dma_cap_set(DMA_SLAVE, mask); | |
1130 | host->dma = dma_request_channel(mask, filter, host); | |
1131 | } | |
f53fbde4 | 1132 | } |
7ff747c4 MP |
1133 | if (host->dma) |
1134 | mmc->max_seg_size = dma_get_max_seg_size( | |
1135 | host->dma->device->dev); | |
1136 | else | |
f53fbde4 | 1137 | dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n"); |
d96be879 | 1138 | |
d96be879 SH |
1139 | INIT_WORK(&host->datawork, mxcmci_datawork); |
1140 | ||
01e4f958 AS |
1141 | ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0, |
1142 | dev_name(&pdev->dev), host); | |
d96be879 SH |
1143 | if (ret) |
1144 | goto out_free_dma; | |
1145 | ||
1146 | platform_set_drvdata(pdev, mmc); | |
1147 | ||
1148 | if (host->pdata && host->pdata->init) { | |
1149 | ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, | |
1150 | host->mmc); | |
1151 | if (ret) | |
01e4f958 | 1152 | goto out_free_dma; |
d96be879 SH |
1153 | } |
1154 | ||
2ee4f620 | 1155 | timer_setup(&host->watchdog, mxcmci_watchdog, 0); |
f6ad0a48 | 1156 | |
cde600af YY |
1157 | ret = mmc_add_host(mmc); |
1158 | if (ret) | |
1159 | goto out_free_dma; | |
abd4190f | 1160 | |
d96be879 SH |
1161 | return 0; |
1162 | ||
d96be879 | 1163 | out_free_dma: |
f53fbde4 SH |
1164 | if (host->dma) |
1165 | dma_release_channel(host->dma); | |
01e4f958 | 1166 | |
d96be879 | 1167 | out_clk_put: |
529aa29e | 1168 | clk_disable_unprepare(host->clk_ipg); |
a2bc74cf AY |
1169 | out_clk_per_put: |
1170 | clk_disable_unprepare(host->clk_per); | |
01e4f958 | 1171 | |
d96be879 SH |
1172 | out_free: |
1173 | mmc_free_host(mmc); | |
01e4f958 | 1174 | |
d96be879 SH |
1175 | return ret; |
1176 | } | |
1177 | ||
0484ed31 | 1178 | static void mxcmci_remove(struct platform_device *pdev) |
d96be879 SH |
1179 | { |
1180 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1181 | struct mxcmci_host *host = mmc_priv(mmc); | |
1182 | ||
d96be879 SH |
1183 | mmc_remove_host(mmc); |
1184 | ||
1185 | if (host->pdata && host->pdata->exit) | |
1186 | host->pdata->exit(&pdev->dev, mmc); | |
1187 | ||
f53fbde4 SH |
1188 | if (host->dma) |
1189 | dma_release_channel(host->dma); | |
1190 | ||
529aa29e SH |
1191 | clk_disable_unprepare(host->clk_per); |
1192 | clk_disable_unprepare(host->clk_ipg); | |
d96be879 | 1193 | |
d96be879 | 1194 | mmc_free_host(mmc); |
d96be879 SH |
1195 | } |
1196 | ||
d8edfc4e | 1197 | static int mxcmci_suspend(struct device *dev) |
d96be879 | 1198 | { |
a7d403cf EB |
1199 | struct mmc_host *mmc = dev_get_drvdata(dev); |
1200 | struct mxcmci_host *host = mmc_priv(mmc); | |
d96be879 | 1201 | |
529aa29e SH |
1202 | clk_disable_unprepare(host->clk_per); |
1203 | clk_disable_unprepare(host->clk_ipg); | |
bd190f90 | 1204 | return 0; |
d96be879 SH |
1205 | } |
1206 | ||
d8edfc4e | 1207 | static int mxcmci_resume(struct device *dev) |
d96be879 | 1208 | { |
a7d403cf EB |
1209 | struct mmc_host *mmc = dev_get_drvdata(dev); |
1210 | struct mxcmci_host *host = mmc_priv(mmc); | |
a2bc74cf | 1211 | int ret; |
d96be879 | 1212 | |
a2bc74cf AY |
1213 | ret = clk_prepare_enable(host->clk_per); |
1214 | if (ret) | |
1215 | return ret; | |
1216 | ||
1217 | ret = clk_prepare_enable(host->clk_ipg); | |
1218 | if (ret) | |
1219 | clk_disable_unprepare(host->clk_per); | |
1220 | ||
1221 | return ret; | |
d96be879 | 1222 | } |
a7d403cf | 1223 | |
52cc1d7f | 1224 | static DEFINE_SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume); |
d96be879 SH |
1225 | |
1226 | static struct platform_driver mxcmci_driver = { | |
1227 | .probe = mxcmci_probe, | |
0484ed31 | 1228 | .remove_new = mxcmci_remove, |
d96be879 SH |
1229 | .driver = { |
1230 | .name = DRIVER_NAME, | |
21b2cec6 | 1231 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
2cdbd92c | 1232 | .pm = pm_sleep_ptr(&mxcmci_pm_ops), |
7ff747c4 | 1233 | .of_match_table = mxcmci_of_match, |
d96be879 SH |
1234 | } |
1235 | }; | |
1236 | ||
d1f81a64 | 1237 | module_platform_driver(mxcmci_driver); |
d96be879 SH |
1238 | |
1239 | MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); | |
1240 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
1241 | MODULE_LICENSE("GPL"); | |
6eb30adf | 1242 | MODULE_ALIAS("platform:mxc-mmc"); |