Commit | Line | Data |
---|---|---|
1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
20848903 CJ |
2 | /* |
3 | * Copyright (c) 2014-2015 MediaTek Inc. | |
4 | * Author: Chaotian.Jing <chaotian.jing@mediatek.com> | |
20848903 CJ |
5 | */ |
6 | ||
7 | #include <linux/module.h> | |
8 | #include <linux/clk.h> | |
9 | #include <linux/delay.h> | |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/ioport.h> | |
12 | #include <linux/irq.h> | |
13 | #include <linux/of_address.h> | |
909b3456 | 14 | #include <linux/of_device.h> |
20848903 CJ |
15 | #include <linux/of_irq.h> |
16 | #include <linux/of_gpio.h> | |
17 | #include <linux/pinctrl/consumer.h> | |
18 | #include <linux/platform_device.h> | |
4b8a43e9 CJ |
19 | #include <linux/pm.h> |
20 | #include <linux/pm_runtime.h> | |
20848903 | 21 | #include <linux/regulator/consumer.h> |
6397b7f5 | 22 | #include <linux/slab.h> |
20848903 | 23 | #include <linux/spinlock.h> |
b8789ec4 | 24 | #include <linux/interrupt.h> |
20848903 CJ |
25 | |
26 | #include <linux/mmc/card.h> | |
27 | #include <linux/mmc/core.h> | |
28 | #include <linux/mmc/host.h> | |
29 | #include <linux/mmc/mmc.h> | |
30 | #include <linux/mmc/sd.h> | |
31 | #include <linux/mmc/sdio.h> | |
8d53e412 | 32 | #include <linux/mmc/slot-gpio.h> |
20848903 CJ |
33 | |
34 | #define MAX_BD_NUM 1024 | |
35 | ||
36 | /*--------------------------------------------------------------------------*/ | |
37 | /* Common Definition */ | |
38 | /*--------------------------------------------------------------------------*/ | |
39 | #define MSDC_BUS_1BITS 0x0 | |
40 | #define MSDC_BUS_4BITS 0x1 | |
41 | #define MSDC_BUS_8BITS 0x2 | |
42 | ||
43 | #define MSDC_BURST_64B 0x6 | |
44 | ||
45 | /*--------------------------------------------------------------------------*/ | |
46 | /* Register Offset */ | |
47 | /*--------------------------------------------------------------------------*/ | |
48 | #define MSDC_CFG 0x0 | |
49 | #define MSDC_IOCON 0x04 | |
50 | #define MSDC_PS 0x08 | |
51 | #define MSDC_INT 0x0c | |
52 | #define MSDC_INTEN 0x10 | |
53 | #define MSDC_FIFOCS 0x14 | |
54 | #define SDC_CFG 0x30 | |
55 | #define SDC_CMD 0x34 | |
56 | #define SDC_ARG 0x38 | |
57 | #define SDC_STS 0x3c | |
58 | #define SDC_RESP0 0x40 | |
59 | #define SDC_RESP1 0x44 | |
60 | #define SDC_RESP2 0x48 | |
61 | #define SDC_RESP3 0x4c | |
62 | #define SDC_BLK_NUM 0x50 | |
d9dcbfc8 | 63 | #define SDC_ADV_CFG0 0x64 |
c9b5061e | 64 | #define EMMC_IOCON 0x7c |
20848903 | 65 | #define SDC_ACMD_RESP 0x80 |
2a9bde19 | 66 | #define DMA_SA_H4BIT 0x8c |
20848903 CJ |
67 | #define MSDC_DMA_SA 0x90 |
68 | #define MSDC_DMA_CTRL 0x98 | |
69 | #define MSDC_DMA_CFG 0x9c | |
70 | #define MSDC_PATCH_BIT 0xb0 | |
71 | #define MSDC_PATCH_BIT1 0xb4 | |
2fea5819 | 72 | #define MSDC_PATCH_BIT2 0xb8 |
20848903 | 73 | #define MSDC_PAD_TUNE 0xec |
39add252 | 74 | #define MSDC_PAD_TUNE0 0xf0 |
6397b7f5 | 75 | #define PAD_DS_TUNE 0x188 |
1ede5cb8 | 76 | #define PAD_CMD_TUNE 0x18c |
6397b7f5 | 77 | #define EMMC50_CFG0 0x208 |
c8609b22 | 78 | #define EMMC50_CFG3 0x220 |
d9dcbfc8 | 79 | #define SDC_FIFO_CFG 0x228 |
20848903 | 80 | |
a2e6d1f6 CJ |
81 | /*--------------------------------------------------------------------------*/ |
82 | /* Top Pad Register Offset */ | |
83 | /*--------------------------------------------------------------------------*/ | |
84 | #define EMMC_TOP_CONTROL 0x00 | |
85 | #define EMMC_TOP_CMD 0x04 | |
86 | #define EMMC50_PAD_DS_TUNE 0x0c | |
87 | ||
20848903 CJ |
88 | /*--------------------------------------------------------------------------*/ |
89 | /* Register Mask */ | |
90 | /*--------------------------------------------------------------------------*/ | |
91 | ||
92 | /* MSDC_CFG mask */ | |
93 | #define MSDC_CFG_MODE (0x1 << 0) /* RW */ | |
94 | #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ | |
95 | #define MSDC_CFG_RST (0x1 << 2) /* RW */ | |
96 | #define MSDC_CFG_PIO (0x1 << 3) /* RW */ | |
97 | #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ | |
98 | #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ | |
99 | #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ | |
100 | #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ | |
101 | #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ | |
102 | #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ | |
6397b7f5 | 103 | #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ |
762d491a CJ |
104 | #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ |
105 | #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ | |
106 | #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ | |
20848903 CJ |
107 | |
108 | /* MSDC_IOCON mask */ | |
109 | #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ | |
110 | #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ | |
111 | #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ | |
112 | #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ | |
113 | #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ | |
114 | #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ | |
115 | #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ | |
116 | #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ | |
117 | #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ | |
118 | #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ | |
119 | #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ | |
120 | #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ | |
121 | #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ | |
122 | #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ | |
123 | #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ | |
124 | #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ | |
125 | ||
126 | /* MSDC_PS mask */ | |
127 | #define MSDC_PS_CDEN (0x1 << 0) /* RW */ | |
128 | #define MSDC_PS_CDSTS (0x1 << 1) /* R */ | |
129 | #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ | |
130 | #define MSDC_PS_DAT (0xff << 16) /* R */ | |
131 | #define MSDC_PS_CMD (0x1 << 24) /* R */ | |
132 | #define MSDC_PS_WP (0x1 << 31) /* R */ | |
133 | ||
134 | /* MSDC_INT mask */ | |
135 | #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ | |
136 | #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ | |
137 | #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ | |
138 | #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ | |
139 | #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ | |
140 | #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ | |
141 | #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ | |
142 | #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ | |
143 | #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ | |
144 | #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ | |
145 | #define MSDC_INT_CSTA (0x1 << 11) /* R */ | |
146 | #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ | |
147 | #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ | |
148 | #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ | |
149 | #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ | |
150 | #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ | |
151 | #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ | |
152 | #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ | |
153 | #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ | |
154 | ||
155 | /* MSDC_INTEN mask */ | |
156 | #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ | |
157 | #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ | |
158 | #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ | |
159 | #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ | |
160 | #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ | |
161 | #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ | |
162 | #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ | |
163 | #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ | |
164 | #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ | |
165 | #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ | |
166 | #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ | |
167 | #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ | |
168 | #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ | |
169 | #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ | |
170 | #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ | |
171 | #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ | |
172 | #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ | |
173 | #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ | |
174 | #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ | |
175 | ||
176 | /* MSDC_FIFOCS mask */ | |
177 | #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ | |
178 | #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ | |
179 | #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ | |
180 | ||
181 | /* SDC_CFG mask */ | |
182 | #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ | |
183 | #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ | |
184 | #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ | |
185 | #define SDC_CFG_SDIO (0x1 << 19) /* RW */ | |
186 | #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ | |
187 | #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ | |
188 | #define SDC_CFG_DTOC (0xff << 24) /* RW */ | |
189 | ||
190 | /* SDC_STS mask */ | |
191 | #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ | |
192 | #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ | |
193 | #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ | |
194 | ||
d9dcbfc8 CJ |
195 | /* SDC_ADV_CFG0 mask */ |
196 | #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ | |
197 | ||
2a9bde19 CJ |
198 | /* DMA_SA_H4BIT mask */ |
199 | #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ | |
200 | ||
20848903 CJ |
201 | /* MSDC_DMA_CTRL mask */ |
202 | #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ | |
203 | #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ | |
204 | #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ | |
205 | #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ | |
206 | #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ | |
207 | #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ | |
208 | ||
209 | /* MSDC_DMA_CFG mask */ | |
210 | #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ | |
211 | #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ | |
212 | #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ | |
213 | #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ | |
214 | #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ | |
215 | ||
216 | /* MSDC_PATCH_BIT mask */ | |
217 | #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ | |
218 | #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) | |
219 | #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) | |
220 | #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ | |
221 | #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ | |
222 | #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ | |
223 | #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ | |
224 | #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ | |
225 | #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ | |
226 | #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ | |
227 | #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ | |
228 | #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ | |
229 | ||
d9dcbfc8 CJ |
230 | #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ |
231 | ||
2fea5819 CJ |
232 | #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ |
233 | #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ | |
2a9bde19 | 234 | #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ |
2fea5819 CJ |
235 | #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ |
236 | #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ | |
237 | #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ | |
238 | ||
1ede5cb8 | 239 | #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ |
6397b7f5 CJ |
240 | #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ |
241 | #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ | |
1ede5cb8 | 242 | #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ |
243 | #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ | |
2fea5819 CJ |
244 | #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ |
245 | #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ | |
246 | #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ | |
6397b7f5 CJ |
247 | |
248 | #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ | |
249 | #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ | |
250 | #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ | |
251 | ||
1ede5cb8 | 252 | #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ |
253 | ||
6397b7f5 CJ |
254 | #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ |
255 | #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ | |
256 | #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ | |
257 | ||
c8609b22 CJ |
258 | #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ |
259 | ||
d9dcbfc8 CJ |
260 | #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ |
261 | #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ | |
262 | ||
a2e6d1f6 CJ |
263 | /* EMMC_TOP_CONTROL mask */ |
264 | #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ | |
265 | #define DELAY_EN (0x1 << 1) /* RW */ | |
266 | #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ | |
267 | #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ | |
268 | #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ | |
269 | #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ | |
270 | #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ | |
271 | #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ | |
272 | ||
273 | /* EMMC_TOP_CMD mask */ | |
274 | #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ | |
275 | #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ | |
276 | #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ | |
277 | #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ | |
278 | #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ | |
279 | ||
20848903 CJ |
280 | #define REQ_CMD_EIO (0x1 << 0) |
281 | #define REQ_CMD_TMO (0x1 << 1) | |
282 | #define REQ_DAT_ERR (0x1 << 2) | |
283 | #define REQ_STOP_EIO (0x1 << 3) | |
284 | #define REQ_STOP_TMO (0x1 << 4) | |
285 | #define REQ_CMD_BUSY (0x1 << 5) | |
286 | ||
287 | #define MSDC_PREPARE_FLAG (0x1 << 0) | |
288 | #define MSDC_ASYNC_FLAG (0x1 << 1) | |
289 | #define MSDC_MMAP_FLAG (0x1 << 2) | |
290 | ||
4b8a43e9 | 291 | #define MTK_MMC_AUTOSUSPEND_DELAY 50 |
20848903 CJ |
292 | #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ |
293 | #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ | |
294 | ||
d087bde5 N |
295 | #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ |
296 | ||
6397b7f5 | 297 | #define PAD_DELAY_MAX 32 /* PAD delay cells */ |
20848903 CJ |
298 | /*--------------------------------------------------------------------------*/ |
299 | /* Descriptor Structure */ | |
300 | /*--------------------------------------------------------------------------*/ | |
301 | struct mt_gpdma_desc { | |
302 | u32 gpd_info; | |
303 | #define GPDMA_DESC_HWO (0x1 << 0) | |
304 | #define GPDMA_DESC_BDP (0x1 << 1) | |
305 | #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ | |
306 | #define GPDMA_DESC_INT (0x1 << 16) | |
2a9bde19 CJ |
307 | #define GPDMA_DESC_NEXT_H4 (0xf << 24) |
308 | #define GPDMA_DESC_PTR_H4 (0xf << 28) | |
20848903 CJ |
309 | u32 next; |
310 | u32 ptr; | |
311 | u32 gpd_data_len; | |
312 | #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ | |
313 | #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ | |
314 | u32 arg; | |
315 | u32 blknum; | |
316 | u32 cmd; | |
317 | }; | |
318 | ||
319 | struct mt_bdma_desc { | |
320 | u32 bd_info; | |
321 | #define BDMA_DESC_EOL (0x1 << 0) | |
322 | #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ | |
323 | #define BDMA_DESC_BLKPAD (0x1 << 17) | |
324 | #define BDMA_DESC_DWPAD (0x1 << 18) | |
2a9bde19 CJ |
325 | #define BDMA_DESC_NEXT_H4 (0xf << 24) |
326 | #define BDMA_DESC_PTR_H4 (0xf << 28) | |
20848903 CJ |
327 | u32 next; |
328 | u32 ptr; | |
329 | u32 bd_data_len; | |
330 | #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ | |
331 | }; | |
332 | ||
333 | struct msdc_dma { | |
334 | struct scatterlist *sg; /* I/O scatter list */ | |
335 | struct mt_gpdma_desc *gpd; /* pointer to gpd array */ | |
336 | struct mt_bdma_desc *bd; /* pointer to bd array */ | |
337 | dma_addr_t gpd_addr; /* the physical address of gpd array */ | |
338 | dma_addr_t bd_addr; /* the physical address of bd array */ | |
339 | }; | |
340 | ||
4b8a43e9 CJ |
341 | struct msdc_save_para { |
342 | u32 msdc_cfg; | |
343 | u32 iocon; | |
344 | u32 sdc_cfg; | |
345 | u32 pad_tune; | |
346 | u32 patch_bit0; | |
347 | u32 patch_bit1; | |
2fea5819 | 348 | u32 patch_bit2; |
6397b7f5 | 349 | u32 pad_ds_tune; |
1ede5cb8 | 350 | u32 pad_cmd_tune; |
6397b7f5 | 351 | u32 emmc50_cfg0; |
c8609b22 | 352 | u32 emmc50_cfg3; |
d9dcbfc8 | 353 | u32 sdc_fifo_cfg; |
a2e6d1f6 CJ |
354 | u32 emmc_top_control; |
355 | u32 emmc_top_cmd; | |
356 | u32 emmc50_pad_ds_tune; | |
6397b7f5 CJ |
357 | }; |
358 | ||
762d491a CJ |
359 | struct mtk_mmc_compatible { |
360 | u8 clk_div_bits; | |
7f3d5852 | 361 | bool hs400_tune; /* only used for MT8173 */ |
39add252 | 362 | u32 pad_tune_reg; |
2fea5819 CJ |
363 | bool async_fifo; |
364 | bool data_tune; | |
acde28c4 | 365 | bool busy_check; |
d9dcbfc8 CJ |
366 | bool stop_clk_fix; |
367 | bool enhance_rx; | |
2a9bde19 | 368 | bool support_64g; |
d087bde5 | 369 | bool use_internal_cd; |
762d491a CJ |
370 | }; |
371 | ||
86beac37 CJ |
372 | struct msdc_tune_para { |
373 | u32 iocon; | |
374 | u32 pad_tune; | |
1ede5cb8 | 375 | u32 pad_cmd_tune; |
a2e6d1f6 CJ |
376 | u32 emmc_top_control; |
377 | u32 emmc_top_cmd; | |
86beac37 CJ |
378 | }; |
379 | ||
6397b7f5 CJ |
380 | struct msdc_delay_phase { |
381 | u8 maxlen; | |
382 | u8 start; | |
383 | u8 final_phase; | |
4b8a43e9 CJ |
384 | }; |
385 | ||
20848903 CJ |
386 | struct msdc_host { |
387 | struct device *dev; | |
762d491a | 388 | const struct mtk_mmc_compatible *dev_comp; |
20848903 CJ |
389 | struct mmc_host *mmc; /* mmc structure */ |
390 | int cmd_rsp; | |
391 | ||
392 | spinlock_t lock; | |
393 | struct mmc_request *mrq; | |
394 | struct mmc_command *cmd; | |
395 | struct mmc_data *data; | |
396 | int error; | |
397 | ||
398 | void __iomem *base; /* host base address */ | |
a2e6d1f6 | 399 | void __iomem *top_base; /* host top register base address */ |
20848903 CJ |
400 | |
401 | struct msdc_dma dma; /* dma channel */ | |
402 | u64 dma_mask; | |
403 | ||
404 | u32 timeout_ns; /* data timeout ns */ | |
405 | u32 timeout_clks; /* data timeout clks */ | |
406 | ||
407 | struct pinctrl *pinctrl; | |
408 | struct pinctrl_state *pins_default; | |
409 | struct pinctrl_state *pins_uhs; | |
410 | struct delayed_work req_timeout; | |
411 | int irq; /* host interrupt */ | |
412 | ||
413 | struct clk *src_clk; /* msdc source clock */ | |
414 | struct clk *h_clk; /* msdc h_clk */ | |
258bac4a | 415 | struct clk *bus_clk; /* bus clock which used to access register */ |
3c1a8844 | 416 | struct clk *src_clk_cg; /* msdc source clock control gate */ |
20848903 CJ |
417 | u32 mclk; /* mmc subsystem clock frequency */ |
418 | u32 src_clk_freq; /* source clock frequency */ | |
6e622947 | 419 | unsigned char timing; |
20848903 | 420 | bool vqmmc_enabled; |
d17bb71c | 421 | u32 latch_ck; |
6397b7f5 | 422 | u32 hs400_ds_delay; |
1ede5cb8 | 423 | u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ |
424 | u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ | |
425 | bool hs400_cmd_resp_sel_rising; | |
426 | /* cmd response sample selection for HS400 */ | |
5462ff39 | 427 | bool hs400_mode; /* current eMMC will run at hs400 mode */ |
d087bde5 | 428 | bool internal_cd; /* Use internal card-detect logic */ |
4b8a43e9 | 429 | struct msdc_save_para save_para; /* used when gate HCLK */ |
86beac37 CJ |
430 | struct msdc_tune_para def_tune_para; /* default tune setting */ |
431 | struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ | |
20848903 CJ |
432 | }; |
433 | ||
762d491a CJ |
434 | static const struct mtk_mmc_compatible mt8135_compat = { |
435 | .clk_div_bits = 8, | |
7f3d5852 | 436 | .hs400_tune = false, |
39add252 | 437 | .pad_tune_reg = MSDC_PAD_TUNE, |
2fea5819 CJ |
438 | .async_fifo = false, |
439 | .data_tune = false, | |
acde28c4 | 440 | .busy_check = false, |
d9dcbfc8 CJ |
441 | .stop_clk_fix = false, |
442 | .enhance_rx = false, | |
2a9bde19 | 443 | .support_64g = false, |
762d491a CJ |
444 | }; |
445 | ||
446 | static const struct mtk_mmc_compatible mt8173_compat = { | |
447 | .clk_div_bits = 8, | |
7f3d5852 | 448 | .hs400_tune = true, |
39add252 | 449 | .pad_tune_reg = MSDC_PAD_TUNE, |
2fea5819 CJ |
450 | .async_fifo = false, |
451 | .data_tune = false, | |
acde28c4 | 452 | .busy_check = false, |
d9dcbfc8 CJ |
453 | .stop_clk_fix = false, |
454 | .enhance_rx = false, | |
2a9bde19 | 455 | .support_64g = false, |
762d491a CJ |
456 | }; |
457 | ||
a2e6d1f6 CJ |
458 | static const struct mtk_mmc_compatible mt8183_compat = { |
459 | .clk_div_bits = 12, | |
460 | .hs400_tune = false, | |
461 | .pad_tune_reg = MSDC_PAD_TUNE0, | |
462 | .async_fifo = true, | |
463 | .data_tune = true, | |
464 | .busy_check = true, | |
465 | .stop_clk_fix = true, | |
466 | .enhance_rx = true, | |
467 | .support_64g = true, | |
468 | }; | |
469 | ||
762d491a CJ |
470 | static const struct mtk_mmc_compatible mt2701_compat = { |
471 | .clk_div_bits = 12, | |
7f3d5852 | 472 | .hs400_tune = false, |
39add252 | 473 | .pad_tune_reg = MSDC_PAD_TUNE0, |
2fea5819 CJ |
474 | .async_fifo = true, |
475 | .data_tune = true, | |
acde28c4 | 476 | .busy_check = false, |
d9dcbfc8 CJ |
477 | .stop_clk_fix = false, |
478 | .enhance_rx = false, | |
2a9bde19 | 479 | .support_64g = false, |
762d491a CJ |
480 | }; |
481 | ||
482 | static const struct mtk_mmc_compatible mt2712_compat = { | |
483 | .clk_div_bits = 12, | |
7f3d5852 | 484 | .hs400_tune = false, |
39add252 | 485 | .pad_tune_reg = MSDC_PAD_TUNE0, |
2fea5819 CJ |
486 | .async_fifo = true, |
487 | .data_tune = true, | |
acde28c4 | 488 | .busy_check = true, |
d9dcbfc8 CJ |
489 | .stop_clk_fix = true, |
490 | .enhance_rx = true, | |
2a9bde19 | 491 | .support_64g = true, |
762d491a CJ |
492 | }; |
493 | ||
966580ad SW |
494 | static const struct mtk_mmc_compatible mt7622_compat = { |
495 | .clk_div_bits = 12, | |
496 | .hs400_tune = false, | |
497 | .pad_tune_reg = MSDC_PAD_TUNE0, | |
498 | .async_fifo = true, | |
499 | .data_tune = true, | |
500 | .busy_check = true, | |
501 | .stop_clk_fix = true, | |
502 | .enhance_rx = true, | |
2a9bde19 | 503 | .support_64g = false, |
966580ad SW |
504 | }; |
505 | ||
89822b73 FP |
506 | static const struct mtk_mmc_compatible mt8516_compat = { |
507 | .clk_div_bits = 12, | |
508 | .hs400_tune = false, | |
509 | .pad_tune_reg = MSDC_PAD_TUNE0, | |
510 | .async_fifo = true, | |
511 | .data_tune = true, | |
512 | .busy_check = true, | |
513 | .stop_clk_fix = true, | |
514 | }; | |
515 | ||
afb7c791 N |
516 | static const struct mtk_mmc_compatible mt7620_compat = { |
517 | .clk_div_bits = 8, | |
518 | .hs400_tune = false, | |
519 | .pad_tune_reg = MSDC_PAD_TUNE, | |
520 | .async_fifo = false, | |
521 | .data_tune = false, | |
522 | .busy_check = false, | |
523 | .stop_clk_fix = false, | |
524 | .enhance_rx = false, | |
d087bde5 | 525 | .use_internal_cd = true, |
afb7c791 N |
526 | }; |
527 | ||
762d491a CJ |
528 | static const struct of_device_id msdc_of_ids[] = { |
529 | { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, | |
530 | { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, | |
a2e6d1f6 | 531 | { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, |
762d491a CJ |
532 | { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, |
533 | { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, | |
966580ad | 534 | { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, |
89822b73 | 535 | { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, |
afb7c791 | 536 | { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, |
762d491a CJ |
537 | {} |
538 | }; | |
539 | MODULE_DEVICE_TABLE(of, msdc_of_ids); | |
540 | ||
20848903 CJ |
541 | static void sdr_set_bits(void __iomem *reg, u32 bs) |
542 | { | |
543 | u32 val = readl(reg); | |
544 | ||
545 | val |= bs; | |
546 | writel(val, reg); | |
547 | } | |
548 | ||
549 | static void sdr_clr_bits(void __iomem *reg, u32 bs) | |
550 | { | |
551 | u32 val = readl(reg); | |
552 | ||
553 | val &= ~bs; | |
554 | writel(val, reg); | |
555 | } | |
556 | ||
557 | static void sdr_set_field(void __iomem *reg, u32 field, u32 val) | |
558 | { | |
559 | unsigned int tv = readl(reg); | |
560 | ||
561 | tv &= ~field; | |
562 | tv |= ((val) << (ffs((unsigned int)field) - 1)); | |
563 | writel(tv, reg); | |
564 | } | |
565 | ||
566 | static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) | |
567 | { | |
568 | unsigned int tv = readl(reg); | |
569 | ||
570 | *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); | |
571 | } | |
572 | ||
573 | static void msdc_reset_hw(struct msdc_host *host) | |
574 | { | |
575 | u32 val; | |
576 | ||
577 | sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); | |
578 | while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) | |
579 | cpu_relax(); | |
580 | ||
581 | sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); | |
582 | while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) | |
583 | cpu_relax(); | |
584 | ||
585 | val = readl(host->base + MSDC_INT); | |
586 | writel(val, host->base + MSDC_INT); | |
587 | } | |
588 | ||
589 | static void msdc_cmd_next(struct msdc_host *host, | |
590 | struct mmc_request *mrq, struct mmc_command *cmd); | |
591 | ||
726a9aac CJ |
592 | static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | |
593 | MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | | |
594 | MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; | |
595 | static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | | |
20848903 CJ |
596 | MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | |
597 | MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; | |
598 | ||
599 | static u8 msdc_dma_calcs(u8 *buf, u32 len) | |
600 | { | |
601 | u32 i, sum = 0; | |
602 | ||
603 | for (i = 0; i < len; i++) | |
604 | sum += buf[i]; | |
605 | return 0xff - (u8) sum; | |
606 | } | |
607 | ||
608 | static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, | |
609 | struct mmc_data *data) | |
610 | { | |
611 | unsigned int j, dma_len; | |
612 | dma_addr_t dma_address; | |
613 | u32 dma_ctrl; | |
614 | struct scatterlist *sg; | |
615 | struct mt_gpdma_desc *gpd; | |
616 | struct mt_bdma_desc *bd; | |
617 | ||
618 | sg = data->sg; | |
619 | ||
620 | gpd = dma->gpd; | |
621 | bd = dma->bd; | |
622 | ||
623 | /* modify gpd */ | |
624 | gpd->gpd_info |= GPDMA_DESC_HWO; | |
625 | gpd->gpd_info |= GPDMA_DESC_BDP; | |
626 | /* need to clear first. use these bits to calc checksum */ | |
627 | gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; | |
628 | gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; | |
629 | ||
630 | /* modify bd */ | |
631 | for_each_sg(data->sg, sg, data->sg_count, j) { | |
632 | dma_address = sg_dma_address(sg); | |
633 | dma_len = sg_dma_len(sg); | |
634 | ||
635 | /* init bd */ | |
636 | bd[j].bd_info &= ~BDMA_DESC_BLKPAD; | |
637 | bd[j].bd_info &= ~BDMA_DESC_DWPAD; | |
2a9bde19 CJ |
638 | bd[j].ptr = lower_32_bits(dma_address); |
639 | if (host->dev_comp->support_64g) { | |
640 | bd[j].bd_info &= ~BDMA_DESC_PTR_H4; | |
641 | bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) | |
642 | << 28; | |
643 | } | |
20848903 CJ |
644 | bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; |
645 | bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); | |
646 | ||
647 | if (j == data->sg_count - 1) /* the last bd */ | |
648 | bd[j].bd_info |= BDMA_DESC_EOL; | |
649 | else | |
650 | bd[j].bd_info &= ~BDMA_DESC_EOL; | |
651 | ||
652 | /* checksume need to clear first */ | |
653 | bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; | |
654 | bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; | |
655 | } | |
656 | ||
657 | sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); | |
658 | dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); | |
659 | dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); | |
660 | dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); | |
661 | writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); | |
2a9bde19 CJ |
662 | if (host->dev_comp->support_64g) |
663 | sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, | |
664 | upper_32_bits(dma->gpd_addr) & 0xf); | |
665 | writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); | |
20848903 CJ |
666 | } |
667 | ||
668 | static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) | |
669 | { | |
670 | struct mmc_data *data = mrq->data; | |
671 | ||
672 | if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { | |
20848903 CJ |
673 | data->host_cookie |= MSDC_PREPARE_FLAG; |
674 | data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, | |
feeef096 | 675 | mmc_get_dma_dir(data)); |
20848903 CJ |
676 | } |
677 | } | |
678 | ||
679 | static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) | |
680 | { | |
681 | struct mmc_data *data = mrq->data; | |
682 | ||
683 | if (data->host_cookie & MSDC_ASYNC_FLAG) | |
684 | return; | |
685 | ||
686 | if (data->host_cookie & MSDC_PREPARE_FLAG) { | |
20848903 | 687 | dma_unmap_sg(host->dev, data->sg, data->sg_len, |
feeef096 | 688 | mmc_get_dma_dir(data)); |
20848903 CJ |
689 | data->host_cookie &= ~MSDC_PREPARE_FLAG; |
690 | } | |
691 | } | |
692 | ||
693 | /* clock control primitives */ | |
694 | static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) | |
695 | { | |
696 | u32 timeout, clk_ns; | |
697 | u32 mode = 0; | |
698 | ||
699 | host->timeout_ns = ns; | |
700 | host->timeout_clks = clks; | |
56f6cbbe | 701 | if (host->mmc->actual_clock == 0) { |
20848903 CJ |
702 | timeout = 0; |
703 | } else { | |
56f6cbbe | 704 | clk_ns = 1000000000UL / host->mmc->actual_clock; |
20848903 CJ |
705 | timeout = (ns + clk_ns - 1) / clk_ns + clks; |
706 | /* in 1048576 sclk cycle unit */ | |
707 | timeout = (timeout + (0x1 << 20) - 1) >> 20; | |
762d491a CJ |
708 | if (host->dev_comp->clk_div_bits == 8) |
709 | sdr_get_field(host->base + MSDC_CFG, | |
710 | MSDC_CFG_CKMOD, &mode); | |
711 | else | |
712 | sdr_get_field(host->base + MSDC_CFG, | |
713 | MSDC_CFG_CKMOD_EXTRA, &mode); | |
20848903 CJ |
714 | /*DDR mode will double the clk cycles for data timeout */ |
715 | timeout = mode >= 2 ? timeout * 2 : timeout; | |
716 | timeout = timeout > 1 ? timeout - 1 : 0; | |
717 | timeout = timeout > 255 ? 255 : timeout; | |
718 | } | |
719 | sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); | |
720 | } | |
721 | ||
722 | static void msdc_gate_clock(struct msdc_host *host) | |
723 | { | |
3c1a8844 | 724 | clk_disable_unprepare(host->src_clk_cg); |
20848903 | 725 | clk_disable_unprepare(host->src_clk); |
258bac4a | 726 | clk_disable_unprepare(host->bus_clk); |
20848903 CJ |
727 | clk_disable_unprepare(host->h_clk); |
728 | } | |
729 | ||
730 | static void msdc_ungate_clock(struct msdc_host *host) | |
731 | { | |
732 | clk_prepare_enable(host->h_clk); | |
258bac4a | 733 | clk_prepare_enable(host->bus_clk); |
20848903 | 734 | clk_prepare_enable(host->src_clk); |
3c1a8844 | 735 | clk_prepare_enable(host->src_clk_cg); |
20848903 CJ |
736 | while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) |
737 | cpu_relax(); | |
738 | } | |
739 | ||
6e622947 | 740 | static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) |
20848903 CJ |
741 | { |
742 | u32 mode; | |
743 | u32 flags; | |
744 | u32 div; | |
745 | u32 sclk; | |
39add252 | 746 | u32 tune_reg = host->dev_comp->pad_tune_reg; |
20848903 CJ |
747 | |
748 | if (!hz) { | |
749 | dev_dbg(host->dev, "set mclk to 0\n"); | |
750 | host->mclk = 0; | |
56f6cbbe | 751 | host->mmc->actual_clock = 0; |
20848903 CJ |
752 | sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); |
753 | return; | |
754 | } | |
755 | ||
756 | flags = readl(host->base + MSDC_INTEN); | |
757 | sdr_clr_bits(host->base + MSDC_INTEN, flags); | |
762d491a CJ |
758 | if (host->dev_comp->clk_div_bits == 8) |
759 | sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); | |
760 | else | |
761 | sdr_clr_bits(host->base + MSDC_CFG, | |
762 | MSDC_CFG_HS400_CK_MODE_EXTRA); | |
6e622947 | 763 | if (timing == MMC_TIMING_UHS_DDR50 || |
6397b7f5 CJ |
764 | timing == MMC_TIMING_MMC_DDR52 || |
765 | timing == MMC_TIMING_MMC_HS400) { | |
766 | if (timing == MMC_TIMING_MMC_HS400) | |
767 | mode = 0x3; | |
768 | else | |
769 | mode = 0x2; /* ddr mode and use divisor */ | |
770 | ||
20848903 CJ |
771 | if (hz >= (host->src_clk_freq >> 2)) { |
772 | div = 0; /* mean div = 1/4 */ | |
773 | sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ | |
774 | } else { | |
775 | div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); | |
776 | sclk = (host->src_clk_freq >> 2) / div; | |
777 | div = (div >> 1); | |
778 | } | |
6397b7f5 CJ |
779 | |
780 | if (timing == MMC_TIMING_MMC_HS400 && | |
781 | hz >= (host->src_clk_freq >> 1)) { | |
762d491a CJ |
782 | if (host->dev_comp->clk_div_bits == 8) |
783 | sdr_set_bits(host->base + MSDC_CFG, | |
784 | MSDC_CFG_HS400_CK_MODE); | |
785 | else | |
786 | sdr_set_bits(host->base + MSDC_CFG, | |
787 | MSDC_CFG_HS400_CK_MODE_EXTRA); | |
6397b7f5 CJ |
788 | sclk = host->src_clk_freq >> 1; |
789 | div = 0; /* div is ignore when bit18 is set */ | |
790 | } | |
20848903 CJ |
791 | } else if (hz >= host->src_clk_freq) { |
792 | mode = 0x1; /* no divisor */ | |
793 | div = 0; | |
794 | sclk = host->src_clk_freq; | |
795 | } else { | |
796 | mode = 0x0; /* use divisor */ | |
797 | if (hz >= (host->src_clk_freq >> 1)) { | |
798 | div = 0; /* mean div = 1/2 */ | |
799 | sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ | |
800 | } else { | |
801 | div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); | |
802 | sclk = (host->src_clk_freq >> 2) / div; | |
803 | } | |
804 | } | |
3c1a8844 CJ |
805 | sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); |
806 | /* | |
807 | * As src_clk/HCLK use the same bit to gate/ungate, | |
808 | * So if want to only gate src_clk, need gate its parent(mux). | |
809 | */ | |
810 | if (host->src_clk_cg) | |
811 | clk_disable_unprepare(host->src_clk_cg); | |
812 | else | |
813 | clk_disable_unprepare(clk_get_parent(host->src_clk)); | |
762d491a CJ |
814 | if (host->dev_comp->clk_div_bits == 8) |
815 | sdr_set_field(host->base + MSDC_CFG, | |
816 | MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, | |
817 | (mode << 8) | div); | |
818 | else | |
819 | sdr_set_field(host->base + MSDC_CFG, | |
820 | MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, | |
821 | (mode << 12) | div); | |
3c1a8844 CJ |
822 | if (host->src_clk_cg) |
823 | clk_prepare_enable(host->src_clk_cg); | |
824 | else | |
825 | clk_prepare_enable(clk_get_parent(host->src_clk)); | |
762d491a | 826 | |
20848903 CJ |
827 | while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) |
828 | cpu_relax(); | |
3c1a8844 | 829 | sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); |
56f6cbbe | 830 | host->mmc->actual_clock = sclk; |
20848903 | 831 | host->mclk = hz; |
6e622947 | 832 | host->timing = timing; |
20848903 CJ |
833 | /* need because clk changed. */ |
834 | msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); | |
835 | sdr_set_bits(host->base + MSDC_INTEN, flags); | |
836 | ||
86beac37 CJ |
837 | /* |
838 | * mmc_select_hs400() will drop to 50Mhz and High speed mode, | |
839 | * tune result of hs200/200Mhz is not suitable for 50Mhz | |
840 | */ | |
56f6cbbe | 841 | if (host->mmc->actual_clock <= 52000000) { |
86beac37 | 842 | writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); |
a2e6d1f6 CJ |
843 | if (host->top_base) { |
844 | writel(host->def_tune_para.emmc_top_control, | |
845 | host->top_base + EMMC_TOP_CONTROL); | |
846 | writel(host->def_tune_para.emmc_top_cmd, | |
847 | host->top_base + EMMC_TOP_CMD); | |
848 | } else { | |
849 | writel(host->def_tune_para.pad_tune, | |
850 | host->base + tune_reg); | |
851 | } | |
86beac37 CJ |
852 | } else { |
853 | writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); | |
1ede5cb8 | 854 | writel(host->saved_tune_para.pad_cmd_tune, |
855 | host->base + PAD_CMD_TUNE); | |
a2e6d1f6 CJ |
856 | if (host->top_base) { |
857 | writel(host->saved_tune_para.emmc_top_control, | |
858 | host->top_base + EMMC_TOP_CONTROL); | |
859 | writel(host->saved_tune_para.emmc_top_cmd, | |
860 | host->top_base + EMMC_TOP_CMD); | |
861 | } else { | |
862 | writel(host->saved_tune_para.pad_tune, | |
863 | host->base + tune_reg); | |
864 | } | |
86beac37 CJ |
865 | } |
866 | ||
7f3d5852 CJ |
867 | if (timing == MMC_TIMING_MMC_HS400 && |
868 | host->dev_comp->hs400_tune) | |
3751e008 | 869 | sdr_set_field(host->base + tune_reg, |
1ede5cb8 | 870 | MSDC_PAD_TUNE_CMDRRDLY, |
871 | host->hs400_cmd_int_delay); | |
56f6cbbe CJ |
872 | dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock, |
873 | timing); | |
20848903 CJ |
874 | } |
875 | ||
876 | static inline u32 msdc_cmd_find_resp(struct msdc_host *host, | |
877 | struct mmc_request *mrq, struct mmc_command *cmd) | |
878 | { | |
879 | u32 resp; | |
880 | ||
881 | switch (mmc_resp_type(cmd)) { | |
882 | /* Actually, R1, R5, R6, R7 are the same */ | |
883 | case MMC_RSP_R1: | |
884 | resp = 0x1; | |
885 | break; | |
886 | case MMC_RSP_R1B: | |
887 | resp = 0x7; | |
888 | break; | |
889 | case MMC_RSP_R2: | |
890 | resp = 0x2; | |
891 | break; | |
892 | case MMC_RSP_R3: | |
893 | resp = 0x3; | |
894 | break; | |
895 | case MMC_RSP_NONE: | |
896 | default: | |
897 | resp = 0x0; | |
898 | break; | |
899 | } | |
900 | ||
901 | return resp; | |
902 | } | |
903 | ||
904 | static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, | |
905 | struct mmc_request *mrq, struct mmc_command *cmd) | |
906 | { | |
907 | /* rawcmd : | |
908 | * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | | |
909 | * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode | |
910 | */ | |
911 | u32 opcode = cmd->opcode; | |
912 | u32 resp = msdc_cmd_find_resp(host, mrq, cmd); | |
913 | u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); | |
914 | ||
915 | host->cmd_rsp = resp; | |
916 | ||
917 | if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || | |
918 | opcode == MMC_STOP_TRANSMISSION) | |
919 | rawcmd |= (0x1 << 14); | |
920 | else if (opcode == SD_SWITCH_VOLTAGE) | |
921 | rawcmd |= (0x1 << 30); | |
922 | else if (opcode == SD_APP_SEND_SCR || | |
923 | opcode == SD_APP_SEND_NUM_WR_BLKS || | |
924 | (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || | |
925 | (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || | |
926 | (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) | |
927 | rawcmd |= (0x1 << 11); | |
928 | ||
929 | if (cmd->data) { | |
930 | struct mmc_data *data = cmd->data; | |
931 | ||
932 | if (mmc_op_multi(opcode)) { | |
933 | if (mmc_card_mmc(host->mmc->card) && mrq->sbc && | |
934 | !(mrq->sbc->arg & 0xFFFF0000)) | |
935 | rawcmd |= 0x2 << 28; /* AutoCMD23 */ | |
936 | } | |
937 | ||
938 | rawcmd |= ((data->blksz & 0xFFF) << 16); | |
939 | if (data->flags & MMC_DATA_WRITE) | |
940 | rawcmd |= (0x1 << 13); | |
941 | if (data->blocks > 1) | |
942 | rawcmd |= (0x2 << 11); | |
943 | else | |
944 | rawcmd |= (0x1 << 11); | |
945 | /* Always use dma mode */ | |
946 | sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); | |
947 | ||
948 | if (host->timeout_ns != data->timeout_ns || | |
949 | host->timeout_clks != data->timeout_clks) | |
950 | msdc_set_timeout(host, data->timeout_ns, | |
951 | data->timeout_clks); | |
952 | ||
953 | writel(data->blocks, host->base + SDC_BLK_NUM); | |
954 | } | |
955 | return rawcmd; | |
956 | } | |
957 | ||
958 | static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, | |
959 | struct mmc_command *cmd, struct mmc_data *data) | |
960 | { | |
961 | bool read; | |
962 | ||
963 | WARN_ON(host->data); | |
964 | host->data = data; | |
965 | read = data->flags & MMC_DATA_READ; | |
966 | ||
967 | mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); | |
968 | msdc_dma_setup(host, &host->dma, data); | |
969 | sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); | |
970 | sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); | |
971 | dev_dbg(host->dev, "DMA start\n"); | |
972 | dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", | |
973 | __func__, cmd->opcode, data->blocks, read); | |
974 | } | |
975 | ||
976 | static int msdc_auto_cmd_done(struct msdc_host *host, int events, | |
977 | struct mmc_command *cmd) | |
978 | { | |
979 | u32 *rsp = cmd->resp; | |
980 | ||
981 | rsp[0] = readl(host->base + SDC_ACMD_RESP); | |
982 | ||
983 | if (events & MSDC_INT_ACMDRDY) { | |
984 | cmd->error = 0; | |
985 | } else { | |
986 | msdc_reset_hw(host); | |
987 | if (events & MSDC_INT_ACMDCRCERR) { | |
988 | cmd->error = -EILSEQ; | |
989 | host->error |= REQ_STOP_EIO; | |
990 | } else if (events & MSDC_INT_ACMDTMO) { | |
991 | cmd->error = -ETIMEDOUT; | |
992 | host->error |= REQ_STOP_TMO; | |
993 | } | |
994 | dev_err(host->dev, | |
995 | "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", | |
996 | __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); | |
997 | } | |
998 | return cmd->error; | |
999 | } | |
1000 | ||
1001 | static void msdc_track_cmd_data(struct msdc_host *host, | |
1002 | struct mmc_command *cmd, struct mmc_data *data) | |
1003 | { | |
1004 | if (host->error) | |
1005 | dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", | |
1006 | __func__, cmd->opcode, cmd->arg, host->error); | |
1007 | } | |
1008 | ||
1009 | static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) | |
1010 | { | |
1011 | unsigned long flags; | |
1012 | bool ret; | |
1013 | ||
1014 | ret = cancel_delayed_work(&host->req_timeout); | |
1015 | if (!ret) { | |
1016 | /* delay work already running */ | |
1017 | return; | |
1018 | } | |
1019 | spin_lock_irqsave(&host->lock, flags); | |
1020 | host->mrq = NULL; | |
1021 | spin_unlock_irqrestore(&host->lock, flags); | |
1022 | ||
1023 | msdc_track_cmd_data(host, mrq->cmd, mrq->data); | |
1024 | if (mrq->data) | |
1025 | msdc_unprepare_data(host, mrq); | |
1026 | mmc_request_done(host->mmc, mrq); | |
1027 | } | |
1028 | ||
1029 | /* returns true if command is fully handled; returns false otherwise */ | |
1030 | static bool msdc_cmd_done(struct msdc_host *host, int events, | |
1031 | struct mmc_request *mrq, struct mmc_command *cmd) | |
1032 | { | |
1033 | bool done = false; | |
1034 | bool sbc_error; | |
1035 | unsigned long flags; | |
1036 | u32 *rsp = cmd->resp; | |
1037 | ||
1038 | if (mrq->sbc && cmd == mrq->cmd && | |
1039 | (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | |
1040 | | MSDC_INT_ACMDTMO))) | |
1041 | msdc_auto_cmd_done(host, events, mrq->sbc); | |
1042 | ||
1043 | sbc_error = mrq->sbc && mrq->sbc->error; | |
1044 | ||
1045 | if (!sbc_error && !(events & (MSDC_INT_CMDRDY | |
1046 | | MSDC_INT_RSPCRCERR | |
1047 | | MSDC_INT_CMDTMO))) | |
1048 | return done; | |
1049 | ||
1050 | spin_lock_irqsave(&host->lock, flags); | |
1051 | done = !host->cmd; | |
1052 | host->cmd = NULL; | |
1053 | spin_unlock_irqrestore(&host->lock, flags); | |
1054 | ||
1055 | if (done) | |
1056 | return true; | |
1057 | ||
726a9aac | 1058 | sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); |
20848903 CJ |
1059 | |
1060 | if (cmd->flags & MMC_RSP_PRESENT) { | |
1061 | if (cmd->flags & MMC_RSP_136) { | |
1062 | rsp[0] = readl(host->base + SDC_RESP3); | |
1063 | rsp[1] = readl(host->base + SDC_RESP2); | |
1064 | rsp[2] = readl(host->base + SDC_RESP1); | |
1065 | rsp[3] = readl(host->base + SDC_RESP0); | |
1066 | } else { | |
1067 | rsp[0] = readl(host->base + SDC_RESP0); | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { | |
ddc71387 CJ |
1072 | if (cmd->opcode != MMC_SEND_TUNING_BLOCK && |
1073 | cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) | |
1074 | /* | |
1075 | * should not clear fifo/interrupt as the tune data | |
1076 | * may have alreay come. | |
1077 | */ | |
1078 | msdc_reset_hw(host); | |
20848903 CJ |
1079 | if (events & MSDC_INT_RSPCRCERR) { |
1080 | cmd->error = -EILSEQ; | |
1081 | host->error |= REQ_CMD_EIO; | |
1082 | } else if (events & MSDC_INT_CMDTMO) { | |
1083 | cmd->error = -ETIMEDOUT; | |
1084 | host->error |= REQ_CMD_TMO; | |
1085 | } | |
1086 | } | |
1087 | if (cmd->error) | |
1088 | dev_dbg(host->dev, | |
1089 | "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", | |
1090 | __func__, cmd->opcode, cmd->arg, rsp[0], | |
1091 | cmd->error); | |
1092 | ||
1093 | msdc_cmd_next(host, mrq, cmd); | |
1094 | return true; | |
1095 | } | |
1096 | ||
1097 | /* It is the core layer's responsibility to ensure card status | |
1098 | * is correct before issue a request. but host design do below | |
1099 | * checks recommended. | |
1100 | */ | |
1101 | static inline bool msdc_cmd_is_ready(struct msdc_host *host, | |
1102 | struct mmc_request *mrq, struct mmc_command *cmd) | |
1103 | { | |
1104 | /* The max busy time we can endure is 20ms */ | |
1105 | unsigned long tmo = jiffies + msecs_to_jiffies(20); | |
1106 | ||
1107 | while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && | |
1108 | time_before(jiffies, tmo)) | |
1109 | cpu_relax(); | |
1110 | if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { | |
1111 | dev_err(host->dev, "CMD bus busy detected\n"); | |
1112 | host->error |= REQ_CMD_BUSY; | |
1113 | msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); | |
1114 | return false; | |
1115 | } | |
1116 | ||
1117 | if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { | |
1118 | tmo = jiffies + msecs_to_jiffies(20); | |
1119 | /* R1B or with data, should check SDCBUSY */ | |
1120 | while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && | |
1121 | time_before(jiffies, tmo)) | |
1122 | cpu_relax(); | |
1123 | if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { | |
1124 | dev_err(host->dev, "Controller busy detected\n"); | |
1125 | host->error |= REQ_CMD_BUSY; | |
1126 | msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); | |
1127 | return false; | |
1128 | } | |
1129 | } | |
1130 | return true; | |
1131 | } | |
1132 | ||
1133 | static void msdc_start_command(struct msdc_host *host, | |
1134 | struct mmc_request *mrq, struct mmc_command *cmd) | |
1135 | { | |
1136 | u32 rawcmd; | |
5215b2e9 | 1137 | unsigned long flags; |
20848903 CJ |
1138 | |
1139 | WARN_ON(host->cmd); | |
1140 | host->cmd = cmd; | |
1141 | ||
f38a9774 | 1142 | mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); |
20848903 CJ |
1143 | if (!msdc_cmd_is_ready(host, mrq, cmd)) |
1144 | return; | |
1145 | ||
1146 | if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || | |
1147 | readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { | |
1148 | dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); | |
1149 | msdc_reset_hw(host); | |
1150 | } | |
1151 | ||
1152 | cmd->error = 0; | |
1153 | rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); | |
20848903 | 1154 | |
5215b2e9 | 1155 | spin_lock_irqsave(&host->lock, flags); |
726a9aac | 1156 | sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); |
5215b2e9 | 1157 | spin_unlock_irqrestore(&host->lock, flags); |
1158 | ||
20848903 CJ |
1159 | writel(cmd->arg, host->base + SDC_ARG); |
1160 | writel(rawcmd, host->base + SDC_CMD); | |
1161 | } | |
1162 | ||
1163 | static void msdc_cmd_next(struct msdc_host *host, | |
1164 | struct mmc_request *mrq, struct mmc_command *cmd) | |
1165 | { | |
ddc71387 CJ |
1166 | if ((cmd->error && |
1167 | !(cmd->error == -EILSEQ && | |
1168 | (cmd->opcode == MMC_SEND_TUNING_BLOCK || | |
1169 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || | |
1170 | (mrq->sbc && mrq->sbc->error)) | |
20848903 CJ |
1171 | msdc_request_done(host, mrq); |
1172 | else if (cmd == mrq->sbc) | |
1173 | msdc_start_command(host, mrq, mrq->cmd); | |
1174 | else if (!cmd->data) | |
1175 | msdc_request_done(host, mrq); | |
1176 | else | |
1177 | msdc_start_data(host, mrq, cmd, cmd->data); | |
1178 | } | |
1179 | ||
1180 | static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1181 | { | |
1182 | struct msdc_host *host = mmc_priv(mmc); | |
1183 | ||
1184 | host->error = 0; | |
1185 | WARN_ON(host->mrq); | |
1186 | host->mrq = mrq; | |
1187 | ||
1188 | if (mrq->data) | |
1189 | msdc_prepare_data(host, mrq); | |
1190 | ||
1191 | /* if SBC is required, we have HW option and SW option. | |
1192 | * if HW option is enabled, and SBC does not have "special" flags, | |
1193 | * use HW option, otherwise use SW option | |
1194 | */ | |
1195 | if (mrq->sbc && (!mmc_card_mmc(mmc->card) || | |
1196 | (mrq->sbc->arg & 0xFFFF0000))) | |
1197 | msdc_start_command(host, mrq, mrq->sbc); | |
1198 | else | |
1199 | msdc_start_command(host, mrq, mrq->cmd); | |
1200 | } | |
1201 | ||
d3c6aac3 | 1202 | static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) |
20848903 CJ |
1203 | { |
1204 | struct msdc_host *host = mmc_priv(mmc); | |
1205 | struct mmc_data *data = mrq->data; | |
1206 | ||
1207 | if (!data) | |
1208 | return; | |
1209 | ||
1210 | msdc_prepare_data(host, mrq); | |
1211 | data->host_cookie |= MSDC_ASYNC_FLAG; | |
1212 | } | |
1213 | ||
1214 | static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
1215 | int err) | |
1216 | { | |
1217 | struct msdc_host *host = mmc_priv(mmc); | |
1218 | struct mmc_data *data; | |
1219 | ||
1220 | data = mrq->data; | |
1221 | if (!data) | |
1222 | return; | |
1223 | if (data->host_cookie) { | |
1224 | data->host_cookie &= ~MSDC_ASYNC_FLAG; | |
1225 | msdc_unprepare_data(host, mrq); | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | static void msdc_data_xfer_next(struct msdc_host *host, | |
1230 | struct mmc_request *mrq, struct mmc_data *data) | |
1231 | { | |
1232 | if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && | |
6397b7f5 | 1233 | !mrq->sbc) |
20848903 CJ |
1234 | msdc_start_command(host, mrq, mrq->stop); |
1235 | else | |
1236 | msdc_request_done(host, mrq); | |
1237 | } | |
1238 | ||
1239 | static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, | |
1240 | struct mmc_request *mrq, struct mmc_data *data) | |
1241 | { | |
1242 | struct mmc_command *stop = data->stop; | |
1243 | unsigned long flags; | |
1244 | bool done; | |
1245 | unsigned int check_data = events & | |
1246 | (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO | |
1247 | | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR | |
1248 | | MSDC_INT_DMA_PROTECT); | |
1249 | ||
1250 | spin_lock_irqsave(&host->lock, flags); | |
1251 | done = !host->data; | |
1252 | if (check_data) | |
1253 | host->data = NULL; | |
1254 | spin_unlock_irqrestore(&host->lock, flags); | |
1255 | ||
1256 | if (done) | |
1257 | return true; | |
1258 | ||
1259 | if (check_data || (stop && stop->error)) { | |
1260 | dev_dbg(host->dev, "DMA status: 0x%8X\n", | |
1261 | readl(host->base + MSDC_DMA_CFG)); | |
1262 | sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, | |
1263 | 1); | |
1264 | while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) | |
1265 | cpu_relax(); | |
1266 | sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); | |
1267 | dev_dbg(host->dev, "DMA stop\n"); | |
1268 | ||
1269 | if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { | |
1270 | data->bytes_xfered = data->blocks * data->blksz; | |
1271 | } else { | |
2066fd28 | 1272 | dev_dbg(host->dev, "interrupt events: %x\n", events); |
20848903 CJ |
1273 | msdc_reset_hw(host); |
1274 | host->error |= REQ_DAT_ERR; | |
1275 | data->bytes_xfered = 0; | |
1276 | ||
1277 | if (events & MSDC_INT_DATTMO) | |
1278 | data->error = -ETIMEDOUT; | |
6397b7f5 CJ |
1279 | else if (events & MSDC_INT_DATCRCERR) |
1280 | data->error = -EILSEQ; | |
20848903 | 1281 | |
2066fd28 | 1282 | dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", |
20848903 | 1283 | __func__, mrq->cmd->opcode, data->blocks); |
2066fd28 CJ |
1284 | dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", |
1285 | (int)data->error, data->bytes_xfered); | |
20848903 CJ |
1286 | } |
1287 | ||
1288 | msdc_data_xfer_next(host, mrq, data); | |
1289 | done = true; | |
1290 | } | |
1291 | return done; | |
1292 | } | |
1293 | ||
1294 | static void msdc_set_buswidth(struct msdc_host *host, u32 width) | |
1295 | { | |
1296 | u32 val = readl(host->base + SDC_CFG); | |
1297 | ||
1298 | val &= ~SDC_CFG_BUSWIDTH; | |
1299 | ||
1300 | switch (width) { | |
1301 | default: | |
1302 | case MMC_BUS_WIDTH_1: | |
1303 | val |= (MSDC_BUS_1BITS << 16); | |
1304 | break; | |
1305 | case MMC_BUS_WIDTH_4: | |
1306 | val |= (MSDC_BUS_4BITS << 16); | |
1307 | break; | |
1308 | case MMC_BUS_WIDTH_8: | |
1309 | val |= (MSDC_BUS_8BITS << 16); | |
1310 | break; | |
1311 | } | |
1312 | ||
1313 | writel(val, host->base + SDC_CFG); | |
1314 | dev_dbg(host->dev, "Bus Width = %d", width); | |
1315 | } | |
1316 | ||
1317 | static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) | |
1318 | { | |
1319 | struct msdc_host *host = mmc_priv(mmc); | |
20848903 CJ |
1320 | int ret = 0; |
1321 | ||
1322 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
fac49ce5 NB |
1323 | if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && |
1324 | ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { | |
20848903 CJ |
1325 | dev_err(host->dev, "Unsupported signal voltage!\n"); |
1326 | return -EINVAL; | |
1327 | } | |
1328 | ||
fac49ce5 | 1329 | ret = mmc_regulator_set_vqmmc(mmc, ios); |
20848903 | 1330 | if (ret) { |
fac49ce5 NB |
1331 | dev_dbg(host->dev, "Regulator set error %d (%d)\n", |
1332 | ret, ios->signal_voltage); | |
20848903 CJ |
1333 | } else { |
1334 | /* Apply different pinctrl settings for different signal voltage */ | |
1335 | if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) | |
1336 | pinctrl_select_state(host->pinctrl, host->pins_uhs); | |
1337 | else | |
1338 | pinctrl_select_state(host->pinctrl, host->pins_default); | |
1339 | } | |
1340 | } | |
1341 | return ret; | |
1342 | } | |
1343 | ||
1344 | static int msdc_card_busy(struct mmc_host *mmc) | |
1345 | { | |
1346 | struct msdc_host *host = mmc_priv(mmc); | |
1347 | u32 status = readl(host->base + MSDC_PS); | |
1348 | ||
3bc702ed | 1349 | /* only check if data0 is low */ |
1350 | return !(status & BIT(16)); | |
20848903 CJ |
1351 | } |
1352 | ||
1353 | static void msdc_request_timeout(struct work_struct *work) | |
1354 | { | |
1355 | struct msdc_host *host = container_of(work, struct msdc_host, | |
1356 | req_timeout.work); | |
1357 | ||
1358 | /* simulate HW timeout status */ | |
1359 | dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); | |
1360 | if (host->mrq) { | |
1361 | dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, | |
1362 | host->mrq, host->mrq->cmd->opcode); | |
1363 | if (host->cmd) { | |
1364 | dev_err(host->dev, "%s: aborting cmd=%d\n", | |
1365 | __func__, host->cmd->opcode); | |
1366 | msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, | |
1367 | host->cmd); | |
1368 | } else if (host->data) { | |
1369 | dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", | |
1370 | __func__, host->mrq->cmd->opcode, | |
1371 | host->data->blocks); | |
1372 | msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, | |
1373 | host->data); | |
1374 | } | |
1375 | } | |
1376 | } | |
1377 | ||
5215b2e9 | 1378 | static void __msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) |
1379 | { | |
1380 | unsigned long flags; | |
1381 | struct msdc_host *host = mmc_priv(mmc); | |
1382 | ||
1383 | spin_lock_irqsave(&host->lock, flags); | |
1384 | if (enb) | |
1385 | sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); | |
1386 | else | |
1387 | sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); | |
1388 | spin_unlock_irqrestore(&host->lock, flags); | |
1389 | } | |
1390 | ||
1391 | static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) | |
1392 | { | |
1393 | struct msdc_host *host = mmc_priv(mmc); | |
1394 | ||
1395 | __msdc_enable_sdio_irq(mmc, enb); | |
1396 | ||
1397 | if (enb) | |
1398 | pm_runtime_get_noresume(host->dev); | |
1399 | else | |
1400 | pm_runtime_put_noidle(host->dev); | |
1401 | } | |
1402 | ||
20848903 CJ |
1403 | static irqreturn_t msdc_irq(int irq, void *dev_id) |
1404 | { | |
1405 | struct msdc_host *host = (struct msdc_host *) dev_id; | |
1406 | ||
1407 | while (true) { | |
1408 | unsigned long flags; | |
1409 | struct mmc_request *mrq; | |
1410 | struct mmc_command *cmd; | |
1411 | struct mmc_data *data; | |
1412 | u32 events, event_mask; | |
1413 | ||
1414 | spin_lock_irqsave(&host->lock, flags); | |
1415 | events = readl(host->base + MSDC_INT); | |
1416 | event_mask = readl(host->base + MSDC_INTEN); | |
1417 | /* clear interrupts */ | |
1418 | writel(events & event_mask, host->base + MSDC_INT); | |
1419 | ||
1420 | mrq = host->mrq; | |
1421 | cmd = host->cmd; | |
1422 | data = host->data; | |
1423 | spin_unlock_irqrestore(&host->lock, flags); | |
1424 | ||
5215b2e9 | 1425 | if ((events & event_mask) & MSDC_INT_SDIOIRQ) { |
1426 | __msdc_enable_sdio_irq(host->mmc, 0); | |
1427 | sdio_signal_irq(host->mmc); | |
1428 | } | |
1429 | ||
d087bde5 N |
1430 | if ((events & event_mask) & MSDC_INT_CDSC) { |
1431 | if (host->internal_cd) | |
1432 | mmc_detect_change(host->mmc, msecs_to_jiffies(20)); | |
1433 | events &= ~MSDC_INT_CDSC; | |
1434 | } | |
1435 | ||
5215b2e9 | 1436 | if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) |
20848903 CJ |
1437 | break; |
1438 | ||
1439 | if (!mrq) { | |
1440 | dev_err(host->dev, | |
1441 | "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", | |
1442 | __func__, events, event_mask); | |
1443 | WARN_ON(1); | |
1444 | break; | |
1445 | } | |
1446 | ||
1447 | dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); | |
1448 | ||
1449 | if (cmd) | |
1450 | msdc_cmd_done(host, events, mrq, cmd); | |
1451 | else if (data) | |
1452 | msdc_data_xfer_done(host, events, mrq, data); | |
1453 | } | |
1454 | ||
1455 | return IRQ_HANDLED; | |
1456 | } | |
1457 | ||
1458 | static void msdc_init_hw(struct msdc_host *host) | |
1459 | { | |
1460 | u32 val; | |
39add252 | 1461 | u32 tune_reg = host->dev_comp->pad_tune_reg; |
20848903 CJ |
1462 | |
1463 | /* Configure to MMC/SD mode, clock free running */ | |
1464 | sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); | |
1465 | ||
1466 | /* Reset */ | |
1467 | msdc_reset_hw(host); | |
1468 | ||
20848903 CJ |
1469 | /* Disable and clear all interrupts */ |
1470 | writel(0, host->base + MSDC_INTEN); | |
1471 | val = readl(host->base + MSDC_INT); | |
1472 | writel(val, host->base + MSDC_INT); | |
1473 | ||
d087bde5 N |
1474 | /* Configure card detection */ |
1475 | if (host->internal_cd) { | |
1476 | sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, | |
1477 | DEFAULT_DEBOUNCE); | |
1478 | sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); | |
1479 | sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); | |
1480 | sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); | |
1481 | } else { | |
1482 | sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); | |
1483 | sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); | |
1484 | sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); | |
1485 | } | |
1486 | ||
a2e6d1f6 CJ |
1487 | if (host->top_base) { |
1488 | writel(0, host->top_base + EMMC_TOP_CONTROL); | |
1489 | writel(0, host->top_base + EMMC_TOP_CMD); | |
1490 | } else { | |
1491 | writel(0, host->base + tune_reg); | |
1492 | } | |
20848903 | 1493 | writel(0, host->base + MSDC_IOCON); |
6397b7f5 CJ |
1494 | sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); |
1495 | writel(0x403c0046, host->base + MSDC_PATCH_BIT); | |
20848903 | 1496 | sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); |
2fea5819 | 1497 | writel(0xffff4089, host->base + MSDC_PATCH_BIT1); |
6397b7f5 | 1498 | sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); |
d9dcbfc8 CJ |
1499 | |
1500 | if (host->dev_comp->stop_clk_fix) { | |
1501 | sdr_set_field(host->base + MSDC_PATCH_BIT1, | |
1502 | MSDC_PATCH_BIT1_STOP_DLY, 3); | |
1503 | sdr_clr_bits(host->base + SDC_FIFO_CFG, | |
1504 | SDC_FIFO_CFG_WRVALIDSEL); | |
1505 | sdr_clr_bits(host->base + SDC_FIFO_CFG, | |
1506 | SDC_FIFO_CFG_RDVALIDSEL); | |
1507 | } | |
1508 | ||
acde28c4 CJ |
1509 | if (host->dev_comp->busy_check) |
1510 | sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); | |
d9dcbfc8 | 1511 | |
2fea5819 CJ |
1512 | if (host->dev_comp->async_fifo) { |
1513 | sdr_set_field(host->base + MSDC_PATCH_BIT2, | |
1514 | MSDC_PB2_RESPWAIT, 3); | |
d9dcbfc8 | 1515 | if (host->dev_comp->enhance_rx) { |
a2e6d1f6 CJ |
1516 | if (host->top_base) |
1517 | sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, | |
1518 | SDC_RX_ENH_EN); | |
1519 | else | |
1520 | sdr_set_bits(host->base + SDC_ADV_CFG0, | |
1521 | SDC_RX_ENHANCE_EN); | |
d9dcbfc8 CJ |
1522 | } else { |
1523 | sdr_set_field(host->base + MSDC_PATCH_BIT2, | |
1524 | MSDC_PB2_RESPSTSENSEL, 2); | |
1525 | sdr_set_field(host->base + MSDC_PATCH_BIT2, | |
1526 | MSDC_PB2_CRCSTSENSEL, 2); | |
1527 | } | |
2fea5819 CJ |
1528 | /* use async fifo, then no need tune internal delay */ |
1529 | sdr_clr_bits(host->base + MSDC_PATCH_BIT2, | |
1530 | MSDC_PATCH_BIT2_CFGRESP); | |
1531 | sdr_set_bits(host->base + MSDC_PATCH_BIT2, | |
1532 | MSDC_PATCH_BIT2_CFGCRCSTS); | |
1533 | } | |
1534 | ||
2a9bde19 CJ |
1535 | if (host->dev_comp->support_64g) |
1536 | sdr_set_bits(host->base + MSDC_PATCH_BIT2, | |
1537 | MSDC_PB2_SUPPORT_64G); | |
2fea5819 | 1538 | if (host->dev_comp->data_tune) { |
a2e6d1f6 CJ |
1539 | if (host->top_base) { |
1540 | sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, | |
1541 | PAD_DAT_RD_RXDLY_SEL); | |
1542 | sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, | |
1543 | DATA_K_VALUE_SEL); | |
1544 | sdr_set_bits(host->top_base + EMMC_TOP_CMD, | |
1545 | PAD_CMD_RD_RXDLY_SEL); | |
1546 | } else { | |
1547 | sdr_set_bits(host->base + tune_reg, | |
1548 | MSDC_PAD_TUNE_RD_SEL | | |
1549 | MSDC_PAD_TUNE_CMD_SEL); | |
1550 | } | |
2fea5819 CJ |
1551 | } else { |
1552 | /* choose clock tune */ | |
a2e6d1f6 CJ |
1553 | if (host->top_base) |
1554 | sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, | |
1555 | PAD_RXDLY_SEL); | |
1556 | else | |
1557 | sdr_set_bits(host->base + tune_reg, | |
1558 | MSDC_PAD_TUNE_RXDLYSEL); | |
2fea5819 | 1559 | } |
6397b7f5 | 1560 | |
20848903 CJ |
1561 | /* Configure to enable SDIO mode. |
1562 | * it's must otherwise sdio cmd5 failed | |
1563 | */ | |
1564 | sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); | |
1565 | ||
5215b2e9 | 1566 | /* Config SDIO device detect interrupt function */ |
1567 | if (host->mmc->caps & MMC_CAP_SDIO_IRQ) | |
1568 | sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); | |
1569 | else | |
1570 | sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); | |
20848903 CJ |
1571 | |
1572 | /* Configure to default data timeout */ | |
1573 | sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); | |
1574 | ||
86beac37 | 1575 | host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); |
2fea5819 | 1576 | host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); |
a2e6d1f6 CJ |
1577 | if (host->top_base) { |
1578 | host->def_tune_para.emmc_top_control = | |
1579 | readl(host->top_base + EMMC_TOP_CONTROL); | |
1580 | host->def_tune_para.emmc_top_cmd = | |
1581 | readl(host->top_base + EMMC_TOP_CMD); | |
1582 | host->saved_tune_para.emmc_top_control = | |
1583 | readl(host->top_base + EMMC_TOP_CONTROL); | |
1584 | host->saved_tune_para.emmc_top_cmd = | |
1585 | readl(host->top_base + EMMC_TOP_CMD); | |
1586 | } else { | |
1587 | host->def_tune_para.pad_tune = readl(host->base + tune_reg); | |
1588 | host->saved_tune_para.pad_tune = readl(host->base + tune_reg); | |
1589 | } | |
20848903 CJ |
1590 | dev_dbg(host->dev, "init hardware done!"); |
1591 | } | |
1592 | ||
1593 | static void msdc_deinit_hw(struct msdc_host *host) | |
1594 | { | |
1595 | u32 val; | |
d087bde5 N |
1596 | |
1597 | if (host->internal_cd) { | |
1598 | /* Disabled card-detect */ | |
1599 | sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); | |
1600 | sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); | |
1601 | } | |
1602 | ||
20848903 CJ |
1603 | /* Disable and clear all interrupts */ |
1604 | writel(0, host->base + MSDC_INTEN); | |
1605 | ||
1606 | val = readl(host->base + MSDC_INT); | |
1607 | writel(val, host->base + MSDC_INT); | |
1608 | } | |
1609 | ||
1610 | /* init gpd and bd list in msdc_drv_probe */ | |
1611 | static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) | |
1612 | { | |
1613 | struct mt_gpdma_desc *gpd = dma->gpd; | |
1614 | struct mt_bdma_desc *bd = dma->bd; | |
2a9bde19 | 1615 | dma_addr_t dma_addr; |
20848903 CJ |
1616 | int i; |
1617 | ||
62b0d27a | 1618 | memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); |
20848903 | 1619 | |
2a9bde19 | 1620 | dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); |
20848903 | 1621 | gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ |
62b0d27a CJ |
1622 | /* gpd->next is must set for desc DMA |
1623 | * That's why must alloc 2 gpd structure. | |
1624 | */ | |
2a9bde19 CJ |
1625 | gpd->next = lower_32_bits(dma_addr); |
1626 | if (host->dev_comp->support_64g) | |
1627 | gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; | |
1628 | ||
1629 | dma_addr = dma->bd_addr; | |
1630 | gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ | |
1631 | if (host->dev_comp->support_64g) | |
1632 | gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; | |
1633 | ||
20848903 | 1634 | memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); |
2a9bde19 CJ |
1635 | for (i = 0; i < (MAX_BD_NUM - 1); i++) { |
1636 | dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); | |
1637 | bd[i].next = lower_32_bits(dma_addr); | |
1638 | if (host->dev_comp->support_64g) | |
1639 | bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; | |
1640 | } | |
20848903 CJ |
1641 | } |
1642 | ||
1643 | static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1644 | { | |
1645 | struct msdc_host *host = mmc_priv(mmc); | |
1646 | int ret; | |
20848903 | 1647 | |
20848903 CJ |
1648 | msdc_set_buswidth(host, ios->bus_width); |
1649 | ||
1650 | /* Suspend/Resume will do power off/on */ | |
1651 | switch (ios->power_mode) { | |
1652 | case MMC_POWER_UP: | |
1653 | if (!IS_ERR(mmc->supply.vmmc)) { | |
6397b7f5 | 1654 | msdc_init_hw(host); |
20848903 CJ |
1655 | ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, |
1656 | ios->vdd); | |
1657 | if (ret) { | |
1658 | dev_err(host->dev, "Failed to set vmmc power!\n"); | |
567979fb | 1659 | return; |
20848903 CJ |
1660 | } |
1661 | } | |
1662 | break; | |
1663 | case MMC_POWER_ON: | |
1664 | if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { | |
1665 | ret = regulator_enable(mmc->supply.vqmmc); | |
1666 | if (ret) | |
1667 | dev_err(host->dev, "Failed to set vqmmc power!\n"); | |
1668 | else | |
1669 | host->vqmmc_enabled = true; | |
1670 | } | |
1671 | break; | |
1672 | case MMC_POWER_OFF: | |
1673 | if (!IS_ERR(mmc->supply.vmmc)) | |
1674 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
1675 | ||
1676 | if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { | |
1677 | regulator_disable(mmc->supply.vqmmc); | |
1678 | host->vqmmc_enabled = false; | |
1679 | } | |
1680 | break; | |
1681 | default: | |
1682 | break; | |
1683 | } | |
1684 | ||
6e622947 CJ |
1685 | if (host->mclk != ios->clock || host->timing != ios->timing) |
1686 | msdc_set_mclk(host, ios->timing, ios->clock); | |
20848903 CJ |
1687 | } |
1688 | ||
6397b7f5 CJ |
1689 | static u32 test_delay_bit(u32 delay, u32 bit) |
1690 | { | |
1691 | bit %= PAD_DELAY_MAX; | |
1692 | return delay & (1 << bit); | |
1693 | } | |
1694 | ||
1695 | static int get_delay_len(u32 delay, u32 start_bit) | |
1696 | { | |
1697 | int i; | |
1698 | ||
1699 | for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { | |
1700 | if (test_delay_bit(delay, start_bit + i) == 0) | |
1701 | return i; | |
1702 | } | |
1703 | return PAD_DELAY_MAX - start_bit; | |
1704 | } | |
1705 | ||
1706 | static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) | |
1707 | { | |
1708 | int start = 0, len = 0; | |
1709 | int start_final = 0, len_final = 0; | |
1710 | u8 final_phase = 0xff; | |
62d494ca | 1711 | struct msdc_delay_phase delay_phase = { 0, }; |
6397b7f5 CJ |
1712 | |
1713 | if (delay == 0) { | |
1714 | dev_err(host->dev, "phase error: [map:%x]\n", delay); | |
1715 | delay_phase.final_phase = final_phase; | |
1716 | return delay_phase; | |
1717 | } | |
1718 | ||
1719 | while (start < PAD_DELAY_MAX) { | |
1720 | len = get_delay_len(delay, start); | |
1721 | if (len_final < len) { | |
1722 | start_final = start; | |
1723 | len_final = len; | |
1724 | } | |
1725 | start += len ? len : 1; | |
1ede5cb8 | 1726 | if (len >= 12 && start_final < 4) |
6397b7f5 CJ |
1727 | break; |
1728 | } | |
1729 | ||
1730 | /* The rule is that to find the smallest delay cell */ | |
1731 | if (start_final == 0) | |
1732 | final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; | |
1733 | else | |
1734 | final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; | |
1735 | dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", | |
1736 | delay, len_final, final_phase); | |
1737 | ||
1738 | delay_phase.maxlen = len_final; | |
1739 | delay_phase.start = start_final; | |
1740 | delay_phase.final_phase = final_phase; | |
1741 | return delay_phase; | |
1742 | } | |
1743 | ||
fd82cc30 CJ |
1744 | static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) |
1745 | { | |
1746 | u32 tune_reg = host->dev_comp->pad_tune_reg; | |
1747 | ||
1748 | if (host->top_base) | |
1749 | sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, | |
1750 | value); | |
1751 | else | |
1752 | sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, | |
1753 | value); | |
1754 | } | |
1755 | ||
1756 | static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) | |
1757 | { | |
1758 | u32 tune_reg = host->dev_comp->pad_tune_reg; | |
1759 | ||
1760 | if (host->top_base) | |
1761 | sdr_set_field(host->top_base + EMMC_TOP_CONTROL, | |
1762 | PAD_DAT_RD_RXDLY, value); | |
1763 | else | |
1764 | sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, | |
1765 | value); | |
1766 | } | |
1767 | ||
6397b7f5 CJ |
1768 | static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) |
1769 | { | |
1770 | struct msdc_host *host = mmc_priv(mmc); | |
1771 | u32 rise_delay = 0, fall_delay = 0; | |
ae9c657e | 1772 | struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; |
1ede5cb8 | 1773 | struct msdc_delay_phase internal_delay_phase; |
6397b7f5 | 1774 | u8 final_delay, final_maxlen; |
1ede5cb8 | 1775 | u32 internal_delay = 0; |
39add252 | 1776 | u32 tune_reg = host->dev_comp->pad_tune_reg; |
6397b7f5 | 1777 | int cmd_err; |
1ede5cb8 | 1778 | int i, j; |
1779 | ||
1780 | if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || | |
1781 | mmc->ios.timing == MMC_TIMING_UHS_SDR104) | |
39add252 | 1782 | sdr_set_field(host->base + tune_reg, |
1ede5cb8 | 1783 | MSDC_PAD_TUNE_CMDRRDLY, |
1784 | host->hs200_cmd_int_delay); | |
6397b7f5 CJ |
1785 | |
1786 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1787 | for (i = 0 ; i < PAD_DELAY_MAX; i++) { | |
fd82cc30 | 1788 | msdc_set_cmd_delay(host, i); |
1ede5cb8 | 1789 | /* |
1790 | * Using the same parameters, it may sometimes pass the test, | |
1791 | * but sometimes it may fail. To make sure the parameters are | |
1792 | * more stable, we test each set of parameters 3 times. | |
1793 | */ | |
1794 | for (j = 0; j < 3; j++) { | |
1795 | mmc_send_tuning(mmc, opcode, &cmd_err); | |
1796 | if (!cmd_err) { | |
1797 | rise_delay |= (1 << i); | |
1798 | } else { | |
1799 | rise_delay &= ~(1 << i); | |
1800 | break; | |
1801 | } | |
1802 | } | |
6397b7f5 | 1803 | } |
ae9c657e CJ |
1804 | final_rise_delay = get_best_delay(host, rise_delay); |
1805 | /* if rising edge has enough margin, then do not scan falling edge */ | |
6b10c9ab CJ |
1806 | if (final_rise_delay.maxlen >= 12 || |
1807 | (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) | |
ae9c657e | 1808 | goto skip_fall; |
6397b7f5 CJ |
1809 | |
1810 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1811 | for (i = 0; i < PAD_DELAY_MAX; i++) { | |
fd82cc30 | 1812 | msdc_set_cmd_delay(host, i); |
1ede5cb8 | 1813 | /* |
1814 | * Using the same parameters, it may sometimes pass the test, | |
1815 | * but sometimes it may fail. To make sure the parameters are | |
1816 | * more stable, we test each set of parameters 3 times. | |
1817 | */ | |
1818 | for (j = 0; j < 3; j++) { | |
1819 | mmc_send_tuning(mmc, opcode, &cmd_err); | |
1820 | if (!cmd_err) { | |
1821 | fall_delay |= (1 << i); | |
1822 | } else { | |
1823 | fall_delay &= ~(1 << i); | |
1824 | break; | |
1825 | } | |
1826 | } | |
6397b7f5 | 1827 | } |
6397b7f5 CJ |
1828 | final_fall_delay = get_best_delay(host, fall_delay); |
1829 | ||
ae9c657e | 1830 | skip_fall: |
6397b7f5 | 1831 | final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); |
1ede5cb8 | 1832 | if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) |
1833 | final_maxlen = final_fall_delay.maxlen; | |
6397b7f5 CJ |
1834 | if (final_maxlen == final_rise_delay.maxlen) { |
1835 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
6397b7f5 CJ |
1836 | final_delay = final_rise_delay.final_phase; |
1837 | } else { | |
1838 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
6397b7f5 CJ |
1839 | final_delay = final_fall_delay.final_phase; |
1840 | } | |
fd82cc30 CJ |
1841 | msdc_set_cmd_delay(host, final_delay); |
1842 | ||
2fea5819 | 1843 | if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) |
1ede5cb8 | 1844 | goto skip_internal; |
1845 | ||
1846 | for (i = 0; i < PAD_DELAY_MAX; i++) { | |
39add252 | 1847 | sdr_set_field(host->base + tune_reg, |
1ede5cb8 | 1848 | MSDC_PAD_TUNE_CMDRRDLY, i); |
1849 | mmc_send_tuning(mmc, opcode, &cmd_err); | |
1850 | if (!cmd_err) | |
1851 | internal_delay |= (1 << i); | |
1852 | } | |
1853 | dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); | |
1854 | internal_delay_phase = get_best_delay(host, internal_delay); | |
39add252 | 1855 | sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, |
1ede5cb8 | 1856 | internal_delay_phase.final_phase); |
1857 | skip_internal: | |
1858 | dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); | |
1859 | return final_delay == 0xff ? -EIO : 0; | |
1860 | } | |
1861 | ||
1862 | static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) | |
1863 | { | |
1864 | struct msdc_host *host = mmc_priv(mmc); | |
1865 | u32 cmd_delay = 0; | |
1866 | struct msdc_delay_phase final_cmd_delay = { 0,}; | |
1867 | u8 final_delay; | |
1868 | int cmd_err; | |
1869 | int i, j; | |
1870 | ||
1871 | /* select EMMC50 PAD CMD tune */ | |
1872 | sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); | |
1873 | ||
1874 | if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || | |
1875 | mmc->ios.timing == MMC_TIMING_UHS_SDR104) | |
1876 | sdr_set_field(host->base + MSDC_PAD_TUNE, | |
1877 | MSDC_PAD_TUNE_CMDRRDLY, | |
1878 | host->hs200_cmd_int_delay); | |
1879 | ||
1880 | if (host->hs400_cmd_resp_sel_rising) | |
1881 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1882 | else | |
1883 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1884 | for (i = 0 ; i < PAD_DELAY_MAX; i++) { | |
1885 | sdr_set_field(host->base + PAD_CMD_TUNE, | |
1886 | PAD_CMD_TUNE_RX_DLY3, i); | |
1887 | /* | |
1888 | * Using the same parameters, it may sometimes pass the test, | |
1889 | * but sometimes it may fail. To make sure the parameters are | |
1890 | * more stable, we test each set of parameters 3 times. | |
1891 | */ | |
1892 | for (j = 0; j < 3; j++) { | |
1893 | mmc_send_tuning(mmc, opcode, &cmd_err); | |
1894 | if (!cmd_err) { | |
1895 | cmd_delay |= (1 << i); | |
1896 | } else { | |
1897 | cmd_delay &= ~(1 << i); | |
1898 | break; | |
1899 | } | |
1900 | } | |
1901 | } | |
1902 | final_cmd_delay = get_best_delay(host, cmd_delay); | |
1903 | sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, | |
1904 | final_cmd_delay.final_phase); | |
1905 | final_delay = final_cmd_delay.final_phase; | |
6397b7f5 | 1906 | |
1ede5cb8 | 1907 | dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); |
6397b7f5 CJ |
1908 | return final_delay == 0xff ? -EIO : 0; |
1909 | } | |
1910 | ||
1911 | static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) | |
1912 | { | |
1913 | struct msdc_host *host = mmc_priv(mmc); | |
1914 | u32 rise_delay = 0, fall_delay = 0; | |
ae9c657e | 1915 | struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; |
6397b7f5 CJ |
1916 | u8 final_delay, final_maxlen; |
1917 | int i, ret; | |
1918 | ||
d17bb71c CJ |
1919 | sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, |
1920 | host->latch_ck); | |
6397b7f5 CJ |
1921 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); |
1922 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); | |
1923 | for (i = 0 ; i < PAD_DELAY_MAX; i++) { | |
fd82cc30 | 1924 | msdc_set_data_delay(host, i); |
6397b7f5 CJ |
1925 | ret = mmc_send_tuning(mmc, opcode, NULL); |
1926 | if (!ret) | |
1927 | rise_delay |= (1 << i); | |
1928 | } | |
ae9c657e CJ |
1929 | final_rise_delay = get_best_delay(host, rise_delay); |
1930 | /* if rising edge has enough margin, then do not scan falling edge */ | |
1ede5cb8 | 1931 | if (final_rise_delay.maxlen >= 12 || |
ae9c657e CJ |
1932 | (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) |
1933 | goto skip_fall; | |
6397b7f5 CJ |
1934 | |
1935 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); | |
1936 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); | |
1937 | for (i = 0; i < PAD_DELAY_MAX; i++) { | |
fd82cc30 | 1938 | msdc_set_data_delay(host, i); |
6397b7f5 CJ |
1939 | ret = mmc_send_tuning(mmc, opcode, NULL); |
1940 | if (!ret) | |
1941 | fall_delay |= (1 << i); | |
1942 | } | |
6397b7f5 CJ |
1943 | final_fall_delay = get_best_delay(host, fall_delay); |
1944 | ||
ae9c657e | 1945 | skip_fall: |
6397b7f5 | 1946 | final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); |
6397b7f5 CJ |
1947 | if (final_maxlen == final_rise_delay.maxlen) { |
1948 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); | |
1949 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); | |
6397b7f5 CJ |
1950 | final_delay = final_rise_delay.final_phase; |
1951 | } else { | |
1952 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); | |
1953 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); | |
6397b7f5 CJ |
1954 | final_delay = final_fall_delay.final_phase; |
1955 | } | |
fd82cc30 | 1956 | msdc_set_data_delay(host, final_delay); |
6397b7f5 | 1957 | |
1ede5cb8 | 1958 | dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); |
6397b7f5 CJ |
1959 | return final_delay == 0xff ? -EIO : 0; |
1960 | } | |
1961 | ||
86601d0e CJ |
1962 | /* |
1963 | * MSDC IP which supports data tune + async fifo can do CMD/DAT tune | |
1964 | * together, which can save the tuning time. | |
1965 | */ | |
1966 | static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) | |
1967 | { | |
1968 | struct msdc_host *host = mmc_priv(mmc); | |
1969 | u32 rise_delay = 0, fall_delay = 0; | |
1970 | struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; | |
1971 | u8 final_delay, final_maxlen; | |
86601d0e CJ |
1972 | int i, ret; |
1973 | ||
1974 | sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, | |
1975 | host->latch_ck); | |
1976 | ||
1977 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1978 | sdr_clr_bits(host->base + MSDC_IOCON, | |
1979 | MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); | |
1980 | for (i = 0 ; i < PAD_DELAY_MAX; i++) { | |
fd82cc30 CJ |
1981 | msdc_set_cmd_delay(host, i); |
1982 | msdc_set_data_delay(host, i); | |
86601d0e CJ |
1983 | ret = mmc_send_tuning(mmc, opcode, NULL); |
1984 | if (!ret) | |
1985 | rise_delay |= (1 << i); | |
1986 | } | |
1987 | final_rise_delay = get_best_delay(host, rise_delay); | |
1988 | /* if rising edge has enough margin, then do not scan falling edge */ | |
1989 | if (final_rise_delay.maxlen >= 12 || | |
1990 | (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) | |
1991 | goto skip_fall; | |
1992 | ||
1993 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1994 | sdr_set_bits(host->base + MSDC_IOCON, | |
1995 | MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); | |
1996 | for (i = 0; i < PAD_DELAY_MAX; i++) { | |
fd82cc30 CJ |
1997 | msdc_set_cmd_delay(host, i); |
1998 | msdc_set_data_delay(host, i); | |
86601d0e CJ |
1999 | ret = mmc_send_tuning(mmc, opcode, NULL); |
2000 | if (!ret) | |
2001 | fall_delay |= (1 << i); | |
2002 | } | |
2003 | final_fall_delay = get_best_delay(host, fall_delay); | |
2004 | ||
2005 | skip_fall: | |
2006 | final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); | |
2007 | if (final_maxlen == final_rise_delay.maxlen) { | |
2008 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
2009 | sdr_clr_bits(host->base + MSDC_IOCON, | |
2010 | MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); | |
86601d0e CJ |
2011 | final_delay = final_rise_delay.final_phase; |
2012 | } else { | |
2013 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
2014 | sdr_set_bits(host->base + MSDC_IOCON, | |
2015 | MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); | |
a2e6d1f6 CJ |
2016 | final_delay = final_fall_delay.final_phase; |
2017 | } | |
2018 | ||
fd82cc30 CJ |
2019 | msdc_set_cmd_delay(host, final_delay); |
2020 | msdc_set_data_delay(host, final_delay); | |
86601d0e CJ |
2021 | |
2022 | dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); | |
2023 | return final_delay == 0xff ? -EIO : 0; | |
2024 | } | |
2025 | ||
6397b7f5 CJ |
2026 | static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) |
2027 | { | |
2028 | struct msdc_host *host = mmc_priv(mmc); | |
2029 | int ret; | |
39add252 | 2030 | u32 tune_reg = host->dev_comp->pad_tune_reg; |
6397b7f5 | 2031 | |
86601d0e CJ |
2032 | if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { |
2033 | ret = msdc_tune_together(mmc, opcode); | |
2034 | if (host->hs400_mode) { | |
2035 | sdr_clr_bits(host->base + MSDC_IOCON, | |
2036 | MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); | |
fd82cc30 | 2037 | msdc_set_data_delay(host, 0); |
86601d0e CJ |
2038 | } |
2039 | goto tune_done; | |
2040 | } | |
7f3d5852 CJ |
2041 | if (host->hs400_mode && |
2042 | host->dev_comp->hs400_tune) | |
1ede5cb8 | 2043 | ret = hs400_tune_response(mmc, opcode); |
2044 | else | |
2045 | ret = msdc_tune_response(mmc, opcode); | |
6397b7f5 CJ |
2046 | if (ret == -EIO) { |
2047 | dev_err(host->dev, "Tune response fail!\n"); | |
567979fb | 2048 | return ret; |
6397b7f5 | 2049 | } |
5462ff39 CJ |
2050 | if (host->hs400_mode == false) { |
2051 | ret = msdc_tune_data(mmc, opcode); | |
2052 | if (ret == -EIO) | |
2053 | dev_err(host->dev, "Tune data fail!\n"); | |
2054 | } | |
6397b7f5 | 2055 | |
86601d0e | 2056 | tune_done: |
86beac37 | 2057 | host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); |
39add252 | 2058 | host->saved_tune_para.pad_tune = readl(host->base + tune_reg); |
1ede5cb8 | 2059 | host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); |
a2e6d1f6 CJ |
2060 | if (host->top_base) { |
2061 | host->saved_tune_para.emmc_top_control = readl(host->top_base + | |
2062 | EMMC_TOP_CONTROL); | |
2063 | host->saved_tune_para.emmc_top_cmd = readl(host->top_base + | |
2064 | EMMC_TOP_CMD); | |
2065 | } | |
6397b7f5 CJ |
2066 | return ret; |
2067 | } | |
2068 | ||
2069 | static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) | |
2070 | { | |
2071 | struct msdc_host *host = mmc_priv(mmc); | |
5462ff39 | 2072 | host->hs400_mode = true; |
6397b7f5 | 2073 | |
a2e6d1f6 CJ |
2074 | if (host->top_base) |
2075 | writel(host->hs400_ds_delay, | |
2076 | host->top_base + EMMC50_PAD_DS_TUNE); | |
2077 | else | |
2078 | writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); | |
2fea5819 CJ |
2079 | /* hs400 mode must set it to 0 */ |
2080 | sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); | |
c8609b22 CJ |
2081 | /* to improve read performance, set outstanding to 2 */ |
2082 | sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); | |
2083 | ||
6397b7f5 CJ |
2084 | return 0; |
2085 | } | |
2086 | ||
c9b5061e CJ |
2087 | static void msdc_hw_reset(struct mmc_host *mmc) |
2088 | { | |
2089 | struct msdc_host *host = mmc_priv(mmc); | |
2090 | ||
2091 | sdr_set_bits(host->base + EMMC_IOCON, 1); | |
2092 | udelay(10); /* 10us is enough */ | |
2093 | sdr_clr_bits(host->base + EMMC_IOCON, 1); | |
2094 | } | |
2095 | ||
5215b2e9 | 2096 | static void msdc_ack_sdio_irq(struct mmc_host *mmc) |
2097 | { | |
2098 | __msdc_enable_sdio_irq(mmc, 1); | |
2099 | } | |
2100 | ||
d087bde5 N |
2101 | static int msdc_get_cd(struct mmc_host *mmc) |
2102 | { | |
2103 | struct msdc_host *host = mmc_priv(mmc); | |
2104 | int val; | |
2105 | ||
2106 | if (mmc->caps & MMC_CAP_NONREMOVABLE) | |
2107 | return 1; | |
2108 | ||
2109 | if (!host->internal_cd) | |
2110 | return mmc_gpio_get_cd(mmc); | |
2111 | ||
2112 | val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; | |
2113 | if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) | |
2114 | return !!val; | |
2115 | else | |
2116 | return !val; | |
2117 | } | |
2118 | ||
be7815d6 | 2119 | static const struct mmc_host_ops mt_msdc_ops = { |
20848903 CJ |
2120 | .post_req = msdc_post_req, |
2121 | .pre_req = msdc_pre_req, | |
2122 | .request = msdc_ops_request, | |
2123 | .set_ios = msdc_ops_set_ios, | |
8d53e412 | 2124 | .get_ro = mmc_gpio_get_ro, |
d087bde5 | 2125 | .get_cd = msdc_get_cd, |
5215b2e9 | 2126 | .enable_sdio_irq = msdc_enable_sdio_irq, |
2127 | .ack_sdio_irq = msdc_ack_sdio_irq, | |
20848903 CJ |
2128 | .start_signal_voltage_switch = msdc_ops_switch_volt, |
2129 | .card_busy = msdc_card_busy, | |
6397b7f5 CJ |
2130 | .execute_tuning = msdc_execute_tuning, |
2131 | .prepare_hs400_tuning = msdc_prepare_hs400_tuning, | |
c9b5061e | 2132 | .hw_reset = msdc_hw_reset, |
20848903 CJ |
2133 | }; |
2134 | ||
1ede5cb8 | 2135 | static void msdc_of_property_parse(struct platform_device *pdev, |
2136 | struct msdc_host *host) | |
2137 | { | |
d17bb71c CJ |
2138 | of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", |
2139 | &host->latch_ck); | |
2140 | ||
1ede5cb8 | 2141 | of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", |
2142 | &host->hs400_ds_delay); | |
2143 | ||
2144 | of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", | |
2145 | &host->hs200_cmd_int_delay); | |
2146 | ||
2147 | of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", | |
2148 | &host->hs400_cmd_int_delay); | |
2149 | ||
2150 | if (of_property_read_bool(pdev->dev.of_node, | |
2151 | "mediatek,hs400-cmd-resp-sel-rising")) | |
2152 | host->hs400_cmd_resp_sel_rising = true; | |
2153 | else | |
2154 | host->hs400_cmd_resp_sel_rising = false; | |
2155 | } | |
2156 | ||
20848903 CJ |
2157 | static int msdc_drv_probe(struct platform_device *pdev) |
2158 | { | |
2159 | struct mmc_host *mmc; | |
2160 | struct msdc_host *host; | |
2161 | struct resource *res; | |
2162 | int ret; | |
2163 | ||
2164 | if (!pdev->dev.of_node) { | |
2165 | dev_err(&pdev->dev, "No DT found\n"); | |
2166 | return -EINVAL; | |
2167 | } | |
762d491a | 2168 | |
20848903 CJ |
2169 | /* Allocate MMC host for this device */ |
2170 | mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); | |
2171 | if (!mmc) | |
2172 | return -ENOMEM; | |
2173 | ||
2174 | host = mmc_priv(mmc); | |
2175 | ret = mmc_of_parse(mmc); | |
2176 | if (ret) | |
2177 | goto host_free; | |
2178 | ||
2179 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2180 | host->base = devm_ioremap_resource(&pdev->dev, res); | |
2181 | if (IS_ERR(host->base)) { | |
2182 | ret = PTR_ERR(host->base); | |
2183 | goto host_free; | |
2184 | } | |
2185 | ||
a2e6d1f6 | 2186 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
b65be635 FP |
2187 | if (res) { |
2188 | host->top_base = devm_ioremap_resource(&pdev->dev, res); | |
2189 | if (IS_ERR(host->top_base)) | |
2190 | host->top_base = NULL; | |
2191 | } | |
a2e6d1f6 | 2192 | |
20848903 | 2193 | ret = mmc_regulator_get_supply(mmc); |
2f98ef63 | 2194 | if (ret) |
20848903 CJ |
2195 | goto host_free; |
2196 | ||
2197 | host->src_clk = devm_clk_get(&pdev->dev, "source"); | |
2198 | if (IS_ERR(host->src_clk)) { | |
2199 | ret = PTR_ERR(host->src_clk); | |
2200 | goto host_free; | |
2201 | } | |
2202 | ||
2203 | host->h_clk = devm_clk_get(&pdev->dev, "hclk"); | |
2204 | if (IS_ERR(host->h_clk)) { | |
2205 | ret = PTR_ERR(host->h_clk); | |
2206 | goto host_free; | |
2207 | } | |
2208 | ||
258bac4a CJ |
2209 | host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); |
2210 | if (IS_ERR(host->bus_clk)) | |
2211 | host->bus_clk = NULL; | |
3c1a8844 CJ |
2212 | /*source clock control gate is optional clock*/ |
2213 | host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); | |
2214 | if (IS_ERR(host->src_clk_cg)) | |
2215 | host->src_clk_cg = NULL; | |
2216 | ||
20848903 CJ |
2217 | host->irq = platform_get_irq(pdev, 0); |
2218 | if (host->irq < 0) { | |
2219 | ret = -EINVAL; | |
2220 | goto host_free; | |
2221 | } | |
2222 | ||
2223 | host->pinctrl = devm_pinctrl_get(&pdev->dev); | |
2224 | if (IS_ERR(host->pinctrl)) { | |
2225 | ret = PTR_ERR(host->pinctrl); | |
2226 | dev_err(&pdev->dev, "Cannot find pinctrl!\n"); | |
2227 | goto host_free; | |
2228 | } | |
2229 | ||
2230 | host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); | |
2231 | if (IS_ERR(host->pins_default)) { | |
2232 | ret = PTR_ERR(host->pins_default); | |
2233 | dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); | |
2234 | goto host_free; | |
2235 | } | |
2236 | ||
2237 | host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); | |
2238 | if (IS_ERR(host->pins_uhs)) { | |
2239 | ret = PTR_ERR(host->pins_uhs); | |
2240 | dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); | |
2241 | goto host_free; | |
2242 | } | |
2243 | ||
1ede5cb8 | 2244 | msdc_of_property_parse(pdev, host); |
6397b7f5 | 2245 | |
20848903 | 2246 | host->dev = &pdev->dev; |
909b3456 | 2247 | host->dev_comp = of_device_get_match_data(&pdev->dev); |
20848903 CJ |
2248 | host->mmc = mmc; |
2249 | host->src_clk_freq = clk_get_rate(host->src_clk); | |
2250 | /* Set host parameters to mmc */ | |
2251 | mmc->ops = &mt_msdc_ops; | |
762d491a CJ |
2252 | if (host->dev_comp->clk_div_bits == 8) |
2253 | mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); | |
2254 | else | |
2255 | mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); | |
20848903 | 2256 | |
d087bde5 N |
2257 | if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && |
2258 | !mmc_can_gpio_cd(mmc) && | |
2259 | host->dev_comp->use_internal_cd) { | |
2260 | /* | |
2261 | * Is removable but no GPIO declared, so | |
2262 | * use internal functionality. | |
2263 | */ | |
2264 | host->internal_cd = true; | |
2265 | } | |
2266 | ||
5215b2e9 | 2267 | if (mmc->caps & MMC_CAP_SDIO_IRQ) |
2268 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; | |
2269 | ||
20848903 CJ |
2270 | mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; |
2271 | /* MMC core transfer sizes tunable parameters */ | |
2272 | mmc->max_segs = MAX_BD_NUM; | |
2273 | mmc->max_seg_size = BDMA_DESC_BUFLEN; | |
2274 | mmc->max_blk_size = 2048; | |
2275 | mmc->max_req_size = 512 * 1024; | |
2276 | mmc->max_blk_count = mmc->max_req_size / 512; | |
2a9bde19 CJ |
2277 | if (host->dev_comp->support_64g) |
2278 | host->dma_mask = DMA_BIT_MASK(36); | |
2279 | else | |
2280 | host->dma_mask = DMA_BIT_MASK(32); | |
20848903 CJ |
2281 | mmc_dev(mmc)->dma_mask = &host->dma_mask; |
2282 | ||
2283 | host->timeout_clks = 3 * 1048576; | |
2284 | host->dma.gpd = dma_alloc_coherent(&pdev->dev, | |
62b0d27a | 2285 | 2 * sizeof(struct mt_gpdma_desc), |
20848903 CJ |
2286 | &host->dma.gpd_addr, GFP_KERNEL); |
2287 | host->dma.bd = dma_alloc_coherent(&pdev->dev, | |
2288 | MAX_BD_NUM * sizeof(struct mt_bdma_desc), | |
2289 | &host->dma.bd_addr, GFP_KERNEL); | |
2290 | if (!host->dma.gpd || !host->dma.bd) { | |
2291 | ret = -ENOMEM; | |
2292 | goto release_mem; | |
2293 | } | |
2294 | msdc_init_gpd_bd(host, &host->dma); | |
2295 | INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); | |
2296 | spin_lock_init(&host->lock); | |
2297 | ||
2298 | platform_set_drvdata(pdev, mmc); | |
2299 | msdc_ungate_clock(host); | |
2300 | msdc_init_hw(host); | |
2301 | ||
2302 | ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, | |
42edb0d5 | 2303 | IRQF_TRIGGER_NONE, pdev->name, host); |
20848903 CJ |
2304 | if (ret) |
2305 | goto release; | |
2306 | ||
4b8a43e9 CJ |
2307 | pm_runtime_set_active(host->dev); |
2308 | pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); | |
2309 | pm_runtime_use_autosuspend(host->dev); | |
2310 | pm_runtime_enable(host->dev); | |
20848903 | 2311 | ret = mmc_add_host(mmc); |
4b8a43e9 | 2312 | |
20848903 | 2313 | if (ret) |
4b8a43e9 | 2314 | goto end; |
20848903 CJ |
2315 | |
2316 | return 0; | |
4b8a43e9 CJ |
2317 | end: |
2318 | pm_runtime_disable(host->dev); | |
20848903 CJ |
2319 | release: |
2320 | platform_set_drvdata(pdev, NULL); | |
2321 | msdc_deinit_hw(host); | |
2322 | msdc_gate_clock(host); | |
2323 | release_mem: | |
2324 | if (host->dma.gpd) | |
2325 | dma_free_coherent(&pdev->dev, | |
62b0d27a | 2326 | 2 * sizeof(struct mt_gpdma_desc), |
20848903 CJ |
2327 | host->dma.gpd, host->dma.gpd_addr); |
2328 | if (host->dma.bd) | |
2329 | dma_free_coherent(&pdev->dev, | |
2330 | MAX_BD_NUM * sizeof(struct mt_bdma_desc), | |
2331 | host->dma.bd, host->dma.bd_addr); | |
2332 | host_free: | |
2333 | mmc_free_host(mmc); | |
2334 | ||
2335 | return ret; | |
2336 | } | |
2337 | ||
2338 | static int msdc_drv_remove(struct platform_device *pdev) | |
2339 | { | |
2340 | struct mmc_host *mmc; | |
2341 | struct msdc_host *host; | |
2342 | ||
2343 | mmc = platform_get_drvdata(pdev); | |
2344 | host = mmc_priv(mmc); | |
2345 | ||
4b8a43e9 CJ |
2346 | pm_runtime_get_sync(host->dev); |
2347 | ||
20848903 CJ |
2348 | platform_set_drvdata(pdev, NULL); |
2349 | mmc_remove_host(host->mmc); | |
2350 | msdc_deinit_hw(host); | |
2351 | msdc_gate_clock(host); | |
2352 | ||
4b8a43e9 CJ |
2353 | pm_runtime_disable(host->dev); |
2354 | pm_runtime_put_noidle(host->dev); | |
20848903 | 2355 | dma_free_coherent(&pdev->dev, |
16f2e0c6 | 2356 | 2 * sizeof(struct mt_gpdma_desc), |
20848903 CJ |
2357 | host->dma.gpd, host->dma.gpd_addr); |
2358 | dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), | |
2359 | host->dma.bd, host->dma.bd_addr); | |
2360 | ||
2361 | mmc_free_host(host->mmc); | |
2362 | ||
2363 | return 0; | |
2364 | } | |
2365 | ||
4b8a43e9 CJ |
2366 | #ifdef CONFIG_PM |
2367 | static void msdc_save_reg(struct msdc_host *host) | |
2368 | { | |
39add252 CJ |
2369 | u32 tune_reg = host->dev_comp->pad_tune_reg; |
2370 | ||
4b8a43e9 CJ |
2371 | host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); |
2372 | host->save_para.iocon = readl(host->base + MSDC_IOCON); | |
2373 | host->save_para.sdc_cfg = readl(host->base + SDC_CFG); | |
4b8a43e9 CJ |
2374 | host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); |
2375 | host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); | |
2fea5819 | 2376 | host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); |
6397b7f5 | 2377 | host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); |
1ede5cb8 | 2378 | host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); |
6397b7f5 | 2379 | host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); |
c8609b22 | 2380 | host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); |
d9dcbfc8 | 2381 | host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); |
a2e6d1f6 CJ |
2382 | if (host->top_base) { |
2383 | host->save_para.emmc_top_control = | |
2384 | readl(host->top_base + EMMC_TOP_CONTROL); | |
2385 | host->save_para.emmc_top_cmd = | |
2386 | readl(host->top_base + EMMC_TOP_CMD); | |
2387 | host->save_para.emmc50_pad_ds_tune = | |
2388 | readl(host->top_base + EMMC50_PAD_DS_TUNE); | |
2389 | } else { | |
2390 | host->save_para.pad_tune = readl(host->base + tune_reg); | |
2391 | } | |
4b8a43e9 CJ |
2392 | } |
2393 | ||
2394 | static void msdc_restore_reg(struct msdc_host *host) | |
2395 | { | |
39add252 CJ |
2396 | u32 tune_reg = host->dev_comp->pad_tune_reg; |
2397 | ||
4b8a43e9 CJ |
2398 | writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); |
2399 | writel(host->save_para.iocon, host->base + MSDC_IOCON); | |
2400 | writel(host->save_para.sdc_cfg, host->base + SDC_CFG); | |
4b8a43e9 CJ |
2401 | writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); |
2402 | writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); | |
2fea5819 | 2403 | writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); |
6397b7f5 | 2404 | writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); |
1ede5cb8 | 2405 | writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); |
6397b7f5 | 2406 | writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); |
c8609b22 | 2407 | writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); |
d9dcbfc8 | 2408 | writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); |
a2e6d1f6 CJ |
2409 | if (host->top_base) { |
2410 | writel(host->save_para.emmc_top_control, | |
2411 | host->top_base + EMMC_TOP_CONTROL); | |
2412 | writel(host->save_para.emmc_top_cmd, | |
2413 | host->top_base + EMMC_TOP_CMD); | |
2414 | writel(host->save_para.emmc50_pad_ds_tune, | |
2415 | host->top_base + EMMC50_PAD_DS_TUNE); | |
2416 | } else { | |
2417 | writel(host->save_para.pad_tune, host->base + tune_reg); | |
2418 | } | |
4b8a43e9 CJ |
2419 | } |
2420 | ||
2421 | static int msdc_runtime_suspend(struct device *dev) | |
2422 | { | |
2423 | struct mmc_host *mmc = dev_get_drvdata(dev); | |
2424 | struct msdc_host *host = mmc_priv(mmc); | |
2425 | ||
2426 | msdc_save_reg(host); | |
2427 | msdc_gate_clock(host); | |
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | static int msdc_runtime_resume(struct device *dev) | |
2432 | { | |
2433 | struct mmc_host *mmc = dev_get_drvdata(dev); | |
2434 | struct msdc_host *host = mmc_priv(mmc); | |
2435 | ||
2436 | msdc_ungate_clock(host); | |
2437 | msdc_restore_reg(host); | |
2438 | return 0; | |
2439 | } | |
2440 | #endif | |
2441 | ||
2442 | static const struct dev_pm_ops msdc_dev_pm_ops = { | |
2443 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
2444 | pm_runtime_force_resume) | |
2445 | SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) | |
2446 | }; | |
2447 | ||
20848903 CJ |
2448 | static struct platform_driver mt_msdc_driver = { |
2449 | .probe = msdc_drv_probe, | |
2450 | .remove = msdc_drv_remove, | |
2451 | .driver = { | |
2452 | .name = "mtk-msdc", | |
2453 | .of_match_table = msdc_of_ids, | |
4b8a43e9 | 2454 | .pm = &msdc_dev_pm_ops, |
20848903 CJ |
2455 | }, |
2456 | }; | |
2457 | ||
2458 | module_platform_driver(mt_msdc_driver); | |
2459 | MODULE_LICENSE("GPL v2"); | |
2460 | MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); |