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9d2bd738 SM |
1 | /* |
2 | * linux/drivers/mmc/host/msmsdcc.h - QCT MSM7K SDC Controller | |
3 | * | |
4 | * Copyright (C) 2008 Google, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * - Based on mmci.h | |
11 | */ | |
12 | ||
13 | #ifndef _MSM_SDCC_H | |
14 | #define _MSM_SDCC_H | |
15 | ||
16 | #define MSMSDCC_CRCI_SDC1 6 | |
17 | #define MSMSDCC_CRCI_SDC2 7 | |
18 | #define MSMSDCC_CRCI_SDC3 12 | |
19 | #define MSMSDCC_CRCI_SDC4 13 | |
20 | ||
21 | #define MMCIPOWER 0x000 | |
22 | #define MCI_PWR_OFF 0x00 | |
23 | #define MCI_PWR_UP 0x02 | |
24 | #define MCI_PWR_ON 0x03 | |
25 | #define MCI_OD (1 << 6) | |
26 | ||
27 | #define MMCICLOCK 0x004 | |
28 | #define MCI_CLK_ENABLE (1 << 8) | |
29 | #define MCI_CLK_PWRSAVE (1 << 9) | |
30 | #define MCI_CLK_WIDEBUS (1 << 10) | |
31 | #define MCI_CLK_FLOWENA (1 << 12) | |
32 | #define MCI_CLK_INVERTOUT (1 << 13) | |
33 | #define MCI_CLK_SELECTIN (1 << 14) | |
34 | ||
35 | #define MMCIARGUMENT 0x008 | |
36 | #define MMCICOMMAND 0x00c | |
37 | #define MCI_CPSM_RESPONSE (1 << 6) | |
38 | #define MCI_CPSM_LONGRSP (1 << 7) | |
39 | #define MCI_CPSM_INTERRUPT (1 << 8) | |
40 | #define MCI_CPSM_PENDING (1 << 9) | |
41 | #define MCI_CPSM_ENABLE (1 << 10) | |
42 | #define MCI_CPSM_PROGENA (1 << 11) | |
43 | #define MCI_CSPM_DATCMD (1 << 12) | |
44 | #define MCI_CSPM_MCIABORT (1 << 13) | |
45 | #define MCI_CSPM_CCSENABLE (1 << 14) | |
46 | #define MCI_CSPM_CCSDISABLE (1 << 15) | |
47 | ||
48 | ||
49 | #define MMCIRESPCMD 0x010 | |
50 | #define MMCIRESPONSE0 0x014 | |
51 | #define MMCIRESPONSE1 0x018 | |
52 | #define MMCIRESPONSE2 0x01c | |
53 | #define MMCIRESPONSE3 0x020 | |
54 | #define MMCIDATATIMER 0x024 | |
55 | #define MMCIDATALENGTH 0x028 | |
56 | ||
57 | #define MMCIDATACTRL 0x02c | |
58 | #define MCI_DPSM_ENABLE (1 << 0) | |
59 | #define MCI_DPSM_DIRECTION (1 << 1) | |
60 | #define MCI_DPSM_MODE (1 << 2) | |
61 | #define MCI_DPSM_DMAENABLE (1 << 3) | |
62 | ||
63 | #define MMCIDATACNT 0x030 | |
64 | #define MMCISTATUS 0x034 | |
65 | #define MCI_CMDCRCFAIL (1 << 0) | |
66 | #define MCI_DATACRCFAIL (1 << 1) | |
67 | #define MCI_CMDTIMEOUT (1 << 2) | |
68 | #define MCI_DATATIMEOUT (1 << 3) | |
69 | #define MCI_TXUNDERRUN (1 << 4) | |
70 | #define MCI_RXOVERRUN (1 << 5) | |
71 | #define MCI_CMDRESPEND (1 << 6) | |
72 | #define MCI_CMDSENT (1 << 7) | |
73 | #define MCI_DATAEND (1 << 8) | |
74 | #define MCI_DATABLOCKEND (1 << 10) | |
75 | #define MCI_CMDACTIVE (1 << 11) | |
76 | #define MCI_TXACTIVE (1 << 12) | |
77 | #define MCI_RXACTIVE (1 << 13) | |
78 | #define MCI_TXFIFOHALFEMPTY (1 << 14) | |
79 | #define MCI_RXFIFOHALFFULL (1 << 15) | |
80 | #define MCI_TXFIFOFULL (1 << 16) | |
81 | #define MCI_RXFIFOFULL (1 << 17) | |
82 | #define MCI_TXFIFOEMPTY (1 << 18) | |
83 | #define MCI_RXFIFOEMPTY (1 << 19) | |
84 | #define MCI_TXDATAAVLBL (1 << 20) | |
85 | #define MCI_RXDATAAVLBL (1 << 21) | |
86 | #define MCI_SDIOINTR (1 << 22) | |
87 | #define MCI_PROGDONE (1 << 23) | |
88 | #define MCI_ATACMDCOMPL (1 << 24) | |
89 | #define MCI_SDIOINTOPER (1 << 25) | |
90 | #define MCI_CCSTIMEOUT (1 << 26) | |
91 | ||
92 | #define MMCICLEAR 0x038 | |
93 | #define MCI_CMDCRCFAILCLR (1 << 0) | |
94 | #define MCI_DATACRCFAILCLR (1 << 1) | |
95 | #define MCI_CMDTIMEOUTCLR (1 << 2) | |
96 | #define MCI_DATATIMEOUTCLR (1 << 3) | |
97 | #define MCI_TXUNDERRUNCLR (1 << 4) | |
98 | #define MCI_RXOVERRUNCLR (1 << 5) | |
99 | #define MCI_CMDRESPENDCLR (1 << 6) | |
100 | #define MCI_CMDSENTCLR (1 << 7) | |
101 | #define MCI_DATAENDCLR (1 << 8) | |
102 | #define MCI_DATABLOCKENDCLR (1 << 10) | |
103 | ||
104 | #define MMCIMASK0 0x03c | |
105 | #define MCI_CMDCRCFAILMASK (1 << 0) | |
106 | #define MCI_DATACRCFAILMASK (1 << 1) | |
107 | #define MCI_CMDTIMEOUTMASK (1 << 2) | |
108 | #define MCI_DATATIMEOUTMASK (1 << 3) | |
109 | #define MCI_TXUNDERRUNMASK (1 << 4) | |
110 | #define MCI_RXOVERRUNMASK (1 << 5) | |
111 | #define MCI_CMDRESPENDMASK (1 << 6) | |
112 | #define MCI_CMDSENTMASK (1 << 7) | |
113 | #define MCI_DATAENDMASK (1 << 8) | |
114 | #define MCI_DATABLOCKENDMASK (1 << 10) | |
115 | #define MCI_CMDACTIVEMASK (1 << 11) | |
116 | #define MCI_TXACTIVEMASK (1 << 12) | |
117 | #define MCI_RXACTIVEMASK (1 << 13) | |
118 | #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) | |
119 | #define MCI_RXFIFOHALFFULLMASK (1 << 15) | |
120 | #define MCI_TXFIFOFULLMASK (1 << 16) | |
121 | #define MCI_RXFIFOFULLMASK (1 << 17) | |
122 | #define MCI_TXFIFOEMPTYMASK (1 << 18) | |
123 | #define MCI_RXFIFOEMPTYMASK (1 << 19) | |
124 | #define MCI_TXDATAAVLBLMASK (1 << 20) | |
125 | #define MCI_RXDATAAVLBLMASK (1 << 21) | |
126 | #define MCI_SDIOINTMASK (1 << 22) | |
127 | #define MCI_PROGDONEMASK (1 << 23) | |
128 | #define MCI_ATACMDCOMPLMASK (1 << 24) | |
129 | #define MCI_SDIOINTOPERMASK (1 << 25) | |
130 | #define MCI_CCSTIMEOUTMASK (1 << 26) | |
131 | ||
132 | #define MMCIMASK1 0x040 | |
133 | #define MMCIFIFOCNT 0x044 | |
134 | #define MCICCSTIMER 0x058 | |
135 | ||
136 | #define MMCIFIFO 0x080 /* to 0x0bc */ | |
137 | ||
138 | #define MCI_IRQENABLE \ | |
139 | (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ | |
140 | MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ | |
d5137bdd | 141 | MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK|MCI_PROGDONEMASK) |
9d2bd738 | 142 | |
4a268e08 ST |
143 | #define MCI_IRQ_PIO \ |
144 | (MCI_RXDATAAVLBLMASK | MCI_TXDATAAVLBLMASK | MCI_RXFIFOEMPTYMASK | \ | |
145 | MCI_TXFIFOEMPTYMASK | MCI_RXFIFOFULLMASK | MCI_TXFIFOFULLMASK | \ | |
146 | MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK | \ | |
147 | MCI_RXACTIVEMASK | MCI_TXACTIVEMASK) | |
9d2bd738 SM |
148 | /* |
149 | * The size of the FIFO in bytes. | |
150 | */ | |
151 | #define MCI_FIFOSIZE (16*4) | |
152 | ||
153 | #define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2) | |
154 | ||
155 | #define NR_SG 32 | |
156 | ||
157 | struct clk; | |
158 | ||
159 | struct msmsdcc_nc_dmadata { | |
160 | dmov_box cmd[NR_SG]; | |
161 | uint32_t cmdptr; | |
162 | }; | |
163 | ||
164 | struct msmsdcc_dma_data { | |
165 | struct msmsdcc_nc_dmadata *nc; | |
166 | dma_addr_t nc_busaddr; | |
167 | dma_addr_t cmd_busaddr; | |
168 | dma_addr_t cmdptr_busaddr; | |
169 | ||
170 | struct msm_dmov_cmd hdr; | |
171 | enum dma_data_direction dir; | |
172 | ||
173 | struct scatterlist *sg; | |
174 | int num_ents; | |
175 | ||
176 | int channel; | |
177 | struct msmsdcc_host *host; | |
178 | int busy; /* Set if DM is busy */ | |
56a8b5b8 | 179 | int active; |
62612cf9 ST |
180 | unsigned int result; |
181 | struct msm_dmov_errdata err; | |
9d2bd738 SM |
182 | }; |
183 | ||
184 | struct msmsdcc_pio_data { | |
185 | struct scatterlist *sg; | |
186 | unsigned int sg_len; | |
187 | unsigned int sg_off; | |
188 | }; | |
189 | ||
190 | struct msmsdcc_curr_req { | |
191 | struct mmc_request *mrq; | |
192 | struct mmc_command *cmd; | |
193 | struct mmc_data *data; | |
194 | unsigned int xfer_size; /* Total data size */ | |
195 | unsigned int xfer_remain; /* Bytes remaining to send */ | |
196 | unsigned int data_xfered; /* Bytes acked by BLKEND irq */ | |
197 | int got_dataend; | |
9d2bd738 SM |
198 | int user_pages; |
199 | }; | |
200 | ||
201 | struct msmsdcc_stats { | |
202 | unsigned int reqs; | |
203 | unsigned int cmds; | |
204 | unsigned int cmdpoll_hits; | |
205 | unsigned int cmdpoll_misses; | |
206 | }; | |
207 | ||
208 | struct msmsdcc_host { | |
209 | struct resource *cmd_irqres; | |
9d2bd738 SM |
210 | struct resource *memres; |
211 | struct resource *dmares; | |
212 | void __iomem *base; | |
213 | int pdev_id; | |
214 | unsigned int stat_irq; | |
215 | ||
216 | struct msmsdcc_curr_req curr; | |
217 | ||
218 | struct mmc_host *mmc; | |
219 | struct clk *clk; /* main MMC bus clock */ | |
220 | struct clk *pclk; /* SDCC peripheral bus clock */ | |
221 | unsigned int clks_on; /* set if clocks are enabled */ | |
865c8064 | 222 | struct timer_list busclk_timer; |
9d2bd738 SM |
223 | |
224 | unsigned int eject; /* eject state */ | |
225 | ||
226 | spinlock_t lock; | |
227 | ||
228 | unsigned int clk_rate; /* Current clock rate */ | |
229 | unsigned int pclk_rate; | |
230 | ||
231 | u32 pwr; | |
232 | u32 saved_irq0mask; /* MMCIMASK0 reg value */ | |
b5d643de | 233 | struct msm_mmc_platform_data *plat; |
9d2bd738 SM |
234 | |
235 | struct timer_list timer; | |
236 | unsigned int oldstat; | |
237 | ||
238 | struct msmsdcc_dma_data dma; | |
239 | struct msmsdcc_pio_data pio; | |
240 | int cmdpoll; | |
241 | struct msmsdcc_stats stats; | |
56a8b5b8 | 242 | |
62612cf9 | 243 | struct tasklet_struct dma_tlet; |
56a8b5b8 SM |
244 | /* Command parameters */ |
245 | unsigned int cmd_timeout; | |
246 | unsigned int cmd_pio_irqmask; | |
247 | unsigned int cmd_datactrl; | |
248 | struct mmc_command *cmd_cmd; | |
249 | u32 cmd_c; | |
7a89248a | 250 | bool gpio_config_status; |
56a8b5b8 | 251 | |
d5137bdd ST |
252 | bool prog_scan; |
253 | bool prog_enable; | |
9d2bd738 SM |
254 | }; |
255 | ||
256 | #endif |