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drivers: mmc: msm: remove clock disable in probe
[linux-2.6-block.git] / drivers / mmc / host / msm_sdcc.c
CommitLineData
9d2bd738
SM		 1/*
2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
3 *
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
56a8b5b8 6 * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
9d2bd738
SM		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Based on mmci.c
13 *
14 * Author: San Mehat (san@android.com)
15 *
16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/device.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/err.h>
26#include <linux/highmem.h>
27#include <linux/log2.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
b3fa5791 30#include <linux/mmc/sdio.h>
9d2bd738
SM		 31#include <linux/clk.h>
32#include <linux/scatterlist.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35#include <linux/debugfs.h>
36#include <linux/io.h>
37#include <linux/memory.h>
5a0e3ad6 38#include <linux/gfp.h>
9d2bd738
SM		 39
40#include <asm/cacheflush.h>
41#include <asm/div64.h>
42#include <asm/sizes.h>
43
3989d178 44#include <mach/mmc.h>
9d2bd738
SM		 45#include <mach/msm_iomap.h>
46#include <mach/dma.h>
b08bb35d 47#include <mach/clk.h>
9d2bd738 48
9d2bd738
SM		 49#include "msm_sdcc.h"
50
51#define DRIVER_NAME "msm-sdcc"
52
24bbd7d5 53#define BUSCLK_PWRSAVE 1
c7fc9370 54#define BUSCLK_TIMEOUT (HZ)
9d2bd738
SM		 55static unsigned int msmsdcc_fmin = 144000;
56static unsigned int msmsdcc_fmax = 50000000;
57static unsigned int msmsdcc_4bit = 1;
58static unsigned int msmsdcc_pwrsave = 1;
59static unsigned int msmsdcc_piopoll = 1;
60static unsigned int msmsdcc_sdioirq;
61
62#define PIO_SPINMAX 30
63#define CMD_SPINMAX 20
64
865c8064 65
d0719e59 66static inline void
c7fc9370 67msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
865c8064 68{
c7fc9370 69 WARN_ON(!host->clks_on);
8b1c2ba2 70
f4748499
SM		 71 BUG_ON(host->curr.mrq);
72
c7fc9370
SM		 73 if (deferr) {
74 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
865c8064 75 } else {
c7fc9370 76 del_timer_sync(&host->busclk_timer);
d0719e59
SM		 77 /* Need to check clks_on again in case the busclk
78 * timer fired
79 */
80 if (host->clks_on) {
81 clk_disable(host->clk);
82 clk_disable(host->pclk);
83 host->clks_on = 0;
84 }
865c8064 85 }
c7fc9370
SM		 86}
87
88static inline int
89msmsdcc_enable_clocks(struct msmsdcc_host *host)
90{
91 int rc;
92
c7fc9370
SM		 93 del_timer_sync(&host->busclk_timer);
94
d0719e59
SM		 95 if (!host->clks_on) {
96 rc = clk_enable(host->pclk);
97 if (rc)
98 return rc;
99 rc = clk_enable(host->clk);
100 if (rc) {
101 clk_disable(host->pclk);
102 return rc;
103 }
104 udelay(1 + ((3 * USEC_PER_SEC) /
105 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
106 host->clks_on = 1;
c7fc9370 107 }
865c8064
SM		 108 return 0;
109}
110
8b1c2ba2
SM		 111static inline unsigned int
112msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
113{
114 return readl(host->base + reg);
115}
116
117static inline void
118msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
119{
120 writel(data, host->base + reg);
121 /* 3 clk delay required! */
122 udelay(1 + ((3 * USEC_PER_SEC) /
123 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
124}
865c8064 125
9d2bd738
SM		 126static void
127msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
128 u32 c);
129
b08bb35d
ST		 130static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
131{
132 u32 mci_clk = 0;
133 u32 mci_mask0 = 0;
134 int ret = 0;
135
136 /* Save the controller state */
137 mci_clk = readl(host->base + MMCICLOCK);
138 mci_mask0 = readl(host->base + MMCIMASK0);
139
140 /* Reset the controller */
141 ret = clk_reset(host->clk, CLK_RESET_ASSERT);
142 if (ret)
143 pr_err("%s: Clock assert failed at %u Hz with err %d\n",
144 mmc_hostname(host->mmc), host->clk_rate, ret);
145
146 ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
147 if (ret)
148 pr_err("%s: Clock deassert failed at %u Hz with err %d\n",
149 mmc_hostname(host->mmc), host->clk_rate, ret);
150
151 pr_info("%s: Controller has been re-initialiazed\n",
152 mmc_hostname(host->mmc));
153
154 /* Restore the contoller state */
155 writel(host->pwr, host->base + MMCIPOWER);
156 writel(mci_clk, host->base + MMCICLOCK);
157 writel(mci_mask0, host->base + MMCIMASK0);
158 ret = clk_set_rate(host->clk, host->clk_rate);
159 if (ret)
160 pr_err("%s: Failed to set clk rate %u Hz (%d)\n",
161 mmc_hostname(host->mmc), host->clk_rate, ret);
162}
163
9d2bd738
SM		 164static void
165msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
166{
9d2bd738
SM		 167 BUG_ON(host->curr.data);
168
169 host->curr.mrq = NULL;
170 host->curr.cmd = NULL;
171
172 if (mrq->data)
173 mrq->data->bytes_xfered = host->curr.data_xfered;
174 if (mrq->cmd->error == -ETIMEDOUT)
175 mdelay(5);
176
f4748499 177#if BUSCLK_PWRSAVE
c7fc9370 178 msmsdcc_disable_clocks(host, 1);
f4748499 179#endif
9d2bd738
SM		 180 /*
181 * Need to drop the host lock here; mmc_request_done may call
182 * back into the driver...
183 */
184 spin_unlock(&host->lock);
185 mmc_request_done(host->mmc, mrq);
186 spin_lock(&host->lock);
187}
188
189static void
190msmsdcc_stop_data(struct msmsdcc_host *host)
191{
9d2bd738 192 host->curr.data = NULL;
0c521ccb 193 host->curr.got_dataend = 0;
9d2bd738
SM		 194}
195
196uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
197{
edd4dd0e 198 return host->memres->start + MMCIFIFO;
9d2bd738
SM		 199}
200
56a8b5b8
SM		 201static inline void
202msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
203 msmsdcc_writel(host, arg, MMCIARGUMENT);
204 msmsdcc_writel(host, c, MMCICOMMAND);
205}
206
207static void
208msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
209{
6ac9ea69 210 struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
56a8b5b8 211
6ac9ea69 212 msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
d0719e59
SM		 213 msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
214 MMCIDATALENGTH);
6ac9ea69
SM		 215 msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1);
216 msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
56a8b5b8 217
6ac9ea69
SM		 218 if (host->cmd_cmd) {
219 msmsdcc_start_command_exec(host,
220 (u32) host->cmd_cmd->arg,
221 (u32) host->cmd_c);
222 }
56a8b5b8
SM		 223 host->dma.active = 1;
224}
225
9d2bd738 226static void
62612cf9 227msmsdcc_dma_complete_tlet(unsigned long data)
9d2bd738 228{
62612cf9 229 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
9d2bd738
SM		 230 unsigned long flags;
231 struct mmc_request *mrq;
62612cf9 232 struct msm_dmov_errdata err;
9d2bd738
SM		 233
234 spin_lock_irqsave(&host->lock, flags);
56a8b5b8
SM		 235 host->dma.active = 0;
236
62612cf9 237 err = host->dma.err;
9d2bd738
SM		 238 mrq = host->curr.mrq;
239 BUG_ON(!mrq);
b3b0ca84 240 WARN_ON(!mrq->data);
9d2bd738 241
62612cf9 242 if (!(host->dma.result & DMOV_RSLT_VALID)) {
0a7ff7c7 243 pr_err("msmsdcc: Invalid DataMover result\n");
9d2bd738
SM		 244 goto out;
245 }
246
62612cf9 247 if (host->dma.result & DMOV_RSLT_DONE) {
9d2bd738
SM		 248 host->curr.data_xfered = host->curr.xfer_size;
249 } else {
250 /* Error or flush */
62612cf9 251 if (host->dma.result & DMOV_RSLT_ERROR)
0a7ff7c7 252 pr_err("%s: DMA error (0x%.8x)\n",
62612cf9
ST		 253 mmc_hostname(host->mmc), host->dma.result);
254 if (host->dma.result & DMOV_RSLT_FLUSH)
0a7ff7c7 255 pr_err("%s: DMA channel flushed (0x%.8x)\n",
62612cf9
ST		 256 mmc_hostname(host->mmc), host->dma.result);
257
258 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
259 err.flush[0], err.flush[1], err.flush[2],
260 err.flush[3], err.flush[4], err.flush[5]);
b08bb35d
ST		 261
262 msmsdcc_reset_and_restore(host);
9d2bd738
SM		 263 if (!mrq->data->error)
264 mrq->data->error = -EIO;
265 }
9d2bd738
SM		 266 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
267 host->dma.dir);
268
269 if (host->curr.user_pages) {
270 struct scatterlist *sg = host->dma.sg;
271 int i;
272
75d14528
JP		 273 for (i = 0; i < host->dma.num_ents; i++)
274 flush_dcache_page(sg_page(sg++));
9d2bd738
SM		 275 }
276
277 host->dma.sg = NULL;
56a8b5b8 278 host->dma.busy = 0;
9d2bd738 279
0c521ccb 280 if (host->curr.got_dataend || mrq->data->error) {
9d2bd738
SM		 281
282 /*
283 * If we've already gotten our DATAEND / DATABLKEND
284 * for this request, then complete it through here.
285 */
286 msmsdcc_stop_data(host);
287
288 if (!mrq->data->error)
289 host->curr.data_xfered = host->curr.xfer_size;
290 if (!mrq->data->stop || mrq->cmd->error) {
9d2bd738
SM		 291 host->curr.mrq = NULL;
292 host->curr.cmd = NULL;
293 mrq->data->bytes_xfered = host->curr.data_xfered;
294
295 spin_unlock_irqrestore(&host->lock, flags);
f4748499 296#if BUSCLK_PWRSAVE
c7fc9370 297 msmsdcc_disable_clocks(host, 1);
f4748499 298#endif
9d2bd738
SM		 299 mmc_request_done(host->mmc, mrq);
300 return;
301 } else
302 msmsdcc_start_command(host, mrq->data->stop, 0);
303 }
304
305out:
306 spin_unlock_irqrestore(&host->lock, flags);
307 return;
308}
309
62612cf9
ST		 310static void
311msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
312 unsigned int result,
313 struct msm_dmov_errdata *err)
314{
315 struct msmsdcc_dma_data *dma_data =
316 container_of(cmd, struct msmsdcc_dma_data, hdr);
317 struct msmsdcc_host *host = dma_data->host;
318
319 dma_data->result = result;
320 if (err)
321 memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata));
322
323 tasklet_schedule(&host->dma_tlet);
324}
325
9d2bd738
SM		 326static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
327{
328 if (host->dma.channel == -1)
329 return -ENOENT;
330
331 if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
332 return -EINVAL;
333 if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
334 return -EINVAL;
335 return 0;
336}
337
338static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
339{
340 struct msmsdcc_nc_dmadata *nc;
341 dmov_box *box;
342 uint32_t rows;
343 uint32_t crci;
344 unsigned int n;
345 int i, rc;
346 struct scatterlist *sg = data->sg;
347
348 rc = validate_dma(host, data);
349 if (rc)
350 return rc;
351
352 host->dma.sg = data->sg;
353 host->dma.num_ents = data->sg_len;
354
56a8b5b8
SM		 355 BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
356
9d2bd738
SM		 357 nc = host->dma.nc;
358
75d14528
JP		 359 switch (host->pdev_id) {
360 case 1:
9d2bd738 361 crci = MSMSDCC_CRCI_SDC1;
75d14528
JP		 362 break;
363 case 2:
9d2bd738 364 crci = MSMSDCC_CRCI_SDC2;
75d14528
JP		 365 break;
366 case 3:
9d2bd738 367 crci = MSMSDCC_CRCI_SDC3;
75d14528
JP		 368 break;
369 case 4:
9d2bd738 370 crci = MSMSDCC_CRCI_SDC4;
75d14528
JP		 371 break;
372 default:
9d2bd738
SM		 373 host->dma.sg = NULL;
374 host->dma.num_ents = 0;
375 return -ENOENT;
376 }
377
378 if (data->flags & MMC_DATA_READ)
379 host->dma.dir = DMA_FROM_DEVICE;
380 else
381 host->dma.dir = DMA_TO_DEVICE;
382
383 host->curr.user_pages = 0;
384
9d2bd738 385 box = &nc->cmd[0];
9d2bd738 386
208028de
DW		 387 /* location of command block must be 64 bit aligned */
388 BUG_ON(host->dma.cmd_busaddr & 0x07);
389
390 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
391 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
392 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
393 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
394
395 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
396 host->dma.num_ents, host->dma.dir);
397 if (n == 0) {
398 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
399 mmc_hostname(host->mmc));
400 host->dma.sg = NULL;
401 host->dma.num_ents = 0;
402 return -ENOMEM;
403 }
404
405 for_each_sg(host->dma.sg, sg, n, i) {
406
407 box->cmd = CMD_MODE_BOX;
56a8b5b8 408
208028de 409 if (i == n - 1)
9d2bd738
SM		 410 box->cmd |= CMD_LC;
411 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
412 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
413 (sg_dma_len(sg) / MCI_FIFOSIZE) ;
414
415 if (data->flags & MMC_DATA_READ) {
416 box->src_row_addr = msmsdcc_fifo_addr(host);
417 box->dst_row_addr = sg_dma_address(sg);
418
419 box->src_dst_len = (MCI_FIFOSIZE << 16) |
420 (MCI_FIFOSIZE);
421 box->row_offset = MCI_FIFOSIZE;
422
423 box->num_rows = rows * ((1 << 16) + 1);
424 box->cmd |= CMD_SRC_CRCI(crci);
425 } else {
426 box->src_row_addr = sg_dma_address(sg);
427 box->dst_row_addr = msmsdcc_fifo_addr(host);
428
429 box->src_dst_len = (MCI_FIFOSIZE << 16) |
430 (MCI_FIFOSIZE);
431 box->row_offset = (MCI_FIFOSIZE << 16);
432
433 box->num_rows = rows * ((1 << 16) + 1);
434 box->cmd |= CMD_DST_CRCI(crci);
435 }
436 box++;
56a8b5b8
SM		 437 }
438
439 return 0;
440}
441
442static int
443snoop_cccr_abort(struct mmc_command *cmd)
444{
445 if ((cmd->opcode == 52) &&
446 (cmd->arg & 0x80000000) &&
447 (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
448 return 1;
9d2bd738
SM		 449 return 0;
450}
451
452static void
56a8b5b8
SM		 453msmsdcc_start_command_deferred(struct msmsdcc_host *host,
454 struct mmc_command *cmd, u32 *c)
455{
456 *c |= (cmd->opcode | MCI_CPSM_ENABLE);
457
458 if (cmd->flags & MMC_RSP_PRESENT) {
459 if (cmd->flags & MMC_RSP_136)
460 *c |= MCI_CPSM_LONGRSP;
461 *c |= MCI_CPSM_RESPONSE;
462 }
463
464 if (/*interrupt*/0)
465 *c |= MCI_CPSM_INTERRUPT;
466
467 if ((((cmd->opcode == 17) || (cmd->opcode == 18)) ||
468 ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
469 (cmd->opcode == 53))
470 *c |= MCI_CSPM_DATCMD;
471
d5137bdd
ST		 472 if (host->prog_scan && (cmd->opcode == 12)) {
473 *c |= MCI_CPSM_PROGENA;
474 host->prog_enable = true;
475 }
476
56a8b5b8
SM		 477 if (cmd == cmd->mrq->stop)
478 *c |= MCI_CSPM_MCIABORT;
479
480 if (snoop_cccr_abort(cmd))
481 *c |= MCI_CSPM_MCIABORT;
482
483 if (host->curr.cmd != NULL) {
484 printk(KERN_ERR "%s: Overlapping command requests\n",
485 mmc_hostname(host->mmc));
486 }
487 host->curr.cmd = cmd;
488}
489
490static void
491msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
492 struct mmc_command *cmd, u32 c)
9d2bd738
SM		 493{
494 unsigned int datactrl, timeout;
495 unsigned long long clks;
9d2bd738
SM		 496 unsigned int pio_irqmask = 0;
497
498 host->curr.data = data;
499 host->curr.xfer_size = data->blksz * data->blocks;
500 host->curr.xfer_remain = host->curr.xfer_size;
501 host->curr.data_xfered = 0;
502 host->curr.got_dataend = 0;
9d2bd738
SM		 503
504 memset(&host->pio, 0, sizeof(host->pio));
505
9d2bd738
SM		 506 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
507
508 if (!msmsdcc_config_dma(host, data))
509 datactrl |= MCI_DPSM_DMAENABLE;
510 else {
511 host->pio.sg = data->sg;
512 host->pio.sg_len = data->sg_len;
513 host->pio.sg_off = 0;
514
515 if (data->flags & MMC_DATA_READ) {
516 pio_irqmask = MCI_RXFIFOHALFFULLMASK;
517 if (host->curr.xfer_remain < MCI_FIFOSIZE)
518 pio_irqmask |= MCI_RXDATAAVLBLMASK;
519 } else
520 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
521 }
522
523 if (data->flags & MMC_DATA_READ)
524 datactrl |= MCI_DPSM_DIRECTION;
525
56a8b5b8
SM		 526 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
527 do_div(clks, NSEC_PER_SEC);
528 timeout = data->timeout_clks + (unsigned int)clks*2 ;
9d2bd738
SM		 529
530 if (datactrl & MCI_DPSM_DMAENABLE) {
56a8b5b8
SM		 531 /* Save parameters for the exec function */
532 host->cmd_timeout = timeout;
533 host->cmd_pio_irqmask = pio_irqmask;
534 host->cmd_datactrl = datactrl;
535 host->cmd_cmd = cmd;
536
537 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
538 host->dma.hdr.data = (void *)host;
9d2bd738 539 host->dma.busy = 1;
56a8b5b8
SM		 540
541 if (cmd) {
542 msmsdcc_start_command_deferred(host, cmd, &c);
543 host->cmd_c = c;
544 }
9d2bd738 545 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
d5137bdd
ST		 546 if (data->flags & MMC_DATA_WRITE)
547 host->prog_scan = true;
56a8b5b8
SM		 548 } else {
549 msmsdcc_writel(host, timeout, MMCIDATATIMER);
9d2bd738 550
56a8b5b8
SM		 551 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
552
553 msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
554 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
555
556 if (cmd) {
557 /* Daisy-chain the command if requested */
558 msmsdcc_start_command(host, cmd, c);
559 }
9d2bd738
SM		 560 }
561}
562
563static void
564msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
565{
9d2bd738
SM		 566 if (cmd == cmd->mrq->stop)
567 c |= MCI_CSPM_MCIABORT;
568
9d2bd738
SM		 569 host->stats.cmds++;
570
56a8b5b8
SM		 571 msmsdcc_start_command_deferred(host, cmd, &c);
572 msmsdcc_start_command_exec(host, cmd->arg, c);
9d2bd738
SM		 573}
574
575static void
576msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
577 unsigned int status)
578{
579 if (status & MCI_DATACRCFAIL) {
0a7ff7c7
JP		 580 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
581 pr_err("%s: opcode 0x%.8x\n", __func__,
9d2bd738 582 data->mrq->cmd->opcode);
0a7ff7c7 583 pr_err("%s: blksz %d, blocks %d\n", __func__,
9d2bd738
SM		 584 data->blksz, data->blocks);
585 data->error = -EILSEQ;
586 } else if (status & MCI_DATATIMEOUT) {
0a7ff7c7 587 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
9d2bd738
SM		 588 data->error = -ETIMEDOUT;
589 } else if (status & MCI_RXOVERRUN) {
0a7ff7c7 590 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
9d2bd738
SM		 591 data->error = -EIO;
592 } else if (status & MCI_TXUNDERRUN) {
0a7ff7c7 593 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
9d2bd738
SM		 594 data->error = -EIO;
595 } else {
0a7ff7c7
JP		 596 pr_err("%s: Unknown error (0x%.8x)\n",
597 mmc_hostname(host->mmc), status);
9d2bd738
SM		 598 data->error = -EIO;
599 }
600}
601
602
603static int
604msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
605{
9d2bd738
SM		 606 uint32_t *ptr = (uint32_t *) buffer;
607 int count = 0;
608
71dd9106
ST		 609 if (remain % 4)
610 remain = ((remain >> 2) + 1) << 2;
611
8b1c2ba2
SM		 612 while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
613 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
9d2bd738
SM		 614 ptr++;
615 count += sizeof(uint32_t);
616
617 remain -= sizeof(uint32_t);
618 if (remain == 0)
619 break;
620 }
621 return count;
622}
623
624static int
625msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
626 unsigned int remain, u32 status)
627{
628 void __iomem *base = host->base;
629 char *ptr = buffer;
630
631 do {
71dd9106 632 unsigned int count, maxcnt, sz;
9d2bd738
SM		 633
634 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
635 MCI_FIFOHALFSIZE;
636 count = min(remain, maxcnt);
637
71dd9106
ST		 638 sz = count % 4 ? (count >> 2) + 1 : (count >> 2);
639 writesl(base + MMCIFIFO, ptr, sz);
9d2bd738
SM		 640 ptr += count;
641 remain -= count;
642
643 if (remain == 0)
644 break;
645
8b1c2ba2 646 status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738
SM		 647 } while (status & MCI_TXFIFOHALFEMPTY);
648
649 return ptr - buffer;
650}
651
652static int
653msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
654{
655 while (maxspin) {
8b1c2ba2 656 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
9d2bd738
SM		 657 return 0;
658 udelay(1);
659 --maxspin;
660 }
661 return -ETIMEDOUT;
662}
663
1cd22969 664static irqreturn_t
9d2bd738
SM		 665msmsdcc_pio_irq(int irq, void *dev_id)
666{
667 struct msmsdcc_host *host = dev_id;
9d2bd738
SM		 668 uint32_t status;
669
8b1c2ba2 670 status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738
SM		 671
672 do {
673 unsigned long flags;
674 unsigned int remain, len;
675 char *buffer;
676
677 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
678 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
679 break;
680
681 if (msmsdcc_spin_on_status(host,
682 (MCI_TXFIFOHALFEMPTY |
683 MCI_RXDATAAVLBL),
684 PIO_SPINMAX)) {
685 break;
686 }
687 }
688
689 /* Map the current scatter buffer */
690 local_irq_save(flags);
691 buffer = kmap_atomic(sg_page(host->pio.sg),
692 KM_BIO_SRC_IRQ) + host->pio.sg->offset;
693 buffer += host->pio.sg_off;
694 remain = host->pio.sg->length - host->pio.sg_off;
695 len = 0;
696 if (status & MCI_RXACTIVE)
697 len = msmsdcc_pio_read(host, buffer, remain);
698 if (status & MCI_TXACTIVE)
699 len = msmsdcc_pio_write(host, buffer, remain, status);
700
701 /* Unmap the buffer */
702 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
703 local_irq_restore(flags);
704
705 host->pio.sg_off += len;
706 host->curr.xfer_remain -= len;
707 host->curr.data_xfered += len;
708 remain -= len;
709
710 if (remain == 0) {
711 /* This sg page is full - do some housekeeping */
712 if (status & MCI_RXACTIVE && host->curr.user_pages)
713 flush_dcache_page(sg_page(host->pio.sg));
714
715 if (!--host->pio.sg_len) {
716 memset(&host->pio, 0, sizeof(host->pio));
717 break;
718 }
719
720 /* Advance to next sg */
721 host->pio.sg++;
722 host->pio.sg_off = 0;
723 }
724
8b1c2ba2 725 status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738
SM		 726 } while (1);
727
728 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
8b1c2ba2 729 msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
9d2bd738
SM		 730
731 if (!host->curr.xfer_remain)
8b1c2ba2 732 msmsdcc_writel(host, 0, MMCIMASK1);
9d2bd738
SM		 733
734 return IRQ_HANDLED;
735}
736
737static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
738{
739 struct mmc_command *cmd = host->curr.cmd;
9d2bd738
SM		 740
741 host->curr.cmd = NULL;
8b1c2ba2
SM		 742 cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
743 cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
744 cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
745 cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
9d2bd738 746
9d2bd738
SM		 747 if (status & MCI_CMDTIMEOUT) {
748 cmd->error = -ETIMEDOUT;
749 } else if (status & MCI_CMDCRCFAIL &&
750 cmd->flags & MMC_RSP_CRC) {
0a7ff7c7 751 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
9d2bd738
SM		 752 cmd->error = -EILSEQ;
753 }
754
755 if (!cmd->data || cmd->error) {
756 if (host->curr.data && host->dma.sg)
757 msm_dmov_stop_cmd(host->dma.channel,
758 &host->dma.hdr, 0);
759 else if (host->curr.data) { /* Non DMA */
b08bb35d 760 msmsdcc_reset_and_restore(host);
9d2bd738
SM		 761 msmsdcc_stop_data(host);
762 msmsdcc_request_end(host, cmd->mrq);
d5137bdd
ST		 763 } else { /* host->data == NULL */
764 if (!cmd->error && host->prog_enable) {
765 if (status & MCI_PROGDONE) {
766 host->prog_scan = false;
767 host->prog_enable = false;
768 msmsdcc_request_end(host, cmd->mrq);
769 } else {
770 host->curr.cmd = cmd;
771 }
772 } else {
773 if (host->prog_enable) {
774 host->prog_scan = false;
775 host->prog_enable = false;
776 }
777 msmsdcc_request_end(host, cmd->mrq);
778 }
779 }
56a8b5b8
SM		 780 } else if (cmd->data)
781 if (!(cmd->data->flags & MMC_DATA_READ))
782 msmsdcc_start_data(host, cmd->data,
783 NULL, 0);
9d2bd738
SM		 784}
785
b5a74d60
JP		 786static void
787msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
788 void __iomem *base)
789{
790 struct mmc_data *data = host->curr.data;
791
56a8b5b8 792 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
d5137bdd 793 MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) {
56a8b5b8
SM		 794 msmsdcc_do_cmdirq(host, status);
795 }
796
b5a74d60
JP		 797 if (!data)
798 return;
799
800 /* Check for data errors */
801 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
802 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
803 msmsdcc_data_err(host, data, status);
804 host->curr.data_xfered = 0;
805 if (host->dma.sg)
806 msm_dmov_stop_cmd(host->dma.channel,
807 &host->dma.hdr, 0);
808 else {
b08bb35d 809 msmsdcc_reset_and_restore(host);
b3b0ca84
SM		 810 if (host->curr.data)
811 msmsdcc_stop_data(host);
b5a74d60
JP		 812 if (!data->stop)
813 msmsdcc_request_end(host, data->mrq);
814 else
815 msmsdcc_start_command(host, data->stop, 0);
816 }
817 }
818
819 /* Check for data done */
820 if (!host->curr.got_dataend && (status & MCI_DATAEND))
821 host->curr.got_dataend = 1;
822
b5a74d60
JP		 823 /*
824 * If DMA is still in progress, we complete via the completion handler
825 */
0c521ccb 826 if (host->curr.got_dataend && !host->dma.busy) {
b5a74d60
JP		 827 /*
828 * There appears to be an issue in the controller where
829 * if you request a small block transfer (< fifo size),
830 * you may get your DATAEND/DATABLKEND irq without the
831 * PIO data irq.
832 *
833 * Check to see if there is still data to be read,
834 * and simulate a PIO irq.
835 */
836 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
837 msmsdcc_pio_irq(1, host);
838
839 msmsdcc_stop_data(host);
840 if (!data->error)
841 host->curr.data_xfered = host->curr.xfer_size;
842
843 if (!data->stop)
844 msmsdcc_request_end(host, data->mrq);
845 else
846 msmsdcc_start_command(host, data->stop, 0);
847 }
848}
849
9d2bd738
SM		 850static irqreturn_t
851msmsdcc_irq(int irq, void *dev_id)
852{
853 struct msmsdcc_host *host = dev_id;
854 void __iomem *base = host->base;
855 u32 status;
856 int ret = 0;
857 int cardint = 0;
858
859 spin_lock(&host->lock);
860
861 do {
8b1c2ba2 862 status = msmsdcc_readl(host, MMCISTATUS);
0c521ccb 863 status &= msmsdcc_readl(host, MMCIMASK0);
8b1c2ba2 864 msmsdcc_writel(host, status, MMCICLEAR);
9d2bd738 865
865c8064
SM		 866 if (status & MCI_SDIOINTR)
867 status &= ~MCI_SDIOINTR;
9d2bd738 868
865c8064
SM		 869 if (!status)
870 break;
9d2bd738 871
b5a74d60 872 msmsdcc_handle_irq_data(host, status, base);
9d2bd738
SM		 873
874 if (status & MCI_SDIOINTOPER) {
875 cardint = 1;
876 status &= ~MCI_SDIOINTOPER;
877 }
878 ret = 1;
879 } while (status);
880
881 spin_unlock(&host->lock);
882
883 /*
884 * We have to delay handling the card interrupt as it calls
885 * back into the driver.
886 */
887 if (cardint)
888 mmc_signal_sdio_irq(host->mmc);
889
890 return IRQ_RETVAL(ret);
891}
892
893static void
894msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
895{
896 struct msmsdcc_host *host = mmc_priv(mmc);
897 unsigned long flags;
898
899 WARN_ON(host->curr.mrq != NULL);
900 WARN_ON(host->pwr == 0);
901
902 spin_lock_irqsave(&host->lock, flags);
903
904 host->stats.reqs++;
905
906 if (host->eject) {
907 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
908 mrq->cmd->error = 0;
909 mrq->data->bytes_xfered = mrq->data->blksz *
910 mrq->data->blocks;
911 } else
912 mrq->cmd->error = -ENOMEDIUM;
913
914 spin_unlock_irqrestore(&host->lock, flags);
915 mmc_request_done(mmc, mrq);
916 return;
917 }
918
d0719e59 919 msmsdcc_enable_clocks(host);
9d2bd738 920
9d2bd738
SM		 921 host->curr.mrq = mrq;
922
923 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
56a8b5b8
SM		 924 /* Queue/read data, daisy-chain command when data starts */
925 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
926 else
927 msmsdcc_start_command(host, mrq->cmd, 0);
9d2bd738
SM		 928
929 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
930 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
931 CMD_SPINMAX)) {
8b1c2ba2 932 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738 933 msmsdcc_do_cmdirq(host, status);
8b1c2ba2
SM		 934 msmsdcc_writel(host,
935 MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
936 MMCICLEAR);
9d2bd738
SM		 937 host->stats.cmdpoll_hits++;
938 } else {
939 host->stats.cmdpoll_misses++;
9d2bd738
SM		 940 }
941 spin_unlock_irqrestore(&host->lock, flags);
942}
943
944static void
945msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
946{
947 struct msmsdcc_host *host = mmc_priv(mmc);
948 u32 clk = 0, pwr = 0;
949 int rc;
4adbbcc7 950 unsigned long flags;
9d2bd738 951
c7fc9370 952 spin_lock_irqsave(&host->lock, flags);
9d2bd738 953
d0719e59
SM		 954 msmsdcc_enable_clocks(host);
955
865c8064 956 if (ios->clock) {
9d2bd738
SM		 957 if (ios->clock != host->clk_rate) {
958 rc = clk_set_rate(host->clk, ios->clock);
959 if (rc < 0)
0a7ff7c7
JP		 960 pr_err("%s: Error setting clock rate (%d)\n",
961 mmc_hostname(host->mmc), rc);
9d2bd738
SM		 962 else
963 host->clk_rate = ios->clock;
964 }
965 clk |= MCI_CLK_ENABLE;
966 }
967
968 if (ios->bus_width == MMC_BUS_WIDTH_4)
969 clk |= (2 << 10); /* Set WIDEBUS */
970
971 if (ios->clock > 400000 && msmsdcc_pwrsave)
972 clk |= (1 << 9); /* PWRSAVE */
973
974 clk |= (1 << 12); /* FLOW_ENA */
975 clk |= (1 << 15); /* feedback clock */
976
977 if (host->plat->translate_vdd)
978 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
979
980 switch (ios->power_mode) {
981 case MMC_POWER_OFF:
9d2bd738
SM		 982 break;
983 case MMC_POWER_UP:
984 pwr |= MCI_PWR_UP;
985 break;
986 case MMC_POWER_ON:
9d2bd738
SM		 987 pwr |= MCI_PWR_ON;
988 break;
989 }
990
991 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
992 pwr |= MCI_OD;
993
8b1c2ba2 994 msmsdcc_writel(host, clk, MMCICLOCK);
9d2bd738
SM		 995
996 if (host->pwr != pwr) {
997 host->pwr = pwr;
8b1c2ba2 998 msmsdcc_writel(host, pwr, MMCIPOWER);
9d2bd738 999 }
f4748499 1000#if BUSCLK_PWRSAVE
c7fc9370 1001 msmsdcc_disable_clocks(host, 1);
f4748499 1002#endif
4adbbcc7 1003 spin_unlock_irqrestore(&host->lock, flags);
9d2bd738
SM		 1004}
1005
1006static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1007{
1008 struct msmsdcc_host *host = mmc_priv(mmc);
1009 unsigned long flags;
1010 u32 status;
1011
1012 spin_lock_irqsave(&host->lock, flags);
1013 if (msmsdcc_sdioirq == 1) {
8b1c2ba2 1014 status = msmsdcc_readl(host, MMCIMASK0);
9d2bd738
SM		 1015 if (enable)
1016 status |= MCI_SDIOINTOPERMASK;
1017 else
1018 status &= ~MCI_SDIOINTOPERMASK;
1019 host->saved_irq0mask = status;
8b1c2ba2 1020 msmsdcc_writel(host, status, MMCIMASK0);
9d2bd738
SM		 1021 }
1022 spin_unlock_irqrestore(&host->lock, flags);
1023}
1024
1025static const struct mmc_host_ops msmsdcc_ops = {
1026 .request = msmsdcc_request,
1027 .set_ios = msmsdcc_set_ios,
1028 .enable_sdio_irq = msmsdcc_enable_sdio_irq,
1029};
1030
1031static void
1032msmsdcc_check_status(unsigned long data)
1033{
1034 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
1035 unsigned int status;
1036
1037 if (!host->plat->status) {
1038 mmc_detect_change(host->mmc, 0);
1039 goto out;
1040 }
1041
1042 status = host->plat->status(mmc_dev(host->mmc));
1043 host->eject = !status;
1044 if (status ^ host->oldstat) {
0a7ff7c7
JP		 1045 pr_info("%s: Slot status change detected (%d -> %d)\n",
1046 mmc_hostname(host->mmc), host->oldstat, status);
9d2bd738
SM		 1047 if (status)
1048 mmc_detect_change(host->mmc, (5 * HZ) / 2);
1049 else
1050 mmc_detect_change(host->mmc, 0);
1051 }
1052
1053 host->oldstat = status;
1054
1055out:
1056 if (host->timer.function)
1057 mod_timer(&host->timer, jiffies + HZ);
1058}
1059
1060static irqreturn_t
1061msmsdcc_platform_status_irq(int irq, void *dev_id)
1062{
1063 struct msmsdcc_host *host = dev_id;
1064
1065 printk(KERN_DEBUG "%s: %d\n", __func__, irq);
1066 msmsdcc_check_status((unsigned long) host);
1067 return IRQ_HANDLED;
1068}
1069
1070static void
1071msmsdcc_status_notify_cb(int card_present, void *dev_id)
1072{
1073 struct msmsdcc_host *host = dev_id;
1074
1075 printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
1076 card_present);
1077 msmsdcc_check_status((unsigned long) host);
1078}
1079
9d2bd738 1080static void
865c8064 1081msmsdcc_busclk_expired(unsigned long _data)
9d2bd738
SM		 1082{
1083 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
9d2bd738 1084
865c8064 1085 if (host->clks_on)
c7fc9370 1086 msmsdcc_disable_clocks(host, 0);
9d2bd738
SM		 1087}
1088
1089static int
1090msmsdcc_init_dma(struct msmsdcc_host *host)
1091{
1092 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1093 host->dma.host = host;
1094 host->dma.channel = -1;
1095
1096 if (!host->dmares)
1097 return -ENODEV;
1098
1099 host->dma.nc = dma_alloc_coherent(NULL,
1100 sizeof(struct msmsdcc_nc_dmadata),
1101 &host->dma.nc_busaddr,
1102 GFP_KERNEL);
1103 if (host->dma.nc == NULL) {
0a7ff7c7 1104 pr_err("Unable to allocate DMA buffer\n");
9d2bd738
SM		 1105 return -ENOMEM;
1106 }
1107 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1108 host->dma.cmd_busaddr = host->dma.nc_busaddr;
1109 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1110 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1111 host->dma.channel = host->dmares->start;
1112
1113 return 0;
1114}
1115
9d2bd738
SM		 1116static int
1117msmsdcc_probe(struct platform_device *pdev)
1118{
b5d643de 1119 struct msm_mmc_platform_data *plat = pdev->dev.platform_data;
9d2bd738
SM		 1120 struct msmsdcc_host *host;
1121 struct mmc_host *mmc;
1122 struct resource *cmd_irqres = NULL;
1123 struct resource *pio_irqres = NULL;
1124 struct resource *stat_irqres = NULL;
1125 struct resource *memres = NULL;
1126 struct resource *dmares = NULL;
1127 int ret;
1128
1129 /* must have platform data */
1130 if (!plat) {
0a7ff7c7 1131 pr_err("%s: Platform data not available\n", __func__);
9d2bd738
SM		 1132 ret = -EINVAL;
1133 goto out;
1134 }
1135
1136 if (pdev->id < 1 || pdev->id > 4)
1137 return -EINVAL;
1138
1139 if (pdev->resource == NULL || pdev->num_resources < 2) {
0a7ff7c7 1140 pr_err("%s: Invalid resource\n", __func__);
9d2bd738
SM		 1141 return -ENXIO;
1142 }
1143
1144 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1146 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1147 "cmd_irq");
1148 pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1149 "pio_irq");
1150 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1151 "status_irq");
1152
1153 if (!cmd_irqres || !pio_irqres || !memres) {
0a7ff7c7 1154 pr_err("%s: Invalid resource\n", __func__);
9d2bd738
SM		 1155 return -ENXIO;
1156 }
1157
1158 /*
1159 * Setup our host structure
1160 */
1161
1162 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1163 if (!mmc) {
1164 ret = -ENOMEM;
1165 goto out;
1166 }
1167
1168 host = mmc_priv(mmc);
1169 host->pdev_id = pdev->id;
1170 host->plat = plat;
1171 host->mmc = mmc;
56a8b5b8 1172 host->curr.cmd = NULL;
9d2bd738
SM		 1173
1174 host->cmdpoll = 1;
1175
1176 host->base = ioremap(memres->start, PAGE_SIZE);
1177 if (!host->base) {
1178 ret = -ENOMEM;
1179 goto out;
1180 }
1181
1182 host->cmd_irqres = cmd_irqres;
1183 host->pio_irqres = pio_irqres;
1184 host->memres = memres;
1185 host->dmares = dmares;
1186 spin_lock_init(&host->lock);
1187
62612cf9
ST		 1188 tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet,
1189 (unsigned long)host);
1190
9d2bd738
SM		 1191 /*
1192 * Setup DMA
1193 */
1194 msmsdcc_init_dma(host);
1195
4adbbcc7 1196 /* Get our clocks */
9d2bd738
SM		 1197 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1198 if (IS_ERR(host->pclk)) {
1199 ret = PTR_ERR(host->pclk);
1200 goto host_free;
1201 }
1202
9d2bd738
SM		 1203 host->clk = clk_get(&pdev->dev, "sdc_clk");
1204 if (IS_ERR(host->clk)) {
1205 ret = PTR_ERR(host->clk);
4adbbcc7 1206 goto pclk_put;
9d2bd738
SM		 1207 }
1208
4adbbcc7 1209 /* Enable clocks */
c7fc9370 1210 ret = msmsdcc_enable_clocks(host);
9d2bd738
SM		 1211 if (ret)
1212 goto clk_put;
1213
1214 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1215 if (ret) {
0a7ff7c7 1216 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
9d2bd738
SM		 1217 goto clk_disable;
1218 }
1219
4adbbcc7 1220 host->pclk_rate = clk_get_rate(host->pclk);
9d2bd738
SM		 1221 host->clk_rate = clk_get_rate(host->clk);
1222
9d2bd738
SM		 1223 /*
1224 * Setup MMC host structure
1225 */
1226 mmc->ops = &msmsdcc_ops;
1227 mmc->f_min = msmsdcc_fmin;
1228 mmc->f_max = msmsdcc_fmax;
1229 mmc->ocr_avail = plat->ocr_mask;
1230
1231 if (msmsdcc_4bit)
1232 mmc->caps |= MMC_CAP_4_BIT_DATA;
1233 if (msmsdcc_sdioirq)
1234 mmc->caps |= MMC_CAP_SDIO_IRQ;
1235 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1236
a36274e0 1237 mmc->max_segs = NR_SG;
9d2bd738
SM		 1238 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1239 mmc->max_blk_count = 65536;
1240
1241 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
1242 mmc->max_seg_size = mmc->max_req_size;
1243
8b1c2ba2
SM		 1244 msmsdcc_writel(host, 0, MMCIMASK0);
1245 msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
9d2bd738 1246
8b1c2ba2 1247 msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
9d2bd738
SM		 1248 host->saved_irq0mask = MCI_IRQENABLE;
1249
1250 /*
1251 * Setup card detect change
1252 */
1253
1254 memset(&host->timer, 0, sizeof(host->timer));
1255
1256 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1257 unsigned long irqflags = IRQF_SHARED |
1258 (stat_irqres->flags & IRQF_TRIGGER_MASK);
1259
1260 host->stat_irq = stat_irqres->start;
1261 ret = request_irq(host->stat_irq,
1262 msmsdcc_platform_status_irq,
1263 irqflags,
1264 DRIVER_NAME " (slot)",
1265 host);
1266 if (ret) {
0a7ff7c7
JP		 1267 pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1268 mmc_hostname(mmc), host->stat_irq, ret);
9d2bd738
SM		 1269 goto clk_disable;
1270 }
1271 } else if (plat->register_status_notify) {
1272 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1273 } else if (!plat->status)
0a7ff7c7 1274 pr_err("%s: No card detect facilities available\n",
9d2bd738
SM		 1275 mmc_hostname(mmc));
1276 else {
1277 init_timer(&host->timer);
1278 host->timer.data = (unsigned long)host;
1279 host->timer.function = msmsdcc_check_status;
1280 host->timer.expires = jiffies + HZ;
1281 add_timer(&host->timer);
1282 }
1283
1284 if (plat->status) {
1285 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1286 host->eject = !host->oldstat;
1287 }
1288
865c8064
SM		 1289 init_timer(&host->busclk_timer);
1290 host->busclk_timer.data = (unsigned long) host;
1291 host->busclk_timer.function = msmsdcc_busclk_expired;
9d2bd738
SM		 1292
1293 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1294 DRIVER_NAME " (cmd)", host);
1295 if (ret)
1296 goto stat_irq_free;
1297
1298 ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1299 DRIVER_NAME " (pio)", host);
1300 if (ret)
1301 goto cmd_irq_free;
1302
1303 mmc_set_drvdata(pdev, mmc);
1304 mmc_add_host(mmc);
1305
0a7ff7c7
JP		 1306 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1307 mmc_hostname(mmc), (unsigned long long)memres->start,
1308 (unsigned int) cmd_irqres->start,
1309 (unsigned int) host->stat_irq, host->dma.channel);
1310 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1311 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1312 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1313 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1314 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1315 pr_info("%s: Power save feature enable = %d\n",
1316 mmc_hostname(mmc), msmsdcc_pwrsave);
9d2bd738
SM		 1317
1318 if (host->dma.channel != -1) {
0a7ff7c7
JP		 1319 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1320 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1321 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1322 mmc_hostname(mmc), host->dma.cmd_busaddr,
1323 host->dma.cmdptr_busaddr);
9d2bd738 1324 } else
0a7ff7c7 1325 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
9d2bd738 1326 if (host->timer.function)
0a7ff7c7 1327 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
9d2bd738
SM		 1328
1329 return 0;
1330 cmd_irq_free:
1331 free_irq(cmd_irqres->start, host);
1332 stat_irq_free:
1333 if (host->stat_irq)
1334 free_irq(host->stat_irq, host);
1335 clk_disable:
c7fc9370 1336 msmsdcc_disable_clocks(host, 0);
9d2bd738
SM		 1337 clk_put:
1338 clk_put(host->clk);
9d2bd738
SM		 1339 pclk_put:
1340 clk_put(host->pclk);
1341 host_free:
1342 mmc_free_host(mmc);
1343 out:
1344 return ret;
1345}
1346
08ecfde4
DW		 1347#ifdef CONFIG_PM
1348#ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1349static void
1350do_resume_work(struct work_struct *work)
1351{
1352 struct msmsdcc_host *host =
1353 container_of(work, struct msmsdcc_host, resume_task);
1354 struct mmc_host *mmc = host->mmc;
1355
1356 if (mmc) {
1357 mmc_resume_host(mmc);
1358 if (host->stat_irq)
1359 enable_irq(host->stat_irq);
1360 }
1361}
1362#endif
1363
1364
9d2bd738
SM		 1365static int
1366msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1367{
1368 struct mmc_host *mmc = mmc_get_drvdata(dev);
1369 int rc = 0;
1370
1371 if (mmc) {
1372 struct msmsdcc_host *host = mmc_priv(mmc);
1373
1374 if (host->stat_irq)
1375 disable_irq(host->stat_irq);
1376
1377 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1a13f8fa 1378 rc = mmc_suspend_host(mmc);
d0719e59 1379 if (!rc)
8b1c2ba2 1380 msmsdcc_writel(host, 0, MMCIMASK0);
c7fc9370
SM		 1381 if (host->clks_on)
1382 msmsdcc_disable_clocks(host, 0);
9d2bd738
SM		 1383 }
1384 return rc;
1385}
1386
1387static int
1388msmsdcc_resume(struct platform_device *dev)
1389{
1390 struct mmc_host *mmc = mmc_get_drvdata(dev);
9d2bd738
SM		 1391
1392 if (mmc) {
1393 struct msmsdcc_host *host = mmc_priv(mmc);
1394
c7fc9370 1395 msmsdcc_enable_clocks(host);
9d2bd738 1396
8b1c2ba2 1397 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
9d2bd738
SM		 1398
1399 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1400 mmc_resume_host(mmc);
5b8a2fb3 1401 if (host->stat_irq)
9d2bd738 1402 enable_irq(host->stat_irq);
f4748499 1403#if BUSCLK_PWRSAVE
c7fc9370 1404 msmsdcc_disable_clocks(host, 1);
f4748499 1405#endif
9d2bd738
SM		 1406 }
1407 return 0;
1408}
08ecfde4
DW		 1409#else
1410#define msmsdcc_suspend 0
1411#define msmsdcc_resume 0
1412#endif
9d2bd738
SM		 1413
1414static struct platform_driver msmsdcc_driver = {
1415 .probe = msmsdcc_probe,
1416 .suspend = msmsdcc_suspend,
1417 .resume = msmsdcc_resume,
1418 .driver = {
1419 .name = "msm_sdcc",
1420 },
1421};
1422
1423static int __init msmsdcc_init(void)
1424{
1425 return platform_driver_register(&msmsdcc_driver);
1426}
1427
1428static void __exit msmsdcc_exit(void)
1429{
1430 platform_driver_unregister(&msmsdcc_driver);
1431}
1432
1433module_init(msmsdcc_init);
1434module_exit(msmsdcc_exit);
1435
1436MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1437MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)