Commit | Line | Data |
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9d2bd738 SM |
1 | /* |
2 | * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver | |
3 | * | |
4 | * Copyright (C) 2007 Google Inc, | |
5 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
56a8b5b8 | 6 | * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved. |
9d2bd738 SM |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Based on mmci.c | |
13 | * | |
14 | * Author: San Mehat (san@android.com) | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/moduleparam.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/highmem.h> | |
27 | #include <linux/log2.h> | |
28 | #include <linux/mmc/host.h> | |
29 | #include <linux/mmc/card.h> | |
b3fa5791 | 30 | #include <linux/mmc/sdio.h> |
9d2bd738 SM |
31 | #include <linux/clk.h> |
32 | #include <linux/scatterlist.h> | |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/debugfs.h> | |
36 | #include <linux/io.h> | |
37 | #include <linux/memory.h> | |
5a0e3ad6 | 38 | #include <linux/gfp.h> |
9d2bd738 SM |
39 | |
40 | #include <asm/cacheflush.h> | |
41 | #include <asm/div64.h> | |
42 | #include <asm/sizes.h> | |
43 | ||
3989d178 | 44 | #include <mach/mmc.h> |
9d2bd738 SM |
45 | #include <mach/msm_iomap.h> |
46 | #include <mach/dma.h> | |
b08bb35d | 47 | #include <mach/clk.h> |
9d2bd738 | 48 | |
9d2bd738 SM |
49 | #include "msm_sdcc.h" |
50 | ||
51 | #define DRIVER_NAME "msm-sdcc" | |
52 | ||
24bbd7d5 | 53 | #define BUSCLK_PWRSAVE 1 |
c7fc9370 | 54 | #define BUSCLK_TIMEOUT (HZ) |
9d2bd738 SM |
55 | static unsigned int msmsdcc_fmin = 144000; |
56 | static unsigned int msmsdcc_fmax = 50000000; | |
57 | static unsigned int msmsdcc_4bit = 1; | |
58 | static unsigned int msmsdcc_pwrsave = 1; | |
59 | static unsigned int msmsdcc_piopoll = 1; | |
60 | static unsigned int msmsdcc_sdioirq; | |
61 | ||
62 | #define PIO_SPINMAX 30 | |
63 | #define CMD_SPINMAX 20 | |
64 | ||
865c8064 | 65 | |
d0719e59 | 66 | static inline void |
c7fc9370 | 67 | msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr) |
865c8064 | 68 | { |
c7fc9370 | 69 | WARN_ON(!host->clks_on); |
8b1c2ba2 | 70 | |
f4748499 SM |
71 | BUG_ON(host->curr.mrq); |
72 | ||
c7fc9370 SM |
73 | if (deferr) { |
74 | mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT); | |
865c8064 | 75 | } else { |
c7fc9370 | 76 | del_timer_sync(&host->busclk_timer); |
d0719e59 SM |
77 | /* Need to check clks_on again in case the busclk |
78 | * timer fired | |
79 | */ | |
80 | if (host->clks_on) { | |
81 | clk_disable(host->clk); | |
82 | clk_disable(host->pclk); | |
83 | host->clks_on = 0; | |
84 | } | |
865c8064 | 85 | } |
c7fc9370 SM |
86 | } |
87 | ||
88 | static inline int | |
89 | msmsdcc_enable_clocks(struct msmsdcc_host *host) | |
90 | { | |
91 | int rc; | |
92 | ||
c7fc9370 SM |
93 | del_timer_sync(&host->busclk_timer); |
94 | ||
d0719e59 SM |
95 | if (!host->clks_on) { |
96 | rc = clk_enable(host->pclk); | |
97 | if (rc) | |
98 | return rc; | |
99 | rc = clk_enable(host->clk); | |
100 | if (rc) { | |
101 | clk_disable(host->pclk); | |
102 | return rc; | |
103 | } | |
104 | udelay(1 + ((3 * USEC_PER_SEC) / | |
105 | (host->clk_rate ? host->clk_rate : msmsdcc_fmin))); | |
106 | host->clks_on = 1; | |
c7fc9370 | 107 | } |
865c8064 SM |
108 | return 0; |
109 | } | |
110 | ||
8b1c2ba2 SM |
111 | static inline unsigned int |
112 | msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg) | |
113 | { | |
114 | return readl(host->base + reg); | |
115 | } | |
116 | ||
117 | static inline void | |
118 | msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg) | |
119 | { | |
120 | writel(data, host->base + reg); | |
121 | /* 3 clk delay required! */ | |
122 | udelay(1 + ((3 * USEC_PER_SEC) / | |
123 | (host->clk_rate ? host->clk_rate : msmsdcc_fmin))); | |
124 | } | |
865c8064 | 125 | |
9d2bd738 SM |
126 | static void |
127 | msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, | |
128 | u32 c); | |
129 | ||
b08bb35d ST |
130 | static void msmsdcc_reset_and_restore(struct msmsdcc_host *host) |
131 | { | |
132 | u32 mci_clk = 0; | |
133 | u32 mci_mask0 = 0; | |
134 | int ret = 0; | |
135 | ||
136 | /* Save the controller state */ | |
137 | mci_clk = readl(host->base + MMCICLOCK); | |
138 | mci_mask0 = readl(host->base + MMCIMASK0); | |
139 | ||
140 | /* Reset the controller */ | |
141 | ret = clk_reset(host->clk, CLK_RESET_ASSERT); | |
142 | if (ret) | |
143 | pr_err("%s: Clock assert failed at %u Hz with err %d\n", | |
144 | mmc_hostname(host->mmc), host->clk_rate, ret); | |
145 | ||
146 | ret = clk_reset(host->clk, CLK_RESET_DEASSERT); | |
147 | if (ret) | |
148 | pr_err("%s: Clock deassert failed at %u Hz with err %d\n", | |
149 | mmc_hostname(host->mmc), host->clk_rate, ret); | |
150 | ||
151 | pr_info("%s: Controller has been re-initialiazed\n", | |
152 | mmc_hostname(host->mmc)); | |
153 | ||
154 | /* Restore the contoller state */ | |
155 | writel(host->pwr, host->base + MMCIPOWER); | |
156 | writel(mci_clk, host->base + MMCICLOCK); | |
157 | writel(mci_mask0, host->base + MMCIMASK0); | |
158 | ret = clk_set_rate(host->clk, host->clk_rate); | |
159 | if (ret) | |
160 | pr_err("%s: Failed to set clk rate %u Hz (%d)\n", | |
161 | mmc_hostname(host->mmc), host->clk_rate, ret); | |
162 | } | |
163 | ||
9d2bd738 SM |
164 | static void |
165 | msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq) | |
166 | { | |
9d2bd738 SM |
167 | BUG_ON(host->curr.data); |
168 | ||
169 | host->curr.mrq = NULL; | |
170 | host->curr.cmd = NULL; | |
171 | ||
172 | if (mrq->data) | |
173 | mrq->data->bytes_xfered = host->curr.data_xfered; | |
174 | if (mrq->cmd->error == -ETIMEDOUT) | |
175 | mdelay(5); | |
176 | ||
f4748499 | 177 | #if BUSCLK_PWRSAVE |
c7fc9370 | 178 | msmsdcc_disable_clocks(host, 1); |
f4748499 | 179 | #endif |
9d2bd738 SM |
180 | /* |
181 | * Need to drop the host lock here; mmc_request_done may call | |
182 | * back into the driver... | |
183 | */ | |
184 | spin_unlock(&host->lock); | |
185 | mmc_request_done(host->mmc, mrq); | |
186 | spin_lock(&host->lock); | |
187 | } | |
188 | ||
189 | static void | |
190 | msmsdcc_stop_data(struct msmsdcc_host *host) | |
191 | { | |
9d2bd738 SM |
192 | host->curr.data = NULL; |
193 | host->curr.got_dataend = host->curr.got_datablkend = 0; | |
194 | } | |
195 | ||
196 | uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host) | |
197 | { | |
edd4dd0e | 198 | return host->memres->start + MMCIFIFO; |
9d2bd738 SM |
199 | } |
200 | ||
56a8b5b8 SM |
201 | static inline void |
202 | msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) { | |
203 | msmsdcc_writel(host, arg, MMCIARGUMENT); | |
204 | msmsdcc_writel(host, c, MMCICOMMAND); | |
205 | } | |
206 | ||
207 | static void | |
208 | msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd) | |
209 | { | |
6ac9ea69 | 210 | struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data; |
56a8b5b8 | 211 | |
6ac9ea69 | 212 | msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER); |
d0719e59 SM |
213 | msmsdcc_writel(host, (unsigned int)host->curr.xfer_size, |
214 | MMCIDATALENGTH); | |
6ac9ea69 SM |
215 | msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1); |
216 | msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL); | |
56a8b5b8 | 217 | |
6ac9ea69 SM |
218 | if (host->cmd_cmd) { |
219 | msmsdcc_start_command_exec(host, | |
220 | (u32) host->cmd_cmd->arg, | |
221 | (u32) host->cmd_c); | |
222 | } | |
56a8b5b8 SM |
223 | host->dma.active = 1; |
224 | } | |
225 | ||
9d2bd738 | 226 | static void |
62612cf9 | 227 | msmsdcc_dma_complete_tlet(unsigned long data) |
9d2bd738 | 228 | { |
62612cf9 | 229 | struct msmsdcc_host *host = (struct msmsdcc_host *)data; |
9d2bd738 SM |
230 | unsigned long flags; |
231 | struct mmc_request *mrq; | |
62612cf9 | 232 | struct msm_dmov_errdata err; |
9d2bd738 SM |
233 | |
234 | spin_lock_irqsave(&host->lock, flags); | |
56a8b5b8 SM |
235 | host->dma.active = 0; |
236 | ||
62612cf9 | 237 | err = host->dma.err; |
9d2bd738 SM |
238 | mrq = host->curr.mrq; |
239 | BUG_ON(!mrq); | |
b3b0ca84 | 240 | WARN_ON(!mrq->data); |
9d2bd738 | 241 | |
62612cf9 | 242 | if (!(host->dma.result & DMOV_RSLT_VALID)) { |
0a7ff7c7 | 243 | pr_err("msmsdcc: Invalid DataMover result\n"); |
9d2bd738 SM |
244 | goto out; |
245 | } | |
246 | ||
62612cf9 | 247 | if (host->dma.result & DMOV_RSLT_DONE) { |
9d2bd738 SM |
248 | host->curr.data_xfered = host->curr.xfer_size; |
249 | } else { | |
250 | /* Error or flush */ | |
62612cf9 | 251 | if (host->dma.result & DMOV_RSLT_ERROR) |
0a7ff7c7 | 252 | pr_err("%s: DMA error (0x%.8x)\n", |
62612cf9 ST |
253 | mmc_hostname(host->mmc), host->dma.result); |
254 | if (host->dma.result & DMOV_RSLT_FLUSH) | |
0a7ff7c7 | 255 | pr_err("%s: DMA channel flushed (0x%.8x)\n", |
62612cf9 ST |
256 | mmc_hostname(host->mmc), host->dma.result); |
257 | ||
258 | pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n", | |
259 | err.flush[0], err.flush[1], err.flush[2], | |
260 | err.flush[3], err.flush[4], err.flush[5]); | |
b08bb35d ST |
261 | |
262 | msmsdcc_reset_and_restore(host); | |
9d2bd738 SM |
263 | if (!mrq->data->error) |
264 | mrq->data->error = -EIO; | |
265 | } | |
9d2bd738 SM |
266 | dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents, |
267 | host->dma.dir); | |
268 | ||
269 | if (host->curr.user_pages) { | |
270 | struct scatterlist *sg = host->dma.sg; | |
271 | int i; | |
272 | ||
75d14528 JP |
273 | for (i = 0; i < host->dma.num_ents; i++) |
274 | flush_dcache_page(sg_page(sg++)); | |
9d2bd738 SM |
275 | } |
276 | ||
277 | host->dma.sg = NULL; | |
56a8b5b8 | 278 | host->dma.busy = 0; |
9d2bd738 SM |
279 | |
280 | if ((host->curr.got_dataend && host->curr.got_datablkend) | |
281 | || mrq->data->error) { | |
282 | ||
283 | /* | |
284 | * If we've already gotten our DATAEND / DATABLKEND | |
285 | * for this request, then complete it through here. | |
286 | */ | |
287 | msmsdcc_stop_data(host); | |
288 | ||
289 | if (!mrq->data->error) | |
290 | host->curr.data_xfered = host->curr.xfer_size; | |
291 | if (!mrq->data->stop || mrq->cmd->error) { | |
9d2bd738 SM |
292 | host->curr.mrq = NULL; |
293 | host->curr.cmd = NULL; | |
294 | mrq->data->bytes_xfered = host->curr.data_xfered; | |
295 | ||
296 | spin_unlock_irqrestore(&host->lock, flags); | |
f4748499 | 297 | #if BUSCLK_PWRSAVE |
c7fc9370 | 298 | msmsdcc_disable_clocks(host, 1); |
f4748499 | 299 | #endif |
9d2bd738 SM |
300 | mmc_request_done(host->mmc, mrq); |
301 | return; | |
302 | } else | |
303 | msmsdcc_start_command(host, mrq->data->stop, 0); | |
304 | } | |
305 | ||
306 | out: | |
307 | spin_unlock_irqrestore(&host->lock, flags); | |
308 | return; | |
309 | } | |
310 | ||
62612cf9 ST |
311 | static void |
312 | msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd, | |
313 | unsigned int result, | |
314 | struct msm_dmov_errdata *err) | |
315 | { | |
316 | struct msmsdcc_dma_data *dma_data = | |
317 | container_of(cmd, struct msmsdcc_dma_data, hdr); | |
318 | struct msmsdcc_host *host = dma_data->host; | |
319 | ||
320 | dma_data->result = result; | |
321 | if (err) | |
322 | memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata)); | |
323 | ||
324 | tasklet_schedule(&host->dma_tlet); | |
325 | } | |
326 | ||
9d2bd738 SM |
327 | static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data) |
328 | { | |
329 | if (host->dma.channel == -1) | |
330 | return -ENOENT; | |
331 | ||
332 | if ((data->blksz * data->blocks) < MCI_FIFOSIZE) | |
333 | return -EINVAL; | |
334 | if ((data->blksz * data->blocks) % MCI_FIFOSIZE) | |
335 | return -EINVAL; | |
336 | return 0; | |
337 | } | |
338 | ||
339 | static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data) | |
340 | { | |
341 | struct msmsdcc_nc_dmadata *nc; | |
342 | dmov_box *box; | |
343 | uint32_t rows; | |
344 | uint32_t crci; | |
345 | unsigned int n; | |
346 | int i, rc; | |
347 | struct scatterlist *sg = data->sg; | |
348 | ||
349 | rc = validate_dma(host, data); | |
350 | if (rc) | |
351 | return rc; | |
352 | ||
353 | host->dma.sg = data->sg; | |
354 | host->dma.num_ents = data->sg_len; | |
355 | ||
56a8b5b8 SM |
356 | BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */ |
357 | ||
9d2bd738 SM |
358 | nc = host->dma.nc; |
359 | ||
75d14528 JP |
360 | switch (host->pdev_id) { |
361 | case 1: | |
9d2bd738 | 362 | crci = MSMSDCC_CRCI_SDC1; |
75d14528 JP |
363 | break; |
364 | case 2: | |
9d2bd738 | 365 | crci = MSMSDCC_CRCI_SDC2; |
75d14528 JP |
366 | break; |
367 | case 3: | |
9d2bd738 | 368 | crci = MSMSDCC_CRCI_SDC3; |
75d14528 JP |
369 | break; |
370 | case 4: | |
9d2bd738 | 371 | crci = MSMSDCC_CRCI_SDC4; |
75d14528 JP |
372 | break; |
373 | default: | |
9d2bd738 SM |
374 | host->dma.sg = NULL; |
375 | host->dma.num_ents = 0; | |
376 | return -ENOENT; | |
377 | } | |
378 | ||
379 | if (data->flags & MMC_DATA_READ) | |
380 | host->dma.dir = DMA_FROM_DEVICE; | |
381 | else | |
382 | host->dma.dir = DMA_TO_DEVICE; | |
383 | ||
384 | host->curr.user_pages = 0; | |
385 | ||
9d2bd738 SM |
386 | box = &nc->cmd[0]; |
387 | for (i = 0; i < host->dma.num_ents; i++) { | |
388 | box->cmd = CMD_MODE_BOX; | |
389 | ||
56a8b5b8 SM |
390 | /* Initialize sg dma address */ |
391 | sg->dma_address = page_to_dma(mmc_dev(host->mmc), sg_page(sg)) | |
392 | + sg->offset; | |
393 | ||
394 | if (i == (host->dma.num_ents - 1)) | |
9d2bd738 SM |
395 | box->cmd |= CMD_LC; |
396 | rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ? | |
397 | (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 : | |
398 | (sg_dma_len(sg) / MCI_FIFOSIZE) ; | |
399 | ||
400 | if (data->flags & MMC_DATA_READ) { | |
401 | box->src_row_addr = msmsdcc_fifo_addr(host); | |
402 | box->dst_row_addr = sg_dma_address(sg); | |
403 | ||
404 | box->src_dst_len = (MCI_FIFOSIZE << 16) | | |
405 | (MCI_FIFOSIZE); | |
406 | box->row_offset = MCI_FIFOSIZE; | |
407 | ||
408 | box->num_rows = rows * ((1 << 16) + 1); | |
409 | box->cmd |= CMD_SRC_CRCI(crci); | |
410 | } else { | |
411 | box->src_row_addr = sg_dma_address(sg); | |
412 | box->dst_row_addr = msmsdcc_fifo_addr(host); | |
413 | ||
414 | box->src_dst_len = (MCI_FIFOSIZE << 16) | | |
415 | (MCI_FIFOSIZE); | |
416 | box->row_offset = (MCI_FIFOSIZE << 16); | |
417 | ||
418 | box->num_rows = rows * ((1 << 16) + 1); | |
419 | box->cmd |= CMD_DST_CRCI(crci); | |
420 | } | |
421 | box++; | |
422 | sg++; | |
423 | } | |
424 | ||
425 | /* location of command block must be 64 bit aligned */ | |
426 | BUG_ON(host->dma.cmd_busaddr & 0x07); | |
427 | ||
428 | nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP; | |
429 | host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST | | |
430 | DMOV_CMD_ADDR(host->dma.cmdptr_busaddr); | |
431 | host->dma.hdr.complete_func = msmsdcc_dma_complete_func; | |
432 | ||
56a8b5b8 SM |
433 | n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg, |
434 | host->dma.num_ents, host->dma.dir); | |
435 | /* dsb inside dma_map_sg will write nc out to mem as well */ | |
436 | ||
437 | if (n != host->dma.num_ents) { | |
438 | printk(KERN_ERR "%s: Unable to map in all sg elements\n", | |
439 | mmc_hostname(host->mmc)); | |
440 | host->dma.sg = NULL; | |
441 | host->dma.num_ents = 0; | |
442 | return -ENOMEM; | |
443 | } | |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
448 | static int | |
449 | snoop_cccr_abort(struct mmc_command *cmd) | |
450 | { | |
451 | if ((cmd->opcode == 52) && | |
452 | (cmd->arg & 0x80000000) && | |
453 | (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT)) | |
454 | return 1; | |
9d2bd738 SM |
455 | return 0; |
456 | } | |
457 | ||
458 | static void | |
56a8b5b8 SM |
459 | msmsdcc_start_command_deferred(struct msmsdcc_host *host, |
460 | struct mmc_command *cmd, u32 *c) | |
461 | { | |
462 | *c |= (cmd->opcode | MCI_CPSM_ENABLE); | |
463 | ||
464 | if (cmd->flags & MMC_RSP_PRESENT) { | |
465 | if (cmd->flags & MMC_RSP_136) | |
466 | *c |= MCI_CPSM_LONGRSP; | |
467 | *c |= MCI_CPSM_RESPONSE; | |
468 | } | |
469 | ||
470 | if (/*interrupt*/0) | |
471 | *c |= MCI_CPSM_INTERRUPT; | |
472 | ||
473 | if ((((cmd->opcode == 17) || (cmd->opcode == 18)) || | |
474 | ((cmd->opcode == 24) || (cmd->opcode == 25))) || | |
475 | (cmd->opcode == 53)) | |
476 | *c |= MCI_CSPM_DATCMD; | |
477 | ||
d5137bdd ST |
478 | if (host->prog_scan && (cmd->opcode == 12)) { |
479 | *c |= MCI_CPSM_PROGENA; | |
480 | host->prog_enable = true; | |
481 | } | |
482 | ||
56a8b5b8 SM |
483 | if (cmd == cmd->mrq->stop) |
484 | *c |= MCI_CSPM_MCIABORT; | |
485 | ||
486 | if (snoop_cccr_abort(cmd)) | |
487 | *c |= MCI_CSPM_MCIABORT; | |
488 | ||
489 | if (host->curr.cmd != NULL) { | |
490 | printk(KERN_ERR "%s: Overlapping command requests\n", | |
491 | mmc_hostname(host->mmc)); | |
492 | } | |
493 | host->curr.cmd = cmd; | |
494 | } | |
495 | ||
496 | static void | |
497 | msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data, | |
498 | struct mmc_command *cmd, u32 c) | |
9d2bd738 SM |
499 | { |
500 | unsigned int datactrl, timeout; | |
501 | unsigned long long clks; | |
9d2bd738 SM |
502 | unsigned int pio_irqmask = 0; |
503 | ||
504 | host->curr.data = data; | |
505 | host->curr.xfer_size = data->blksz * data->blocks; | |
506 | host->curr.xfer_remain = host->curr.xfer_size; | |
507 | host->curr.data_xfered = 0; | |
508 | host->curr.got_dataend = 0; | |
509 | host->curr.got_datablkend = 0; | |
510 | ||
511 | memset(&host->pio, 0, sizeof(host->pio)); | |
512 | ||
9d2bd738 SM |
513 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); |
514 | ||
515 | if (!msmsdcc_config_dma(host, data)) | |
516 | datactrl |= MCI_DPSM_DMAENABLE; | |
517 | else { | |
518 | host->pio.sg = data->sg; | |
519 | host->pio.sg_len = data->sg_len; | |
520 | host->pio.sg_off = 0; | |
521 | ||
522 | if (data->flags & MMC_DATA_READ) { | |
523 | pio_irqmask = MCI_RXFIFOHALFFULLMASK; | |
524 | if (host->curr.xfer_remain < MCI_FIFOSIZE) | |
525 | pio_irqmask |= MCI_RXDATAAVLBLMASK; | |
526 | } else | |
527 | pio_irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
528 | } | |
529 | ||
530 | if (data->flags & MMC_DATA_READ) | |
531 | datactrl |= MCI_DPSM_DIRECTION; | |
532 | ||
56a8b5b8 SM |
533 | clks = (unsigned long long)data->timeout_ns * host->clk_rate; |
534 | do_div(clks, NSEC_PER_SEC); | |
535 | timeout = data->timeout_clks + (unsigned int)clks*2 ; | |
9d2bd738 SM |
536 | |
537 | if (datactrl & MCI_DPSM_DMAENABLE) { | |
56a8b5b8 SM |
538 | /* Save parameters for the exec function */ |
539 | host->cmd_timeout = timeout; | |
540 | host->cmd_pio_irqmask = pio_irqmask; | |
541 | host->cmd_datactrl = datactrl; | |
542 | host->cmd_cmd = cmd; | |
543 | ||
544 | host->dma.hdr.execute_func = msmsdcc_dma_exec_func; | |
545 | host->dma.hdr.data = (void *)host; | |
9d2bd738 | 546 | host->dma.busy = 1; |
56a8b5b8 SM |
547 | |
548 | if (cmd) { | |
549 | msmsdcc_start_command_deferred(host, cmd, &c); | |
550 | host->cmd_c = c; | |
551 | } | |
9d2bd738 | 552 | msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr); |
d5137bdd ST |
553 | if (data->flags & MMC_DATA_WRITE) |
554 | host->prog_scan = true; | |
56a8b5b8 SM |
555 | } else { |
556 | msmsdcc_writel(host, timeout, MMCIDATATIMER); | |
9d2bd738 | 557 | |
56a8b5b8 SM |
558 | msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH); |
559 | ||
560 | msmsdcc_writel(host, pio_irqmask, MMCIMASK1); | |
561 | msmsdcc_writel(host, datactrl, MMCIDATACTRL); | |
562 | ||
563 | if (cmd) { | |
564 | /* Daisy-chain the command if requested */ | |
565 | msmsdcc_start_command(host, cmd, c); | |
566 | } | |
9d2bd738 SM |
567 | } |
568 | } | |
569 | ||
570 | static void | |
571 | msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c) | |
572 | { | |
9d2bd738 SM |
573 | if (cmd == cmd->mrq->stop) |
574 | c |= MCI_CSPM_MCIABORT; | |
575 | ||
9d2bd738 SM |
576 | host->stats.cmds++; |
577 | ||
56a8b5b8 SM |
578 | msmsdcc_start_command_deferred(host, cmd, &c); |
579 | msmsdcc_start_command_exec(host, cmd->arg, c); | |
9d2bd738 SM |
580 | } |
581 | ||
582 | static void | |
583 | msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data, | |
584 | unsigned int status) | |
585 | { | |
586 | if (status & MCI_DATACRCFAIL) { | |
0a7ff7c7 JP |
587 | pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc)); |
588 | pr_err("%s: opcode 0x%.8x\n", __func__, | |
9d2bd738 | 589 | data->mrq->cmd->opcode); |
0a7ff7c7 | 590 | pr_err("%s: blksz %d, blocks %d\n", __func__, |
9d2bd738 SM |
591 | data->blksz, data->blocks); |
592 | data->error = -EILSEQ; | |
593 | } else if (status & MCI_DATATIMEOUT) { | |
0a7ff7c7 | 594 | pr_err("%s: Data timeout\n", mmc_hostname(host->mmc)); |
9d2bd738 SM |
595 | data->error = -ETIMEDOUT; |
596 | } else if (status & MCI_RXOVERRUN) { | |
0a7ff7c7 | 597 | pr_err("%s: RX overrun\n", mmc_hostname(host->mmc)); |
9d2bd738 SM |
598 | data->error = -EIO; |
599 | } else if (status & MCI_TXUNDERRUN) { | |
0a7ff7c7 | 600 | pr_err("%s: TX underrun\n", mmc_hostname(host->mmc)); |
9d2bd738 SM |
601 | data->error = -EIO; |
602 | } else { | |
0a7ff7c7 JP |
603 | pr_err("%s: Unknown error (0x%.8x)\n", |
604 | mmc_hostname(host->mmc), status); | |
9d2bd738 SM |
605 | data->error = -EIO; |
606 | } | |
607 | } | |
608 | ||
609 | ||
610 | static int | |
611 | msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain) | |
612 | { | |
9d2bd738 SM |
613 | uint32_t *ptr = (uint32_t *) buffer; |
614 | int count = 0; | |
615 | ||
71dd9106 ST |
616 | if (remain % 4) |
617 | remain = ((remain >> 2) + 1) << 2; | |
618 | ||
8b1c2ba2 SM |
619 | while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) { |
620 | *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE)); | |
9d2bd738 SM |
621 | ptr++; |
622 | count += sizeof(uint32_t); | |
623 | ||
624 | remain -= sizeof(uint32_t); | |
625 | if (remain == 0) | |
626 | break; | |
627 | } | |
628 | return count; | |
629 | } | |
630 | ||
631 | static int | |
632 | msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer, | |
633 | unsigned int remain, u32 status) | |
634 | { | |
635 | void __iomem *base = host->base; | |
636 | char *ptr = buffer; | |
637 | ||
638 | do { | |
71dd9106 | 639 | unsigned int count, maxcnt, sz; |
9d2bd738 SM |
640 | |
641 | maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : | |
642 | MCI_FIFOHALFSIZE; | |
643 | count = min(remain, maxcnt); | |
644 | ||
71dd9106 ST |
645 | sz = count % 4 ? (count >> 2) + 1 : (count >> 2); |
646 | writesl(base + MMCIFIFO, ptr, sz); | |
9d2bd738 SM |
647 | ptr += count; |
648 | remain -= count; | |
649 | ||
650 | if (remain == 0) | |
651 | break; | |
652 | ||
8b1c2ba2 | 653 | status = msmsdcc_readl(host, MMCISTATUS); |
9d2bd738 SM |
654 | } while (status & MCI_TXFIFOHALFEMPTY); |
655 | ||
656 | return ptr - buffer; | |
657 | } | |
658 | ||
659 | static int | |
660 | msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin) | |
661 | { | |
662 | while (maxspin) { | |
8b1c2ba2 | 663 | if ((msmsdcc_readl(host, MMCISTATUS) & mask)) |
9d2bd738 SM |
664 | return 0; |
665 | udelay(1); | |
666 | --maxspin; | |
667 | } | |
668 | return -ETIMEDOUT; | |
669 | } | |
670 | ||
1cd22969 | 671 | static irqreturn_t |
9d2bd738 SM |
672 | msmsdcc_pio_irq(int irq, void *dev_id) |
673 | { | |
674 | struct msmsdcc_host *host = dev_id; | |
9d2bd738 SM |
675 | uint32_t status; |
676 | ||
8b1c2ba2 | 677 | status = msmsdcc_readl(host, MMCISTATUS); |
9d2bd738 SM |
678 | |
679 | do { | |
680 | unsigned long flags; | |
681 | unsigned int remain, len; | |
682 | char *buffer; | |
683 | ||
684 | if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) { | |
685 | if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll) | |
686 | break; | |
687 | ||
688 | if (msmsdcc_spin_on_status(host, | |
689 | (MCI_TXFIFOHALFEMPTY | | |
690 | MCI_RXDATAAVLBL), | |
691 | PIO_SPINMAX)) { | |
692 | break; | |
693 | } | |
694 | } | |
695 | ||
696 | /* Map the current scatter buffer */ | |
697 | local_irq_save(flags); | |
698 | buffer = kmap_atomic(sg_page(host->pio.sg), | |
699 | KM_BIO_SRC_IRQ) + host->pio.sg->offset; | |
700 | buffer += host->pio.sg_off; | |
701 | remain = host->pio.sg->length - host->pio.sg_off; | |
702 | len = 0; | |
703 | if (status & MCI_RXACTIVE) | |
704 | len = msmsdcc_pio_read(host, buffer, remain); | |
705 | if (status & MCI_TXACTIVE) | |
706 | len = msmsdcc_pio_write(host, buffer, remain, status); | |
707 | ||
708 | /* Unmap the buffer */ | |
709 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
710 | local_irq_restore(flags); | |
711 | ||
712 | host->pio.sg_off += len; | |
713 | host->curr.xfer_remain -= len; | |
714 | host->curr.data_xfered += len; | |
715 | remain -= len; | |
716 | ||
717 | if (remain == 0) { | |
718 | /* This sg page is full - do some housekeeping */ | |
719 | if (status & MCI_RXACTIVE && host->curr.user_pages) | |
720 | flush_dcache_page(sg_page(host->pio.sg)); | |
721 | ||
722 | if (!--host->pio.sg_len) { | |
723 | memset(&host->pio, 0, sizeof(host->pio)); | |
724 | break; | |
725 | } | |
726 | ||
727 | /* Advance to next sg */ | |
728 | host->pio.sg++; | |
729 | host->pio.sg_off = 0; | |
730 | } | |
731 | ||
8b1c2ba2 | 732 | status = msmsdcc_readl(host, MMCISTATUS); |
9d2bd738 SM |
733 | } while (1); |
734 | ||
735 | if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE) | |
8b1c2ba2 | 736 | msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1); |
9d2bd738 SM |
737 | |
738 | if (!host->curr.xfer_remain) | |
8b1c2ba2 | 739 | msmsdcc_writel(host, 0, MMCIMASK1); |
9d2bd738 SM |
740 | |
741 | return IRQ_HANDLED; | |
742 | } | |
743 | ||
744 | static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status) | |
745 | { | |
746 | struct mmc_command *cmd = host->curr.cmd; | |
9d2bd738 SM |
747 | |
748 | host->curr.cmd = NULL; | |
8b1c2ba2 SM |
749 | cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0); |
750 | cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1); | |
751 | cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2); | |
752 | cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3); | |
9d2bd738 | 753 | |
9d2bd738 SM |
754 | if (status & MCI_CMDTIMEOUT) { |
755 | cmd->error = -ETIMEDOUT; | |
756 | } else if (status & MCI_CMDCRCFAIL && | |
757 | cmd->flags & MMC_RSP_CRC) { | |
0a7ff7c7 | 758 | pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc)); |
9d2bd738 SM |
759 | cmd->error = -EILSEQ; |
760 | } | |
761 | ||
762 | if (!cmd->data || cmd->error) { | |
763 | if (host->curr.data && host->dma.sg) | |
764 | msm_dmov_stop_cmd(host->dma.channel, | |
765 | &host->dma.hdr, 0); | |
766 | else if (host->curr.data) { /* Non DMA */ | |
b08bb35d | 767 | msmsdcc_reset_and_restore(host); |
9d2bd738 SM |
768 | msmsdcc_stop_data(host); |
769 | msmsdcc_request_end(host, cmd->mrq); | |
d5137bdd ST |
770 | } else { /* host->data == NULL */ |
771 | if (!cmd->error && host->prog_enable) { | |
772 | if (status & MCI_PROGDONE) { | |
773 | host->prog_scan = false; | |
774 | host->prog_enable = false; | |
775 | msmsdcc_request_end(host, cmd->mrq); | |
776 | } else { | |
777 | host->curr.cmd = cmd; | |
778 | } | |
779 | } else { | |
780 | if (host->prog_enable) { | |
781 | host->prog_scan = false; | |
782 | host->prog_enable = false; | |
783 | } | |
784 | msmsdcc_request_end(host, cmd->mrq); | |
785 | } | |
786 | } | |
56a8b5b8 SM |
787 | } else if (cmd->data) |
788 | if (!(cmd->data->flags & MMC_DATA_READ)) | |
789 | msmsdcc_start_data(host, cmd->data, | |
790 | NULL, 0); | |
9d2bd738 SM |
791 | } |
792 | ||
b5a74d60 JP |
793 | static void |
794 | msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status, | |
795 | void __iomem *base) | |
796 | { | |
797 | struct mmc_data *data = host->curr.data; | |
798 | ||
56a8b5b8 | 799 | if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL | |
d5137bdd | 800 | MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) { |
56a8b5b8 SM |
801 | msmsdcc_do_cmdirq(host, status); |
802 | } | |
803 | ||
b5a74d60 JP |
804 | if (!data) |
805 | return; | |
806 | ||
807 | /* Check for data errors */ | |
808 | if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT | | |
809 | MCI_TXUNDERRUN | MCI_RXOVERRUN)) { | |
810 | msmsdcc_data_err(host, data, status); | |
811 | host->curr.data_xfered = 0; | |
812 | if (host->dma.sg) | |
813 | msm_dmov_stop_cmd(host->dma.channel, | |
814 | &host->dma.hdr, 0); | |
815 | else { | |
b08bb35d | 816 | msmsdcc_reset_and_restore(host); |
b3b0ca84 SM |
817 | if (host->curr.data) |
818 | msmsdcc_stop_data(host); | |
b5a74d60 JP |
819 | if (!data->stop) |
820 | msmsdcc_request_end(host, data->mrq); | |
821 | else | |
822 | msmsdcc_start_command(host, data->stop, 0); | |
823 | } | |
824 | } | |
825 | ||
826 | /* Check for data done */ | |
827 | if (!host->curr.got_dataend && (status & MCI_DATAEND)) | |
828 | host->curr.got_dataend = 1; | |
829 | ||
830 | if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND)) | |
831 | host->curr.got_datablkend = 1; | |
832 | ||
833 | /* | |
834 | * If DMA is still in progress, we complete via the completion handler | |
835 | */ | |
836 | if (host->curr.got_dataend && host->curr.got_datablkend && | |
837 | !host->dma.busy) { | |
838 | /* | |
839 | * There appears to be an issue in the controller where | |
840 | * if you request a small block transfer (< fifo size), | |
841 | * you may get your DATAEND/DATABLKEND irq without the | |
842 | * PIO data irq. | |
843 | * | |
844 | * Check to see if there is still data to be read, | |
845 | * and simulate a PIO irq. | |
846 | */ | |
847 | if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL) | |
848 | msmsdcc_pio_irq(1, host); | |
849 | ||
850 | msmsdcc_stop_data(host); | |
851 | if (!data->error) | |
852 | host->curr.data_xfered = host->curr.xfer_size; | |
853 | ||
854 | if (!data->stop) | |
855 | msmsdcc_request_end(host, data->mrq); | |
856 | else | |
857 | msmsdcc_start_command(host, data->stop, 0); | |
858 | } | |
859 | } | |
860 | ||
9d2bd738 SM |
861 | static irqreturn_t |
862 | msmsdcc_irq(int irq, void *dev_id) | |
863 | { | |
864 | struct msmsdcc_host *host = dev_id; | |
865 | void __iomem *base = host->base; | |
866 | u32 status; | |
867 | int ret = 0; | |
868 | int cardint = 0; | |
869 | ||
870 | spin_lock(&host->lock); | |
871 | ||
872 | do { | |
8b1c2ba2 SM |
873 | status = msmsdcc_readl(host, MMCISTATUS); |
874 | status &= (msmsdcc_readl(host, MMCIMASK0) | | |
875 | MCI_DATABLOCKENDMASK); | |
876 | msmsdcc_writel(host, status, MMCICLEAR); | |
9d2bd738 | 877 | |
865c8064 SM |
878 | if (status & MCI_SDIOINTR) |
879 | status &= ~MCI_SDIOINTR; | |
9d2bd738 | 880 | |
865c8064 SM |
881 | if (!status) |
882 | break; | |
9d2bd738 | 883 | |
b5a74d60 | 884 | msmsdcc_handle_irq_data(host, status, base); |
9d2bd738 SM |
885 | |
886 | if (status & MCI_SDIOINTOPER) { | |
887 | cardint = 1; | |
888 | status &= ~MCI_SDIOINTOPER; | |
889 | } | |
890 | ret = 1; | |
891 | } while (status); | |
892 | ||
893 | spin_unlock(&host->lock); | |
894 | ||
895 | /* | |
896 | * We have to delay handling the card interrupt as it calls | |
897 | * back into the driver. | |
898 | */ | |
899 | if (cardint) | |
900 | mmc_signal_sdio_irq(host->mmc); | |
901 | ||
902 | return IRQ_RETVAL(ret); | |
903 | } | |
904 | ||
905 | static void | |
906 | msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
907 | { | |
908 | struct msmsdcc_host *host = mmc_priv(mmc); | |
909 | unsigned long flags; | |
910 | ||
911 | WARN_ON(host->curr.mrq != NULL); | |
912 | WARN_ON(host->pwr == 0); | |
913 | ||
914 | spin_lock_irqsave(&host->lock, flags); | |
915 | ||
916 | host->stats.reqs++; | |
917 | ||
918 | if (host->eject) { | |
919 | if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) { | |
920 | mrq->cmd->error = 0; | |
921 | mrq->data->bytes_xfered = mrq->data->blksz * | |
922 | mrq->data->blocks; | |
923 | } else | |
924 | mrq->cmd->error = -ENOMEDIUM; | |
925 | ||
926 | spin_unlock_irqrestore(&host->lock, flags); | |
927 | mmc_request_done(mmc, mrq); | |
928 | return; | |
929 | } | |
930 | ||
d0719e59 | 931 | msmsdcc_enable_clocks(host); |
9d2bd738 | 932 | |
9d2bd738 SM |
933 | host->curr.mrq = mrq; |
934 | ||
935 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
56a8b5b8 SM |
936 | /* Queue/read data, daisy-chain command when data starts */ |
937 | msmsdcc_start_data(host, mrq->data, mrq->cmd, 0); | |
938 | else | |
939 | msmsdcc_start_command(host, mrq->cmd, 0); | |
9d2bd738 SM |
940 | |
941 | if (host->cmdpoll && !msmsdcc_spin_on_status(host, | |
942 | MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT, | |
943 | CMD_SPINMAX)) { | |
8b1c2ba2 | 944 | uint32_t status = msmsdcc_readl(host, MMCISTATUS); |
9d2bd738 | 945 | msmsdcc_do_cmdirq(host, status); |
8b1c2ba2 SM |
946 | msmsdcc_writel(host, |
947 | MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT, | |
948 | MMCICLEAR); | |
9d2bd738 SM |
949 | host->stats.cmdpoll_hits++; |
950 | } else { | |
951 | host->stats.cmdpoll_misses++; | |
9d2bd738 SM |
952 | } |
953 | spin_unlock_irqrestore(&host->lock, flags); | |
954 | } | |
955 | ||
956 | static void | |
957 | msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
958 | { | |
959 | struct msmsdcc_host *host = mmc_priv(mmc); | |
960 | u32 clk = 0, pwr = 0; | |
961 | int rc; | |
4adbbcc7 | 962 | unsigned long flags; |
9d2bd738 | 963 | |
c7fc9370 | 964 | spin_lock_irqsave(&host->lock, flags); |
9d2bd738 | 965 | |
d0719e59 SM |
966 | msmsdcc_enable_clocks(host); |
967 | ||
865c8064 | 968 | if (ios->clock) { |
9d2bd738 SM |
969 | if (ios->clock != host->clk_rate) { |
970 | rc = clk_set_rate(host->clk, ios->clock); | |
971 | if (rc < 0) | |
0a7ff7c7 JP |
972 | pr_err("%s: Error setting clock rate (%d)\n", |
973 | mmc_hostname(host->mmc), rc); | |
9d2bd738 SM |
974 | else |
975 | host->clk_rate = ios->clock; | |
976 | } | |
977 | clk |= MCI_CLK_ENABLE; | |
978 | } | |
979 | ||
980 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
981 | clk |= (2 << 10); /* Set WIDEBUS */ | |
982 | ||
983 | if (ios->clock > 400000 && msmsdcc_pwrsave) | |
984 | clk |= (1 << 9); /* PWRSAVE */ | |
985 | ||
986 | clk |= (1 << 12); /* FLOW_ENA */ | |
987 | clk |= (1 << 15); /* feedback clock */ | |
988 | ||
989 | if (host->plat->translate_vdd) | |
990 | pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); | |
991 | ||
992 | switch (ios->power_mode) { | |
993 | case MMC_POWER_OFF: | |
9d2bd738 SM |
994 | break; |
995 | case MMC_POWER_UP: | |
996 | pwr |= MCI_PWR_UP; | |
997 | break; | |
998 | case MMC_POWER_ON: | |
9d2bd738 SM |
999 | pwr |= MCI_PWR_ON; |
1000 | break; | |
1001 | } | |
1002 | ||
1003 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
1004 | pwr |= MCI_OD; | |
1005 | ||
8b1c2ba2 | 1006 | msmsdcc_writel(host, clk, MMCICLOCK); |
9d2bd738 SM |
1007 | |
1008 | if (host->pwr != pwr) { | |
1009 | host->pwr = pwr; | |
8b1c2ba2 | 1010 | msmsdcc_writel(host, pwr, MMCIPOWER); |
9d2bd738 | 1011 | } |
f4748499 | 1012 | #if BUSCLK_PWRSAVE |
c7fc9370 | 1013 | msmsdcc_disable_clocks(host, 1); |
f4748499 | 1014 | #endif |
4adbbcc7 | 1015 | spin_unlock_irqrestore(&host->lock, flags); |
9d2bd738 SM |
1016 | } |
1017 | ||
1018 | static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
1019 | { | |
1020 | struct msmsdcc_host *host = mmc_priv(mmc); | |
1021 | unsigned long flags; | |
1022 | u32 status; | |
1023 | ||
1024 | spin_lock_irqsave(&host->lock, flags); | |
1025 | if (msmsdcc_sdioirq == 1) { | |
8b1c2ba2 | 1026 | status = msmsdcc_readl(host, MMCIMASK0); |
9d2bd738 SM |
1027 | if (enable) |
1028 | status |= MCI_SDIOINTOPERMASK; | |
1029 | else | |
1030 | status &= ~MCI_SDIOINTOPERMASK; | |
1031 | host->saved_irq0mask = status; | |
8b1c2ba2 | 1032 | msmsdcc_writel(host, status, MMCIMASK0); |
9d2bd738 SM |
1033 | } |
1034 | spin_unlock_irqrestore(&host->lock, flags); | |
1035 | } | |
1036 | ||
1037 | static const struct mmc_host_ops msmsdcc_ops = { | |
1038 | .request = msmsdcc_request, | |
1039 | .set_ios = msmsdcc_set_ios, | |
1040 | .enable_sdio_irq = msmsdcc_enable_sdio_irq, | |
1041 | }; | |
1042 | ||
1043 | static void | |
1044 | msmsdcc_check_status(unsigned long data) | |
1045 | { | |
1046 | struct msmsdcc_host *host = (struct msmsdcc_host *)data; | |
1047 | unsigned int status; | |
1048 | ||
1049 | if (!host->plat->status) { | |
1050 | mmc_detect_change(host->mmc, 0); | |
1051 | goto out; | |
1052 | } | |
1053 | ||
1054 | status = host->plat->status(mmc_dev(host->mmc)); | |
1055 | host->eject = !status; | |
1056 | if (status ^ host->oldstat) { | |
0a7ff7c7 JP |
1057 | pr_info("%s: Slot status change detected (%d -> %d)\n", |
1058 | mmc_hostname(host->mmc), host->oldstat, status); | |
9d2bd738 SM |
1059 | if (status) |
1060 | mmc_detect_change(host->mmc, (5 * HZ) / 2); | |
1061 | else | |
1062 | mmc_detect_change(host->mmc, 0); | |
1063 | } | |
1064 | ||
1065 | host->oldstat = status; | |
1066 | ||
1067 | out: | |
1068 | if (host->timer.function) | |
1069 | mod_timer(&host->timer, jiffies + HZ); | |
1070 | } | |
1071 | ||
1072 | static irqreturn_t | |
1073 | msmsdcc_platform_status_irq(int irq, void *dev_id) | |
1074 | { | |
1075 | struct msmsdcc_host *host = dev_id; | |
1076 | ||
1077 | printk(KERN_DEBUG "%s: %d\n", __func__, irq); | |
1078 | msmsdcc_check_status((unsigned long) host); | |
1079 | return IRQ_HANDLED; | |
1080 | } | |
1081 | ||
1082 | static void | |
1083 | msmsdcc_status_notify_cb(int card_present, void *dev_id) | |
1084 | { | |
1085 | struct msmsdcc_host *host = dev_id; | |
1086 | ||
1087 | printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc), | |
1088 | card_present); | |
1089 | msmsdcc_check_status((unsigned long) host); | |
1090 | } | |
1091 | ||
9d2bd738 | 1092 | static void |
865c8064 | 1093 | msmsdcc_busclk_expired(unsigned long _data) |
9d2bd738 SM |
1094 | { |
1095 | struct msmsdcc_host *host = (struct msmsdcc_host *) _data; | |
9d2bd738 | 1096 | |
865c8064 | 1097 | if (host->clks_on) |
c7fc9370 | 1098 | msmsdcc_disable_clocks(host, 0); |
9d2bd738 SM |
1099 | } |
1100 | ||
1101 | static int | |
1102 | msmsdcc_init_dma(struct msmsdcc_host *host) | |
1103 | { | |
1104 | memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data)); | |
1105 | host->dma.host = host; | |
1106 | host->dma.channel = -1; | |
1107 | ||
1108 | if (!host->dmares) | |
1109 | return -ENODEV; | |
1110 | ||
1111 | host->dma.nc = dma_alloc_coherent(NULL, | |
1112 | sizeof(struct msmsdcc_nc_dmadata), | |
1113 | &host->dma.nc_busaddr, | |
1114 | GFP_KERNEL); | |
1115 | if (host->dma.nc == NULL) { | |
0a7ff7c7 | 1116 | pr_err("Unable to allocate DMA buffer\n"); |
9d2bd738 SM |
1117 | return -ENOMEM; |
1118 | } | |
1119 | memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata)); | |
1120 | host->dma.cmd_busaddr = host->dma.nc_busaddr; | |
1121 | host->dma.cmdptr_busaddr = host->dma.nc_busaddr + | |
1122 | offsetof(struct msmsdcc_nc_dmadata, cmdptr); | |
1123 | host->dma.channel = host->dmares->start; | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
9d2bd738 SM |
1128 | static int |
1129 | msmsdcc_probe(struct platform_device *pdev) | |
1130 | { | |
b5d643de | 1131 | struct msm_mmc_platform_data *plat = pdev->dev.platform_data; |
9d2bd738 SM |
1132 | struct msmsdcc_host *host; |
1133 | struct mmc_host *mmc; | |
1134 | struct resource *cmd_irqres = NULL; | |
1135 | struct resource *pio_irqres = NULL; | |
1136 | struct resource *stat_irqres = NULL; | |
1137 | struct resource *memres = NULL; | |
1138 | struct resource *dmares = NULL; | |
1139 | int ret; | |
1140 | ||
1141 | /* must have platform data */ | |
1142 | if (!plat) { | |
0a7ff7c7 | 1143 | pr_err("%s: Platform data not available\n", __func__); |
9d2bd738 SM |
1144 | ret = -EINVAL; |
1145 | goto out; | |
1146 | } | |
1147 | ||
1148 | if (pdev->id < 1 || pdev->id > 4) | |
1149 | return -EINVAL; | |
1150 | ||
1151 | if (pdev->resource == NULL || pdev->num_resources < 2) { | |
0a7ff7c7 | 1152 | pr_err("%s: Invalid resource\n", __func__); |
9d2bd738 SM |
1153 | return -ENXIO; |
1154 | } | |
1155 | ||
1156 | memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1157 | dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1158 | cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, | |
1159 | "cmd_irq"); | |
1160 | pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, | |
1161 | "pio_irq"); | |
1162 | stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, | |
1163 | "status_irq"); | |
1164 | ||
1165 | if (!cmd_irqres || !pio_irqres || !memres) { | |
0a7ff7c7 | 1166 | pr_err("%s: Invalid resource\n", __func__); |
9d2bd738 SM |
1167 | return -ENXIO; |
1168 | } | |
1169 | ||
1170 | /* | |
1171 | * Setup our host structure | |
1172 | */ | |
1173 | ||
1174 | mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev); | |
1175 | if (!mmc) { | |
1176 | ret = -ENOMEM; | |
1177 | goto out; | |
1178 | } | |
1179 | ||
1180 | host = mmc_priv(mmc); | |
1181 | host->pdev_id = pdev->id; | |
1182 | host->plat = plat; | |
1183 | host->mmc = mmc; | |
56a8b5b8 | 1184 | host->curr.cmd = NULL; |
9d2bd738 SM |
1185 | |
1186 | host->cmdpoll = 1; | |
1187 | ||
1188 | host->base = ioremap(memres->start, PAGE_SIZE); | |
1189 | if (!host->base) { | |
1190 | ret = -ENOMEM; | |
1191 | goto out; | |
1192 | } | |
1193 | ||
1194 | host->cmd_irqres = cmd_irqres; | |
1195 | host->pio_irqres = pio_irqres; | |
1196 | host->memres = memres; | |
1197 | host->dmares = dmares; | |
1198 | spin_lock_init(&host->lock); | |
1199 | ||
62612cf9 ST |
1200 | tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet, |
1201 | (unsigned long)host); | |
1202 | ||
9d2bd738 SM |
1203 | /* |
1204 | * Setup DMA | |
1205 | */ | |
1206 | msmsdcc_init_dma(host); | |
1207 | ||
4adbbcc7 | 1208 | /* Get our clocks */ |
9d2bd738 SM |
1209 | host->pclk = clk_get(&pdev->dev, "sdc_pclk"); |
1210 | if (IS_ERR(host->pclk)) { | |
1211 | ret = PTR_ERR(host->pclk); | |
1212 | goto host_free; | |
1213 | } | |
1214 | ||
9d2bd738 SM |
1215 | host->clk = clk_get(&pdev->dev, "sdc_clk"); |
1216 | if (IS_ERR(host->clk)) { | |
1217 | ret = PTR_ERR(host->clk); | |
4adbbcc7 | 1218 | goto pclk_put; |
9d2bd738 SM |
1219 | } |
1220 | ||
4adbbcc7 | 1221 | /* Enable clocks */ |
c7fc9370 | 1222 | ret = msmsdcc_enable_clocks(host); |
9d2bd738 SM |
1223 | if (ret) |
1224 | goto clk_put; | |
1225 | ||
1226 | ret = clk_set_rate(host->clk, msmsdcc_fmin); | |
1227 | if (ret) { | |
0a7ff7c7 | 1228 | pr_err("%s: Clock rate set failed (%d)\n", __func__, ret); |
9d2bd738 SM |
1229 | goto clk_disable; |
1230 | } | |
1231 | ||
4adbbcc7 | 1232 | host->pclk_rate = clk_get_rate(host->pclk); |
9d2bd738 SM |
1233 | host->clk_rate = clk_get_rate(host->clk); |
1234 | ||
9d2bd738 SM |
1235 | /* |
1236 | * Setup MMC host structure | |
1237 | */ | |
1238 | mmc->ops = &msmsdcc_ops; | |
1239 | mmc->f_min = msmsdcc_fmin; | |
1240 | mmc->f_max = msmsdcc_fmax; | |
1241 | mmc->ocr_avail = plat->ocr_mask; | |
1242 | ||
1243 | if (msmsdcc_4bit) | |
1244 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1245 | if (msmsdcc_sdioirq) | |
1246 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
1247 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; | |
1248 | ||
a36274e0 | 1249 | mmc->max_segs = NR_SG; |
9d2bd738 SM |
1250 | mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */ |
1251 | mmc->max_blk_count = 65536; | |
1252 | ||
1253 | mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */ | |
1254 | mmc->max_seg_size = mmc->max_req_size; | |
1255 | ||
8b1c2ba2 SM |
1256 | msmsdcc_writel(host, 0, MMCIMASK0); |
1257 | msmsdcc_writel(host, 0x5e007ff, MMCICLEAR); | |
9d2bd738 | 1258 | |
8b1c2ba2 | 1259 | msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0); |
9d2bd738 SM |
1260 | host->saved_irq0mask = MCI_IRQENABLE; |
1261 | ||
1262 | /* | |
1263 | * Setup card detect change | |
1264 | */ | |
1265 | ||
1266 | memset(&host->timer, 0, sizeof(host->timer)); | |
1267 | ||
1268 | if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) { | |
1269 | unsigned long irqflags = IRQF_SHARED | | |
1270 | (stat_irqres->flags & IRQF_TRIGGER_MASK); | |
1271 | ||
1272 | host->stat_irq = stat_irqres->start; | |
1273 | ret = request_irq(host->stat_irq, | |
1274 | msmsdcc_platform_status_irq, | |
1275 | irqflags, | |
1276 | DRIVER_NAME " (slot)", | |
1277 | host); | |
1278 | if (ret) { | |
0a7ff7c7 JP |
1279 | pr_err("%s: Unable to get slot IRQ %d (%d)\n", |
1280 | mmc_hostname(mmc), host->stat_irq, ret); | |
9d2bd738 SM |
1281 | goto clk_disable; |
1282 | } | |
1283 | } else if (plat->register_status_notify) { | |
1284 | plat->register_status_notify(msmsdcc_status_notify_cb, host); | |
1285 | } else if (!plat->status) | |
0a7ff7c7 | 1286 | pr_err("%s: No card detect facilities available\n", |
9d2bd738 SM |
1287 | mmc_hostname(mmc)); |
1288 | else { | |
1289 | init_timer(&host->timer); | |
1290 | host->timer.data = (unsigned long)host; | |
1291 | host->timer.function = msmsdcc_check_status; | |
1292 | host->timer.expires = jiffies + HZ; | |
1293 | add_timer(&host->timer); | |
1294 | } | |
1295 | ||
1296 | if (plat->status) { | |
1297 | host->oldstat = host->plat->status(mmc_dev(host->mmc)); | |
1298 | host->eject = !host->oldstat; | |
1299 | } | |
1300 | ||
865c8064 SM |
1301 | init_timer(&host->busclk_timer); |
1302 | host->busclk_timer.data = (unsigned long) host; | |
1303 | host->busclk_timer.function = msmsdcc_busclk_expired; | |
9d2bd738 SM |
1304 | |
1305 | ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED, | |
1306 | DRIVER_NAME " (cmd)", host); | |
1307 | if (ret) | |
1308 | goto stat_irq_free; | |
1309 | ||
1310 | ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED, | |
1311 | DRIVER_NAME " (pio)", host); | |
1312 | if (ret) | |
1313 | goto cmd_irq_free; | |
1314 | ||
1315 | mmc_set_drvdata(pdev, mmc); | |
1316 | mmc_add_host(mmc); | |
1317 | ||
0a7ff7c7 JP |
1318 | pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n", |
1319 | mmc_hostname(mmc), (unsigned long long)memres->start, | |
1320 | (unsigned int) cmd_irqres->start, | |
1321 | (unsigned int) host->stat_irq, host->dma.channel); | |
1322 | pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc), | |
1323 | (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled")); | |
1324 | pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n", | |
1325 | mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate); | |
1326 | pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject); | |
1327 | pr_info("%s: Power save feature enable = %d\n", | |
1328 | mmc_hostname(mmc), msmsdcc_pwrsave); | |
9d2bd738 SM |
1329 | |
1330 | if (host->dma.channel != -1) { | |
0a7ff7c7 JP |
1331 | pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n", |
1332 | mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr); | |
1333 | pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n", | |
1334 | mmc_hostname(mmc), host->dma.cmd_busaddr, | |
1335 | host->dma.cmdptr_busaddr); | |
9d2bd738 | 1336 | } else |
0a7ff7c7 | 1337 | pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc)); |
9d2bd738 | 1338 | if (host->timer.function) |
0a7ff7c7 | 1339 | pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc)); |
9d2bd738 | 1340 | |
f4748499 | 1341 | #if BUSCLK_PWRSAVE |
c7fc9370 | 1342 | msmsdcc_disable_clocks(host, 1); |
f4748499 | 1343 | #endif |
9d2bd738 SM |
1344 | return 0; |
1345 | cmd_irq_free: | |
1346 | free_irq(cmd_irqres->start, host); | |
1347 | stat_irq_free: | |
1348 | if (host->stat_irq) | |
1349 | free_irq(host->stat_irq, host); | |
1350 | clk_disable: | |
c7fc9370 | 1351 | msmsdcc_disable_clocks(host, 0); |
9d2bd738 SM |
1352 | clk_put: |
1353 | clk_put(host->clk); | |
9d2bd738 SM |
1354 | pclk_put: |
1355 | clk_put(host->pclk); | |
1356 | host_free: | |
1357 | mmc_free_host(mmc); | |
1358 | out: | |
1359 | return ret; | |
1360 | } | |
1361 | ||
08ecfde4 DW |
1362 | #ifdef CONFIG_PM |
1363 | #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ | |
1364 | static void | |
1365 | do_resume_work(struct work_struct *work) | |
1366 | { | |
1367 | struct msmsdcc_host *host = | |
1368 | container_of(work, struct msmsdcc_host, resume_task); | |
1369 | struct mmc_host *mmc = host->mmc; | |
1370 | ||
1371 | if (mmc) { | |
1372 | mmc_resume_host(mmc); | |
1373 | if (host->stat_irq) | |
1374 | enable_irq(host->stat_irq); | |
1375 | } | |
1376 | } | |
1377 | #endif | |
1378 | ||
1379 | ||
9d2bd738 SM |
1380 | static int |
1381 | msmsdcc_suspend(struct platform_device *dev, pm_message_t state) | |
1382 | { | |
1383 | struct mmc_host *mmc = mmc_get_drvdata(dev); | |
1384 | int rc = 0; | |
1385 | ||
1386 | if (mmc) { | |
1387 | struct msmsdcc_host *host = mmc_priv(mmc); | |
1388 | ||
1389 | if (host->stat_irq) | |
1390 | disable_irq(host->stat_irq); | |
1391 | ||
1392 | if (mmc->card && mmc->card->type != MMC_TYPE_SDIO) | |
1a13f8fa | 1393 | rc = mmc_suspend_host(mmc); |
d0719e59 | 1394 | if (!rc) |
8b1c2ba2 | 1395 | msmsdcc_writel(host, 0, MMCIMASK0); |
c7fc9370 SM |
1396 | if (host->clks_on) |
1397 | msmsdcc_disable_clocks(host, 0); | |
9d2bd738 SM |
1398 | } |
1399 | return rc; | |
1400 | } | |
1401 | ||
1402 | static int | |
1403 | msmsdcc_resume(struct platform_device *dev) | |
1404 | { | |
1405 | struct mmc_host *mmc = mmc_get_drvdata(dev); | |
9d2bd738 SM |
1406 | |
1407 | if (mmc) { | |
1408 | struct msmsdcc_host *host = mmc_priv(mmc); | |
1409 | ||
c7fc9370 | 1410 | msmsdcc_enable_clocks(host); |
9d2bd738 | 1411 | |
8b1c2ba2 | 1412 | msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0); |
9d2bd738 SM |
1413 | |
1414 | if (mmc->card && mmc->card->type != MMC_TYPE_SDIO) | |
1415 | mmc_resume_host(mmc); | |
5b8a2fb3 | 1416 | if (host->stat_irq) |
9d2bd738 | 1417 | enable_irq(host->stat_irq); |
f4748499 | 1418 | #if BUSCLK_PWRSAVE |
c7fc9370 | 1419 | msmsdcc_disable_clocks(host, 1); |
f4748499 | 1420 | #endif |
9d2bd738 SM |
1421 | } |
1422 | return 0; | |
1423 | } | |
08ecfde4 DW |
1424 | #else |
1425 | #define msmsdcc_suspend 0 | |
1426 | #define msmsdcc_resume 0 | |
1427 | #endif | |
9d2bd738 SM |
1428 | |
1429 | static struct platform_driver msmsdcc_driver = { | |
1430 | .probe = msmsdcc_probe, | |
1431 | .suspend = msmsdcc_suspend, | |
1432 | .resume = msmsdcc_resume, | |
1433 | .driver = { | |
1434 | .name = "msm_sdcc", | |
1435 | }, | |
1436 | }; | |
1437 | ||
1438 | static int __init msmsdcc_init(void) | |
1439 | { | |
1440 | return platform_driver_register(&msmsdcc_driver); | |
1441 | } | |
1442 | ||
1443 | static void __exit msmsdcc_exit(void) | |
1444 | { | |
1445 | platform_driver_unregister(&msmsdcc_driver); | |
1446 | } | |
1447 | ||
1448 | module_init(msmsdcc_init); | |
1449 | module_exit(msmsdcc_exit); | |
1450 | ||
1451 | MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver"); | |
1452 | MODULE_LICENSE("GPL"); |