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1b66e94e JJ |
1 | /* |
2 | * MOXA ART MMC host driver. | |
3 | * | |
4 | * Copyright (C) 2014 Jonas Jensen | |
5 | * | |
6 | * Jonas Jensen <jonas.jensen@gmail.com> | |
7 | * | |
8 | * Based on code from | |
9 | * Moxa Technologies Co., Ltd. <www.moxa.com> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
1b66e94e JJ |
16 | #include <linux/module.h> |
17 | #include <linux/init.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/blkdev.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/dmaengine.h> | |
24 | #include <linux/mmc/host.h> | |
25 | #include <linux/mmc/sd.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/of_address.h> | |
29 | #include <linux/of_irq.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/bitops.h> | |
32 | #include <linux/of_dma.h> | |
33 | #include <linux/spinlock.h> | |
34 | ||
35 | #define REG_COMMAND 0 | |
36 | #define REG_ARGUMENT 4 | |
37 | #define REG_RESPONSE0 8 | |
38 | #define REG_RESPONSE1 12 | |
39 | #define REG_RESPONSE2 16 | |
40 | #define REG_RESPONSE3 20 | |
41 | #define REG_RESPONSE_COMMAND 24 | |
42 | #define REG_DATA_CONTROL 28 | |
43 | #define REG_DATA_TIMER 32 | |
44 | #define REG_DATA_LENGTH 36 | |
45 | #define REG_STATUS 40 | |
46 | #define REG_CLEAR 44 | |
47 | #define REG_INTERRUPT_MASK 48 | |
48 | #define REG_POWER_CONTROL 52 | |
49 | #define REG_CLOCK_CONTROL 56 | |
50 | #define REG_BUS_WIDTH 60 | |
51 | #define REG_DATA_WINDOW 64 | |
52 | #define REG_FEATURE 68 | |
53 | #define REG_REVISION 72 | |
54 | ||
55 | /* REG_COMMAND */ | |
56 | #define CMD_SDC_RESET BIT(10) | |
57 | #define CMD_EN BIT(9) | |
58 | #define CMD_APP_CMD BIT(8) | |
59 | #define CMD_LONG_RSP BIT(7) | |
60 | #define CMD_NEED_RSP BIT(6) | |
61 | #define CMD_IDX_MASK 0x3f | |
62 | ||
63 | /* REG_RESPONSE_COMMAND */ | |
64 | #define RSP_CMD_APP BIT(6) | |
65 | #define RSP_CMD_IDX_MASK 0x3f | |
66 | ||
67 | /* REG_DATA_CONTROL */ | |
68 | #define DCR_DATA_FIFO_RESET BIT(8) | |
69 | #define DCR_DATA_THRES BIT(7) | |
70 | #define DCR_DATA_EN BIT(6) | |
71 | #define DCR_DMA_EN BIT(5) | |
72 | #define DCR_DATA_WRITE BIT(4) | |
73 | #define DCR_BLK_SIZE 0x0f | |
74 | ||
75 | /* REG_DATA_LENGTH */ | |
76 | #define DATA_LEN_MASK 0xffffff | |
77 | ||
78 | /* REG_STATUS */ | |
79 | #define WRITE_PROT BIT(12) | |
80 | #define CARD_DETECT BIT(11) | |
81 | /* 1-10 below can be sent to either registers, interrupt or clear. */ | |
82 | #define CARD_CHANGE BIT(10) | |
83 | #define FIFO_ORUN BIT(9) | |
84 | #define FIFO_URUN BIT(8) | |
85 | #define DATA_END BIT(7) | |
86 | #define CMD_SENT BIT(6) | |
87 | #define DATA_CRC_OK BIT(5) | |
88 | #define RSP_CRC_OK BIT(4) | |
89 | #define DATA_TIMEOUT BIT(3) | |
90 | #define RSP_TIMEOUT BIT(2) | |
91 | #define DATA_CRC_FAIL BIT(1) | |
92 | #define RSP_CRC_FAIL BIT(0) | |
93 | ||
94 | #define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \ | |
95 | RSP_CRC_OK | CARD_DETECT | CMD_SENT) | |
96 | ||
97 | #define MASK_DATA (DATA_CRC_OK | DATA_END | \ | |
98 | DATA_CRC_FAIL | DATA_TIMEOUT) | |
99 | ||
100 | #define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE) | |
101 | ||
102 | /* REG_POWER_CONTROL */ | |
103 | #define SD_POWER_ON BIT(4) | |
104 | #define SD_POWER_MASK 0x0f | |
105 | ||
106 | /* REG_CLOCK_CONTROL */ | |
107 | #define CLK_HISPD BIT(9) | |
108 | #define CLK_OFF BIT(8) | |
109 | #define CLK_SD BIT(7) | |
110 | #define CLK_DIV_MASK 0x7f | |
111 | ||
112 | /* REG_BUS_WIDTH */ | |
113 | #define BUS_WIDTH_8 BIT(2) | |
114 | #define BUS_WIDTH_4 BIT(1) | |
115 | #define BUS_WIDTH_1 BIT(0) | |
116 | ||
117 | #define MMC_VDD_360 23 | |
118 | #define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK) | |
119 | #define MAX_RETRIES 500000 | |
120 | ||
121 | struct moxart_host { | |
122 | spinlock_t lock; | |
123 | ||
124 | void __iomem *base; | |
125 | ||
126 | phys_addr_t reg_phys; | |
127 | ||
128 | struct dma_chan *dma_chan_tx; | |
129 | struct dma_chan *dma_chan_rx; | |
130 | struct dma_async_tx_descriptor *tx_desc; | |
131 | struct mmc_host *mmc; | |
132 | struct mmc_request *mrq; | |
133 | struct scatterlist *cur_sg; | |
134 | struct completion dma_complete; | |
135 | struct completion pio_complete; | |
136 | ||
137 | u32 num_sg; | |
138 | u32 data_remain; | |
139 | u32 data_len; | |
140 | u32 fifo_width; | |
141 | u32 timeout; | |
142 | u32 rate; | |
143 | ||
144 | long sysclk; | |
145 | ||
146 | bool have_dma; | |
147 | bool is_removed; | |
148 | }; | |
149 | ||
150 | static inline void moxart_init_sg(struct moxart_host *host, | |
151 | struct mmc_data *data) | |
152 | { | |
153 | host->cur_sg = data->sg; | |
154 | host->num_sg = data->sg_len; | |
155 | host->data_remain = host->cur_sg->length; | |
156 | ||
157 | if (host->data_remain > host->data_len) | |
158 | host->data_remain = host->data_len; | |
159 | } | |
160 | ||
161 | static inline int moxart_next_sg(struct moxart_host *host) | |
162 | { | |
163 | int remain; | |
164 | struct mmc_data *data = host->mrq->cmd->data; | |
165 | ||
166 | host->cur_sg++; | |
167 | host->num_sg--; | |
168 | ||
169 | if (host->num_sg > 0) { | |
170 | host->data_remain = host->cur_sg->length; | |
171 | remain = host->data_len - data->bytes_xfered; | |
172 | if (remain > 0 && remain < host->data_remain) | |
173 | host->data_remain = remain; | |
174 | } | |
175 | ||
176 | return host->num_sg; | |
177 | } | |
178 | ||
179 | static int moxart_wait_for_status(struct moxart_host *host, | |
180 | u32 mask, u32 *status) | |
181 | { | |
182 | int ret = -ETIMEDOUT; | |
183 | u32 i; | |
184 | ||
185 | for (i = 0; i < MAX_RETRIES; i++) { | |
186 | *status = readl(host->base + REG_STATUS); | |
187 | if (!(*status & mask)) { | |
188 | udelay(5); | |
189 | continue; | |
190 | } | |
191 | writel(*status & mask, host->base + REG_CLEAR); | |
192 | ret = 0; | |
193 | break; | |
194 | } | |
195 | ||
196 | if (ret) | |
197 | dev_err(mmc_dev(host->mmc), "timed out waiting for status\n"); | |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
202 | ||
203 | static void moxart_send_command(struct moxart_host *host, | |
204 | struct mmc_command *cmd) | |
205 | { | |
206 | u32 status, cmdctrl; | |
207 | ||
208 | writel(RSP_TIMEOUT | RSP_CRC_OK | | |
209 | RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR); | |
210 | writel(cmd->arg, host->base + REG_ARGUMENT); | |
211 | ||
212 | cmdctrl = cmd->opcode & CMD_IDX_MASK; | |
213 | if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND || | |
214 | cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS || | |
215 | cmdctrl == SD_APP_SEND_NUM_WR_BLKS) | |
216 | cmdctrl |= CMD_APP_CMD; | |
217 | ||
218 | if (cmd->flags & MMC_RSP_PRESENT) | |
219 | cmdctrl |= CMD_NEED_RSP; | |
220 | ||
221 | if (cmd->flags & MMC_RSP_136) | |
222 | cmdctrl |= CMD_LONG_RSP; | |
223 | ||
224 | writel(cmdctrl | CMD_EN, host->base + REG_COMMAND); | |
225 | ||
226 | if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT) | |
227 | cmd->error = -ETIMEDOUT; | |
228 | ||
229 | if (status & RSP_TIMEOUT) { | |
230 | cmd->error = -ETIMEDOUT; | |
231 | return; | |
232 | } | |
233 | if (status & RSP_CRC_FAIL) { | |
234 | cmd->error = -EIO; | |
235 | return; | |
236 | } | |
237 | if (status & RSP_CRC_OK) { | |
238 | if (cmd->flags & MMC_RSP_136) { | |
239 | cmd->resp[3] = readl(host->base + REG_RESPONSE0); | |
240 | cmd->resp[2] = readl(host->base + REG_RESPONSE1); | |
241 | cmd->resp[1] = readl(host->base + REG_RESPONSE2); | |
242 | cmd->resp[0] = readl(host->base + REG_RESPONSE3); | |
243 | } else { | |
244 | cmd->resp[0] = readl(host->base + REG_RESPONSE0); | |
245 | } | |
246 | } | |
247 | } | |
248 | ||
249 | static void moxart_dma_complete(void *param) | |
250 | { | |
251 | struct moxart_host *host = param; | |
252 | ||
253 | complete(&host->dma_complete); | |
254 | } | |
255 | ||
256 | static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host) | |
257 | { | |
258 | u32 len, dir_data, dir_slave; | |
259 | unsigned long dma_time; | |
260 | struct dma_async_tx_descriptor *desc = NULL; | |
261 | struct dma_chan *dma_chan; | |
262 | ||
263 | if (host->data_len == data->bytes_xfered) | |
264 | return; | |
265 | ||
266 | if (data->flags & MMC_DATA_WRITE) { | |
267 | dma_chan = host->dma_chan_tx; | |
268 | dir_data = DMA_TO_DEVICE; | |
269 | dir_slave = DMA_MEM_TO_DEV; | |
270 | } else { | |
271 | dma_chan = host->dma_chan_rx; | |
272 | dir_data = DMA_FROM_DEVICE; | |
273 | dir_slave = DMA_DEV_TO_MEM; | |
274 | } | |
275 | ||
276 | len = dma_map_sg(dma_chan->device->dev, data->sg, | |
277 | data->sg_len, dir_data); | |
278 | ||
279 | if (len > 0) { | |
280 | desc = dmaengine_prep_slave_sg(dma_chan, data->sg, | |
281 | len, dir_slave, | |
282 | DMA_PREP_INTERRUPT | | |
283 | DMA_CTRL_ACK); | |
284 | } else { | |
285 | dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); | |
286 | } | |
287 | ||
288 | if (desc) { | |
289 | host->tx_desc = desc; | |
290 | desc->callback = moxart_dma_complete; | |
291 | desc->callback_param = host; | |
292 | dmaengine_submit(desc); | |
293 | dma_async_issue_pending(dma_chan); | |
294 | } | |
295 | ||
296 | data->bytes_xfered += host->data_remain; | |
297 | ||
298 | dma_time = wait_for_completion_interruptible_timeout( | |
299 | &host->dma_complete, host->timeout); | |
300 | ||
301 | dma_unmap_sg(dma_chan->device->dev, | |
302 | data->sg, data->sg_len, | |
303 | dir_data); | |
304 | } | |
305 | ||
306 | ||
307 | static void moxart_transfer_pio(struct moxart_host *host) | |
308 | { | |
309 | struct mmc_data *data = host->mrq->cmd->data; | |
310 | u32 *sgp, len = 0, remain, status; | |
311 | ||
312 | if (host->data_len == data->bytes_xfered) | |
313 | return; | |
314 | ||
315 | sgp = sg_virt(host->cur_sg); | |
316 | remain = host->data_remain; | |
317 | ||
318 | if (data->flags & MMC_DATA_WRITE) { | |
319 | while (remain > 0) { | |
320 | if (moxart_wait_for_status(host, FIFO_URUN, &status) | |
321 | == -ETIMEDOUT) { | |
322 | data->error = -ETIMEDOUT; | |
323 | complete(&host->pio_complete); | |
324 | return; | |
325 | } | |
326 | for (len = 0; len < remain && len < host->fifo_width;) { | |
327 | iowrite32(*sgp, host->base + REG_DATA_WINDOW); | |
328 | sgp++; | |
329 | len += 4; | |
330 | } | |
331 | remain -= len; | |
332 | } | |
333 | ||
334 | } else { | |
335 | while (remain > 0) { | |
336 | if (moxart_wait_for_status(host, FIFO_ORUN, &status) | |
337 | == -ETIMEDOUT) { | |
338 | data->error = -ETIMEDOUT; | |
339 | complete(&host->pio_complete); | |
340 | return; | |
341 | } | |
342 | for (len = 0; len < remain && len < host->fifo_width;) { | |
343 | /* SCR data must be read in big endian. */ | |
344 | if (data->mrq->cmd->opcode == SD_APP_SEND_SCR) | |
345 | *sgp = ioread32be(host->base + | |
346 | REG_DATA_WINDOW); | |
347 | else | |
348 | *sgp = ioread32(host->base + | |
349 | REG_DATA_WINDOW); | |
350 | sgp++; | |
351 | len += 4; | |
352 | } | |
353 | remain -= len; | |
354 | } | |
355 | } | |
356 | ||
357 | data->bytes_xfered += host->data_remain - remain; | |
358 | host->data_remain = remain; | |
359 | ||
360 | if (host->data_len != data->bytes_xfered) | |
361 | moxart_next_sg(host); | |
362 | else | |
363 | complete(&host->pio_complete); | |
364 | } | |
365 | ||
366 | static void moxart_prepare_data(struct moxart_host *host) | |
367 | { | |
368 | struct mmc_data *data = host->mrq->cmd->data; | |
369 | u32 datactrl; | |
370 | int blksz_bits; | |
371 | ||
372 | if (!data) | |
373 | return; | |
374 | ||
375 | host->data_len = data->blocks * data->blksz; | |
376 | blksz_bits = ffs(data->blksz) - 1; | |
377 | BUG_ON(1 << blksz_bits != data->blksz); | |
378 | ||
379 | moxart_init_sg(host, data); | |
380 | ||
381 | datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE); | |
382 | ||
383 | if (data->flags & MMC_DATA_WRITE) | |
384 | datactrl |= DCR_DATA_WRITE; | |
385 | ||
386 | if ((host->data_len > host->fifo_width) && host->have_dma) | |
387 | datactrl |= DCR_DMA_EN; | |
388 | ||
389 | writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL); | |
390 | writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR); | |
391 | writel(host->rate, host->base + REG_DATA_TIMER); | |
392 | writel(host->data_len, host->base + REG_DATA_LENGTH); | |
393 | writel(datactrl, host->base + REG_DATA_CONTROL); | |
394 | } | |
395 | ||
396 | static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
397 | { | |
398 | struct moxart_host *host = mmc_priv(mmc); | |
399 | unsigned long pio_time, flags; | |
400 | u32 status; | |
401 | ||
402 | spin_lock_irqsave(&host->lock, flags); | |
403 | ||
404 | init_completion(&host->dma_complete); | |
405 | init_completion(&host->pio_complete); | |
406 | ||
407 | host->mrq = mrq; | |
408 | ||
409 | if (readl(host->base + REG_STATUS) & CARD_DETECT) { | |
410 | mrq->cmd->error = -ETIMEDOUT; | |
411 | goto request_done; | |
412 | } | |
413 | ||
414 | moxart_prepare_data(host); | |
415 | moxart_send_command(host, host->mrq->cmd); | |
416 | ||
417 | if (mrq->cmd->data) { | |
418 | if ((host->data_len > host->fifo_width) && host->have_dma) { | |
419 | ||
420 | writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); | |
421 | ||
422 | spin_unlock_irqrestore(&host->lock, flags); | |
423 | ||
424 | moxart_transfer_dma(mrq->cmd->data, host); | |
425 | ||
426 | spin_lock_irqsave(&host->lock, flags); | |
427 | } else { | |
428 | ||
429 | writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK); | |
430 | ||
431 | spin_unlock_irqrestore(&host->lock, flags); | |
432 | ||
433 | /* PIO transfers start from interrupt. */ | |
434 | pio_time = wait_for_completion_interruptible_timeout( | |
435 | &host->pio_complete, host->timeout); | |
436 | ||
437 | spin_lock_irqsave(&host->lock, flags); | |
438 | } | |
439 | ||
440 | if (host->is_removed) { | |
441 | dev_err(mmc_dev(host->mmc), "card removed\n"); | |
442 | mrq->cmd->error = -ETIMEDOUT; | |
443 | goto request_done; | |
444 | } | |
445 | ||
446 | if (moxart_wait_for_status(host, MASK_DATA, &status) | |
447 | == -ETIMEDOUT) { | |
448 | mrq->cmd->data->error = -ETIMEDOUT; | |
449 | goto request_done; | |
450 | } | |
451 | ||
452 | if (status & DATA_CRC_FAIL) | |
453 | mrq->cmd->data->error = -ETIMEDOUT; | |
454 | ||
455 | if (mrq->cmd->data->stop) | |
456 | moxart_send_command(host, mrq->cmd->data->stop); | |
457 | } | |
458 | ||
459 | request_done: | |
460 | spin_unlock_irqrestore(&host->lock, flags); | |
461 | mmc_request_done(host->mmc, mrq); | |
462 | } | |
463 | ||
464 | static irqreturn_t moxart_irq(int irq, void *devid) | |
465 | { | |
466 | struct moxart_host *host = (struct moxart_host *)devid; | |
467 | u32 status; | |
468 | unsigned long flags; | |
469 | ||
470 | spin_lock_irqsave(&host->lock, flags); | |
471 | ||
472 | status = readl(host->base + REG_STATUS); | |
473 | if (status & CARD_CHANGE) { | |
474 | host->is_removed = status & CARD_DETECT; | |
475 | if (host->is_removed && host->have_dma) { | |
476 | dmaengine_terminate_all(host->dma_chan_tx); | |
477 | dmaengine_terminate_all(host->dma_chan_rx); | |
478 | } | |
479 | host->mrq = NULL; | |
480 | writel(MASK_INTR_PIO, host->base + REG_CLEAR); | |
481 | writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); | |
482 | mmc_detect_change(host->mmc, 0); | |
483 | } | |
484 | if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq) | |
485 | moxart_transfer_pio(host); | |
486 | ||
487 | spin_unlock_irqrestore(&host->lock, flags); | |
488 | ||
489 | return IRQ_HANDLED; | |
490 | } | |
491 | ||
492 | static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
493 | { | |
494 | struct moxart_host *host = mmc_priv(mmc); | |
495 | unsigned long flags; | |
496 | u8 power, div; | |
497 | u32 ctrl; | |
498 | ||
499 | spin_lock_irqsave(&host->lock, flags); | |
500 | ||
501 | if (ios->clock) { | |
502 | for (div = 0; div < CLK_DIV_MASK; ++div) { | |
503 | if (ios->clock >= host->sysclk / (2 * (div + 1))) | |
504 | break; | |
505 | } | |
506 | ctrl = CLK_SD | div; | |
507 | host->rate = host->sysclk / (2 * (div + 1)); | |
508 | if (host->rate > host->sysclk) | |
509 | ctrl |= CLK_HISPD; | |
510 | writel(ctrl, host->base + REG_CLOCK_CONTROL); | |
511 | } | |
512 | ||
513 | if (ios->power_mode == MMC_POWER_OFF) { | |
514 | writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON, | |
515 | host->base + REG_POWER_CONTROL); | |
516 | } else { | |
517 | if (ios->vdd < MIN_POWER) | |
518 | power = 0; | |
519 | else | |
520 | power = ios->vdd - MIN_POWER; | |
521 | ||
522 | writel(SD_POWER_ON | (u32) power, | |
523 | host->base + REG_POWER_CONTROL); | |
524 | } | |
525 | ||
526 | switch (ios->bus_width) { | |
527 | case MMC_BUS_WIDTH_4: | |
528 | writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH); | |
529 | break; | |
530 | case MMC_BUS_WIDTH_8: | |
531 | writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH); | |
532 | break; | |
533 | default: | |
534 | writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH); | |
535 | break; | |
536 | } | |
537 | ||
538 | spin_unlock_irqrestore(&host->lock, flags); | |
539 | } | |
540 | ||
541 | ||
542 | static int moxart_get_ro(struct mmc_host *mmc) | |
543 | { | |
544 | struct moxart_host *host = mmc_priv(mmc); | |
545 | ||
546 | return !!(readl(host->base + REG_STATUS) & WRITE_PROT); | |
547 | } | |
548 | ||
549 | static struct mmc_host_ops moxart_ops = { | |
550 | .request = moxart_request, | |
551 | .set_ios = moxart_set_ios, | |
552 | .get_ro = moxart_get_ro, | |
553 | }; | |
554 | ||
555 | static int moxart_probe(struct platform_device *pdev) | |
556 | { | |
557 | struct device *dev = &pdev->dev; | |
558 | struct device_node *node = dev->of_node; | |
559 | struct resource res_mmc; | |
560 | struct mmc_host *mmc; | |
561 | struct moxart_host *host = NULL; | |
562 | struct dma_slave_config cfg; | |
563 | struct clk *clk; | |
564 | void __iomem *reg_mmc; | |
565 | dma_cap_mask_t mask; | |
566 | int irq, ret; | |
567 | u32 i; | |
568 | ||
569 | mmc = mmc_alloc_host(sizeof(struct moxart_host), dev); | |
570 | if (!mmc) { | |
571 | dev_err(dev, "mmc_alloc_host failed\n"); | |
572 | ret = -ENOMEM; | |
573 | goto out; | |
574 | } | |
575 | ||
576 | ret = of_address_to_resource(node, 0, &res_mmc); | |
577 | if (ret) { | |
578 | dev_err(dev, "of_address_to_resource failed\n"); | |
579 | goto out; | |
580 | } | |
581 | ||
582 | irq = irq_of_parse_and_map(node, 0); | |
583 | if (irq <= 0) { | |
584 | dev_err(dev, "irq_of_parse_and_map failed\n"); | |
585 | ret = -EINVAL; | |
586 | goto out; | |
587 | } | |
588 | ||
589 | clk = of_clk_get(node, 0); | |
590 | if (IS_ERR(clk)) { | |
591 | dev_err(dev, "of_clk_get failed\n"); | |
592 | ret = PTR_ERR(clk); | |
593 | goto out; | |
594 | } | |
595 | ||
596 | reg_mmc = devm_ioremap_resource(dev, &res_mmc); | |
597 | if (IS_ERR(reg_mmc)) { | |
598 | ret = PTR_ERR(reg_mmc); | |
599 | goto out; | |
600 | } | |
601 | ||
602 | mmc_of_parse(mmc); | |
603 | ||
604 | dma_cap_zero(mask); | |
605 | dma_cap_set(DMA_SLAVE, mask); | |
606 | ||
607 | host = mmc_priv(mmc); | |
608 | host->mmc = mmc; | |
609 | host->base = reg_mmc; | |
610 | host->reg_phys = res_mmc.start; | |
611 | host->timeout = msecs_to_jiffies(1000); | |
612 | host->sysclk = clk_get_rate(clk); | |
613 | host->fifo_width = readl(host->base + REG_FEATURE) << 2; | |
614 | host->dma_chan_tx = of_dma_request_slave_channel(node, "tx"); | |
615 | host->dma_chan_rx = of_dma_request_slave_channel(node, "rx"); | |
616 | ||
617 | spin_lock_init(&host->lock); | |
618 | ||
619 | mmc->ops = &moxart_ops; | |
620 | mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2); | |
621 | mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2); | |
622 | mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */ | |
623 | ||
624 | if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) { | |
625 | dev_dbg(dev, "PIO mode transfer enabled\n"); | |
626 | host->have_dma = false; | |
627 | } else { | |
628 | dev_dbg(dev, "DMA channels found (%p,%p)\n", | |
629 | host->dma_chan_tx, host->dma_chan_rx); | |
630 | host->have_dma = true; | |
631 | ||
632 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
633 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
634 | ||
635 | cfg.direction = DMA_MEM_TO_DEV; | |
636 | cfg.src_addr = 0; | |
637 | cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW; | |
638 | dmaengine_slave_config(host->dma_chan_tx, &cfg); | |
639 | ||
640 | cfg.direction = DMA_DEV_TO_MEM; | |
641 | cfg.src_addr = host->reg_phys + REG_DATA_WINDOW; | |
642 | cfg.dst_addr = 0; | |
643 | dmaengine_slave_config(host->dma_chan_rx, &cfg); | |
644 | } | |
645 | ||
646 | switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) { | |
647 | case 1: | |
648 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
649 | break; | |
650 | case 2: | |
651 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; | |
652 | break; | |
653 | default: | |
654 | break; | |
655 | } | |
656 | ||
657 | writel(0, host->base + REG_INTERRUPT_MASK); | |
658 | ||
659 | writel(CMD_SDC_RESET, host->base + REG_COMMAND); | |
660 | for (i = 0; i < MAX_RETRIES; i++) { | |
661 | if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET)) | |
662 | break; | |
663 | udelay(5); | |
664 | } | |
665 | ||
666 | ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host); | |
667 | if (ret) | |
668 | goto out; | |
669 | ||
670 | dev_set_drvdata(dev, mmc); | |
671 | mmc_add_host(mmc); | |
672 | ||
673 | dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width); | |
674 | ||
675 | return 0; | |
676 | ||
677 | out: | |
678 | if (mmc) | |
679 | mmc_free_host(mmc); | |
680 | return ret; | |
681 | } | |
682 | ||
683 | static int moxart_remove(struct platform_device *pdev) | |
684 | { | |
685 | struct mmc_host *mmc = dev_get_drvdata(&pdev->dev); | |
686 | struct moxart_host *host = mmc_priv(mmc); | |
687 | ||
688 | dev_set_drvdata(&pdev->dev, NULL); | |
689 | ||
690 | if (mmc) { | |
691 | if (!IS_ERR(host->dma_chan_tx)) | |
692 | dma_release_channel(host->dma_chan_tx); | |
693 | if (!IS_ERR(host->dma_chan_rx)) | |
694 | dma_release_channel(host->dma_chan_rx); | |
695 | mmc_remove_host(mmc); | |
696 | mmc_free_host(mmc); | |
697 | ||
698 | writel(0, host->base + REG_INTERRUPT_MASK); | |
699 | writel(0, host->base + REG_POWER_CONTROL); | |
700 | writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF, | |
701 | host->base + REG_CLOCK_CONTROL); | |
702 | } | |
703 | ||
704 | kfree(host); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static const struct of_device_id moxart_mmc_match[] = { | |
710 | { .compatible = "moxa,moxart-mmc" }, | |
711 | { .compatible = "faraday,ftsdc010" }, | |
712 | { } | |
713 | }; | |
714 | ||
715 | static struct platform_driver moxart_mmc_driver = { | |
716 | .probe = moxart_probe, | |
717 | .remove = moxart_remove, | |
718 | .driver = { | |
719 | .name = "mmc-moxart", | |
1b66e94e JJ |
720 | .of_match_table = moxart_mmc_match, |
721 | }, | |
722 | }; | |
723 | module_platform_driver(moxart_mmc_driver); | |
724 | ||
725 | MODULE_ALIAS("platform:mmc-moxart"); | |
726 | MODULE_DESCRIPTION("MOXA ART MMC driver"); | |
727 | MODULE_LICENSE("GPL v2"); | |
728 | MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>"); |