[linux-2.6-block.git] / drivers / mmc / host / mmci.h

/*
 *  linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
 *
 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#define MMCIPOWER		0x000
#define MCI_PWR_OFF		0x00
#define MCI_PWR_UP		0x02
#define MCI_PWR_ON		0x03
#define MCI_OD			(1 << 6)
#define MCI_ROD			(1 << 7)
/*
 * The ST Micro version does not have ROD and reuse the voltage registers for
 * direction settings.
 */
#define MCI_ST_DATA2DIREN	(1 << 2)
#define MCI_ST_CMDDIREN		(1 << 3)
#define MCI_ST_DATA0DIREN	(1 << 4)
#define MCI_ST_DATA31DIREN	(1 << 5)
#define MCI_ST_FBCLKEN		(1 << 7)
#define MCI_ST_DATA74DIREN	(1 << 8)

#define MMCICLOCK		0x004
#define MCI_CLK_ENABLE		(1 << 8)
#define MCI_CLK_PWRSAVE		(1 << 9)
#define MCI_CLK_BYPASS		(1 << 10)
#define MCI_4BIT_BUS		(1 << 11)
/*
 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
 * supported in ST Micro U300 and Ux500 versions
 */
#define MCI_ST_8BIT_BUS		(1 << 12)
#define MCI_ST_U300_HWFCEN	(1 << 13)
#define MCI_ST_UX500_NEG_EDGE	(1 << 13)
#define MCI_ST_UX500_HWFCEN	(1 << 14)
#define MCI_ST_UX500_CLK_INV	(1 << 15)
/* Modified PL180 on Versatile Express platform */
#define MCI_ARM_HWFCEN		(1 << 12)

/* Modified on Qualcomm Integrations */
#define MCI_QCOM_CLK_WIDEBUS_8	(BIT(10) | BIT(11))
#define MCI_QCOM_CLK_FLOWENA	BIT(12)
#define MCI_QCOM_CLK_INVERTOUT	BIT(13)

/* select in latch data and command in */
#define MCI_QCOM_CLK_SELECT_IN_FBCLK	BIT(15)
#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE	(BIT(14) | BIT(15))

#define MMCIARGUMENT		0x008
#define MMCICOMMAND		0x00c
#define MCI_CPSM_RESPONSE	(1 << 6)
#define MCI_CPSM_LONGRSP	(1 << 7)
#define MCI_CPSM_INTERRUPT	(1 << 8)
#define MCI_CPSM_PENDING	(1 << 9)
#define MCI_CPSM_ENABLE		(1 << 10)
/* Argument flag extenstions in the ST Micro versions */
#define MCI_ST_SDIO_SUSP	(1 << 11)
#define MCI_ST_ENCMD_COMPL	(1 << 12)
#define MCI_ST_NIEN		(1 << 13)
#define MCI_ST_CE_ATACMD	(1 << 14)

/* Modified on Qualcomm Integrations */
#define MCI_QCOM_CSPM_DATCMD		BIT(12)
#define MCI_QCOM_CSPM_MCIABORT		BIT(13)
#define MCI_QCOM_CSPM_CCSENABLE		BIT(14)
#define MCI_QCOM_CSPM_CCSDISABLE	BIT(15)
#define MCI_QCOM_CSPM_AUTO_CMD19	BIT(16)
#define MCI_QCOM_CSPM_AUTO_CMD21	BIT(21)

#define MMCIRESPCMD		0x010
#define MMCIRESPONSE0		0x014
#define MMCIRESPONSE1		0x018
#define MMCIRESPONSE2		0x01c
#define MMCIRESPONSE3		0x020
#define MMCIDATATIMER		0x024
#define MMCIDATALENGTH		0x028
#define MMCIDATACTRL		0x02c
#define MCI_DPSM_ENABLE		(1 << 0)
#define MCI_DPSM_DIRECTION	(1 << 1)
#define MCI_DPSM_MODE		(1 << 2)
#define MCI_DPSM_DMAENABLE	(1 << 3)
#define MCI_DPSM_BLOCKSIZE	(1 << 4)
/* Control register extensions in the ST Micro U300 and Ux500 versions */
#define MCI_ST_DPSM_RWSTART	(1 << 8)
#define MCI_ST_DPSM_RWSTOP	(1 << 9)
#define MCI_ST_DPSM_RWMOD	(1 << 10)
#define MCI_ST_DPSM_SDIOEN	(1 << 11)
/* Control register extensions in the ST Micro Ux500 versions */
#define MCI_ST_DPSM_DMAREQCTL	(1 << 12)
#define MCI_ST_DPSM_DBOOTMODEEN	(1 << 13)
#define MCI_ST_DPSM_BUSYMODE	(1 << 14)
#define MCI_ST_DPSM_DDRMODE	(1 << 15)

#define MMCIDATACNT		0x030
#define MMCISTATUS		0x034
#define MCI_CMDCRCFAIL		(1 << 0)
#define MCI_DATACRCFAIL		(1 << 1)
#define MCI_CMDTIMEOUT		(1 << 2)
#define MCI_DATATIMEOUT		(1 << 3)
#define MCI_TXUNDERRUN		(1 << 4)
#define MCI_RXOVERRUN		(1 << 5)
#define MCI_CMDRESPEND		(1 << 6)
#define MCI_CMDSENT		(1 << 7)
#define MCI_DATAEND		(1 << 8)
#define MCI_STARTBITERR		(1 << 9)
#define MCI_DATABLOCKEND	(1 << 10)
#define MCI_CMDACTIVE		(1 << 11)
#define MCI_TXACTIVE		(1 << 12)
#define MCI_RXACTIVE		(1 << 13)
#define MCI_TXFIFOHALFEMPTY	(1 << 14)
#define MCI_RXFIFOHALFFULL	(1 << 15)
#define MCI_TXFIFOFULL		(1 << 16)
#define MCI_RXFIFOFULL		(1 << 17)
#define MCI_TXFIFOEMPTY		(1 << 18)
#define MCI_RXFIFOEMPTY		(1 << 19)
#define MCI_TXDATAAVLBL		(1 << 20)
#define MCI_RXDATAAVLBL		(1 << 21)
/* Extended status bits for the ST Micro variants */
#define MCI_ST_SDIOIT		(1 << 22)
#define MCI_ST_CEATAEND		(1 << 23)
#define MCI_ST_CARDBUSY		(1 << 24)

#define MMCICLEAR		0x038
#define MCI_CMDCRCFAILCLR	(1 << 0)
#define MCI_DATACRCFAILCLR	(1 << 1)
#define MCI_CMDTIMEOUTCLR	(1 << 2)
#define MCI_DATATIMEOUTCLR	(1 << 3)
#define MCI_TXUNDERRUNCLR	(1 << 4)
#define MCI_RXOVERRUNCLR	(1 << 5)
#define MCI_CMDRESPENDCLR	(1 << 6)
#define MCI_CMDSENTCLR		(1 << 7)
#define MCI_DATAENDCLR		(1 << 8)
#define MCI_STARTBITERRCLR	(1 << 9)
#define MCI_DATABLOCKENDCLR	(1 << 10)
/* Extended status bits for the ST Micro variants */
#define MCI_ST_SDIOITC		(1 << 22)
#define MCI_ST_CEATAENDC	(1 << 23)
#define MCI_ST_BUSYENDC		(1 << 24)

#define MMCIMASK0		0x03c
#define MCI_CMDCRCFAILMASK	(1 << 0)
#define MCI_DATACRCFAILMASK	(1 << 1)
#define MCI_CMDTIMEOUTMASK	(1 << 2)
#define MCI_DATATIMEOUTMASK	(1 << 3)
#define MCI_TXUNDERRUNMASK	(1 << 4)
#define MCI_RXOVERRUNMASK	(1 << 5)
#define MCI_CMDRESPENDMASK	(1 << 6)
#define MCI_CMDSENTMASK		(1 << 7)
#define MCI_DATAENDMASK		(1 << 8)
#define MCI_STARTBITERRMASK	(1 << 9)
#define MCI_DATABLOCKENDMASK	(1 << 10)
#define MCI_CMDACTIVEMASK	(1 << 11)
#define MCI_TXACTIVEMASK	(1 << 12)
#define MCI_RXACTIVEMASK	(1 << 13)
#define MCI_TXFIFOHALFEMPTYMASK	(1 << 14)
#define MCI_RXFIFOHALFFULLMASK	(1 << 15)
#define MCI_TXFIFOFULLMASK	(1 << 16)
#define MCI_RXFIFOFULLMASK	(1 << 17)
#define MCI_TXFIFOEMPTYMASK	(1 << 18)
#define MCI_RXFIFOEMPTYMASK	(1 << 19)
#define MCI_TXDATAAVLBLMASK	(1 << 20)
#define MCI_RXDATAAVLBLMASK	(1 << 21)
/* Extended status bits for the ST Micro variants */
#define MCI_ST_SDIOITMASK	(1 << 22)
#define MCI_ST_CEATAENDMASK	(1 << 23)
#define MCI_ST_BUSYEND		(1 << 24)

#define MMCIMASK1		0x040
#define MMCIFIFOCNT		0x048
#define MMCIFIFO		0x080 /* to 0x0bc */

#define MCI_IRQENABLE	\
	(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK|	\
	MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK|	\
	MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK)

/* These interrupts are directed to IRQ1 when two IRQ lines are available */
#define MCI_IRQ1MASK \
	(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
	 MCI_TXFIFOHALFEMPTYMASK)

#define NR_SG		128

struct clk;
struct variant_data;
struct dma_chan;

struct mmci_host_next {
	struct dma_async_tx_descriptor	*dma_desc;
	struct dma_chan			*dma_chan;
	s32				cookie;
};

struct mmci_host {
	phys_addr_t		phybase;
	void __iomem		*base;
	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;
	struct mmc_host		*mmc;
	struct clk		*clk;
	bool			singleirq;

	spinlock_t		lock;

	unsigned int		mclk;
	/* cached value of requested clk in set_ios */
	unsigned int		clock_cache;
	unsigned int		cclk;
	u32			pwr_reg;
	u32			pwr_reg_add;
	u32			clk_reg;
	u32			datactrl_reg;
	u32			busy_status;
	bool			vqmmc_enabled;
	struct mmci_platform_data *plat;
	struct variant_data	*variant;

	u8			hw_designer;
	u8			hw_revision:4;

	struct timer_list	timer;
	unsigned int		oldstat;

	/* pio stuff */
	struct sg_mapping_iter	sg_miter;
	unsigned int		size;
	int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);

#ifdef CONFIG_DMA_ENGINE
	/* DMA stuff */
	struct dma_chan		*dma_current;
	struct dma_chan		*dma_rx_channel;
	struct dma_chan		*dma_tx_channel;
	struct dma_async_tx_descriptor	*dma_desc_current;
	struct mmci_host_next	next_data;

#define dma_inprogress(host)	((host)->dma_current)
#else
#define dma_inprogress(host)	(0)
#endif
};
Commit	Line	Data
1da177e4	1	/*
70f10482	2	* linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
1da177e4 LT	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#define MMCIPOWER 0x000
	11	#define MCI_PWR_OFF 0x00
	12	#define MCI_PWR_UP 0x02
	13	#define MCI_PWR_ON 0x03
	14	#define MCI_OD (1 << 6)
	15	#define MCI_ROD (1 << 7)
4593df29 UH	16	/*
	17	* The ST Micro version does not have ROD and reuse the voltage registers for
	18	* direction settings.
	19	*/
	20	#define MCI_ST_DATA2DIREN (1 << 2)
	21	#define MCI_ST_CMDDIREN (1 << 3)
	22	#define MCI_ST_DATA0DIREN (1 << 4)
	23	#define MCI_ST_DATA31DIREN (1 << 5)
	24	#define MCI_ST_FBCLKEN (1 << 7)
	25	#define MCI_ST_DATA74DIREN (1 << 8)
1da177e4 LT	26
	27	#define MMCICLOCK 0x004
	28	#define MCI_CLK_ENABLE (1 << 8)
	29	#define MCI_CLK_PWRSAVE (1 << 9)
	30	#define MCI_CLK_BYPASS (1 << 10)
771dc157	31	#define MCI_4BIT_BUS (1 << 11)
49ac215e LW	32	/*
	33	* 8bit wide buses, hardware flow contronl, negative edges and clock inversion
	34	* supported in ST Micro U300 and Ux500 versions
	35	*/
771dc157	36	#define MCI_ST_8BIT_BUS (1 << 12)
49ac215e LW	37	#define MCI_ST_U300_HWFCEN (1 << 13)
	38	#define MCI_ST_UX500_NEG_EDGE (1 << 13)
	39	#define MCI_ST_UX500_HWFCEN (1 << 14)
	40	#define MCI_ST_UX500_CLK_INV (1 << 15)
3a37298a PM	41	/* Modified PL180 on Versatile Express platform */
3a37298a PM	42	#define MCI_ARM_HWFCEN (1 << 12)
1da177e4	43
9681a4e8 SK	44	/* Modified on Qualcomm Integrations */
	45	#define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) \| BIT(11))
	46	#define MCI_QCOM_CLK_FLOWENA BIT(12)
	47	#define MCI_QCOM_CLK_INVERTOUT BIT(13)
	48
	49	/* select in latch data and command in */
	50	#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
	51	#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) \| BIT(15))
	52
1da177e4 LT	53	#define MMCIARGUMENT 0x008
	54	#define MMCICOMMAND 0x00c
	55	#define MCI_CPSM_RESPONSE (1 << 6)
	56	#define MCI_CPSM_LONGRSP (1 << 7)
	57	#define MCI_CPSM_INTERRUPT (1 << 8)
	58	#define MCI_CPSM_PENDING (1 << 9)
	59	#define MCI_CPSM_ENABLE (1 << 10)
dfdf5f63 LW	60	/* Argument flag extenstions in the ST Micro versions */
	61	#define MCI_ST_SDIO_SUSP (1 << 11)
	62	#define MCI_ST_ENCMD_COMPL (1 << 12)
	63	#define MCI_ST_NIEN (1 << 13)
	64	#define MCI_ST_CE_ATACMD (1 << 14)
1da177e4	65
9681a4e8 SK	66	/* Modified on Qualcomm Integrations */
	67	#define MCI_QCOM_CSPM_DATCMD BIT(12)
	68	#define MCI_QCOM_CSPM_MCIABORT BIT(13)
	69	#define MCI_QCOM_CSPM_CCSENABLE BIT(14)
	70	#define MCI_QCOM_CSPM_CCSDISABLE BIT(15)
	71	#define MCI_QCOM_CSPM_AUTO_CMD19 BIT(16)
	72	#define MCI_QCOM_CSPM_AUTO_CMD21 BIT(21)
	73
1da177e4 LT	74	#define MMCIRESPCMD 0x010
	75	#define MMCIRESPONSE0 0x014
	76	#define MMCIRESPONSE1 0x018
	77	#define MMCIRESPONSE2 0x01c
	78	#define MMCIRESPONSE3 0x020
	79	#define MMCIDATATIMER 0x024
	80	#define MMCIDATALENGTH 0x028
	81	#define MMCIDATACTRL 0x02c
	82	#define MCI_DPSM_ENABLE (1 << 0)
	83	#define MCI_DPSM_DIRECTION (1 << 1)
	84	#define MCI_DPSM_MODE (1 << 2)
	85	#define MCI_DPSM_DMAENABLE (1 << 3)
cc30d60e	86	#define MCI_DPSM_BLOCKSIZE (1 << 4)
725343fa LW	87	/* Control register extensions in the ST Micro U300 and Ux500 versions */
	88	#define MCI_ST_DPSM_RWSTART (1 << 8)
	89	#define MCI_ST_DPSM_RWSTOP (1 << 9)
	90	#define MCI_ST_DPSM_RWMOD (1 << 10)
	91	#define MCI_ST_DPSM_SDIOEN (1 << 11)
	92	/* Control register extensions in the ST Micro Ux500 versions */
	93	#define MCI_ST_DPSM_DMAREQCTL (1 << 12)
	94	#define MCI_ST_DPSM_DBOOTMODEEN (1 << 13)
	95	#define MCI_ST_DPSM_BUSYMODE (1 << 14)
	96	#define MCI_ST_DPSM_DDRMODE (1 << 15)
1da177e4 LT	97
	98	#define MMCIDATACNT 0x030
	99	#define MMCISTATUS 0x034
	100	#define MCI_CMDCRCFAIL (1 << 0)
	101	#define MCI_DATACRCFAIL (1 << 1)
	102	#define MCI_CMDTIMEOUT (1 << 2)
	103	#define MCI_DATATIMEOUT (1 << 3)
	104	#define MCI_TXUNDERRUN (1 << 4)
	105	#define MCI_RXOVERRUN (1 << 5)
	106	#define MCI_CMDRESPEND (1 << 6)
	107	#define MCI_CMDSENT (1 << 7)
	108	#define MCI_DATAEND (1 << 8)
757df746	109	#define MCI_STARTBITERR (1 << 9)
1da177e4 LT	110	#define MCI_DATABLOCKEND (1 << 10)
	111	#define MCI_CMDACTIVE (1 << 11)
	112	#define MCI_TXACTIVE (1 << 12)
	113	#define MCI_RXACTIVE (1 << 13)
	114	#define MCI_TXFIFOHALFEMPTY (1 << 14)
	115	#define MCI_RXFIFOHALFFULL (1 << 15)
	116	#define MCI_TXFIFOFULL (1 << 16)
	117	#define MCI_RXFIFOFULL (1 << 17)
	118	#define MCI_TXFIFOEMPTY (1 << 18)
	119	#define MCI_RXFIFOEMPTY (1 << 19)
	120	#define MCI_TXDATAAVLBL (1 << 20)
	121	#define MCI_RXDATAAVLBL (1 << 21)
49ac215e LW	122	/* Extended status bits for the ST Micro variants */
	123	#define MCI_ST_SDIOIT (1 << 22)
	124	#define MCI_ST_CEATAEND (1 << 23)
01259620	125	#define MCI_ST_CARDBUSY (1 << 24)
1da177e4 LT	126
	127	#define MMCICLEAR 0x038
	128	#define MCI_CMDCRCFAILCLR (1 << 0)
	129	#define MCI_DATACRCFAILCLR (1 << 1)
	130	#define MCI_CMDTIMEOUTCLR (1 << 2)
	131	#define MCI_DATATIMEOUTCLR (1 << 3)
	132	#define MCI_TXUNDERRUNCLR (1 << 4)
	133	#define MCI_RXOVERRUNCLR (1 << 5)
	134	#define MCI_CMDRESPENDCLR (1 << 6)
	135	#define MCI_CMDSENTCLR (1 << 7)
	136	#define MCI_DATAENDCLR (1 << 8)
757df746	137	#define MCI_STARTBITERRCLR (1 << 9)
1da177e4	138	#define MCI_DATABLOCKENDCLR (1 << 10)
49ac215e LW	139	/* Extended status bits for the ST Micro variants */
	140	#define MCI_ST_SDIOITC (1 << 22)
	141	#define MCI_ST_CEATAENDC (1 << 23)
01259620	142	#define MCI_ST_BUSYENDC (1 << 24)
1da177e4 LT	143
	144	#define MMCIMASK0 0x03c
	145	#define MCI_CMDCRCFAILMASK (1 << 0)
	146	#define MCI_DATACRCFAILMASK (1 << 1)
	147	#define MCI_CMDTIMEOUTMASK (1 << 2)
	148	#define MCI_DATATIMEOUTMASK (1 << 3)
	149	#define MCI_TXUNDERRUNMASK (1 << 4)
	150	#define MCI_RXOVERRUNMASK (1 << 5)
	151	#define MCI_CMDRESPENDMASK (1 << 6)
	152	#define MCI_CMDSENTMASK (1 << 7)
	153	#define MCI_DATAENDMASK (1 << 8)
757df746	154	#define MCI_STARTBITERRMASK (1 << 9)
1da177e4 LT	155	#define MCI_DATABLOCKENDMASK (1 << 10)
	156	#define MCI_CMDACTIVEMASK (1 << 11)
	157	#define MCI_TXACTIVEMASK (1 << 12)
	158	#define MCI_RXACTIVEMASK (1 << 13)
	159	#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
	160	#define MCI_RXFIFOHALFFULLMASK (1 << 15)
	161	#define MCI_TXFIFOFULLMASK (1 << 16)
	162	#define MCI_RXFIFOFULLMASK (1 << 17)
	163	#define MCI_TXFIFOEMPTYMASK (1 << 18)
	164	#define MCI_RXFIFOEMPTYMASK (1 << 19)
	165	#define MCI_TXDATAAVLBLMASK (1 << 20)
	166	#define MCI_RXDATAAVLBLMASK (1 << 21)
49ac215e LW	167	/* Extended status bits for the ST Micro variants */
	168	#define MCI_ST_SDIOITMASK (1 << 22)
	169	#define MCI_ST_CEATAENDMASK (1 << 23)
8d94b54d	170	#define MCI_ST_BUSYEND (1 << 24)
1da177e4 LT	171
	172	#define MMCIMASK1 0x040
	173	#define MMCIFIFOCNT 0x048
	174	#define MMCIFIFO 0x080 /* to 0x0bc */
	175
	176	#define MCI_IRQENABLE \
	177	(MCI_CMDCRCFAILMASK\|MCI_DATACRCFAILMASK\|MCI_CMDTIMEOUTMASK\| \
	178	MCI_DATATIMEOUTMASK\|MCI_TXUNDERRUNMASK\|MCI_RXOVERRUNMASK\| \
757df746	179	MCI_CMDRESPENDMASK\|MCI_CMDSENTMASK\|MCI_STARTBITERRMASK)
1da177e4	180
2686b4b4 LW	181	/* These interrupts are directed to IRQ1 when two IRQ lines are available */
	182	#define MCI_IRQ1MASK \
	183	(MCI_RXFIFOHALFFULLMASK \| MCI_RXDATAAVLBLMASK \| \
	184	MCI_TXFIFOHALFEMPTYMASK)
	185
859dd55d	186	#define NR_SG 128
1da177e4 LT	187
1da177e4 LT	188	struct clk;
4956e109	189	struct variant_data;
c8ebae37	190	struct dma_chan;
1da177e4	191
58c7ccbf PF	192	struct mmci_host_next {
	193	struct dma_async_tx_descriptor *dma_desc;
	194	struct dma_chan *dma_chan;
	195	s32 cookie;
	196	};
	197
1da177e4	198	struct mmci_host {
c8ebae37	199	phys_addr_t phybase;
1da177e4 LT	200	void __iomem *base;
	201	struct mmc_request *mrq;
	202	struct mmc_command *cmd;
	203	struct mmc_data *data;
	204	struct mmc_host *mmc;
	205	struct clk *clk;
2686b4b4	206	bool singleirq;
1da177e4	207
1da177e4 LT	208	spinlock_t lock;
	209
	210	unsigned int mclk;
3f4e6f7b SK	211	/* cached value of requested clk in set_ios */
3f4e6f7b SK	212	unsigned int clock_cache;
1da177e4	213	unsigned int cclk;
7437cfa5	214	u32 pwr_reg;
4593df29	215	u32 pwr_reg_add;
7437cfa5	216	u32 clk_reg;
9cc639a2	217	u32 datactrl_reg;
8d94b54d	218	u32 busy_status;
7c0136ef	219	bool vqmmc_enabled;
6ef297f8	220	struct mmci_platform_data *plat;
4956e109	221	struct variant_data *variant;
1da177e4	222
cc30d60e LW	223	u8 hw_designer;
	224	u8 hw_revision:4;
	225
1da177e4 LT	226	struct timer_list timer;
	227	unsigned int oldstat;
	228
1da177e4	229	/* pio stuff */
4ce1d6cb	230	struct sg_mapping_iter sg_miter;
1da177e4	231	unsigned int size;
9c34b73d	232	int (get_rx_fifocnt)(struct mmci_host h, u32 status, int remain);
c8ebae37 RK	233
	234	#ifdef CONFIG_DMA_ENGINE
	235	/* DMA stuff */
	236	struct dma_chan *dma_current;
	237	struct dma_chan *dma_rx_channel;
	238	struct dma_chan *dma_tx_channel;
58c7ccbf PF	239	struct dma_async_tx_descriptor *dma_desc_current;
58c7ccbf PF	240	struct mmci_host_next next_data;
c8ebae37 RK	241
	242	#define dma_inprogress(host) ((host)->dma_current)
	243	#else
	244	#define dma_inprogress(host) (0)
	245	#endif
1da177e4 LT	246	};
1da177e4 LT	247