[linux-2.6-block.git] / drivers / mmc / host / mmci.h

/*
 *  linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
 *
 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#define MMCIPOWER		0x000
#define MCI_PWR_OFF		0x00
#define MCI_PWR_UP		0x02
#define MCI_PWR_ON		0x03
#define MCI_OD			(1 << 6)
#define MCI_ROD			(1 << 7)
/*
 * The ST Micro version does not have ROD and reuse the voltage registers for
 * direction settings.
 */
#define MCI_ST_DATA2DIREN	(1 << 2)
#define MCI_ST_CMDDIREN		(1 << 3)
#define MCI_ST_DATA0DIREN	(1 << 4)
#define MCI_ST_DATA31DIREN	(1 << 5)
#define MCI_ST_FBCLKEN		(1 << 7)
#define MCI_ST_DATA74DIREN	(1 << 8)
/*
 * The STM32 sdmmc does not have PWR_UP/OD/ROD
 * and uses the power register for
 */
#define MCI_STM32_PWR_CYC	0x02
#define MCI_STM32_VSWITCH	BIT(2)
#define MCI_STM32_VSWITCHEN	BIT(3)
#define MCI_STM32_DIRPOL	BIT(4)

#define MMCICLOCK		0x004
#define MCI_CLK_ENABLE		(1 << 8)
#define MCI_CLK_PWRSAVE		(1 << 9)
#define MCI_CLK_BYPASS		(1 << 10)
#define MCI_4BIT_BUS		(1 << 11)
/*
 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
 * supported in ST Micro U300 and Ux500 versions
 */
#define MCI_ST_8BIT_BUS		(1 << 12)
#define MCI_ST_U300_HWFCEN	(1 << 13)
#define MCI_ST_UX500_NEG_EDGE	(1 << 13)
#define MCI_ST_UX500_HWFCEN	(1 << 14)
#define MCI_ST_UX500_CLK_INV	(1 << 15)
/* Modified PL180 on Versatile Express platform */
#define MCI_ARM_HWFCEN		(1 << 12)

/* Modified on Qualcomm Integrations */
#define MCI_QCOM_CLK_WIDEBUS_8	(BIT(10) | BIT(11))
#define MCI_QCOM_CLK_FLOWENA	BIT(12)
#define MCI_QCOM_CLK_INVERTOUT	BIT(13)

/* select in latch data and command in */
#define MCI_QCOM_CLK_SELECT_IN_FBCLK	BIT(15)
#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE	(BIT(14) | BIT(15))

/* Modified on STM32 sdmmc */
#define MCI_STM32_CLK_CLKDIV_MSK	GENMASK(9, 0)
#define MCI_STM32_CLK_WIDEBUS_4		BIT(14)
#define MCI_STM32_CLK_WIDEBUS_8		BIT(15)
#define MCI_STM32_CLK_NEGEDGE		BIT(16)
#define MCI_STM32_CLK_HWFCEN		BIT(17)
#define MCI_STM32_CLK_DDR		BIT(18)
#define MCI_STM32_CLK_BUSSPEED		BIT(19)
#define MCI_STM32_CLK_SEL_MSK		GENMASK(21, 20)
#define MCI_STM32_CLK_SELCK		(0 << 20)
#define MCI_STM32_CLK_SELCKIN		(1 << 20)
#define MCI_STM32_CLK_SELFBCK		(2 << 20)

#define MMCIARGUMENT		0x008

/* The command register controls the Command Path State Machine (CPSM) */
#define MMCICOMMAND		0x00c
#define MCI_CPSM_RESPONSE	BIT(6)
#define MCI_CPSM_LONGRSP	BIT(7)
#define MCI_CPSM_INTERRUPT	BIT(8)
#define MCI_CPSM_PENDING	BIT(9)
#define MCI_CPSM_ENABLE		BIT(10)
/* Command register flag extenstions in the ST Micro versions */
#define MCI_CPSM_ST_SDIO_SUSP		BIT(11)
#define MCI_CPSM_ST_ENCMD_COMPL		BIT(12)
#define MCI_CPSM_ST_NIEN		BIT(13)
#define MCI_CPSM_ST_CE_ATACMD		BIT(14)
/* Command register flag extensions in the Qualcomm versions */
#define MCI_CPSM_QCOM_PROGENA		BIT(11)
#define MCI_CPSM_QCOM_DATCMD		BIT(12)
#define MCI_CPSM_QCOM_MCIABORT		BIT(13)
#define MCI_CPSM_QCOM_CCSENABLE		BIT(14)
#define MCI_CPSM_QCOM_CCSDISABLE	BIT(15)
#define MCI_CPSM_QCOM_AUTO_CMD19	BIT(16)
#define MCI_CPSM_QCOM_AUTO_CMD21	BIT(21)
/* Command register in STM32 sdmmc versions */
#define MCI_CPSM_STM32_CMDTRANS		BIT(6)
#define MCI_CPSM_STM32_CMDSTOP		BIT(7)
#define MCI_CPSM_STM32_WAITRESP_MASK	GENMASK(9, 8)
#define MCI_CPSM_STM32_NORSP		(0 << 8)
#define MCI_CPSM_STM32_SRSP_CRC		(1 << 8)
#define MCI_CPSM_STM32_SRSP		(2 << 8)
#define MCI_CPSM_STM32_LRSP_CRC		(3 << 8)
#define MCI_CPSM_STM32_ENABLE		BIT(12)

#define MMCIRESPCMD		0x010
#define MMCIRESPONSE0		0x014
#define MMCIRESPONSE1		0x018
#define MMCIRESPONSE2		0x01c
#define MMCIRESPONSE3		0x020
#define MMCIDATATIMER		0x024
#define MMCIDATALENGTH		0x028

/* The data control register controls the Data Path State Machine (DPSM) */
#define MMCIDATACTRL		0x02c
#define MCI_DPSM_ENABLE		BIT(0)
#define MCI_DPSM_DIRECTION	BIT(1)
#define MCI_DPSM_MODE		BIT(2)
#define MCI_DPSM_DMAENABLE	BIT(3)
#define MCI_DPSM_BLOCKSIZE	BIT(4)
/* Control register extensions in the ST Micro U300 and Ux500 versions */
#define MCI_DPSM_ST_RWSTART	BIT(8)
#define MCI_DPSM_ST_RWSTOP	BIT(9)
#define MCI_DPSM_ST_RWMOD	BIT(10)
#define MCI_DPSM_ST_SDIOEN	BIT(11)
/* Control register extensions in the ST Micro Ux500 versions */
#define MCI_DPSM_ST_DMAREQCTL	BIT(12)
#define MCI_DPSM_ST_DBOOTMODEEN	BIT(13)
#define MCI_DPSM_ST_BUSYMODE	BIT(14)
#define MCI_DPSM_ST_DDRMODE	BIT(15)
/* Control register extensions in the Qualcomm versions */
#define MCI_DPSM_QCOM_DATA_PEND	BIT(17)
#define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)

#define MMCIDATACNT		0x030
#define MMCISTATUS		0x034
#define MCI_CMDCRCFAIL		(1 << 0)
#define MCI_DATACRCFAIL		(1 << 1)
#define MCI_CMDTIMEOUT		(1 << 2)
#define MCI_DATATIMEOUT		(1 << 3)
#define MCI_TXUNDERRUN		(1 << 4)
#define MCI_RXOVERRUN		(1 << 5)
#define MCI_CMDRESPEND		(1 << 6)
#define MCI_CMDSENT		(1 << 7)
#define MCI_DATAEND		(1 << 8)
#define MCI_STARTBITERR		(1 << 9)
#define MCI_DATABLOCKEND	(1 << 10)
#define MCI_CMDACTIVE		(1 << 11)
#define MCI_TXACTIVE		(1 << 12)
#define MCI_RXACTIVE		(1 << 13)
#define MCI_TXFIFOHALFEMPTY	(1 << 14)
#define MCI_RXFIFOHALFFULL	(1 << 15)
#define MCI_TXFIFOFULL		(1 << 16)
#define MCI_RXFIFOFULL		(1 << 17)
#define MCI_TXFIFOEMPTY		(1 << 18)
#define MCI_RXFIFOEMPTY		(1 << 19)
#define MCI_TXDATAAVLBL		(1 << 20)
#define MCI_RXDATAAVLBL		(1 << 21)
/* Extended status bits for the ST Micro variants */
#define MCI_ST_SDIOIT		(1 << 22)
#define MCI_ST_CEATAEND		(1 << 23)
#define MCI_ST_CARDBUSY		(1 << 24)
/* Extended status bits for the STM32 variants */
#define MCI_STM32_BUSYD0	BIT(20)

#define MMCICLEAR		0x038
#define MCI_CMDCRCFAILCLR	(1 << 0)
#define MCI_DATACRCFAILCLR	(1 << 1)
#define MCI_CMDTIMEOUTCLR	(1 << 2)
#define MCI_DATATIMEOUTCLR	(1 << 3)
#define MCI_TXUNDERRUNCLR	(1 << 4)
#define MCI_RXOVERRUNCLR	(1 << 5)
#define MCI_CMDRESPENDCLR	(1 << 6)
#define MCI_CMDSENTCLR		(1 << 7)
#define MCI_DATAENDCLR		(1 << 8)
#define MCI_STARTBITERRCLR	(1 << 9)
#define MCI_DATABLOCKENDCLR	(1 << 10)
/* Extended status bits for the ST Micro variants */
#define MCI_ST_SDIOITC		(1 << 22)
#define MCI_ST_CEATAENDC	(1 << 23)
#define MCI_ST_BUSYENDC		(1 << 24)

#define MMCIMASK0		0x03c
#define MCI_CMDCRCFAILMASK	(1 << 0)
#define MCI_DATACRCFAILMASK	(1 << 1)
#define MCI_CMDTIMEOUTMASK	(1 << 2)
#define MCI_DATATIMEOUTMASK	(1 << 3)
#define MCI_TXUNDERRUNMASK	(1 << 4)
#define MCI_RXOVERRUNMASK	(1 << 5)
#define MCI_CMDRESPENDMASK	(1 << 6)
#define MCI_CMDSENTMASK		(1 << 7)
#define MCI_DATAENDMASK		(1 << 8)
#define MCI_STARTBITERRMASK	(1 << 9)
#define MCI_DATABLOCKENDMASK	(1 << 10)
#define MCI_CMDACTIVEMASK	(1 << 11)
#define MCI_TXACTIVEMASK	(1 << 12)
#define MCI_RXACTIVEMASK	(1 << 13)
#define MCI_TXFIFOHALFEMPTYMASK	(1 << 14)
#define MCI_RXFIFOHALFFULLMASK	(1 << 15)
#define MCI_TXFIFOFULLMASK	(1 << 16)
#define MCI_RXFIFOFULLMASK	(1 << 17)
#define MCI_TXFIFOEMPTYMASK	(1 << 18)
#define MCI_RXFIFOEMPTYMASK	(1 << 19)
#define MCI_TXDATAAVLBLMASK	(1 << 20)
#define MCI_RXDATAAVLBLMASK	(1 << 21)
/* Extended status bits for the ST Micro variants */
#define MCI_ST_SDIOITMASK	(1 << 22)
#define MCI_ST_CEATAENDMASK	(1 << 23)
#define MCI_ST_BUSYENDMASK	(1 << 24)
/* Extended status bits for the STM32 variants */
#define MCI_STM32_BUSYD0ENDMASK	BIT(21)

#define MMCIMASK1		0x040
#define MMCIFIFOCNT		0x048
#define MMCIFIFO		0x080 /* to 0x0bc */

/* STM32 sdmmc registers for IDMA (Internal DMA) */
#define MMCI_STM32_IDMACTRLR	0x050
#define MMCI_STM32_IDMAEN	BIT(0)
#define MMCI_STM32_IDMALLIEN	BIT(1)

#define MMCI_STM32_IDMABSIZER		0x054
#define MMCI_STM32_IDMABNDT_SHIFT	5
#define MMCI_STM32_IDMABNDT_MASK	GENMASK(12, 5)

#define MMCI_STM32_IDMABASE0R	0x058

#define MMCI_STM32_IDMALAR	0x64
#define MMCI_STM32_IDMALA_MASK	GENMASK(13, 0)
#define MMCI_STM32_ABR		BIT(29)
#define MMCI_STM32_ULS		BIT(30)
#define MMCI_STM32_ULA		BIT(31)

#define MMCI_STM32_IDMABAR	0x68

#define MCI_IRQENABLE	\
	(MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
	MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK |	\
	MCI_CMDRESPENDMASK | MCI_CMDSENTMASK)

/* These interrupts are directed to IRQ1 when two IRQ lines are available */
#define MCI_IRQ_PIO_MASK \
	(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
	 MCI_TXFIFOHALFEMPTYMASK)

#define MCI_IRQ_PIO_STM32_MASK \
	(MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)

#define NR_SG		128

#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"

struct clk;
struct dma_chan;
struct mmci_host;

/**
 * struct variant_data - MMCI variant-specific quirks
 * @clkreg: default value for MCICLOCK register
 * @clkreg_enable: enable value for MMCICLOCK register
 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
 * @cmdreg_cpsm_enable: enable value for CPSM
 * @cmdreg_lrsp_crc: enable value for long response with crc
 * @cmdreg_srsp_crc: enable value for short response with crc
 * @cmdreg_srsp: enable value for short response without crc
 * @datalength_bits: number of bits in the MMCIDATALENGTH register
 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
 *	      is asserted (likewise for RX)
 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
 *		  is asserted (likewise for RX)
 * @data_cmd_enable: enable value for data commands.
 * @st_sdio: enable ST specific SDIO logic
 * @st_clkdiv: true if using a ST-specific clock divider algorithm
 * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm
 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
 *		     register
 * @datactrl_mask_sdio: SDIO enable mask in datactrl register
 * @datactrl_blksz: block size in power of two
 * @datactrl_dpsm_enable: enable value for DPSM
 * @datactrl_first: true if data must be setup before send command
 * @datacnt_useless: true if you could not use datacnt register to read
 *		     remaining data
 * @pwrreg_powerup: power up value for MMCIPOWER register
 * @f_max: maximum clk frequency supported by the controller.
 * @signal_direction: input/out direction of bus signals can be indicated
 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
 * @busy_detect: true if the variant supports busy detection on DAT0.
 * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
 * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
 *		      indicating that the card is busy
 * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
 *		      getting busy end detection interrupts
 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
 * @explicit_mclk_control: enable explicit mclk control in driver.
 * @qcom_fifo: enables qcom specific fifo pio read logic.
 * @qcom_dml: enables qcom specific dma glue for dma transfers.
 * @reversed_irq_handling: handle data irq before cmd irq.
 * @mmcimask1: true if variant have a MMCIMASK1 register.
 * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask
 *		  register
 * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
 *	       register.
 * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
 * @dma_lli: true if variant has dma link list feature.
 * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
 */
struct variant_data {
	unsigned int		clkreg;
	unsigned int		clkreg_enable;
	unsigned int		clkreg_8bit_bus_enable;
	unsigned int		clkreg_neg_edge_enable;
	unsigned int		cmdreg_cpsm_enable;
	unsigned int		cmdreg_lrsp_crc;
	unsigned int		cmdreg_srsp_crc;
	unsigned int		cmdreg_srsp;
	unsigned int		datalength_bits;
	unsigned int		fifosize;
	unsigned int		fifohalfsize;
	unsigned int		data_cmd_enable;
	unsigned int		datactrl_mask_ddrmode;
	unsigned int		datactrl_mask_sdio;
	unsigned int		datactrl_blocksz;
	unsigned int		datactrl_dpsm_enable;
	u8			datactrl_first:1;
	u8			datacnt_useless:1;
	u8			st_sdio:1;
	u8			st_clkdiv:1;
	u8			stm32_clkdiv:1;
	u8			blksz_datactrl16:1;
	u8			blksz_datactrl4:1;
	u32			pwrreg_powerup;
	u32			f_max;
	u8			signal_direction:1;
	u8			pwrreg_clkgate:1;
	u8			busy_detect:1;
	u32			busy_dpsm_flag;
	u32			busy_detect_flag;
	u32			busy_detect_mask;
	u8			pwrreg_nopower:1;
	u8			explicit_mclk_control:1;
	u8			qcom_fifo:1;
	u8			qcom_dml:1;
	u8			reversed_irq_handling:1;
	u8			mmcimask1:1;
	unsigned int		irq_pio_mask;
	u32			start_err;
	u32			opendrain;
	u8			dma_lli:1;
	u32			stm32_idmabsize_mask;
	void (*init)(struct mmci_host *host);
};

/* mmci variant callbacks */
struct mmci_host_ops {
	int (*validate_data)(struct mmci_host *host, struct mmc_data *data);
	int (*prep_data)(struct mmci_host *host, struct mmc_data *data,
			 bool next);
	void (*unprep_data)(struct mmci_host *host, struct mmc_data *data,
			    int err);
	void (*get_next_data)(struct mmci_host *host, struct mmc_data *data);
	int (*dma_setup)(struct mmci_host *host);
	void (*dma_release)(struct mmci_host *host);
	int (*dma_start)(struct mmci_host *host, unsigned int *datactrl);
	void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data);
	void (*dma_error)(struct mmci_host *host);
	void (*set_clkreg)(struct mmci_host *host, unsigned int desired);
	void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr);
};

struct mmci_host {
	phys_addr_t		phybase;
	void __iomem		*base;
	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;
	struct mmc_host		*mmc;
	struct clk		*clk;
	u8			singleirq:1;

	struct reset_control	*rst;

	spinlock_t		lock;

	unsigned int		mclk;
	/* cached value of requested clk in set_ios */
	unsigned int		clock_cache;
	unsigned int		cclk;
	u32			pwr_reg;
	u32			pwr_reg_add;
	u32			clk_reg;
	u32			clk_reg_add;
	u32			datactrl_reg;
	u32			busy_status;
	u32			mask1_reg;
	u8			vqmmc_enabled:1;
	struct mmci_platform_data *plat;
	struct mmci_host_ops	*ops;
	struct variant_data	*variant;
	struct pinctrl		*pinctrl;
	struct pinctrl_state	*pins_default;
	struct pinctrl_state	*pins_opendrain;

	u8			hw_designer;
	u8			hw_revision:4;

	struct timer_list	timer;
	unsigned int		oldstat;

	/* pio stuff */
	struct sg_mapping_iter	sg_miter;
	unsigned int		size;
	int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);

	u8			use_dma:1;
	u8			dma_in_progress:1;
	void			*dma_priv;

	s32			next_cookie;
};

#define dma_inprogress(host)	((host)->dma_in_progress)

void mmci_write_clkreg(struct mmci_host *host, u32 clk);
void mmci_write_pwrreg(struct mmci_host *host, u32 pwr);

int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
			bool next);
void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data,
			   int err);
void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data);
int mmci_dmae_setup(struct mmci_host *host);
void mmci_dmae_release(struct mmci_host *host);
int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl);
void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data);
void mmci_dmae_error(struct mmci_host *host);
Commit	Line	Data
1da177e4	1	/*
70f10482	2	* linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
1da177e4 LT	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#define MMCIPOWER 0x000
	11	#define MCI_PWR_OFF 0x00
	12	#define MCI_PWR_UP 0x02
	13	#define MCI_PWR_ON 0x03
	14	#define MCI_OD (1 << 6)
	15	#define MCI_ROD (1 << 7)
4593df29 UH	16	/*
	17	* The ST Micro version does not have ROD and reuse the voltage registers for
	18	* direction settings.
	19	*/
	20	#define MCI_ST_DATA2DIREN (1 << 2)
	21	#define MCI_ST_CMDDIREN (1 << 3)
	22	#define MCI_ST_DATA0DIREN (1 << 4)
	23	#define MCI_ST_DATA31DIREN (1 << 5)
	24	#define MCI_ST_FBCLKEN (1 << 7)
	25	#define MCI_ST_DATA74DIREN (1 << 8)
f3f64334 LB	26	/*
	27	* The STM32 sdmmc does not have PWR_UP/OD/ROD
	28	* and uses the power register for
	29	*/
	30	#define MCI_STM32_PWR_CYC 0x02
	31	#define MCI_STM32_VSWITCH BIT(2)
	32	#define MCI_STM32_VSWITCHEN BIT(3)
	33	#define MCI_STM32_DIRPOL BIT(4)
1da177e4 LT	34
	35	#define MMCICLOCK 0x004
	36	#define MCI_CLK_ENABLE (1 << 8)
	37	#define MCI_CLK_PWRSAVE (1 << 9)
	38	#define MCI_CLK_BYPASS (1 << 10)
771dc157	39	#define MCI_4BIT_BUS (1 << 11)
49ac215e LW	40	/*
	41	* 8bit wide buses, hardware flow contronl, negative edges and clock inversion
	42	* supported in ST Micro U300 and Ux500 versions
	43	*/
771dc157	44	#define MCI_ST_8BIT_BUS (1 << 12)
49ac215e LW	45	#define MCI_ST_U300_HWFCEN (1 << 13)
	46	#define MCI_ST_UX500_NEG_EDGE (1 << 13)
	47	#define MCI_ST_UX500_HWFCEN (1 << 14)
	48	#define MCI_ST_UX500_CLK_INV (1 << 15)
3a37298a PM	49	/* Modified PL180 on Versatile Express platform */
3a37298a PM	50	#define MCI_ARM_HWFCEN (1 << 12)
1da177e4	51
9681a4e8 SK	52	/* Modified on Qualcomm Integrations */
	53	#define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) \| BIT(11))
	54	#define MCI_QCOM_CLK_FLOWENA BIT(12)
	55	#define MCI_QCOM_CLK_INVERTOUT BIT(13)
	56
	57	/* select in latch data and command in */
	58	#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
	59	#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) \| BIT(15))
	60
f3f64334 LB	61	/* Modified on STM32 sdmmc */
	62	#define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0)
	63	#define MCI_STM32_CLK_WIDEBUS_4 BIT(14)
	64	#define MCI_STM32_CLK_WIDEBUS_8 BIT(15)
	65	#define MCI_STM32_CLK_NEGEDGE BIT(16)
	66	#define MCI_STM32_CLK_HWFCEN BIT(17)
	67	#define MCI_STM32_CLK_DDR BIT(18)
	68	#define MCI_STM32_CLK_BUSSPEED BIT(19)
	69	#define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20)
	70	#define MCI_STM32_CLK_SELCK (0 << 20)
	71	#define MCI_STM32_CLK_SELCKIN (1 << 20)
	72	#define MCI_STM32_CLK_SELFBCK (2 << 20)
	73
1da177e4	74	#define MMCIARGUMENT 0x008
1da177e4	75
5db3eee7 LW	76	/* The command register controls the Command Path State Machine (CPSM) */
	77	#define MMCICOMMAND 0x00c
	78	#define MCI_CPSM_RESPONSE BIT(6)
	79	#define MCI_CPSM_LONGRSP BIT(7)
	80	#define MCI_CPSM_INTERRUPT BIT(8)
	81	#define MCI_CPSM_PENDING BIT(9)
	82	#define MCI_CPSM_ENABLE BIT(10)
	83	/* Command register flag extenstions in the ST Micro versions */
	84	#define MCI_CPSM_ST_SDIO_SUSP BIT(11)
	85	#define MCI_CPSM_ST_ENCMD_COMPL BIT(12)
	86	#define MCI_CPSM_ST_NIEN BIT(13)
	87	#define MCI_CPSM_ST_CE_ATACMD BIT(14)
	88	/* Command register flag extensions in the Qualcomm versions */
	89	#define MCI_CPSM_QCOM_PROGENA BIT(11)
	90	#define MCI_CPSM_QCOM_DATCMD BIT(12)
	91	#define MCI_CPSM_QCOM_MCIABORT BIT(13)
	92	#define MCI_CPSM_QCOM_CCSENABLE BIT(14)
	93	#define MCI_CPSM_QCOM_CCSDISABLE BIT(15)
	94	#define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16)
	95	#define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21)
f3f64334 LB	96	/* Command register in STM32 sdmmc versions */
	97	#define MCI_CPSM_STM32_CMDTRANS BIT(6)
	98	#define MCI_CPSM_STM32_CMDSTOP BIT(7)
	99	#define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8)
	100	#define MCI_CPSM_STM32_NORSP (0 << 8)
	101	#define MCI_CPSM_STM32_SRSP_CRC (1 << 8)
	102	#define MCI_CPSM_STM32_SRSP (2 << 8)
	103	#define MCI_CPSM_STM32_LRSP_CRC (3 << 8)
	104	#define MCI_CPSM_STM32_ENABLE BIT(12)
9681a4e8	105
1da177e4 LT	106	#define MMCIRESPCMD 0x010
	107	#define MMCIRESPONSE0 0x014
	108	#define MMCIRESPONSE1 0x018
	109	#define MMCIRESPONSE2 0x01c
	110	#define MMCIRESPONSE3 0x020
	111	#define MMCIDATATIMER 0x024
	112	#define MMCIDATALENGTH 0x028
5db3eee7 LW	113
5db3eee7 LW	114	/* The data control register controls the Data Path State Machine (DPSM) */
1da177e4	115	#define MMCIDATACTRL 0x02c
5db3eee7 LW	116	#define MCI_DPSM_ENABLE BIT(0)
	117	#define MCI_DPSM_DIRECTION BIT(1)
	118	#define MCI_DPSM_MODE BIT(2)
	119	#define MCI_DPSM_DMAENABLE BIT(3)
	120	#define MCI_DPSM_BLOCKSIZE BIT(4)
725343fa	121	/* Control register extensions in the ST Micro U300 and Ux500 versions */
5db3eee7 LW	122	#define MCI_DPSM_ST_RWSTART BIT(8)
	123	#define MCI_DPSM_ST_RWSTOP BIT(9)
	124	#define MCI_DPSM_ST_RWMOD BIT(10)
	125	#define MCI_DPSM_ST_SDIOEN BIT(11)
725343fa	126	/* Control register extensions in the ST Micro Ux500 versions */
5db3eee7 LW	127	#define MCI_DPSM_ST_DMAREQCTL BIT(12)
	128	#define MCI_DPSM_ST_DBOOTMODEEN BIT(13)
	129	#define MCI_DPSM_ST_BUSYMODE BIT(14)
	130	#define MCI_DPSM_ST_DDRMODE BIT(15)
	131	/* Control register extensions in the Qualcomm versions */
	132	#define MCI_DPSM_QCOM_DATA_PEND BIT(17)
	133	#define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
1da177e4 LT	134
	135	#define MMCIDATACNT 0x030
	136	#define MMCISTATUS 0x034
	137	#define MCI_CMDCRCFAIL (1 << 0)
	138	#define MCI_DATACRCFAIL (1 << 1)
	139	#define MCI_CMDTIMEOUT (1 << 2)
	140	#define MCI_DATATIMEOUT (1 << 3)
	141	#define MCI_TXUNDERRUN (1 << 4)
	142	#define MCI_RXOVERRUN (1 << 5)
	143	#define MCI_CMDRESPEND (1 << 6)
	144	#define MCI_CMDSENT (1 << 7)
	145	#define MCI_DATAEND (1 << 8)
757df746	146	#define MCI_STARTBITERR (1 << 9)
1da177e4 LT	147	#define MCI_DATABLOCKEND (1 << 10)
	148	#define MCI_CMDACTIVE (1 << 11)
	149	#define MCI_TXACTIVE (1 << 12)
	150	#define MCI_RXACTIVE (1 << 13)
	151	#define MCI_TXFIFOHALFEMPTY (1 << 14)
	152	#define MCI_RXFIFOHALFFULL (1 << 15)
	153	#define MCI_TXFIFOFULL (1 << 16)
	154	#define MCI_RXFIFOFULL (1 << 17)
	155	#define MCI_TXFIFOEMPTY (1 << 18)
	156	#define MCI_RXFIFOEMPTY (1 << 19)
	157	#define MCI_TXDATAAVLBL (1 << 20)
	158	#define MCI_RXDATAAVLBL (1 << 21)
49ac215e LW	159	/* Extended status bits for the ST Micro variants */
	160	#define MCI_ST_SDIOIT (1 << 22)
	161	#define MCI_ST_CEATAEND (1 << 23)
01259620	162	#define MCI_ST_CARDBUSY (1 << 24)
f3f64334 LB	163	/* Extended status bits for the STM32 variants */
f3f64334 LB	164	#define MCI_STM32_BUSYD0 BIT(20)
1da177e4 LT	165
	166	#define MMCICLEAR 0x038
	167	#define MCI_CMDCRCFAILCLR (1 << 0)
	168	#define MCI_DATACRCFAILCLR (1 << 1)
	169	#define MCI_CMDTIMEOUTCLR (1 << 2)
	170	#define MCI_DATATIMEOUTCLR (1 << 3)
	171	#define MCI_TXUNDERRUNCLR (1 << 4)
	172	#define MCI_RXOVERRUNCLR (1 << 5)
	173	#define MCI_CMDRESPENDCLR (1 << 6)
	174	#define MCI_CMDSENTCLR (1 << 7)
	175	#define MCI_DATAENDCLR (1 << 8)
757df746	176	#define MCI_STARTBITERRCLR (1 << 9)
1da177e4	177	#define MCI_DATABLOCKENDCLR (1 << 10)
49ac215e LW	178	/* Extended status bits for the ST Micro variants */
	179	#define MCI_ST_SDIOITC (1 << 22)
	180	#define MCI_ST_CEATAENDC (1 << 23)
01259620	181	#define MCI_ST_BUSYENDC (1 << 24)
1da177e4 LT	182
	183	#define MMCIMASK0 0x03c
	184	#define MCI_CMDCRCFAILMASK (1 << 0)
	185	#define MCI_DATACRCFAILMASK (1 << 1)
	186	#define MCI_CMDTIMEOUTMASK (1 << 2)
	187	#define MCI_DATATIMEOUTMASK (1 << 3)
	188	#define MCI_TXUNDERRUNMASK (1 << 4)
	189	#define MCI_RXOVERRUNMASK (1 << 5)
	190	#define MCI_CMDRESPENDMASK (1 << 6)
	191	#define MCI_CMDSENTMASK (1 << 7)
	192	#define MCI_DATAENDMASK (1 << 8)
757df746	193	#define MCI_STARTBITERRMASK (1 << 9)
1da177e4 LT	194	#define MCI_DATABLOCKENDMASK (1 << 10)
	195	#define MCI_CMDACTIVEMASK (1 << 11)
	196	#define MCI_TXACTIVEMASK (1 << 12)
	197	#define MCI_RXACTIVEMASK (1 << 13)
	198	#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
	199	#define MCI_RXFIFOHALFFULLMASK (1 << 15)
	200	#define MCI_TXFIFOFULLMASK (1 << 16)
	201	#define MCI_RXFIFOFULLMASK (1 << 17)
	202	#define MCI_TXFIFOEMPTYMASK (1 << 18)
	203	#define MCI_RXFIFOEMPTYMASK (1 << 19)
	204	#define MCI_TXDATAAVLBLMASK (1 << 20)
	205	#define MCI_RXDATAAVLBLMASK (1 << 21)
49ac215e LW	206	/* Extended status bits for the ST Micro variants */
	207	#define MCI_ST_SDIOITMASK (1 << 22)
	208	#define MCI_ST_CEATAENDMASK (1 << 23)
49adc0ca	209	#define MCI_ST_BUSYENDMASK (1 << 24)
f3f64334 LB	210	/* Extended status bits for the STM32 variants */
f3f64334 LB	211	#define MCI_STM32_BUSYD0ENDMASK BIT(21)
1da177e4 LT	212
	213	#define MMCIMASK1 0x040
	214	#define MMCIFIFOCNT 0x048
	215	#define MMCIFIFO 0x080 /* to 0x0bc */
	216
f3f64334 LB	217	/* STM32 sdmmc registers for IDMA (Internal DMA) */
	218	#define MMCI_STM32_IDMACTRLR 0x050
	219	#define MMCI_STM32_IDMAEN BIT(0)
	220	#define MMCI_STM32_IDMALLIEN BIT(1)
	221
	222	#define MMCI_STM32_IDMABSIZER 0x054
	223	#define MMCI_STM32_IDMABNDT_SHIFT 5
	224	#define MMCI_STM32_IDMABNDT_MASK GENMASK(12, 5)
	225
	226	#define MMCI_STM32_IDMABASE0R 0x058
	227
	228	#define MMCI_STM32_IDMALAR 0x64
	229	#define MMCI_STM32_IDMALA_MASK GENMASK(13, 0)
	230	#define MMCI_STM32_ABR BIT(29)
	231	#define MMCI_STM32_ULS BIT(30)
	232	#define MMCI_STM32_ULA BIT(31)
	233
	234	#define MMCI_STM32_IDMABAR 0x68
	235
1da177e4	236	#define MCI_IRQENABLE \
daf9713c LB	237	(MCI_CMDCRCFAILMASK \| MCI_DATACRCFAILMASK \| MCI_CMDTIMEOUTMASK \| \
	238	MCI_DATATIMEOUTMASK \| MCI_TXUNDERRUNMASK \| MCI_RXOVERRUNMASK \| \
	239	MCI_CMDRESPENDMASK \| MCI_CMDSENTMASK)
1da177e4	240
2686b4b4	241	/* These interrupts are directed to IRQ1 when two IRQ lines are available */
59db5e2d	242	#define MCI_IRQ_PIO_MASK \
2686b4b4 LW	243	(MCI_RXFIFOHALFFULLMASK \| MCI_RXDATAAVLBLMASK \| \
	244	MCI_TXFIFOHALFEMPTYMASK)
	245
f3f64334 LB	246	#define MCI_IRQ_PIO_STM32_MASK \
	247	(MCI_RXFIFOHALFFULLMASK \| MCI_TXFIFOHALFEMPTYMASK)
	248
859dd55d	249	#define NR_SG 128
1da177e4	250
f9bb304c PC	251	#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
f9bb304c PC	252
1da177e4	253	struct clk;
c8ebae37	254	struct dma_chan;
ed9067fd UH	255	struct mmci_host;
	256
	257	/**
	258	* struct variant_data - MMCI variant-specific quirks
	259	* @clkreg: default value for MCICLOCK register
	260	* @clkreg_enable: enable value for MMCICLOCK register
	261	* @clkreg_8bit_bus_enable: enable value for 8 bit bus
	262	* @clkreg_neg_edge_enable: enable value for inverted data/cmd output
0f244804 LB	263	* @cmdreg_cpsm_enable: enable value for CPSM
	264	* @cmdreg_lrsp_crc: enable value for long response with crc
	265	* @cmdreg_srsp_crc: enable value for short response with crc
	266	* @cmdreg_srsp: enable value for short response without crc
ed9067fd UH	267	* @datalength_bits: number of bits in the MMCIDATALENGTH register
	268	* @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
	269	* is asserted (likewise for RX)
	270	* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
	271	* is asserted (likewise for RX)
	272	* @data_cmd_enable: enable value for data commands.
	273	* @st_sdio: enable ST specific SDIO logic
	274	* @st_clkdiv: true if using a ST-specific clock divider algorithm
00e930d8	275	* @stm32_clkdiv: true if using a STM32-specific clock divider algorithm
ed9067fd UH	276	* @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
	277	* @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
	278	* @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
	279	* register
	280	* @datactrl_mask_sdio: SDIO enable mask in datactrl register
c931d495	281	* @datactrl_blksz: block size in power of two
9b279941	282	* @datactrl_dpsm_enable: enable value for DPSM
d2141547	283	* @datactrl_first: true if data must be setup before send command
b79220b3 LB	284	* @datacnt_useless: true if you could not use datacnt register to read
b79220b3 LB	285	* remaining data
ed9067fd UH	286	* @pwrreg_powerup: power up value for MMCIPOWER register
	287	* @f_max: maximum clk frequency supported by the controller.
	288	* @signal_direction: input/out direction of bus signals can be indicated
	289	* @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
	290	* @busy_detect: true if the variant supports busy detection on DAT0.
	291	* @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
	292	* @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
	293	* indicating that the card is busy
	294	* @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
	295	* getting busy end detection interrupts
	296	* @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
	297	* @explicit_mclk_control: enable explicit mclk control in driver.
	298	* @qcom_fifo: enables qcom specific fifo pio read logic.
	299	* @qcom_dml: enables qcom specific dma glue for dma transfers.
	300	* @reversed_irq_handling: handle data irq before cmd irq.
	301	* @mmcimask1: true if variant have a MMCIMASK1 register.
59db5e2d LB	302	* @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask
59db5e2d LB	303	* register
ed9067fd UH	304	* @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
	305	* register.
	306	* @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
46b723dd LB	307	* @dma_lli: true if variant has dma link list feature.
46b723dd LB	308	* @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
ed9067fd UH	309	*/
	310	struct variant_data {
	311	unsigned int clkreg;
	312	unsigned int clkreg_enable;
	313	unsigned int clkreg_8bit_bus_enable;
	314	unsigned int clkreg_neg_edge_enable;
0f244804 LB	315	unsigned int cmdreg_cpsm_enable;
	316	unsigned int cmdreg_lrsp_crc;
	317	unsigned int cmdreg_srsp_crc;
	318	unsigned int cmdreg_srsp;
ed9067fd UH	319	unsigned int datalength_bits;
	320	unsigned int fifosize;
	321	unsigned int fifohalfsize;
	322	unsigned int data_cmd_enable;
	323	unsigned int datactrl_mask_ddrmode;
	324	unsigned int datactrl_mask_sdio;
c931d495	325	unsigned int datactrl_blocksz;
9b279941	326	unsigned int datactrl_dpsm_enable;
d2141547	327	u8 datactrl_first:1;
b79220b3	328	u8 datacnt_useless:1;
19a25d57 LB	329	u8 st_sdio:1;
19a25d57 LB	330	u8 st_clkdiv:1;
00e930d8	331	u8 stm32_clkdiv:1;
19a25d57 LB	332	u8 blksz_datactrl16:1;
19a25d57 LB	333	u8 blksz_datactrl4:1;
ed9067fd UH	334	u32 pwrreg_powerup;
ed9067fd UH	335	u32 f_max;
19a25d57 LB	336	u8 signal_direction:1;
	337	u8 pwrreg_clkgate:1;
	338	u8 busy_detect:1;
ed9067fd UH	339	u32 busy_dpsm_flag;
	340	u32 busy_detect_flag;
	341	u32 busy_detect_mask;
19a25d57 LB	342	u8 pwrreg_nopower:1;
	343	u8 explicit_mclk_control:1;
	344	u8 qcom_fifo:1;
	345	u8 qcom_dml:1;
	346	u8 reversed_irq_handling:1;
	347	u8 mmcimask1:1;
59db5e2d	348	unsigned int irq_pio_mask;
ed9067fd UH	349	u32 start_err;
ed9067fd UH	350	u32 opendrain;
46b723dd LB	351	u8 dma_lli:1;
46b723dd LB	352	u32 stm32_idmabsize_mask;
ed9067fd UH	353	void (init)(struct mmci_host host);
	354	};
	355
	356	/* mmci variant callbacks */
	357	struct mmci_host_ops {
e0da1721	358	int (validate_data)(struct mmci_host host, struct mmc_data *data);
47983510 LB	359	int (prep_data)(struct mmci_host host, struct mmc_data *data,
	360	bool next);
	361	void (unprep_data)(struct mmci_host host, struct mmc_data *data,
	362	int err);
02769968	363	void (get_next_data)(struct mmci_host host, struct mmc_data *data);
c3647fdc LB	364	int (dma_setup)(struct mmci_host host);
c3647fdc LB	365	void (dma_release)(struct mmci_host host);
135ea30e	366	int (dma_start)(struct mmci_host host, unsigned int *datactrl);
5a9f10c3	367	void (dma_finalize)(struct mmci_host host, struct mmc_data *data);
cfccc6ac	368	void (dma_error)(struct mmci_host host);
cd3ee8c5 LB	369	void (set_clkreg)(struct mmci_host host, unsigned int desired);
cd3ee8c5 LB	370	void (set_pwrreg)(struct mmci_host host, unsigned int pwr);
ed9067fd	371	};
1da177e4 LT	372
1da177e4 LT	373	struct mmci_host {
c8ebae37	374	phys_addr_t phybase;
1da177e4 LT	375	void __iomem *base;
	376	struct mmc_request *mrq;
	377	struct mmc_command *cmd;
	378	struct mmc_data *data;
	379	struct mmc_host *mmc;
	380	struct clk *clk;
19a25d57	381	u8 singleirq:1;
1da177e4	382
15878e58 LB	383	struct reset_control *rst;
15878e58 LB	384
1da177e4 LT	385	spinlock_t lock;
	386
	387	unsigned int mclk;
3f4e6f7b SK	388	/* cached value of requested clk in set_ios */
3f4e6f7b SK	389	unsigned int clock_cache;
1da177e4	390	unsigned int cclk;
7437cfa5	391	u32 pwr_reg;
4593df29	392	u32 pwr_reg_add;
7437cfa5	393	u32 clk_reg;
46b723dd	394	u32 clk_reg_add;
9cc639a2	395	u32 datactrl_reg;
8d94b54d	396	u32 busy_status;
6ea9cdf3	397	u32 mask1_reg;
19a25d57	398	u8 vqmmc_enabled:1;
6ef297f8	399	struct mmci_platform_data *plat;
ed9067fd	400	struct mmci_host_ops *ops;
4956e109	401	struct variant_data *variant;
f9bb304c PC	402	struct pinctrl *pinctrl;
	403	struct pinctrl_state *pins_default;
	404	struct pinctrl_state *pins_opendrain;
1da177e4	405
cc30d60e LW	406	u8 hw_designer;
	407	u8 hw_revision:4;
	408
1da177e4 LT	409	struct timer_list timer;
	410	unsigned int oldstat;
	411
1da177e4	412	/* pio stuff */
4ce1d6cb	413	struct sg_mapping_iter sg_miter;
1da177e4	414	unsigned int size;
9c34b73d	415	int (get_rx_fifocnt)(struct mmci_host h, u32 status, int remain);
c8ebae37	416
c3647fdc	417	u8 use_dma:1;
19a25d57	418	u8 dma_in_progress:1;
a813f2a2	419	void *dma_priv;
c8ebae37	420
a813f2a2	421	s32 next_cookie;
1da177e4 LT	422	};
1da177e4 LT	423
a813f2a2 LB	424	#define dma_inprogress(host) ((host)->dma_in_progress)
a813f2a2 LB	425
cd3ee8c5 LB	426	void mmci_write_clkreg(struct mmci_host *host, u32 clk);
	427	void mmci_write_pwrreg(struct mmci_host *host, u32 pwr);
	428
47983510 LB	429	int mmci_dmae_prep_data(struct mmci_host host, struct mmc_data data,
	430	bool next);
	431	void mmci_dmae_unprep_data(struct mmci_host host, struct mmc_data data,
	432	int err);
02769968	433	void mmci_dmae_get_next_data(struct mmci_host host, struct mmc_data data);
c3647fdc LB	434	int mmci_dmae_setup(struct mmci_host *host);
c3647fdc LB	435	void mmci_dmae_release(struct mmci_host *host);
135ea30e	436	int mmci_dmae_start(struct mmci_host host, unsigned int datactrl);
5a9f10c3	437	void mmci_dmae_finalize(struct mmci_host host, struct mmc_data data);
cfccc6ac	438	void mmci_dmae_error(struct mmci_host *host);