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Merge branch 'stable-4.12' of git://git.infradead.org/users/pcmoore/audit
[linux-2.6-block.git] / drivers / mmc / host / mmci.c
CommitLineData
1da177e4 1/*
70f10482 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
1da177e4
LT		 3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
c8ebae37 5 * Copyright (C) 2010 ST-Ericsson SA
1da177e4
LT		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
ef289982 16#include <linux/io.h>
1da177e4 17#include <linux/interrupt.h>
613b152c 18#include <linux/kernel.h>
000bc9d5 19#include <linux/slab.h>
1da177e4
LT		 20#include <linux/delay.h>
21#include <linux/err.h>
22#include <linux/highmem.h>
019a5f56 23#include <linux/log2.h>
70be208f 24#include <linux/mmc/pm.h>
1da177e4 25#include <linux/mmc/host.h>
34177802 26#include <linux/mmc/card.h>
d2762090 27#include <linux/mmc/slot-gpio.h>
a62c80e5 28#include <linux/amba/bus.h>
f8ce2547 29#include <linux/clk.h>
bd6dee6f 30#include <linux/scatterlist.h>
89001446 31#include <linux/gpio.h>
9a597016 32#include <linux/of_gpio.h>
34e84f39 33#include <linux/regulator/consumer.h>
c8ebae37
RK		 34#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h>
36#include <linux/amba/mmci.h>
1c3be369 37#include <linux/pm_runtime.h>
258aea76 38#include <linux/types.h>
a9a83785 39#include <linux/pinctrl/consumer.h>
1da177e4 40
7b09cdac 41#include <asm/div64.h>
1da177e4 42#include <asm/io.h>
1da177e4
LT		 43
44#include "mmci.h"
9cb15142 45#include "mmci_qcom_dml.h"
1da177e4
LT		 46
47#define DRIVER_NAME "mmci-pl18x"
48
1da177e4
LT		 49static unsigned int fmax = 515633;
50
4956e109
RV		 51/**
52 * struct variant_data - MMCI variant-specific quirks
53 * @clkreg: default value for MCICLOCK register
4380c14f 54 * @clkreg_enable: enable value for MMCICLOCK register
e1412d85 55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
e8740644 56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
08458ef6 57 * @datalength_bits: number of bits in the MMCIDATALENGTH register
8301bb68
RV		 58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
59 * is asserted (likewise for RX)
60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
61 * is asserted (likewise for RX)
ae7b0061 62 * @data_cmd_enable: enable value for data commands.
c7354133 63 * @st_sdio: enable ST specific SDIO logic
b70a67f9 64 * @st_clkdiv: true if using a ST-specific clock divider algorithm
e17dca2b 65 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
1784b157 66 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
ff783233
SK		 67 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
68 * register
5df014df 69 * @datactrl_mask_sdio: SDIO enable mask in datactrl register
7d72a1d4 70 * @pwrreg_powerup: power up value for MMCIPOWER register
dc6500bf 71 * @f_max: maximum clk frequency supported by the controller.
4d1a3a0d 72 * @signal_direction: input/out direction of bus signals can be indicated
f4670dae 73 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
49adc0ca
LW		 74 * @busy_detect: true if the variant supports busy detection on DAT0.
75 * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
76 * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
77 * indicating that the card is busy
78 * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
79 * getting busy end detection interrupts
1ff44433 80 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
3f4e6f7b 81 * @explicit_mclk_control: enable explicit mclk control in driver.
9c34b73d 82 * @qcom_fifo: enables qcom specific fifo pio read logic.
9cb15142 83 * @qcom_dml: enables qcom specific dma glue for dma transfers.
7878289b 84 * @reversed_irq_handling: handle data irq before cmd irq.
4956e109
RV		 85 */
86struct variant_data {
87 unsigned int clkreg;
4380c14f 88 unsigned int clkreg_enable;
e1412d85 89 unsigned int clkreg_8bit_bus_enable;
e8740644 90 unsigned int clkreg_neg_edge_enable;
08458ef6 91 unsigned int datalength_bits;
8301bb68
RV		 92 unsigned int fifosize;
93 unsigned int fifohalfsize;
ae7b0061 94 unsigned int data_cmd_enable;
e17dca2b 95 unsigned int datactrl_mask_ddrmode;
5df014df 96 unsigned int datactrl_mask_sdio;
c7354133 97 bool st_sdio;
b70a67f9 98 bool st_clkdiv;
1784b157 99 bool blksz_datactrl16;
ff783233 100 bool blksz_datactrl4;
7d72a1d4 101 u32 pwrreg_powerup;
dc6500bf 102 u32 f_max;
4d1a3a0d 103 bool signal_direction;
f4670dae 104 bool pwrreg_clkgate;
01259620 105 bool busy_detect;
49adc0ca
LW		 106 u32 busy_dpsm_flag;
107 u32 busy_detect_flag;
108 u32 busy_detect_mask;
1ff44433 109 bool pwrreg_nopower;
3f4e6f7b 110 bool explicit_mclk_control;
9c34b73d 111 bool qcom_fifo;
9cb15142 112 bool qcom_dml;
7878289b 113 bool reversed_irq_handling;
4956e109
RV		 114};
115
116static struct variant_data variant_arm = {
8301bb68
RV		 117 .fifosize = 16 * 4,
118 .fifohalfsize = 8 * 4,
08458ef6 119 .datalength_bits = 16,
7d72a1d4 120 .pwrreg_powerup = MCI_PWR_UP,
dc6500bf 121 .f_max = 100000000,
7878289b 122 .reversed_irq_handling = true,
4956e109
RV		 123};
124
768fbc18
PM		 125static struct variant_data variant_arm_extended_fifo = {
126 .fifosize = 128 * 4,
127 .fifohalfsize = 64 * 4,
128 .datalength_bits = 16,
7d72a1d4 129 .pwrreg_powerup = MCI_PWR_UP,
dc6500bf 130 .f_max = 100000000,
768fbc18
PM		 131};
132
3a37298a
PM		 133static struct variant_data variant_arm_extended_fifo_hwfc = {
134 .fifosize = 128 * 4,
135 .fifohalfsize = 64 * 4,
136 .clkreg_enable = MCI_ARM_HWFCEN,
137 .datalength_bits = 16,
138 .pwrreg_powerup = MCI_PWR_UP,
dc6500bf 139 .f_max = 100000000,
3a37298a
PM		 140};
141
4956e109 142static struct variant_data variant_u300 = {
8301bb68
RV		 143 .fifosize = 16 * 4,
144 .fifohalfsize = 8 * 4,
49ac215e 145 .clkreg_enable = MCI_ST_U300_HWFCEN,
e1412d85 146 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
08458ef6 147 .datalength_bits = 16,
5db3eee7 148 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
c7354133 149 .st_sdio = true,
7d72a1d4 150 .pwrreg_powerup = MCI_PWR_ON,
dc6500bf 151 .f_max = 100000000,
4d1a3a0d 152 .signal_direction = true,
f4670dae 153 .pwrreg_clkgate = true,
1ff44433 154 .pwrreg_nopower = true,
4956e109
RV		 155};
156
34fd4213
LW		 157static struct variant_data variant_nomadik = {
158 .fifosize = 16 * 4,
159 .fifohalfsize = 8 * 4,
160 .clkreg = MCI_CLK_ENABLE,
f5abc767 161 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
34fd4213 162 .datalength_bits = 24,
5db3eee7 163 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
c7354133 164 .st_sdio = true,
34fd4213
LW		 165 .st_clkdiv = true,
166 .pwrreg_powerup = MCI_PWR_ON,
dc6500bf 167 .f_max = 100000000,
34fd4213 168 .signal_direction = true,
f4670dae 169 .pwrreg_clkgate = true,
1ff44433 170 .pwrreg_nopower = true,
34fd4213
LW		 171};
172
4956e109 173static struct variant_data variant_ux500 = {
8301bb68
RV		 174 .fifosize = 30 * 4,
175 .fifohalfsize = 8 * 4,
4956e109 176 .clkreg = MCI_CLK_ENABLE,
49ac215e 177 .clkreg_enable = MCI_ST_UX500_HWFCEN,
e1412d85 178 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
e8740644 179 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
08458ef6 180 .datalength_bits = 24,
5db3eee7 181 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
c7354133 182 .st_sdio = true,
b70a67f9 183 .st_clkdiv = true,
7d72a1d4 184 .pwrreg_powerup = MCI_PWR_ON,
dc6500bf 185 .f_max = 100000000,
4d1a3a0d 186 .signal_direction = true,
f4670dae 187 .pwrreg_clkgate = true,
01259620 188 .busy_detect = true,
49adc0ca
LW		 189 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
190 .busy_detect_flag = MCI_ST_CARDBUSY,
191 .busy_detect_mask = MCI_ST_BUSYENDMASK,
1ff44433 192 .pwrreg_nopower = true,
4956e109 193};
b70a67f9 194
1784b157
PL		 195static struct variant_data variant_ux500v2 = {
196 .fifosize = 30 * 4,
197 .fifohalfsize = 8 * 4,
198 .clkreg = MCI_CLK_ENABLE,
199 .clkreg_enable = MCI_ST_UX500_HWFCEN,
e1412d85 200 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
e8740644 201 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
5db3eee7 202 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
1784b157 203 .datalength_bits = 24,
5db3eee7 204 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
c7354133 205 .st_sdio = true,
1784b157
PL		 206 .st_clkdiv = true,
207 .blksz_datactrl16 = true,
7d72a1d4 208 .pwrreg_powerup = MCI_PWR_ON,
dc6500bf 209 .f_max = 100000000,
4d1a3a0d 210 .signal_direction = true,
f4670dae 211 .pwrreg_clkgate = true,
01259620 212 .busy_detect = true,
49adc0ca
LW		 213 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
214 .busy_detect_flag = MCI_ST_CARDBUSY,
215 .busy_detect_mask = MCI_ST_BUSYENDMASK,
1ff44433 216 .pwrreg_nopower = true,
1784b157
PL		 217};
218
55b604ae
SK		 219static struct variant_data variant_qcom = {
220 .fifosize = 16 * 4,
221 .fifohalfsize = 8 * 4,
222 .clkreg = MCI_CLK_ENABLE,
223 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
224 MCI_QCOM_CLK_SELECT_IN_FBCLK,
225 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
226 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
5db3eee7 227 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
55b604ae
SK		 228 .blksz_datactrl4 = true,
229 .datalength_bits = 24,
230 .pwrreg_powerup = MCI_PWR_UP,
231 .f_max = 208000000,
232 .explicit_mclk_control = true,
233 .qcom_fifo = true,
9cb15142 234 .qcom_dml = true,
55b604ae
SK		 235};
236
49adc0ca 237/* Busy detection for the ST Micro variant */
01259620
UH		 238static int mmci_card_busy(struct mmc_host *mmc)
239{
240 struct mmci_host *host = mmc_priv(mmc);
241 unsigned long flags;
242 int busy = 0;
243
01259620 244 spin_lock_irqsave(&host->lock, flags);
49adc0ca 245 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
01259620
UH		 246 busy = 1;
247 spin_unlock_irqrestore(&host->lock, flags);
248
01259620
UH		 249 return busy;
250}
251
653a761e
UH		 252/*
253 * Validate mmc prerequisites
254 */
255static int mmci_validate_data(struct mmci_host *host,
256 struct mmc_data *data)
257{
258 if (!data)
259 return 0;
260
261 if (!is_power_of_2(data->blksz)) {
262 dev_err(mmc_dev(host->mmc),
263 "unsupported block size (%d bytes)\n", data->blksz);
264 return -EINVAL;
265 }
266
267 return 0;
268}
269
f829c042
UH		 270static void mmci_reg_delay(struct mmci_host *host)
271{
272 /*
273 * According to the spec, at least three feedback clock cycles
274 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
275 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
276 * Worst delay time during card init is at 100 kHz => 30 us.
277 * Worst delay time when up and running is at 25 MHz => 120 ns.
278 */
279 if (host->cclk < 25000000)
280 udelay(30);
281 else
282 ndelay(120);
283}
284
7437cfa5
UH		 285/*
286 * This must be called with host->lock held
287 */
288static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
289{
290 if (host->clk_reg != clk) {
291 host->clk_reg = clk;
292 writel(clk, host->base + MMCICLOCK);
293 }
294}
295
296/*
297 * This must be called with host->lock held
298 */
299static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
300{
301 if (host->pwr_reg != pwr) {
302 host->pwr_reg = pwr;
303 writel(pwr, host->base + MMCIPOWER);
304 }
305}
306
9cc639a2
UH		 307/*
308 * This must be called with host->lock held
309 */
310static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
311{
49adc0ca
LW		 312 /* Keep busy mode in DPSM if enabled */
313 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
01259620 314
9cc639a2
UH		 315 if (host->datactrl_reg != datactrl) {
316 host->datactrl_reg = datactrl;
317 writel(datactrl, host->base + MMCIDATACTRL);
318 }
319}
320
a6a6464a
LW		 321/*
322 * This must be called with host->lock held
323 */
324static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
325{
4956e109
RV		 326 struct variant_data *variant = host->variant;
327 u32 clk = variant->clkreg;
a6a6464a 328
c58a8509
UH		 329 /* Make sure cclk reflects the current calculated clock */
330 host->cclk = 0;
331
a6a6464a 332 if (desired) {
3f4e6f7b
SK		 333 if (variant->explicit_mclk_control) {
334 host->cclk = host->mclk;
335 } else if (desired >= host->mclk) {
991a86e1 336 clk = MCI_CLK_BYPASS;
399bc486
LW		 337 if (variant->st_clkdiv)
338 clk |= MCI_ST_UX500_NEG_EDGE;
a6a6464a 339 host->cclk = host->mclk;
b70a67f9
LW		 340 } else if (variant->st_clkdiv) {
341 /*
342 * DB8500 TRM says f = mclk / (clkdiv + 2)
343 * => clkdiv = (mclk / f) - 2
344 * Round the divider up so we don't exceed the max
345 * frequency
346 */
347 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
348 if (clk >= 256)
349 clk = 255;
350 host->cclk = host->mclk / (clk + 2);
a6a6464a 351 } else {
b70a67f9
LW		 352 /*
353 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
354 * => clkdiv = mclk / (2 * f) - 1
355 */
a6a6464a
LW		 356 clk = host->mclk / (2 * desired) - 1;
357 if (clk >= 256)
358 clk = 255;
359 host->cclk = host->mclk / (2 * (clk + 1));
360 }
4380c14f
RV		 361
362 clk |= variant->clkreg_enable;
a6a6464a
LW		 363 clk |= MCI_CLK_ENABLE;
364 /* This hasn't proven to be worthwhile */
365 /* clk |= MCI_CLK_PWRSAVE; */
366 }
367
c58a8509
UH		 368 /* Set actual clock for debug */
369 host->mmc->actual_clock = host->cclk;
370
9e6c82cd 371 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
771dc157
LW		 372 clk |= MCI_4BIT_BUS;
373 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
e1412d85 374 clk |= variant->clkreg_8bit_bus_enable;
9e6c82cd 375
6dad6c95
SJ		 376 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
377 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
e8740644 378 clk |= variant->clkreg_neg_edge_enable;
6dbb6ee0 379
7437cfa5 380 mmci_write_clkreg(host, clk);
a6a6464a
LW		 381}
382
1da177e4
LT		 383static void
384mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
385{
386 writel(0, host->base + MMCICOMMAND);
387
e47c222b
RK		 388 BUG_ON(host->data);
389
1da177e4
LT		 390 host->mrq = NULL;
391 host->cmd = NULL;
392
1da177e4 393 mmc_request_done(host->mmc, mrq);
1da177e4
LT		 394}
395
2686b4b4
LW		 396static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
397{
398 void __iomem *base = host->base;
399
400 if (host->singleirq) {
401 unsigned int mask0 = readl(base + MMCIMASK0);
402
403 mask0 &= ~MCI_IRQ1MASK;
404 mask0 |= mask;
405
406 writel(mask0, base + MMCIMASK0);
407 }
408
409 writel(mask, base + MMCIMASK1);
410}
411
1da177e4
LT		 412static void mmci_stop_data(struct mmci_host *host)
413{
9cc639a2 414 mmci_write_datactrlreg(host, 0);
2686b4b4 415 mmci_set_mask1(host, 0);
1da177e4
LT		 416 host->data = NULL;
417}
418
4ce1d6cb
RV		 419static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
420{
421 unsigned int flags = SG_MITER_ATOMIC;
422
423 if (data->flags & MMC_DATA_READ)
424 flags |= SG_MITER_TO_SG;
425 else
426 flags |= SG_MITER_FROM_SG;
427
428 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
429}
430
c8ebae37
RK		 431/*
432 * All the DMA operation mode stuff goes inside this ifdef.
433 * This assumes that you have a generic DMA device interface,
434 * no custom DMA interfaces are supported.
435 */
436#ifdef CONFIG_DMA_ENGINE
c3be1efd 437static void mmci_dma_setup(struct mmci_host *host)
c8ebae37 438{
c8ebae37 439 const char *rxname, *txname;
9cb15142 440 struct variant_data *variant = host->variant;
c8ebae37 441
1fd83f0e
LJ		 442 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
443 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
c8ebae37 444
58c7ccbf
PF		 445 /* initialize pre request cookie */
446 host->next_data.cookie = 1;
447
1fd83f0e
LJ		 448 /*
449 * If only an RX channel is specified, the driver will
450 * attempt to use it bidirectionally, however if it is
451 * is specified but cannot be located, DMA will be disabled.
452 */
453 if (host->dma_rx_channel && !host->dma_tx_channel)
454 host->dma_tx_channel = host->dma_rx_channel;
455
c8ebae37
RK		 456 if (host->dma_rx_channel)
457 rxname = dma_chan_name(host->dma_rx_channel);
458 else
459 rxname = "none";
460
461 if (host->dma_tx_channel)
462 txname = dma_chan_name(host->dma_tx_channel);
463 else
464 txname = "none";
465
466 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
467 rxname, txname);
468
469 /*
470 * Limit the maximum segment size in any SG entry according to
471 * the parameters of the DMA engine device.
472 */
473 if (host->dma_tx_channel) {
474 struct device *dev = host->dma_tx_channel->device->dev;
475 unsigned int max_seg_size = dma_get_max_seg_size(dev);
476
477 if (max_seg_size < host->mmc->max_seg_size)
478 host->mmc->max_seg_size = max_seg_size;
479 }
480 if (host->dma_rx_channel) {
481 struct device *dev = host->dma_rx_channel->device->dev;
482 unsigned int max_seg_size = dma_get_max_seg_size(dev);
483
484 if (max_seg_size < host->mmc->max_seg_size)
485 host->mmc->max_seg_size = max_seg_size;
486 }
9cb15142
SK		 487
488 if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel)
489 if (dml_hw_init(host, host->mmc->parent->of_node))
490 variant->qcom_dml = false;
c8ebae37
RK		 491}
492
493/*
6e0ee714 494 * This is used in or so inline it
c8ebae37
RK		 495 * so it can be discarded.
496 */
497static inline void mmci_dma_release(struct mmci_host *host)
498{
c8ebae37
RK		 499 if (host->dma_rx_channel)
500 dma_release_channel(host->dma_rx_channel);
8c3a05b4 501 if (host->dma_tx_channel)
c8ebae37
RK		 502 dma_release_channel(host->dma_tx_channel);
503 host->dma_rx_channel = host->dma_tx_channel = NULL;
504}
505
653a761e
UH		 506static void mmci_dma_data_error(struct mmci_host *host)
507{
508 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
509 dmaengine_terminate_all(host->dma_current);
e13934bd 510 host->dma_in_progress = false;
653a761e
UH		 511 host->dma_current = NULL;
512 host->dma_desc_current = NULL;
513 host->data->host_cookie = 0;
514}
515
c8ebae37
RK		 516static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
517{
653a761e 518 struct dma_chan *chan;
653a761e 519
feeef096 520 if (data->flags & MMC_DATA_READ)
653a761e 521 chan = host->dma_rx_channel;
feeef096 522 else
653a761e 523 chan = host->dma_tx_channel;
653a761e 524
feeef096
HK		 525 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
526 mmc_get_dma_dir(data));
653a761e
UH		 527}
528
529static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
530{
c8ebae37
RK		 531 u32 status;
532 int i;
533
534 /* Wait up to 1ms for the DMA to complete */
535 for (i = 0; ; i++) {
536 status = readl(host->base + MMCISTATUS);
537 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
538 break;
539 udelay(10);
540 }
541
542 /*
543 * Check to see whether we still have some data left in the FIFO -
544 * this catches DMA controllers which are unable to monitor the
545 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
546 * contiguous buffers. On TX, we'll get a FIFO underrun error.
547 */
548 if (status & MCI_RXDATAAVLBLMASK) {
653a761e 549 mmci_dma_data_error(host);
c8ebae37
RK		 550 if (!data->error)
551 data->error = -EIO;
552 }
553
58c7ccbf 554 if (!data->host_cookie)
653a761e 555 mmci_dma_unmap(host, data);
c8ebae37
RK		 556
557 /*
558 * Use of DMA with scatter-gather is impossible.
559 * Give up with DMA and switch back to PIO mode.
560 */
561 if (status & MCI_RXDATAAVLBLMASK) {
562 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
563 mmci_dma_release(host);
564 }
c8ebae37 565
e13934bd 566 host->dma_in_progress = false;
653a761e
UH		 567 host->dma_current = NULL;
568 host->dma_desc_current = NULL;
c8ebae37
RK		 569}
570
653a761e
UH		 571/* prepares DMA channel and DMA descriptor, returns non-zero on failure */
572static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
573 struct dma_chan **dma_chan,
574 struct dma_async_tx_descriptor **dma_desc)
c8ebae37
RK		 575{
576 struct variant_data *variant = host->variant;
577 struct dma_slave_config conf = {
578 .src_addr = host->phybase + MMCIFIFO,
579 .dst_addr = host->phybase + MMCIFIFO,
580 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
581 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
582 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
583 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
258aea76 584 .device_fc = false,
c8ebae37 585 };
c8ebae37
RK		 586 struct dma_chan *chan;
587 struct dma_device *device;
588 struct dma_async_tx_descriptor *desc;
589 int nr_sg;
9cb15142 590 unsigned long flags = DMA_CTRL_ACK;
c8ebae37 591
c8ebae37 592 if (data->flags & MMC_DATA_READ) {
05f5799c 593 conf.direction = DMA_DEV_TO_MEM;
c8ebae37
RK		 594 chan = host->dma_rx_channel;
595 } else {
05f5799c 596 conf.direction = DMA_MEM_TO_DEV;
c8ebae37
RK		 597 chan = host->dma_tx_channel;
598 }
599
600 /* If there's no DMA channel, fall back to PIO */
601 if (!chan)
602 return -EINVAL;
603
604 /* If less than or equal to the fifo size, don't bother with DMA */
58c7ccbf 605 if (data->blksz * data->blocks <= variant->fifosize)
c8ebae37
RK		 606 return -EINVAL;
607
608 device = chan->device;
feeef096
HK		 609 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
610 mmc_get_dma_dir(data));
c8ebae37
RK		 611 if (nr_sg == 0)
612 return -EINVAL;
613
9cb15142
SK		 614 if (host->variant->qcom_dml)
615 flags |= DMA_PREP_INTERRUPT;
616
c8ebae37 617 dmaengine_slave_config(chan, &conf);
16052827 618 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
9cb15142 619 conf.direction, flags);
c8ebae37
RK		 620 if (!desc)
621 goto unmap_exit;
622
653a761e
UH		 623 *dma_chan = chan;
624 *dma_desc = desc;
58c7ccbf
PF		 625
626 return 0;
c8ebae37 627
58c7ccbf 628 unmap_exit:
feeef096
HK		 629 dma_unmap_sg(device->dev, data->sg, data->sg_len,
630 mmc_get_dma_dir(data));
58c7ccbf
PF		 631 return -ENOMEM;
632}
633
653a761e
UH		 634static inline int mmci_dma_prep_data(struct mmci_host *host,
635 struct mmc_data *data)
636{
637 /* Check if next job is already prepared. */
638 if (host->dma_current && host->dma_desc_current)
639 return 0;
640
641 /* No job were prepared thus do it now. */
642 return __mmci_dma_prep_data(host, data, &host->dma_current,
643 &host->dma_desc_current);
644}
645
646static inline int mmci_dma_prep_next(struct mmci_host *host,
647 struct mmc_data *data)
648{
649 struct mmci_host_next *nd = &host->next_data;
650 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
651}
652
58c7ccbf
PF		 653static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
654{
655 int ret;
656 struct mmc_data *data = host->data;
657
653a761e 658 ret = mmci_dma_prep_data(host, host->data);
58c7ccbf
PF		 659 if (ret)
660 return ret;
661
662 /* Okay, go for it. */
c8ebae37
RK		 663 dev_vdbg(mmc_dev(host->mmc),
664 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
665 data->sg_len, data->blksz, data->blocks, data->flags);
e13934bd 666 host->dma_in_progress = true;
58c7ccbf
PF		 667 dmaengine_submit(host->dma_desc_current);
668 dma_async_issue_pending(host->dma_current);
c8ebae37 669
9cb15142
SK		 670 if (host->variant->qcom_dml)
671 dml_start_xfer(host, data);
672
c8ebae37
RK		 673 datactrl |= MCI_DPSM_DMAENABLE;
674
675 /* Trigger the DMA transfer */
9cc639a2 676 mmci_write_datactrlreg(host, datactrl);
c8ebae37
RK		 677
678 /*
679 * Let the MMCI say when the data is ended and it's time
680 * to fire next DMA request. When that happens, MMCI will
681 * call mmci_data_end()
682 */
683 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
684 host->base + MMCIMASK0);
685 return 0;
58c7ccbf 686}
c8ebae37 687
58c7ccbf
PF		 688static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
689{
690 struct mmci_host_next *next = &host->next_data;
691
653a761e
UH		 692 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
693 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
58c7ccbf
PF		 694
695 host->dma_desc_current = next->dma_desc;
696 host->dma_current = next->dma_chan;
58c7ccbf
PF		 697 next->dma_desc = NULL;
698 next->dma_chan = NULL;
c8ebae37 699}
58c7ccbf 700
d3c6aac3 701static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
58c7ccbf
PF		 702{
703 struct mmci_host *host = mmc_priv(mmc);
704 struct mmc_data *data = mrq->data;
705 struct mmci_host_next *nd = &host->next_data;
706
707 if (!data)
708 return;
709
653a761e
UH		 710 BUG_ON(data->host_cookie);
711
712 if (mmci_validate_data(host, data))
58c7ccbf 713 return;
58c7ccbf 714
653a761e
UH		 715 if (!mmci_dma_prep_next(host, data))
716 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
58c7ccbf
PF		 717}
718
719static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
720 int err)
721{
722 struct mmci_host *host = mmc_priv(mmc);
723 struct mmc_data *data = mrq->data;
58c7ccbf 724
653a761e 725 if (!data || !data->host_cookie)
58c7ccbf
PF		 726 return;
727
653a761e 728 mmci_dma_unmap(host, data);
58c7ccbf 729
653a761e
UH		 730 if (err) {
731 struct mmci_host_next *next = &host->next_data;
732 struct dma_chan *chan;
733 if (data->flags & MMC_DATA_READ)
734 chan = host->dma_rx_channel;
735 else
736 chan = host->dma_tx_channel;
737 dmaengine_terminate_all(chan);
58c7ccbf 738
b5c16a60
SK		 739 if (host->dma_desc_current == next->dma_desc)
740 host->dma_desc_current = NULL;
741
e13934bd
LW		 742 if (host->dma_current == next->dma_chan) {
743 host->dma_in_progress = false;
b5c16a60 744 host->dma_current = NULL;
e13934bd 745 }
b5c16a60 746
653a761e
UH		 747 next->dma_desc = NULL;
748 next->dma_chan = NULL;
b5c16a60 749 data->host_cookie = 0;
58c7ccbf
PF		 750 }
751}
752
c8ebae37
RK		 753#else
754/* Blank functions if the DMA engine is not available */
58c7ccbf
PF		 755static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
756{
757}
c8ebae37
RK		 758static inline void mmci_dma_setup(struct mmci_host *host)
759{
760}
761
762static inline void mmci_dma_release(struct mmci_host *host)
763{
764}
765
766static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
767{
768}
769
653a761e
UH		 770static inline void mmci_dma_finalize(struct mmci_host *host,
771 struct mmc_data *data)
772{
773}
774
c8ebae37
RK		 775static inline void mmci_dma_data_error(struct mmci_host *host)
776{
777}
778
779static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
780{
781 return -ENOSYS;
782}
58c7ccbf
PF		 783
784#define mmci_pre_request NULL
785#define mmci_post_request NULL
786
c8ebae37
RK		 787#endif
788
1da177e4
LT		 789static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
790{
8301bb68 791 struct variant_data *variant = host->variant;
1da177e4 792 unsigned int datactrl, timeout, irqmask;
7b09cdac 793 unsigned long long clks;
1da177e4 794 void __iomem *base;
3bc87f24 795 int blksz_bits;
1da177e4 796
64de0289
LW		 797 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
798 data->blksz, data->blocks, data->flags);
1da177e4
LT		 799
800 host->data = data;
528320db 801 host->size = data->blksz * data->blocks;
51d4375d 802 data->bytes_xfered = 0;
1da177e4 803
7b09cdac 804 clks = (unsigned long long)data->timeout_ns * host->cclk;
c4a35769 805 do_div(clks, NSEC_PER_SEC);
7b09cdac
RK		 806
807 timeout = data->timeout_clks + (unsigned int)clks;
1da177e4
LT		 808
809 base = host->base;
810 writel(timeout, base + MMCIDATATIMER);
811 writel(host->size, base + MMCIDATALENGTH);
812
3bc87f24
RK		 813 blksz_bits = ffs(data->blksz) - 1;
814 BUG_ON(1 << blksz_bits != data->blksz);
815
1784b157
PL		 816 if (variant->blksz_datactrl16)
817 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
ff783233
SK		 818 else if (variant->blksz_datactrl4)
819 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
1784b157
PL		 820 else
821 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
c8ebae37
RK		 822
823 if (data->flags & MMC_DATA_READ)
1da177e4 824 datactrl |= MCI_DPSM_DIRECTION;
c8ebae37 825
c7354133
SK		 826 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
827 u32 clk;
7258db7e 828
c7354133
SK		 829 datactrl |= variant->datactrl_mask_sdio;
830
831 /*
832 * The ST Micro variant for SDIO small write transfers
833 * needs to have clock H/W flow control disabled,
834 * otherwise the transfer will not start. The threshold
835 * depends on the rate of MCLK.
836 */
837 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
838 (host->size < 8 ||
839 (host->size <= 8 && host->mclk > 50000000)))
840 clk = host->clk_reg & ~variant->clkreg_enable;
841 else
842 clk = host->clk_reg | variant->clkreg_enable;
843
844 mmci_write_clkreg(host, clk);
845 }
06c1a121 846
6dad6c95
SJ		 847 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
848 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
e17dca2b 849 datactrl |= variant->datactrl_mask_ddrmode;
6dbb6ee0 850
c8ebae37
RK		 851 /*
852 * Attempt to use DMA operation mode, if this
853 * should fail, fall back to PIO mode
854 */
855 if (!mmci_dma_start_data(host, datactrl))
856 return;
857
858 /* IRQ mode, map the SG list for CPU reading/writing */
859 mmci_init_sg(host, data);
860
861 if (data->flags & MMC_DATA_READ) {
1da177e4 862 irqmask = MCI_RXFIFOHALFFULLMASK;
0425a142
RK		 863
864 /*
c4d877c1
RK		 865 * If we have less than the fifo 'half-full' threshold to
866 * transfer, trigger a PIO interrupt as soon as any data
867 * is available.
0425a142 868 */
c4d877c1 869 if (host->size < variant->fifohalfsize)
0425a142 870 irqmask |= MCI_RXDATAAVLBLMASK;
1da177e4
LT		 871 } else {
872 /*
873 * We don't actually need to include "FIFO empty" here
874 * since its implicit in "FIFO half empty".
875 */
876 irqmask = MCI_TXFIFOHALFEMPTYMASK;
877 }
878
9cc639a2 879 mmci_write_datactrlreg(host, datactrl);
1da177e4 880 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
2686b4b4 881 mmci_set_mask1(host, irqmask);
1da177e4
LT		 882}
883
884static void
885mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
886{
887 void __iomem *base = host->base;
888
64de0289 889 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1da177e4
LT		 890 cmd->opcode, cmd->arg, cmd->flags);
891
892 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
893 writel(0, base + MMCICOMMAND);
6adb2a80 894 mmci_reg_delay(host);
1da177e4
LT		 895 }
896
897 c |= cmd->opcode | MCI_CPSM_ENABLE;
e9225176
RK		 898 if (cmd->flags & MMC_RSP_PRESENT) {
899 if (cmd->flags & MMC_RSP_136)
900 c |= MCI_CPSM_LONGRSP;
1da177e4 901 c |= MCI_CPSM_RESPONSE;
1da177e4
LT		 902 }
903 if (/*interrupt*/0)
904 c |= MCI_CPSM_INTERRUPT;
905
ae7b0061
SK		 906 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
907 c |= host->variant->data_cmd_enable;
908
1da177e4
LT		 909 host->cmd = cmd;
910
911 writel(cmd->arg, base + MMCIARGUMENT);
912 writel(c, base + MMCICOMMAND);
913}
914
915static void
916mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
917 unsigned int status)
918{
1cb9da50
UH		 919 /* Make sure we have data to handle */
920 if (!data)
921 return;
922
f20f8f21 923 /* First check for errors */
b63038d6
UH		 924 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
925 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
8cb28155 926 u32 remain, success;
f20f8f21 927
c8ebae37 928 /* Terminate the DMA transfer */
653a761e 929 if (dma_inprogress(host)) {
c8ebae37 930 mmci_dma_data_error(host);
653a761e
UH		 931 mmci_dma_unmap(host, data);
932 }
e9c091b4
RK		 933
934 /*
c8afc9d5
RK		 935 * Calculate how far we are into the transfer. Note that
936 * the data counter gives the number of bytes transferred
937 * on the MMC bus, not on the host side. On reads, this
938 * can be as much as a FIFO-worth of data ahead. This
939 * matters for FIFO overruns only.
e9c091b4 940 */
f5a106d9 941 remain = readl(host->base + MMCIDATACNT);
8cb28155
LW		 942 success = data->blksz * data->blocks - remain;
943
c8afc9d5
RK		 944 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
945 status, success);
8cb28155
LW		 946 if (status & MCI_DATACRCFAIL) {
947 /* Last block was not successful */
c8afc9d5 948 success -= 1;
17b0429d 949 data->error = -EILSEQ;
8cb28155 950 } else if (status & MCI_DATATIMEOUT) {
17b0429d 951 data->error = -ETIMEDOUT;
757df746
LW		 952 } else if (status & MCI_STARTBITERR) {
953 data->error = -ECOMM;
c8afc9d5
RK		 954 } else if (status & MCI_TXUNDERRUN) {
955 data->error = -EIO;
956 } else if (status & MCI_RXOVERRUN) {
957 if (success > host->variant->fifosize)
958 success -= host->variant->fifosize;
959 else
960 success = 0;
17b0429d 961 data->error = -EIO;
4ce1d6cb 962 }
51d4375d 963 data->bytes_xfered = round_down(success, data->blksz);
1da177e4 964 }
f20f8f21 965
8cb28155
LW		 966 if (status & MCI_DATABLOCKEND)
967 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
f20f8f21 968
ccff9b51 969 if (status & MCI_DATAEND || data->error) {
c8ebae37 970 if (dma_inprogress(host))
653a761e 971 mmci_dma_finalize(host, data);
1da177e4
LT		 972 mmci_stop_data(host);
973
8cb28155
LW		 974 if (!data->error)
975 /* The error clause is handled above, success! */
51d4375d 976 data->bytes_xfered = data->blksz * data->blocks;
f20f8f21 977
024629c6 978 if (!data->stop || host->mrq->sbc) {
1da177e4
LT		 979 mmci_request_end(host, data->mrq);
980 } else {
981 mmci_start_command(host, data->stop, 0);
982 }
983 }
984}
985
986static void
987mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
988 unsigned int status)
989{
990 void __iomem *base = host->base;
49adc0ca 991 bool sbc;
ad82bfea
UH		 992
993 if (!cmd)
994 return;
995
996 sbc = (cmd == host->mrq->sbc);
ad82bfea 997
49adc0ca
LW		 998 /*
999 * We need to be one of these interrupts to be considered worth
1000 * handling. Note that we tag on any latent IRQs postponed
1001 * due to waiting for busy status.
1002 */
1003 if (!((status|host->busy_status) &
1004 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
ad82bfea 1005 return;
8d94b54d 1006
49adc0ca
LW		 1007 /*
1008 * ST Micro variant: handle busy detection.
1009 */
1010 if (host->variant->busy_detect) {
1011 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
8d94b54d 1012
49adc0ca
LW		 1013 /* We are busy with a command, return */
1014 if (host->busy_status &&
1015 (status & host->variant->busy_detect_flag))
1016 return;
1017
1018 /*
1019 * We were not busy, but we now got a busy response on
1020 * something that was not an error, and we double-check
1021 * that the special busy status bit is still set before
1022 * proceeding.
1023 */
1024 if (!host->busy_status && busy_resp &&
1025 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1026 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
5cad24d8
JNG		 1027
1028 /* Clear the busy start IRQ */
1029 writel(host->variant->busy_detect_mask,
1030 host->base + MMCICLEAR);
1031
1032 /* Unmask the busy end IRQ */
49adc0ca
LW		 1033 writel(readl(base + MMCIMASK0) |
1034 host->variant->busy_detect_mask,
1035 base + MMCIMASK0);
1036 /*
1037 * Now cache the last response status code (until
1038 * the busy bit goes low), and return.
1039 */
1040 host->busy_status =
1041 status & (MCI_CMDSENT|MCI_CMDRESPEND);
1042 return;
1043 }
8d94b54d 1044
49adc0ca
LW		 1045 /*
1046 * At this point we are not busy with a command, we have
5cad24d8
JNG		 1047 * not received a new busy request, clear and mask the busy
1048 * end IRQ and fall through to process the IRQ.
49adc0ca
LW		 1049 */
1050 if (host->busy_status) {
5cad24d8
JNG		 1051
1052 writel(host->variant->busy_detect_mask,
1053 host->base + MMCICLEAR);
1054
49adc0ca
LW		 1055 writel(readl(base + MMCIMASK0) &
1056 ~host->variant->busy_detect_mask,
1057 base + MMCIMASK0);
1058 host->busy_status = 0;
1059 }
8d94b54d 1060 }
1da177e4
LT		 1061
1062 host->cmd = NULL;
1063
1da177e4 1064 if (status & MCI_CMDTIMEOUT) {
17b0429d 1065 cmd->error = -ETIMEDOUT;
1da177e4 1066 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
17b0429d 1067 cmd->error = -EILSEQ;
9047b435
RKAL		 1068 } else {
1069 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1070 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1071 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1072 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1da177e4
LT		 1073 }
1074
024629c6 1075 if ((!sbc && !cmd->data) || cmd->error) {
3b6e3c73
UH		 1076 if (host->data) {
1077 /* Terminate the DMA transfer */
653a761e 1078 if (dma_inprogress(host)) {
3b6e3c73 1079 mmci_dma_data_error(host);
653a761e
UH		 1080 mmci_dma_unmap(host, host->data);
1081 }
e47c222b 1082 mmci_stop_data(host);
3b6e3c73 1083 }
024629c6
UH		 1084 mmci_request_end(host, host->mrq);
1085 } else if (sbc) {
1086 mmci_start_command(host, host->mrq->cmd, 0);
1da177e4
LT		 1087 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
1088 mmci_start_data(host, cmd->data);
1089 }
1090}
1091
9c34b73d
SK		 1092static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1093{
1094 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1095}
1096
1097static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1098{
1099 /*
1100 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1101 * from the fifo range should be used
1102 */
1103 if (status & MCI_RXFIFOHALFFULL)
1104 return host->variant->fifohalfsize;
1105 else if (status & MCI_RXDATAAVLBL)
1106 return 4;
1107
1108 return 0;
1109}
1110
1da177e4
LT		 1111static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1112{
1113 void __iomem *base = host->base;
1114 char *ptr = buffer;
9c34b73d 1115 u32 status = readl(host->base + MMCISTATUS);
26eed9a5 1116 int host_remain = host->size;
1da177e4
LT		 1117
1118 do {
9c34b73d 1119 int count = host->get_rx_fifocnt(host, status, host_remain);
1da177e4
LT		 1120
1121 if (count > remain)
1122 count = remain;
1123
1124 if (count <= 0)
1125 break;
1126
393e5e24
UH		 1127 /*
1128 * SDIO especially may want to send something that is
1129 * not divisible by 4 (as opposed to card sectors
1130 * etc). Therefore make sure to always read the last bytes
1131 * while only doing full 32-bit reads towards the FIFO.
1132 */
1133 if (unlikely(count & 0x3)) {
1134 if (count < 4) {
1135 unsigned char buf[4];
4b85da08 1136 ioread32_rep(base + MMCIFIFO, buf, 1);
393e5e24
UH		 1137 memcpy(ptr, buf, count);
1138 } else {
4b85da08 1139 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
393e5e24
UH		 1140 count &= ~0x3;
1141 }
1142 } else {
4b85da08 1143 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
393e5e24 1144 }
1da177e4
LT		 1145
1146 ptr += count;
1147 remain -= count;
26eed9a5 1148 host_remain -= count;
1da177e4
LT		 1149
1150 if (remain == 0)
1151 break;
1152
1153 status = readl(base + MMCISTATUS);
1154 } while (status & MCI_RXDATAAVLBL);
1155
1156 return ptr - buffer;
1157}
1158
1159static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1160{
8301bb68 1161 struct variant_data *variant = host->variant;
1da177e4
LT		 1162 void __iomem *base = host->base;
1163 char *ptr = buffer;
1164
1165 do {
1166 unsigned int count, maxcnt;
1167
8301bb68
RV		 1168 maxcnt = status & MCI_TXFIFOEMPTY ?
1169 variant->fifosize : variant->fifohalfsize;
1da177e4
LT		 1170 count = min(remain, maxcnt);
1171
34177802
LW		 1172 /*
1173 * SDIO especially may want to send something that is
1174 * not divisible by 4 (as opposed to card sectors
1175 * etc), and the FIFO only accept full 32-bit writes.
1176 * So compensate by adding +3 on the count, a single
1177 * byte become a 32bit write, 7 bytes will be two
1178 * 32bit writes etc.
1179 */
4b85da08 1180 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1da177e4
LT		 1181
1182 ptr += count;
1183 remain -= count;
1184
1185 if (remain == 0)
1186 break;
1187
1188 status = readl(base + MMCISTATUS);
1189 } while (status & MCI_TXFIFOHALFEMPTY);
1190
1191 return ptr - buffer;
1192}
1193
1194/*
1195 * PIO data transfer IRQ handler.
1196 */
7d12e780 1197static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1da177e4
LT		 1198{
1199 struct mmci_host *host = dev_id;
4ce1d6cb 1200 struct sg_mapping_iter *sg_miter = &host->sg_miter;
8301bb68 1201 struct variant_data *variant = host->variant;
1da177e4 1202 void __iomem *base = host->base;
4ce1d6cb 1203 unsigned long flags;
1da177e4
LT		 1204 u32 status;
1205
1206 status = readl(base + MMCISTATUS);
1207
64de0289 1208 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1da177e4 1209
4ce1d6cb
RV		 1210 local_irq_save(flags);
1211
1da177e4 1212 do {
1da177e4
LT		 1213 unsigned int remain, len;
1214 char *buffer;
1215
1216 /*
1217 * For write, we only need to test the half-empty flag
1218 * here - if the FIFO is completely empty, then by
1219 * definition it is more than half empty.
1220 *
1221 * For read, check for data available.
1222 */
1223 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1224 break;
1225
4ce1d6cb
RV		 1226 if (!sg_miter_next(sg_miter))
1227 break;
1228
1229 buffer = sg_miter->addr;
1230 remain = sg_miter->length;
1da177e4
LT		 1231
1232 len = 0;
1233 if (status & MCI_RXACTIVE)
1234 len = mmci_pio_read(host, buffer, remain);
1235 if (status & MCI_TXACTIVE)
1236 len = mmci_pio_write(host, buffer, remain, status);
1237
4ce1d6cb 1238 sg_miter->consumed = len;
1da177e4 1239
1da177e4
LT		 1240 host->size -= len;
1241 remain -= len;
1242
1243 if (remain)
1244 break;
1245
1da177e4
LT		 1246 status = readl(base + MMCISTATUS);
1247 } while (1);
1248
4ce1d6cb
RV		 1249 sg_miter_stop(sg_miter);
1250
1251 local_irq_restore(flags);
1252
1da177e4 1253 /*
c4d877c1
RK		 1254 * If we have less than the fifo 'half-full' threshold to transfer,
1255 * trigger a PIO interrupt as soon as any data is available.
1da177e4 1256 */
c4d877c1 1257 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
2686b4b4 1258 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1da177e4
LT		 1259
1260 /*
1261 * If we run out of data, disable the data IRQs; this
1262 * prevents a race where the FIFO becomes empty before
1263 * the chip itself has disabled the data path, and
1264 * stops us racing with our data end IRQ.
1265 */
1266 if (host->size == 0) {
2686b4b4 1267 mmci_set_mask1(host, 0);
1da177e4
LT		 1268 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1269 }
1270
1271 return IRQ_HANDLED;
1272}
1273
1274/*
1275 * Handle completion of command and data transfers.
1276 */
7d12e780 1277static irqreturn_t mmci_irq(int irq, void *dev_id)
1da177e4
LT		 1278{
1279 struct mmci_host *host = dev_id;
1280 u32 status;
1281 int ret = 0;
1282
1283 spin_lock(&host->lock);
1284
1285 do {
1da177e4 1286 status = readl(host->base + MMCISTATUS);
2686b4b4
LW		 1287
1288 if (host->singleirq) {
1289 if (status & readl(host->base + MMCIMASK1))
1290 mmci_pio_irq(irq, dev_id);
1291
1292 status &= ~MCI_IRQ1MASK;
1293 }
1294
8d94b54d 1295 /*
5cad24d8
JNG		 1296 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
1297 * enabled) in mmci_cmd_irq() function where ST Micro busy
1298 * detection variant is handled. Considering the HW seems to be
1299 * triggering the IRQ on both edges while monitoring DAT0 for
1300 * busy completion and that same status bit is used to monitor
1301 * start and end of busy detection, special care must be taken
1302 * to make sure that both start and end interrupts are always
1303 * cleared one after the other.
8d94b54d 1304 */
1da177e4 1305 status &= readl(host->base + MMCIMASK0);
5cad24d8
JNG		 1306 if (host->variant->busy_detect)
1307 writel(status & ~host->variant->busy_detect_mask,
1308 host->base + MMCICLEAR);
1309 else
1310 writel(status, host->base + MMCICLEAR);
1da177e4 1311
64de0289 1312 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1da177e4 1313
7878289b
UH		 1314 if (host->variant->reversed_irq_handling) {
1315 mmci_data_irq(host, host->data, status);
1316 mmci_cmd_irq(host, host->cmd, status);
1317 } else {
1318 mmci_cmd_irq(host, host->cmd, status);
1319 mmci_data_irq(host, host->data, status);
1320 }
1da177e4 1321
49adc0ca
LW		 1322 /*
1323 * Don't poll for busy completion in irq context.
1324 */
1325 if (host->variant->busy_detect && host->busy_status)
1326 status &= ~host->variant->busy_detect_flag;
8d94b54d 1327
1da177e4
LT		 1328 ret = 1;
1329 } while (status);
1330
1331 spin_unlock(&host->lock);
1332
1333 return IRQ_RETVAL(ret);
1334}
1335
1336static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1337{
1338 struct mmci_host *host = mmc_priv(mmc);
9e943021 1339 unsigned long flags;
1da177e4
LT		 1340
1341 WARN_ON(host->mrq != NULL);
1342
653a761e
UH		 1343 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1344 if (mrq->cmd->error) {
255d01af
PO		 1345 mmc_request_done(mmc, mrq);
1346 return;
1347 }
1348
9e943021 1349 spin_lock_irqsave(&host->lock, flags);
1da177e4
LT		 1350
1351 host->mrq = mrq;
1352
58c7ccbf
PF		 1353 if (mrq->data)
1354 mmci_get_next_data(host, mrq->data);
1355
1da177e4
LT		 1356 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1357 mmci_start_data(host, mrq->data);
1358
024629c6
UH		 1359 if (mrq->sbc)
1360 mmci_start_command(host, mrq->sbc, 0);
1361 else
1362 mmci_start_command(host, mrq->cmd, 0);
1da177e4 1363
9e943021 1364 spin_unlock_irqrestore(&host->lock, flags);
1da177e4
LT		 1365}
1366
1367static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1368{
1369 struct mmci_host *host = mmc_priv(mmc);
7d72a1d4 1370 struct variant_data *variant = host->variant;
a6a6464a
LW		 1371 u32 pwr = 0;
1372 unsigned long flags;
db90f91f 1373 int ret;
1da177e4 1374
bc521818
UH		 1375 if (host->plat->ios_handler &&
1376 host->plat->ios_handler(mmc_dev(mmc), ios))
1377 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1378
1da177e4
LT		 1379 switch (ios->power_mode) {
1380 case MMC_POWER_OFF:
599c1d5c
UH		 1381 if (!IS_ERR(mmc->supply.vmmc))
1382 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
237fb5e6 1383
7c0136ef 1384 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
237fb5e6 1385 regulator_disable(mmc->supply.vqmmc);
7c0136ef
UH		 1386 host->vqmmc_enabled = false;
1387 }
237fb5e6 1388
1da177e4
LT		 1389 break;
1390 case MMC_POWER_UP:
599c1d5c
UH		 1391 if (!IS_ERR(mmc->supply.vmmc))
1392 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1393
7d72a1d4
UH		 1394 /*
1395 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1396 * and instead uses MCI_PWR_ON so apply whatever value is
1397 * configured in the variant data.
1398 */
1399 pwr |= variant->pwrreg_powerup;
1400
1401 break;
1da177e4 1402 case MMC_POWER_ON:
7c0136ef 1403 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
db90f91f
LJ		 1404 ret = regulator_enable(mmc->supply.vqmmc);
1405 if (ret < 0)
1406 dev_err(mmc_dev(mmc),
1407 "failed to enable vqmmc regulator\n");
7c0136ef
UH		 1408 else
1409 host->vqmmc_enabled = true;
db90f91f 1410 }
237fb5e6 1411
1da177e4
LT		 1412 pwr |= MCI_PWR_ON;
1413 break;
1414 }
1415
4d1a3a0d
UH		 1416 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1417 /*
1418 * The ST Micro variant has some additional bits
1419 * indicating signal direction for the signals in
1420 * the SD/MMC bus and feedback-clock usage.
1421 */
4593df29 1422 pwr |= host->pwr_reg_add;
4d1a3a0d
UH		 1423
1424 if (ios->bus_width == MMC_BUS_WIDTH_4)
1425 pwr &= ~MCI_ST_DATA74DIREN;
1426 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1427 pwr &= (~MCI_ST_DATA74DIREN &
1428 ~MCI_ST_DATA31DIREN &
1429 ~MCI_ST_DATA2DIREN);
1430 }
1431
cc30d60e 1432 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
f17a1f06 1433 if (host->hw_designer != AMBA_VENDOR_ST)
cc30d60e
LW		 1434 pwr |= MCI_ROD;
1435 else {
1436 /*
1437 * The ST Micro variant use the ROD bit for something
1438 * else and only has OD (Open Drain).
1439 */
1440 pwr |= MCI_OD;
1441 }
1442 }
1da177e4 1443
f4670dae
UH		 1444 /*
1445 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1446 * gating the clock, the MCI_PWR_ON bit is cleared.
1447 */
1448 if (!ios->clock && variant->pwrreg_clkgate)
1449 pwr &= ~MCI_PWR_ON;
1450
3f4e6f7b
SK		 1451 if (host->variant->explicit_mclk_control &&
1452 ios->clock != host->clock_cache) {
1453 ret = clk_set_rate(host->clk, ios->clock);
1454 if (ret < 0)
1455 dev_err(mmc_dev(host->mmc),
1456 "Error setting clock rate (%d)\n", ret);
1457 else
1458 host->mclk = clk_get_rate(host->clk);
1459 }
1460 host->clock_cache = ios->clock;
1461
a6a6464a
LW		 1462 spin_lock_irqsave(&host->lock, flags);
1463
1464 mmci_set_clkreg(host, ios->clock);
7437cfa5 1465 mmci_write_pwrreg(host, pwr);
f829c042 1466 mmci_reg_delay(host);
a6a6464a
LW		 1467
1468 spin_unlock_irqrestore(&host->lock, flags);
1da177e4
LT		 1469}
1470
89001446
RK		 1471static int mmci_get_cd(struct mmc_host *mmc)
1472{
1473 struct mmci_host *host = mmc_priv(mmc);
29719445 1474 struct mmci_platform_data *plat = host->plat;
d2762090 1475 unsigned int status = mmc_gpio_get_cd(mmc);
89001446 1476
d2762090 1477 if (status == -ENOSYS) {
4b8caec0
RV		 1478 if (!plat->status)
1479 return 1; /* Assume always present */
1480
29719445 1481 status = plat->status(mmc_dev(host->mmc));
d2762090 1482 }
74bc8093 1483 return status;
89001446
RK		 1484}
1485
0f3ed7f7
UH		 1486static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1487{
1488 int ret = 0;
1489
1490 if (!IS_ERR(mmc->supply.vqmmc)) {
1491
0f3ed7f7
UH		 1492 switch (ios->signal_voltage) {
1493 case MMC_SIGNAL_VOLTAGE_330:
1494 ret = regulator_set_voltage(mmc->supply.vqmmc,
1495 2700000, 3600000);
1496 break;
1497 case MMC_SIGNAL_VOLTAGE_180:
1498 ret = regulator_set_voltage(mmc->supply.vqmmc,
1499 1700000, 1950000);
1500 break;
1501 case MMC_SIGNAL_VOLTAGE_120:
1502 ret = regulator_set_voltage(mmc->supply.vqmmc,
1503 1100000, 1300000);
1504 break;
1505 }
1506
1507 if (ret)
1508 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
0f3ed7f7
UH		 1509 }
1510
1511 return ret;
1512}
1513
01259620 1514static struct mmc_host_ops mmci_ops = {
1da177e4 1515 .request = mmci_request,
58c7ccbf
PF		 1516 .pre_req = mmci_pre_request,
1517 .post_req = mmci_post_request,
1da177e4 1518 .set_ios = mmci_set_ios,
d2762090 1519 .get_ro = mmc_gpio_get_ro,
89001446 1520 .get_cd = mmci_get_cd,
0f3ed7f7 1521 .start_signal_voltage_switch = mmci_sig_volt_switch,
1da177e4
LT		 1522};
1523
4593df29 1524static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
000bc9d5 1525{
4593df29
UH		 1526 struct mmci_host *host = mmc_priv(mmc);
1527 int ret = mmc_of_parse(mmc);
1528
1529 if (ret)
1530 return ret;
1531
ae94cafe 1532 if (of_get_property(np, "st,sig-dir-dat0", NULL))
4593df29 1533 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
ae94cafe 1534 if (of_get_property(np, "st,sig-dir-dat2", NULL))
4593df29 1535 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
ae94cafe 1536 if (of_get_property(np, "st,sig-dir-dat31", NULL))
4593df29 1537 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
ae94cafe 1538 if (of_get_property(np, "st,sig-dir-dat74", NULL))
4593df29 1539 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
ae94cafe 1540 if (of_get_property(np, "st,sig-dir-cmd", NULL))
4593df29 1541 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1a7e99c1 1542 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
4593df29 1543 host->pwr_reg_add |= MCI_ST_FBCLKEN;
000bc9d5
LJ		 1544
1545 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
78f87df2 1546 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
000bc9d5 1547 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
78f87df2 1548 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
000bc9d5 1549
78f87df2 1550 return 0;
c0a120a4 1551}
000bc9d5 1552
c3be1efd 1553static int mmci_probe(struct amba_device *dev,
aa25afad 1554 const struct amba_id *id)
1da177e4 1555{
6ef297f8 1556 struct mmci_platform_data *plat = dev->dev.platform_data;
000bc9d5 1557 struct device_node *np = dev->dev.of_node;
4956e109 1558 struct variant_data *variant = id->data;
1da177e4
LT		 1559 struct mmci_host *host;
1560 struct mmc_host *mmc;
1561 int ret;
1562
000bc9d5
LJ		 1563 /* Must have platform data or Device Tree. */
1564 if (!plat && !np) {
1565 dev_err(&dev->dev, "No plat data or DT found\n");
1566 return -EINVAL;
1da177e4
LT		 1567 }
1568
b9b52918
LJ		 1569 if (!plat) {
1570 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1571 if (!plat)
1572 return -ENOMEM;
1573 }
1574
1da177e4 1575 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
ef289982
UH		 1576 if (!mmc)
1577 return -ENOMEM;
1da177e4 1578
78f87df2
UH		 1579 ret = mmci_of_parse(np, mmc);
1580 if (ret)
1581 goto host_free;
1582
1da177e4 1583 host = mmc_priv(mmc);
4ea580f1 1584 host->mmc = mmc;
012b7d33
RK		 1585
1586 host->hw_designer = amba_manf(dev);
1587 host->hw_revision = amba_rev(dev);
64de0289
LW		 1588 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1589 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
012b7d33 1590
665ba56f 1591 host->clk = devm_clk_get(&dev->dev, NULL);
1da177e4
LT		 1592 if (IS_ERR(host->clk)) {
1593 ret = PTR_ERR(host->clk);
1da177e4
LT		 1594 goto host_free;
1595 }
1596
ac940938 1597 ret = clk_prepare_enable(host->clk);
1da177e4 1598 if (ret)
665ba56f 1599 goto host_free;
1da177e4 1600
9c34b73d
SK		 1601 if (variant->qcom_fifo)
1602 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1603 else
1604 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1605
1da177e4 1606 host->plat = plat;
4956e109 1607 host->variant = variant;
1da177e4 1608 host->mclk = clk_get_rate(host->clk);
c8df9a53
LW		 1609 /*
1610 * According to the spec, mclk is max 100 MHz,
1611 * so we try to adjust the clock down to this,
1612 * (if possible).
1613 */
dc6500bf
SK		 1614 if (host->mclk > variant->f_max) {
1615 ret = clk_set_rate(host->clk, variant->f_max);
c8df9a53
LW		 1616 if (ret < 0)
1617 goto clk_disable;
1618 host->mclk = clk_get_rate(host->clk);
64de0289
LW		 1619 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1620 host->mclk);
c8df9a53 1621 }
ef289982 1622
c8ebae37 1623 host->phybase = dev->res.start;
ef289982
UH		 1624 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1625 if (IS_ERR(host->base)) {
1626 ret = PTR_ERR(host->base);
1da177e4
LT		 1627 goto clk_disable;
1628 }
1629
7f294e49
LW		 1630 /*
1631 * The ARM and ST versions of the block have slightly different
1632 * clock divider equations which means that the minimum divider
1633 * differs too.
3f4e6f7b 1634 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
7f294e49
LW		 1635 */
1636 if (variant->st_clkdiv)
1637 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
3f4e6f7b
SK		 1638 else if (variant->explicit_mclk_control)
1639 mmc->f_min = clk_round_rate(host->clk, 100000);
7f294e49
LW		 1640 else
1641 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
808d97cc 1642 /*
78f87df2
UH		 1643 * If no maximum operating frequency is supplied, fall back to use
1644 * the module parameter, which has a (low) default value in case it
1645 * is not specified. Either value must not exceed the clock rate into
5080a08d 1646 * the block, of course.
808d97cc 1647 */
78f87df2 1648 if (mmc->f_max)
3f4e6f7b
SK		 1649 mmc->f_max = variant->explicit_mclk_control ?
1650 min(variant->f_max, mmc->f_max) :
1651 min(host->mclk, mmc->f_max);
808d97cc 1652 else
3f4e6f7b
SK		 1653 mmc->f_max = variant->explicit_mclk_control ?
1654 fmax : min(host->mclk, fmax);
1655
1656
64de0289
LW		 1657 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1658
599c1d5c 1659 /* Get regulators and the supported OCR mask */
9369c97c
BA		 1660 ret = mmc_regulator_get_supply(mmc);
1661 if (ret == -EPROBE_DEFER)
1662 goto clk_disable;
1663
599c1d5c 1664 if (!mmc->ocr_avail)
34e84f39 1665 mmc->ocr_avail = plat->ocr_mask;
599c1d5c
UH		 1666 else if (plat->ocr_mask)
1667 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1668
78f87df2 1669 /* DT takes precedence over platform data. */
78f87df2
UH		 1670 if (!np) {
1671 if (!plat->cd_invert)
1672 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1673 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1674 }
1da177e4 1675
9dd8a8b8
UH		 1676 /* We support these capabilities. */
1677 mmc->caps |= MMC_CAP_CMD23;
1678
49adc0ca
LW		 1679 /*
1680 * Enable busy detection.
1681 */
8d94b54d
UH		 1682 if (variant->busy_detect) {
1683 mmci_ops.card_busy = mmci_card_busy;
49adc0ca
LW		 1684 /*
1685 * Not all variants have a flag to enable busy detection
1686 * in the DPSM, but if they do, set it here.
1687 */
1688 if (variant->busy_dpsm_flag)
1689 mmci_write_datactrlreg(host,
1690 host->variant->busy_dpsm_flag);
8d94b54d
UH		 1691 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1692 mmc->max_busy_timeout = 0;
1693 }
1694
1695 mmc->ops = &mmci_ops;
1696
70be208f 1697 /* We support these PM capabilities. */
78f87df2 1698 mmc->pm_caps |= MMC_PM_KEEP_POWER;
70be208f 1699
1da177e4
LT		 1700 /*
1701 * We can do SGIO
1702 */
a36274e0 1703 mmc->max_segs = NR_SG;
1da177e4
LT		 1704
1705 /*
08458ef6
RV		 1706 * Since only a certain number of bits are valid in the data length
1707 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1708 * single request.
1da177e4 1709 */
08458ef6 1710 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1da177e4
LT		 1711
1712 /*
1713 * Set the maximum segment size. Since we aren't doing DMA
1714 * (yet) we are only limited by the data length register.
1715 */
55db890a 1716 mmc->max_seg_size = mmc->max_req_size;
1da177e4 1717
fe4a3c7a
PO		 1718 /*
1719 * Block size can be up to 2048 bytes, but must be a power of two.
1720 */
8f7f6b7e 1721 mmc->max_blk_size = 1 << 11;
fe4a3c7a 1722
55db890a 1723 /*
8f7f6b7e
WD		 1724 * Limit the number of blocks transferred so that we don't overflow
1725 * the maximum request size.
55db890a 1726 */
8f7f6b7e 1727 mmc->max_blk_count = mmc->max_req_size >> 11;
55db890a 1728
1da177e4
LT		 1729 spin_lock_init(&host->lock);
1730
1731 writel(0, host->base + MMCIMASK0);
1732 writel(0, host->base + MMCIMASK1);
1733 writel(0xfff, host->base + MMCICLEAR);
1734
ce437aa4
LW		 1735 /*
1736 * If:
1737 * - not using DT but using a descriptor table, or
1738 * - using a table of descriptors ALONGSIDE DT, or
1739 * look up these descriptors named "cd" and "wp" right here, fail
1740 * silently of these do not exist and proceed to try platform data
1741 */
1742 if (!np) {
89168b48 1743 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
ce437aa4
LW		 1744 if (ret < 0) {
1745 if (ret == -EPROBE_DEFER)
1746 goto clk_disable;
1747 else if (gpio_is_valid(plat->gpio_cd)) {
1748 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1749 if (ret)
1750 goto clk_disable;
1751 }
1752 }
1753
89168b48 1754 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
ce437aa4
LW		 1755 if (ret < 0) {
1756 if (ret == -EPROBE_DEFER)
1757 goto clk_disable;
1758 else if (gpio_is_valid(plat->gpio_wp)) {
1759 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1760 if (ret)
1761 goto clk_disable;
1762 }
1763 }
89001446
RK		 1764 }
1765
ef289982
UH		 1766 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1767 DRIVER_NAME " (cmd)", host);
1da177e4 1768 if (ret)
ef289982 1769 goto clk_disable;
1da177e4 1770
dfb85185 1771 if (!dev->irq[1])
2686b4b4
LW		 1772 host->singleirq = true;
1773 else {
ef289982
UH		 1774 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1775 IRQF_SHARED, DRIVER_NAME " (pio)", host);
2686b4b4 1776 if (ret)
ef289982 1777 goto clk_disable;
2686b4b4 1778 }
1da177e4 1779
8cb28155 1780 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1da177e4
LT		 1781
1782 amba_set_drvdata(dev, mmc);
1783
c8ebae37
RK		 1784 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1785 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1786 amba_rev(dev), (unsigned long long)dev->res.start,
1787 dev->irq[0], dev->irq[1]);
1788
1789 mmci_dma_setup(host);
1da177e4 1790
2cd976c4
UH		 1791 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1792 pm_runtime_use_autosuspend(&dev->dev);
1c3be369 1793
8c11a94d
RK		 1794 mmc_add_host(mmc);
1795
6f2d3c89 1796 pm_runtime_put(&dev->dev);
1da177e4
LT		 1797 return 0;
1798
1da177e4 1799 clk_disable:
ac940938 1800 clk_disable_unprepare(host->clk);
1da177e4
LT		 1801 host_free:
1802 mmc_free_host(mmc);
1da177e4
LT		 1803 return ret;
1804}
1805
6e0ee714 1806static int mmci_remove(struct amba_device *dev)
1da177e4
LT		 1807{
1808 struct mmc_host *mmc = amba_get_drvdata(dev);
1809
1da177e4
LT		 1810 if (mmc) {
1811 struct mmci_host *host = mmc_priv(mmc);
1812
1c3be369
RK		 1813 /*
1814 * Undo pm_runtime_put() in probe. We use the _sync
1815 * version here so that we can access the primecell.
1816 */
1817 pm_runtime_get_sync(&dev->dev);
1818
1da177e4
LT		 1819 mmc_remove_host(mmc);
1820
1821 writel(0, host->base + MMCIMASK0);
1822 writel(0, host->base + MMCIMASK1);
1823
1824 writel(0, host->base + MMCICOMMAND);
1825 writel(0, host->base + MMCIDATACTRL);
1826
c8ebae37 1827 mmci_dma_release(host);
ac940938 1828 clk_disable_unprepare(host->clk);
1da177e4 1829 mmc_free_host(mmc);
1da177e4
LT		 1830 }
1831
1832 return 0;
1833}
1834
571dce4f 1835#ifdef CONFIG_PM
1ff44433
UH		 1836static void mmci_save(struct mmci_host *host)
1837{
1838 unsigned long flags;
1839
42dcc89a 1840 spin_lock_irqsave(&host->lock, flags);
1ff44433 1841
42dcc89a
UH		 1842 writel(0, host->base + MMCIMASK0);
1843 if (host->variant->pwrreg_nopower) {
1ff44433
UH		 1844 writel(0, host->base + MMCIDATACTRL);
1845 writel(0, host->base + MMCIPOWER);
1846 writel(0, host->base + MMCICLOCK);
1ff44433 1847 }
42dcc89a 1848 mmci_reg_delay(host);
1ff44433 1849
42dcc89a 1850 spin_unlock_irqrestore(&host->lock, flags);
1ff44433
UH		 1851}
1852
1853static void mmci_restore(struct mmci_host *host)
1854{
1855 unsigned long flags;
1856
42dcc89a 1857 spin_lock_irqsave(&host->lock, flags);
1ff44433 1858
42dcc89a 1859 if (host->variant->pwrreg_nopower) {
1ff44433
UH		 1860 writel(host->clk_reg, host->base + MMCICLOCK);
1861 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1862 writel(host->pwr_reg, host->base + MMCIPOWER);
1ff44433 1863 }
42dcc89a
UH		 1864 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1865 mmci_reg_delay(host);
1866
1867 spin_unlock_irqrestore(&host->lock, flags);
1ff44433
UH		 1868}
1869
8259293a
UH		 1870static int mmci_runtime_suspend(struct device *dev)
1871{
1872 struct amba_device *adev = to_amba_device(dev);
1873 struct mmc_host *mmc = amba_get_drvdata(adev);
1874
1875 if (mmc) {
1876 struct mmci_host *host = mmc_priv(mmc);
e36bd9c6 1877 pinctrl_pm_select_sleep_state(dev);
1ff44433 1878 mmci_save(host);
8259293a
UH		 1879 clk_disable_unprepare(host->clk);
1880 }
1881
1882 return 0;
1883}
1884
1885static int mmci_runtime_resume(struct device *dev)
1886{
1887 struct amba_device *adev = to_amba_device(dev);
1888 struct mmc_host *mmc = amba_get_drvdata(adev);
1889
1890 if (mmc) {
1891 struct mmci_host *host = mmc_priv(mmc);
1892 clk_prepare_enable(host->clk);
1ff44433 1893 mmci_restore(host);
e36bd9c6 1894 pinctrl_pm_select_default_state(dev);
8259293a
UH		 1895 }
1896
1897 return 0;
1898}
1899#endif
1900
48fa7003 1901static const struct dev_pm_ops mmci_dev_pm_ops = {
f3737fa3
UH		 1902 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1903 pm_runtime_force_resume)
6ed23b80 1904 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
48fa7003
UH		 1905};
1906
1da177e4
LT		 1907static struct amba_id mmci_ids[] = {
1908 {
1909 .id = 0x00041180,
768fbc18 1910 .mask = 0xff0fffff,
4956e109 1911 .data = &variant_arm,
1da177e4 1912 },
768fbc18
PM		 1913 {
1914 .id = 0x01041180,
1915 .mask = 0xff0fffff,
1916 .data = &variant_arm_extended_fifo,
1917 },
3a37298a
PM		 1918 {
1919 .id = 0x02041180,
1920 .mask = 0xff0fffff,
1921 .data = &variant_arm_extended_fifo_hwfc,
1922 },
1da177e4
LT		 1923 {
1924 .id = 0x00041181,
1925 .mask = 0x000fffff,
4956e109 1926 .data = &variant_arm,
1da177e4 1927 },
cc30d60e
LW		 1928 /* ST Micro variants */
1929 {
1930 .id = 0x00180180,
1931 .mask = 0x00ffffff,
4956e109 1932 .data = &variant_u300,
cc30d60e 1933 },
34fd4213
LW		 1934 {
1935 .id = 0x10180180,
1936 .mask = 0xf0ffffff,
1937 .data = &variant_nomadik,
1938 },
cc30d60e
LW		 1939 {
1940 .id = 0x00280180,
1941 .mask = 0x00ffffff,
0bcb7efd 1942 .data = &variant_nomadik,
4956e109
RV		 1943 },
1944 {
1945 .id = 0x00480180,
1784b157 1946 .mask = 0xf0ffffff,
4956e109 1947 .data = &variant_ux500,
cc30d60e 1948 },
1784b157
PL		 1949 {
1950 .id = 0x10480180,
1951 .mask = 0xf0ffffff,
1952 .data = &variant_ux500v2,
1953 },
55b604ae
SK		 1954 /* Qualcomm variants */
1955 {
1956 .id = 0x00051180,
1957 .mask = 0x000fffff,
1958 .data = &variant_qcom,
1959 },
1da177e4
LT		 1960 { 0, 0 },
1961};
1962
9f99835f
DM		 1963MODULE_DEVICE_TABLE(amba, mmci_ids);
1964
1da177e4
LT		 1965static struct amba_driver mmci_driver = {
1966 .drv = {
1967 .name = DRIVER_NAME,
48fa7003 1968 .pm = &mmci_dev_pm_ops,
1da177e4
LT		 1969 },
1970 .probe = mmci_probe,
0433c143 1971 .remove = mmci_remove,
1da177e4
LT		 1972 .id_table = mmci_ids,
1973};
1974
9e5ed094 1975module_amba_driver(mmci_driver);
1da177e4 1976
1da177e4
LT		 1977module_param(fmax, uint, 0444);
1978
1979MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1980MODULE_LICENSE("GPL");
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