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a912e80b | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
61bfbdb8 LPC |
2 | /* |
3 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> | |
6a78768a AS |
4 | * Copyright (C) 2013, Imagination Technologies |
5 | * | |
61bfbdb8 | 6 | * JZ4740 SD/MMC controller driver |
61bfbdb8 LPC |
7 | */ |
8 | ||
7e7845f3 EG |
9 | #include <linux/bitops.h> |
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/dmaengine.h> | |
13 | #include <linux/dma-mapping.h> | |
3119cbda | 14 | #include <linux/err.h> |
7e7845f3 | 15 | #include <linux/interrupt.h> |
61bfbdb8 LPC |
16 | #include <linux/io.h> |
17 | #include <linux/irq.h> | |
7e7845f3 EG |
18 | #include <linux/mmc/host.h> |
19 | #include <linux/mmc/slot-gpio.h> | |
61bfbdb8 | 20 | #include <linux/module.h> |
61e11eba | 21 | #include <linux/of_device.h> |
fa5ed6bc | 22 | #include <linux/pinctrl/consumer.h> |
61bfbdb8 | 23 | #include <linux/platform_device.h> |
152b5245 | 24 | #include <linux/regulator/consumer.h> |
61bfbdb8 | 25 | #include <linux/scatterlist.h> |
61bfbdb8 | 26 | |
61bfbdb8 | 27 | #include <asm/cacheflush.h> |
61bfbdb8 | 28 | |
61bfbdb8 LPC |
29 | #define JZ_REG_MMC_STRPCL 0x00 |
30 | #define JZ_REG_MMC_STATUS 0x04 | |
31 | #define JZ_REG_MMC_CLKRT 0x08 | |
32 | #define JZ_REG_MMC_CMDAT 0x0C | |
33 | #define JZ_REG_MMC_RESTO 0x10 | |
34 | #define JZ_REG_MMC_RDTO 0x14 | |
35 | #define JZ_REG_MMC_BLKLEN 0x18 | |
36 | #define JZ_REG_MMC_NOB 0x1C | |
37 | #define JZ_REG_MMC_SNOB 0x20 | |
38 | #define JZ_REG_MMC_IMASK 0x24 | |
39 | #define JZ_REG_MMC_IREG 0x28 | |
40 | #define JZ_REG_MMC_CMD 0x2C | |
41 | #define JZ_REG_MMC_ARG 0x30 | |
42 | #define JZ_REG_MMC_RESP_FIFO 0x34 | |
43 | #define JZ_REG_MMC_RXFIFO 0x38 | |
44 | #define JZ_REG_MMC_TXFIFO 0x3C | |
80fe4e90 | 45 | #define JZ_REG_MMC_LPM 0x40 |
6a78768a | 46 | #define JZ_REG_MMC_DMAC 0x44 |
61bfbdb8 LPC |
47 | |
48 | #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) | |
49 | #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) | |
50 | #define JZ_MMC_STRPCL_START_READWAIT BIT(5) | |
51 | #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) | |
52 | #define JZ_MMC_STRPCL_RESET BIT(3) | |
53 | #define JZ_MMC_STRPCL_START_OP BIT(2) | |
54 | #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) | |
55 | #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) | |
56 | #define JZ_MMC_STRPCL_CLOCK_START BIT(1) | |
57 | ||
58 | ||
59 | #define JZ_MMC_STATUS_IS_RESETTING BIT(15) | |
60 | #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) | |
61 | #define JZ_MMC_STATUS_PRG_DONE BIT(13) | |
62 | #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) | |
63 | #define JZ_MMC_STATUS_END_CMD_RES BIT(11) | |
64 | #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) | |
65 | #define JZ_MMC_STATUS_IS_READWAIT BIT(9) | |
66 | #define JZ_MMC_STATUS_CLK_EN BIT(8) | |
67 | #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) | |
68 | #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) | |
69 | #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) | |
70 | #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) | |
71 | #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) | |
72 | #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) | |
73 | #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) | |
74 | #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) | |
75 | ||
76 | #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) | |
77 | #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) | |
78 | ||
79 | ||
80 | #define JZ_MMC_CMDAT_IO_ABORT BIT(11) | |
81 | #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) | |
a02f8f48 ZY |
82 | #define JZ_MMC_CMDAT_BUS_WIDTH_8BIT (BIT(10) | BIT(9)) |
83 | #define JZ_MMC_CMDAT_BUS_WIDTH_MASK (BIT(10) | BIT(9)) | |
61bfbdb8 LPC |
84 | #define JZ_MMC_CMDAT_DMA_EN BIT(8) |
85 | #define JZ_MMC_CMDAT_INIT BIT(7) | |
86 | #define JZ_MMC_CMDAT_BUSY BIT(6) | |
87 | #define JZ_MMC_CMDAT_STREAM BIT(5) | |
88 | #define JZ_MMC_CMDAT_WRITE BIT(4) | |
89 | #define JZ_MMC_CMDAT_DATA_EN BIT(3) | |
90 | #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) | |
91 | #define JZ_MMC_CMDAT_RSP_R1 1 | |
92 | #define JZ_MMC_CMDAT_RSP_R2 2 | |
93 | #define JZ_MMC_CMDAT_RSP_R3 3 | |
94 | ||
95 | #define JZ_MMC_IRQ_SDIO BIT(7) | |
96 | #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) | |
97 | #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) | |
98 | #define JZ_MMC_IRQ_END_CMD_RES BIT(2) | |
99 | #define JZ_MMC_IRQ_PRG_DONE BIT(1) | |
100 | #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) | |
101 | ||
6a78768a AS |
102 | #define JZ_MMC_DMAC_DMA_SEL BIT(1) |
103 | #define JZ_MMC_DMAC_DMA_EN BIT(0) | |
61bfbdb8 | 104 | |
80fe4e90 ZY |
105 | #define JZ_MMC_LPM_DRV_RISING BIT(31) |
106 | #define JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY BIT(31) | |
107 | #define JZ_MMC_LPM_DRV_RISING_1NS_DLY BIT(30) | |
108 | #define JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY BIT(29) | |
109 | #define JZ_MMC_LPM_LOW_POWER_MODE_EN BIT(0) | |
110 | ||
61bfbdb8 | 111 | #define JZ_MMC_CLK_RATE 24000000 |
d422f8b9 | 112 | #define JZ_MMC_REQ_TIMEOUT_MS 5000 |
61bfbdb8 | 113 | |
61e11eba EG |
114 | enum jz4740_mmc_version { |
115 | JZ_MMC_JZ4740, | |
a0c938b5 | 116 | JZ_MMC_JZ4725B, |
2af2af99 | 117 | JZ_MMC_JZ4760, |
6a78768a | 118 | JZ_MMC_JZ4780, |
fea5fcc2 | 119 | JZ_MMC_X1000, |
61e11eba EG |
120 | }; |
121 | ||
61bfbdb8 LPC |
122 | enum jz4740_mmc_state { |
123 | JZ4740_MMC_STATE_READ_RESPONSE, | |
124 | JZ4740_MMC_STATE_TRANSFER_DATA, | |
125 | JZ4740_MMC_STATE_SEND_STOP, | |
126 | JZ4740_MMC_STATE_DONE, | |
127 | }; | |
128 | ||
96e03fff EG |
129 | /* |
130 | * The MMC core allows to prepare a mmc_request while another mmc_request | |
131 | * is in-flight. This is used via the pre_req/post_req hooks. | |
132 | * This driver uses the pre_req/post_req hooks to map/unmap the mmc_request. | |
133 | * Following what other drivers do (sdhci, dw_mmc) we use the following cookie | |
134 | * flags to keep track of the mmc_request mapping state. | |
135 | * | |
136 | * COOKIE_UNMAPPED: the request is not mapped. | |
137 | * COOKIE_PREMAPPED: the request was mapped in pre_req, | |
138 | * and should be unmapped in post_req. | |
139 | * COOKIE_MAPPED: the request was mapped in the irq handler, | |
140 | * and should be unmapped before mmc_request_done is called.. | |
141 | */ | |
142 | enum jz4780_cookie { | |
143 | COOKIE_UNMAPPED = 0, | |
144 | COOKIE_PREMAPPED, | |
145 | COOKIE_MAPPED, | |
bb2f4592 AS |
146 | }; |
147 | ||
61bfbdb8 LPC |
148 | struct jz4740_mmc_host { |
149 | struct mmc_host *mmc; | |
150 | struct platform_device *pdev; | |
61bfbdb8 LPC |
151 | struct clk *clk; |
152 | ||
61e11eba EG |
153 | enum jz4740_mmc_version version; |
154 | ||
61bfbdb8 | 155 | int irq; |
61bfbdb8 | 156 | |
61bfbdb8 | 157 | void __iomem *base; |
7ca27a6f | 158 | struct resource *mem_res; |
61bfbdb8 LPC |
159 | struct mmc_request *req; |
160 | struct mmc_command *cmd; | |
161 | ||
152b5245 PC |
162 | bool vqmmc_enabled; |
163 | ||
61bfbdb8 LPC |
164 | unsigned long waiting; |
165 | ||
166 | uint32_t cmdat; | |
167 | ||
6a78768a | 168 | uint32_t irq_mask; |
61bfbdb8 LPC |
169 | |
170 | spinlock_t lock; | |
171 | ||
172 | struct timer_list timeout_timer; | |
173 | struct sg_mapping_iter miter; | |
174 | enum jz4740_mmc_state state; | |
7ca27a6f AS |
175 | |
176 | /* DMA support */ | |
177 | struct dma_chan *dma_rx; | |
178 | struct dma_chan *dma_tx; | |
179 | bool use_dma; | |
7ca27a6f AS |
180 | |
181 | /* The DMA trigger level is 8 words, that is to say, the DMA read | |
182 | * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write | |
183 | * trigger is when data words in MSC_TXFIFO is < 8. | |
184 | */ | |
185 | #define JZ4740_MMC_FIFO_HALF_SIZE 8 | |
61bfbdb8 LPC |
186 | }; |
187 | ||
6a78768a AS |
188 | static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host, |
189 | uint32_t val) | |
190 | { | |
a0c938b5 | 191 | if (host->version >= JZ_MMC_JZ4725B) |
6a78768a AS |
192 | return writel(val, host->base + JZ_REG_MMC_IMASK); |
193 | else | |
194 | return writew(val, host->base + JZ_REG_MMC_IMASK); | |
195 | } | |
196 | ||
197 | static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host, | |
198 | uint32_t val) | |
199 | { | |
200 | if (host->version >= JZ_MMC_JZ4780) | |
65af9866 | 201 | writel(val, host->base + JZ_REG_MMC_IREG); |
6a78768a | 202 | else |
65af9866 | 203 | writew(val, host->base + JZ_REG_MMC_IREG); |
6a78768a AS |
204 | } |
205 | ||
206 | static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host) | |
207 | { | |
208 | if (host->version >= JZ_MMC_JZ4780) | |
209 | return readl(host->base + JZ_REG_MMC_IREG); | |
210 | else | |
211 | return readw(host->base + JZ_REG_MMC_IREG); | |
212 | } | |
213 | ||
7ca27a6f AS |
214 | /*----------------------------------------------------------------------------*/ |
215 | /* DMA infrastructure */ | |
216 | ||
217 | static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host) | |
218 | { | |
219 | if (!host->use_dma) | |
220 | return; | |
221 | ||
222 | dma_release_channel(host->dma_tx); | |
a474e52c PC |
223 | if (host->dma_rx) |
224 | dma_release_channel(host->dma_rx); | |
7ca27a6f AS |
225 | } |
226 | ||
227 | static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host) | |
228 | { | |
a474e52c PC |
229 | struct device *dev = mmc_dev(host->mmc); |
230 | ||
231 | host->dma_tx = dma_request_chan(dev, "tx-rx"); | |
232 | if (!IS_ERR(host->dma_tx)) | |
233 | return 0; | |
234 | ||
235 | if (PTR_ERR(host->dma_tx) != -ENODEV) { | |
236 | dev_err(dev, "Failed to get dma tx-rx channel\n"); | |
237 | return PTR_ERR(host->dma_tx); | |
238 | } | |
239 | ||
fb0ce9dd EG |
240 | host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); |
241 | if (IS_ERR(host->dma_tx)) { | |
7ca27a6f | 242 | dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n"); |
fb0ce9dd | 243 | return PTR_ERR(host->dma_tx); |
7ca27a6f AS |
244 | } |
245 | ||
fb0ce9dd EG |
246 | host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); |
247 | if (IS_ERR(host->dma_rx)) { | |
7ca27a6f | 248 | dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n"); |
fb0ce9dd EG |
249 | dma_release_channel(host->dma_tx); |
250 | return PTR_ERR(host->dma_rx); | |
7ca27a6f AS |
251 | } |
252 | ||
afadb04f AM |
253 | /* |
254 | * Limit the maximum segment size in any SG entry according to | |
255 | * the parameters of the DMA engine device. | |
256 | */ | |
257 | if (host->dma_tx) { | |
258 | struct device *dev = host->dma_tx->device->dev; | |
259 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
260 | ||
261 | if (max_seg_size < host->mmc->max_seg_size) | |
262 | host->mmc->max_seg_size = max_seg_size; | |
263 | } | |
264 | ||
265 | if (host->dma_rx) { | |
266 | struct device *dev = host->dma_rx->device->dev; | |
267 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
268 | ||
269 | if (max_seg_size < host->mmc->max_seg_size) | |
270 | host->mmc->max_seg_size = max_seg_size; | |
271 | } | |
272 | ||
7ca27a6f | 273 | return 0; |
7ca27a6f AS |
274 | } |
275 | ||
bb2f4592 AS |
276 | static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host, |
277 | struct mmc_data *data) | |
278 | { | |
a474e52c PC |
279 | if ((data->flags & MMC_DATA_READ) && host->dma_rx) |
280 | return host->dma_rx; | |
281 | else | |
282 | return host->dma_tx; | |
bb2f4592 AS |
283 | } |
284 | ||
7ca27a6f AS |
285 | static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host, |
286 | struct mmc_data *data) | |
287 | { | |
bb2f4592 | 288 | struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); |
feeef096 | 289 | enum dma_data_direction dir = mmc_get_dma_dir(data); |
7ca27a6f | 290 | |
7ca27a6f | 291 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); |
96e03fff | 292 | data->host_cookie = COOKIE_UNMAPPED; |
7ca27a6f AS |
293 | } |
294 | ||
96e03fff EG |
295 | /* Prepares DMA data for current or next transfer. |
296 | * A request can be in-flight when this is called. | |
297 | */ | |
bb2f4592 AS |
298 | static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host, |
299 | struct mmc_data *data, | |
96e03fff | 300 | int cookie) |
bb2f4592 | 301 | { |
96e03fff | 302 | struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); |
feeef096 | 303 | enum dma_data_direction dir = mmc_get_dma_dir(data); |
8827f85e | 304 | unsigned int sg_count; |
bb2f4592 | 305 | |
96e03fff EG |
306 | if (data->host_cookie == COOKIE_PREMAPPED) |
307 | return data->sg_count; | |
bb2f4592 | 308 | |
96e03fff EG |
309 | sg_count = dma_map_sg(chan->device->dev, |
310 | data->sg, | |
311 | data->sg_len, | |
312 | dir); | |
bb2f4592 | 313 | |
8827f85e | 314 | if (!sg_count) { |
bb2f4592 AS |
315 | dev_err(mmc_dev(host->mmc), |
316 | "Failed to map scatterlist for DMA operation\n"); | |
317 | return -EINVAL; | |
318 | } | |
319 | ||
96e03fff EG |
320 | data->sg_count = sg_count; |
321 | data->host_cookie = cookie; | |
bb2f4592 | 322 | |
96e03fff | 323 | return data->sg_count; |
bb2f4592 AS |
324 | } |
325 | ||
7ca27a6f AS |
326 | static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host, |
327 | struct mmc_data *data) | |
328 | { | |
96e03fff | 329 | struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); |
7ca27a6f AS |
330 | struct dma_async_tx_descriptor *desc; |
331 | struct dma_slave_config conf = { | |
332 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
333 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
334 | .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, | |
335 | .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, | |
336 | }; | |
96e03fff | 337 | int sg_count; |
7ca27a6f | 338 | |
bb2f4592 | 339 | if (data->flags & MMC_DATA_WRITE) { |
7ca27a6f AS |
340 | conf.direction = DMA_MEM_TO_DEV; |
341 | conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO; | |
7ca27a6f AS |
342 | } else { |
343 | conf.direction = DMA_DEV_TO_MEM; | |
344 | conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO; | |
7ca27a6f AS |
345 | } |
346 | ||
96e03fff EG |
347 | sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED); |
348 | if (sg_count < 0) | |
349 | return sg_count; | |
7ca27a6f AS |
350 | |
351 | dmaengine_slave_config(chan, &conf); | |
96e03fff EG |
352 | desc = dmaengine_prep_slave_sg(chan, data->sg, sg_count, |
353 | conf.direction, | |
354 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
7ca27a6f AS |
355 | if (!desc) { |
356 | dev_err(mmc_dev(host->mmc), | |
357 | "Failed to allocate DMA %s descriptor", | |
358 | conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX"); | |
359 | goto dma_unmap; | |
360 | } | |
361 | ||
362 | dmaengine_submit(desc); | |
363 | dma_async_issue_pending(chan); | |
364 | ||
365 | return 0; | |
366 | ||
367 | dma_unmap: | |
96e03fff EG |
368 | if (data->host_cookie == COOKIE_MAPPED) |
369 | jz4740_mmc_dma_unmap(host, data); | |
7ca27a6f AS |
370 | return -ENOMEM; |
371 | } | |
372 | ||
bb2f4592 | 373 | static void jz4740_mmc_pre_request(struct mmc_host *mmc, |
d3c6aac3 | 374 | struct mmc_request *mrq) |
bb2f4592 AS |
375 | { |
376 | struct jz4740_mmc_host *host = mmc_priv(mmc); | |
377 | struct mmc_data *data = mrq->data; | |
bb2f4592 | 378 | |
96e03fff EG |
379 | if (!host->use_dma) |
380 | return; | |
bb2f4592 | 381 | |
96e03fff EG |
382 | data->host_cookie = COOKIE_UNMAPPED; |
383 | if (jz4740_mmc_prepare_dma_data(host, data, COOKIE_PREMAPPED) < 0) | |
384 | data->host_cookie = COOKIE_UNMAPPED; | |
bb2f4592 AS |
385 | } |
386 | ||
387 | static void jz4740_mmc_post_request(struct mmc_host *mmc, | |
388 | struct mmc_request *mrq, | |
389 | int err) | |
390 | { | |
391 | struct jz4740_mmc_host *host = mmc_priv(mmc); | |
392 | struct mmc_data *data = mrq->data; | |
393 | ||
96e03fff | 394 | if (data && data->host_cookie != COOKIE_UNMAPPED) |
bb2f4592 | 395 | jz4740_mmc_dma_unmap(host, data); |
bb2f4592 AS |
396 | |
397 | if (err) { | |
398 | struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); | |
399 | ||
400 | dmaengine_terminate_all(chan); | |
401 | } | |
402 | } | |
403 | ||
7ca27a6f AS |
404 | /*----------------------------------------------------------------------------*/ |
405 | ||
61bfbdb8 LPC |
406 | static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, |
407 | unsigned int irq, bool enabled) | |
408 | { | |
409 | unsigned long flags; | |
410 | ||
411 | spin_lock_irqsave(&host->lock, flags); | |
412 | if (enabled) | |
413 | host->irq_mask &= ~irq; | |
414 | else | |
415 | host->irq_mask |= irq; | |
61bfbdb8 | 416 | |
6a78768a | 417 | jz4740_mmc_write_irq_mask(host, host->irq_mask); |
a04f0017 | 418 | spin_unlock_irqrestore(&host->lock, flags); |
61bfbdb8 LPC |
419 | } |
420 | ||
421 | static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, | |
422 | bool start_transfer) | |
423 | { | |
424 | uint16_t val = JZ_MMC_STRPCL_CLOCK_START; | |
425 | ||
426 | if (start_transfer) | |
427 | val |= JZ_MMC_STRPCL_START_OP; | |
428 | ||
429 | writew(val, host->base + JZ_REG_MMC_STRPCL); | |
430 | } | |
431 | ||
432 | static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) | |
433 | { | |
434 | uint32_t status; | |
435 | unsigned int timeout = 1000; | |
436 | ||
437 | writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); | |
438 | do { | |
439 | status = readl(host->base + JZ_REG_MMC_STATUS); | |
440 | } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); | |
441 | } | |
442 | ||
443 | static void jz4740_mmc_reset(struct jz4740_mmc_host *host) | |
444 | { | |
445 | uint32_t status; | |
446 | unsigned int timeout = 1000; | |
447 | ||
448 | writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); | |
449 | udelay(10); | |
450 | do { | |
451 | status = readl(host->base + JZ_REG_MMC_STATUS); | |
452 | } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); | |
453 | } | |
454 | ||
455 | static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) | |
456 | { | |
457 | struct mmc_request *req; | |
96e03fff | 458 | struct mmc_data *data; |
61bfbdb8 LPC |
459 | |
460 | req = host->req; | |
96e03fff | 461 | data = req->data; |
61bfbdb8 LPC |
462 | host->req = NULL; |
463 | ||
96e03fff EG |
464 | if (data && data->host_cookie == COOKIE_MAPPED) |
465 | jz4740_mmc_dma_unmap(host, data); | |
61bfbdb8 LPC |
466 | mmc_request_done(host->mmc, req); |
467 | } | |
468 | ||
469 | static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, | |
470 | unsigned int irq) | |
471 | { | |
472 | unsigned int timeout = 0x800; | |
6a78768a | 473 | uint32_t status; |
61bfbdb8 LPC |
474 | |
475 | do { | |
6a78768a | 476 | status = jz4740_mmc_read_irq_reg(host); |
61bfbdb8 LPC |
477 | } while (!(status & irq) && --timeout); |
478 | ||
479 | if (timeout == 0) { | |
480 | set_bit(0, &host->waiting); | |
d422f8b9 UH |
481 | mod_timer(&host->timeout_timer, |
482 | jiffies + msecs_to_jiffies(JZ_MMC_REQ_TIMEOUT_MS)); | |
61bfbdb8 LPC |
483 | jz4740_mmc_set_irq_enabled(host, irq, true); |
484 | return true; | |
485 | } | |
486 | ||
487 | return false; | |
488 | } | |
489 | ||
490 | static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, | |
491 | struct mmc_data *data) | |
492 | { | |
493 | int status; | |
494 | ||
495 | status = readl(host->base + JZ_REG_MMC_STATUS); | |
496 | if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { | |
497 | if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { | |
498 | host->req->cmd->error = -ETIMEDOUT; | |
499 | data->error = -ETIMEDOUT; | |
500 | } else { | |
501 | host->req->cmd->error = -EIO; | |
502 | data->error = -EIO; | |
503 | } | |
8a489aa1 PC |
504 | } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) { |
505 | if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) { | |
506 | host->req->cmd->error = -ETIMEDOUT; | |
507 | data->error = -ETIMEDOUT; | |
508 | } else { | |
509 | host->req->cmd->error = -EIO; | |
510 | data->error = -EIO; | |
511 | } | |
61bfbdb8 LPC |
512 | } |
513 | } | |
514 | ||
515 | static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, | |
516 | struct mmc_data *data) | |
517 | { | |
518 | struct sg_mapping_iter *miter = &host->miter; | |
519 | void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; | |
520 | uint32_t *buf; | |
521 | bool timeout; | |
522 | size_t i, j; | |
523 | ||
524 | while (sg_miter_next(miter)) { | |
525 | buf = miter->addr; | |
526 | i = miter->length / 4; | |
527 | j = i / 8; | |
528 | i = i & 0x7; | |
529 | while (j) { | |
530 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); | |
531 | if (unlikely(timeout)) | |
532 | goto poll_timeout; | |
533 | ||
534 | writel(buf[0], fifo_addr); | |
535 | writel(buf[1], fifo_addr); | |
536 | writel(buf[2], fifo_addr); | |
537 | writel(buf[3], fifo_addr); | |
538 | writel(buf[4], fifo_addr); | |
539 | writel(buf[5], fifo_addr); | |
540 | writel(buf[6], fifo_addr); | |
541 | writel(buf[7], fifo_addr); | |
542 | buf += 8; | |
543 | --j; | |
544 | } | |
545 | if (unlikely(i)) { | |
546 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); | |
547 | if (unlikely(timeout)) | |
548 | goto poll_timeout; | |
549 | ||
550 | while (i) { | |
551 | writel(*buf, fifo_addr); | |
552 | ++buf; | |
553 | --i; | |
554 | } | |
555 | } | |
556 | data->bytes_xfered += miter->length; | |
557 | } | |
558 | sg_miter_stop(miter); | |
559 | ||
560 | return false; | |
561 | ||
562 | poll_timeout: | |
563 | miter->consumed = (void *)buf - miter->addr; | |
564 | data->bytes_xfered += miter->consumed; | |
565 | sg_miter_stop(miter); | |
566 | ||
567 | return true; | |
568 | } | |
569 | ||
570 | static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, | |
571 | struct mmc_data *data) | |
572 | { | |
573 | struct sg_mapping_iter *miter = &host->miter; | |
574 | void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; | |
575 | uint32_t *buf; | |
576 | uint32_t d; | |
6a78768a | 577 | uint32_t status; |
61bfbdb8 LPC |
578 | size_t i, j; |
579 | unsigned int timeout; | |
580 | ||
581 | while (sg_miter_next(miter)) { | |
582 | buf = miter->addr; | |
583 | i = miter->length; | |
584 | j = i / 32; | |
585 | i = i & 0x1f; | |
586 | while (j) { | |
587 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); | |
588 | if (unlikely(timeout)) | |
589 | goto poll_timeout; | |
590 | ||
591 | buf[0] = readl(fifo_addr); | |
592 | buf[1] = readl(fifo_addr); | |
593 | buf[2] = readl(fifo_addr); | |
594 | buf[3] = readl(fifo_addr); | |
595 | buf[4] = readl(fifo_addr); | |
596 | buf[5] = readl(fifo_addr); | |
597 | buf[6] = readl(fifo_addr); | |
598 | buf[7] = readl(fifo_addr); | |
599 | ||
600 | buf += 8; | |
601 | --j; | |
602 | } | |
603 | ||
604 | if (unlikely(i)) { | |
605 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); | |
606 | if (unlikely(timeout)) | |
607 | goto poll_timeout; | |
608 | ||
609 | while (i >= 4) { | |
610 | *buf++ = readl(fifo_addr); | |
611 | i -= 4; | |
612 | } | |
613 | if (unlikely(i > 0)) { | |
614 | d = readl(fifo_addr); | |
615 | memcpy(buf, &d, i); | |
616 | } | |
617 | } | |
618 | data->bytes_xfered += miter->length; | |
61bfbdb8 LPC |
619 | } |
620 | sg_miter_stop(miter); | |
621 | ||
622 | /* For whatever reason there is sometime one word more in the fifo then | |
623 | * requested */ | |
624 | timeout = 1000; | |
625 | status = readl(host->base + JZ_REG_MMC_STATUS); | |
626 | while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { | |
627 | d = readl(fifo_addr); | |
628 | status = readl(host->base + JZ_REG_MMC_STATUS); | |
629 | } | |
630 | ||
631 | return false; | |
632 | ||
633 | poll_timeout: | |
634 | miter->consumed = (void *)buf - miter->addr; | |
635 | data->bytes_xfered += miter->consumed; | |
636 | sg_miter_stop(miter); | |
637 | ||
638 | return true; | |
639 | } | |
640 | ||
2ee4f620 | 641 | static void jz4740_mmc_timeout(struct timer_list *t) |
61bfbdb8 | 642 | { |
2ee4f620 | 643 | struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer); |
61bfbdb8 LPC |
644 | |
645 | if (!test_and_clear_bit(0, &host->waiting)) | |
646 | return; | |
647 | ||
648 | jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); | |
649 | ||
650 | host->req->cmd->error = -ETIMEDOUT; | |
651 | jz4740_mmc_request_done(host); | |
652 | } | |
653 | ||
654 | static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, | |
655 | struct mmc_command *cmd) | |
656 | { | |
657 | int i; | |
658 | uint16_t tmp; | |
659 | void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; | |
660 | ||
661 | if (cmd->flags & MMC_RSP_136) { | |
662 | tmp = readw(fifo_addr); | |
663 | for (i = 0; i < 4; ++i) { | |
664 | cmd->resp[i] = tmp << 24; | |
665 | tmp = readw(fifo_addr); | |
666 | cmd->resp[i] |= tmp << 8; | |
667 | tmp = readw(fifo_addr); | |
668 | cmd->resp[i] |= tmp >> 8; | |
669 | } | |
670 | } else { | |
671 | cmd->resp[0] = readw(fifo_addr) << 24; | |
672 | cmd->resp[0] |= readw(fifo_addr) << 8; | |
673 | cmd->resp[0] |= readw(fifo_addr) & 0xff; | |
674 | } | |
675 | } | |
676 | ||
677 | static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, | |
678 | struct mmc_command *cmd) | |
679 | { | |
680 | uint32_t cmdat = host->cmdat; | |
681 | ||
682 | host->cmdat &= ~JZ_MMC_CMDAT_INIT; | |
683 | jz4740_mmc_clock_disable(host); | |
684 | ||
685 | host->cmd = cmd; | |
686 | ||
687 | if (cmd->flags & MMC_RSP_BUSY) | |
688 | cmdat |= JZ_MMC_CMDAT_BUSY; | |
689 | ||
690 | switch (mmc_resp_type(cmd)) { | |
691 | case MMC_RSP_R1B: | |
692 | case MMC_RSP_R1: | |
693 | cmdat |= JZ_MMC_CMDAT_RSP_R1; | |
694 | break; | |
695 | case MMC_RSP_R2: | |
696 | cmdat |= JZ_MMC_CMDAT_RSP_R2; | |
697 | break; | |
698 | case MMC_RSP_R3: | |
699 | cmdat |= JZ_MMC_CMDAT_RSP_R3; | |
700 | break; | |
701 | default: | |
702 | break; | |
703 | } | |
704 | ||
705 | if (cmd->data) { | |
706 | cmdat |= JZ_MMC_CMDAT_DATA_EN; | |
707 | if (cmd->data->flags & MMC_DATA_WRITE) | |
708 | cmdat |= JZ_MMC_CMDAT_WRITE; | |
6a78768a AS |
709 | if (host->use_dma) { |
710 | /* | |
d1c777ee | 711 | * The JZ4780's MMC controller has integrated DMA ability |
6a78768a AS |
712 | * in addition to being able to use the external DMA |
713 | * controller. It moves DMA control bits to a separate | |
714 | * register. The DMA_SEL bit chooses the external | |
715 | * controller over the integrated one. Earlier SoCs | |
716 | * can only use the external controller, and have a | |
717 | * single DMA enable bit in CMDAT. | |
718 | */ | |
719 | if (host->version >= JZ_MMC_JZ4780) { | |
720 | writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL, | |
721 | host->base + JZ_REG_MMC_DMAC); | |
722 | } else { | |
723 | cmdat |= JZ_MMC_CMDAT_DMA_EN; | |
724 | } | |
725 | } else if (host->version >= JZ_MMC_JZ4780) { | |
726 | writel(0, host->base + JZ_REG_MMC_DMAC); | |
727 | } | |
61bfbdb8 LPC |
728 | |
729 | writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); | |
730 | writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); | |
731 | } | |
732 | ||
733 | writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); | |
734 | writel(cmd->arg, host->base + JZ_REG_MMC_ARG); | |
735 | writel(cmdat, host->base + JZ_REG_MMC_CMDAT); | |
736 | ||
737 | jz4740_mmc_clock_enable(host, 1); | |
738 | } | |
739 | ||
740 | static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) | |
741 | { | |
742 | struct mmc_command *cmd = host->req->cmd; | |
743 | struct mmc_data *data = cmd->data; | |
744 | int direction; | |
745 | ||
746 | if (data->flags & MMC_DATA_READ) | |
747 | direction = SG_MITER_TO_SG; | |
748 | else | |
749 | direction = SG_MITER_FROM_SG; | |
750 | ||
751 | sg_miter_start(&host->miter, data->sg, data->sg_len, direction); | |
752 | } | |
753 | ||
754 | ||
755 | static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) | |
756 | { | |
757 | struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; | |
758 | struct mmc_command *cmd = host->req->cmd; | |
759 | struct mmc_request *req = host->req; | |
7ca27a6f | 760 | struct mmc_data *data = cmd->data; |
61bfbdb8 LPC |
761 | bool timeout = false; |
762 | ||
763 | if (cmd->error) | |
764 | host->state = JZ4740_MMC_STATE_DONE; | |
765 | ||
766 | switch (host->state) { | |
767 | case JZ4740_MMC_STATE_READ_RESPONSE: | |
768 | if (cmd->flags & MMC_RSP_PRESENT) | |
769 | jz4740_mmc_read_response(host, cmd); | |
770 | ||
7ca27a6f | 771 | if (!data) |
61bfbdb8 LPC |
772 | break; |
773 | ||
774 | jz_mmc_prepare_data_transfer(host); | |
df561f66 | 775 | fallthrough; |
61bfbdb8 LPC |
776 | |
777 | case JZ4740_MMC_STATE_TRANSFER_DATA: | |
7ca27a6f | 778 | if (host->use_dma) { |
bb2f4592 AS |
779 | /* Use DMA if enabled. |
780 | * Data transfer direction is defined later by | |
781 | * relying on data flags in | |
782 | * jz4740_mmc_prepare_dma_data() and | |
783 | * jz4740_mmc_start_dma_transfer(). | |
7ca27a6f AS |
784 | */ |
785 | timeout = jz4740_mmc_start_dma_transfer(host, data); | |
786 | data->bytes_xfered = data->blocks * data->blksz; | |
787 | } else if (data->flags & MMC_DATA_READ) | |
bb2f4592 AS |
788 | /* Use PIO if DMA is not enabled. |
789 | * Data transfer direction was defined before | |
790 | * by relying on data flags in | |
791 | * jz_mmc_prepare_data_transfer(). | |
7ca27a6f AS |
792 | */ |
793 | timeout = jz4740_mmc_read_data(host, data); | |
61bfbdb8 | 794 | else |
7ca27a6f | 795 | timeout = jz4740_mmc_write_data(host, data); |
61bfbdb8 LPC |
796 | |
797 | if (unlikely(timeout)) { | |
798 | host->state = JZ4740_MMC_STATE_TRANSFER_DATA; | |
799 | break; | |
800 | } | |
801 | ||
7ca27a6f | 802 | jz4740_mmc_transfer_check_state(host, data); |
61bfbdb8 LPC |
803 | |
804 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); | |
805 | if (unlikely(timeout)) { | |
806 | host->state = JZ4740_MMC_STATE_SEND_STOP; | |
807 | break; | |
808 | } | |
6a78768a | 809 | jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE); |
df561f66 | 810 | fallthrough; |
61bfbdb8 LPC |
811 | |
812 | case JZ4740_MMC_STATE_SEND_STOP: | |
813 | if (!req->stop) | |
814 | break; | |
815 | ||
816 | jz4740_mmc_send_command(host, req->stop); | |
817 | ||
1acee84b AS |
818 | if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) { |
819 | timeout = jz4740_mmc_poll_irq(host, | |
820 | JZ_MMC_IRQ_PRG_DONE); | |
821 | if (timeout) { | |
822 | host->state = JZ4740_MMC_STATE_DONE; | |
823 | break; | |
824 | } | |
61bfbdb8 | 825 | } |
f95deaec GS |
826 | fallthrough; |
827 | ||
61bfbdb8 LPC |
828 | case JZ4740_MMC_STATE_DONE: |
829 | break; | |
830 | } | |
831 | ||
832 | if (!timeout) | |
833 | jz4740_mmc_request_done(host); | |
834 | ||
835 | return IRQ_HANDLED; | |
836 | } | |
837 | ||
838 | static irqreturn_t jz_mmc_irq(int irq, void *devid) | |
839 | { | |
840 | struct jz4740_mmc_host *host = devid; | |
841 | struct mmc_command *cmd = host->cmd; | |
6a78768a | 842 | uint32_t irq_reg, status, tmp; |
61bfbdb8 | 843 | |
6a78768a AS |
844 | status = readl(host->base + JZ_REG_MMC_STATUS); |
845 | irq_reg = jz4740_mmc_read_irq_reg(host); | |
61bfbdb8 LPC |
846 | |
847 | tmp = irq_reg; | |
848 | irq_reg &= ~host->irq_mask; | |
849 | ||
850 | tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | | |
851 | JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); | |
852 | ||
853 | if (tmp != irq_reg) | |
6a78768a | 854 | jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg); |
61bfbdb8 LPC |
855 | |
856 | if (irq_reg & JZ_MMC_IRQ_SDIO) { | |
6a78768a | 857 | jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO); |
61bfbdb8 LPC |
858 | mmc_signal_sdio_irq(host->mmc); |
859 | irq_reg &= ~JZ_MMC_IRQ_SDIO; | |
860 | } | |
861 | ||
862 | if (host->req && cmd && irq_reg) { | |
863 | if (test_and_clear_bit(0, &host->waiting)) { | |
864 | del_timer(&host->timeout_timer); | |
865 | ||
61bfbdb8 | 866 | if (status & JZ_MMC_STATUS_TIMEOUT_RES) { |
65af9866 | 867 | cmd->error = -ETIMEDOUT; |
61bfbdb8 | 868 | } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { |
65af9866 | 869 | cmd->error = -EIO; |
61bfbdb8 LPC |
870 | } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | |
871 | JZ_MMC_STATUS_CRC_WRITE_ERROR)) { | |
65af9866 PC |
872 | if (cmd->data) |
873 | cmd->data->error = -EIO; | |
874 | cmd->error = -EIO; | |
61bfbdb8 LPC |
875 | } |
876 | ||
877 | jz4740_mmc_set_irq_enabled(host, irq_reg, false); | |
6a78768a | 878 | jz4740_mmc_write_irq_reg(host, irq_reg); |
61bfbdb8 LPC |
879 | |
880 | return IRQ_WAKE_THREAD; | |
881 | } | |
882 | } | |
883 | ||
884 | return IRQ_HANDLED; | |
885 | } | |
886 | ||
887 | static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) | |
888 | { | |
889 | int div = 0; | |
890 | int real_rate; | |
891 | ||
892 | jz4740_mmc_clock_disable(host); | |
6861fce6 | 893 | clk_set_rate(host->clk, host->mmc->f_max); |
61bfbdb8 LPC |
894 | |
895 | real_rate = clk_get_rate(host->clk); | |
896 | ||
897 | while (real_rate > rate && div < 7) { | |
898 | ++div; | |
899 | real_rate >>= 1; | |
900 | } | |
901 | ||
902 | writew(div, host->base + JZ_REG_MMC_CLKRT); | |
80fe4e90 ZY |
903 | |
904 | if (real_rate > 25000000) { | |
d1c777ee | 905 | if (host->version >= JZ_MMC_JZ4780) { |
80fe4e90 ZY |
906 | writel(JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY | |
907 | JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY | | |
908 | JZ_MMC_LPM_LOW_POWER_MODE_EN, | |
909 | host->base + JZ_REG_MMC_LPM); | |
910 | } else if (host->version >= JZ_MMC_JZ4760) { | |
911 | writel(JZ_MMC_LPM_DRV_RISING | | |
912 | JZ_MMC_LPM_LOW_POWER_MODE_EN, | |
913 | host->base + JZ_REG_MMC_LPM); | |
914 | } else if (host->version >= JZ_MMC_JZ4725B) | |
915 | writel(JZ_MMC_LPM_LOW_POWER_MODE_EN, | |
916 | host->base + JZ_REG_MMC_LPM); | |
917 | } | |
918 | ||
61bfbdb8 LPC |
919 | return real_rate; |
920 | } | |
921 | ||
922 | static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) | |
923 | { | |
924 | struct jz4740_mmc_host *host = mmc_priv(mmc); | |
925 | ||
926 | host->req = req; | |
927 | ||
6a78768a | 928 | jz4740_mmc_write_irq_reg(host, ~0); |
61bfbdb8 LPC |
929 | jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); |
930 | ||
931 | host->state = JZ4740_MMC_STATE_READ_RESPONSE; | |
932 | set_bit(0, &host->waiting); | |
d422f8b9 UH |
933 | mod_timer(&host->timeout_timer, |
934 | jiffies + msecs_to_jiffies(JZ_MMC_REQ_TIMEOUT_MS)); | |
61bfbdb8 LPC |
935 | jz4740_mmc_send_command(host, req->cmd); |
936 | } | |
937 | ||
938 | static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
939 | { | |
940 | struct jz4740_mmc_host *host = mmc_priv(mmc); | |
152b5245 PC |
941 | int ret; |
942 | ||
61bfbdb8 LPC |
943 | if (ios->clock) |
944 | jz4740_mmc_set_clock_rate(host, ios->clock); | |
945 | ||
946 | switch (ios->power_mode) { | |
947 | case MMC_POWER_UP: | |
948 | jz4740_mmc_reset(host); | |
05395527 PC |
949 | if (!IS_ERR(mmc->supply.vmmc)) |
950 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); | |
61bfbdb8 | 951 | host->cmdat |= JZ_MMC_CMDAT_INIT; |
fca9661c | 952 | clk_prepare_enable(host->clk); |
61bfbdb8 LPC |
953 | break; |
954 | case MMC_POWER_ON: | |
152b5245 PC |
955 | if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { |
956 | ret = regulator_enable(mmc->supply.vqmmc); | |
957 | if (ret) | |
958 | dev_err(&host->pdev->dev, "Failed to set vqmmc power!\n"); | |
959 | else | |
960 | host->vqmmc_enabled = true; | |
961 | } | |
61bfbdb8 | 962 | break; |
152b5245 | 963 | case MMC_POWER_OFF: |
05395527 PC |
964 | if (!IS_ERR(mmc->supply.vmmc)) |
965 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
152b5245 PC |
966 | if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { |
967 | regulator_disable(mmc->supply.vqmmc); | |
968 | host->vqmmc_enabled = false; | |
969 | } | |
fca9661c | 970 | clk_disable_unprepare(host->clk); |
61bfbdb8 | 971 | break; |
152b5245 PC |
972 | default: |
973 | break; | |
61bfbdb8 LPC |
974 | } |
975 | ||
976 | switch (ios->bus_width) { | |
977 | case MMC_BUS_WIDTH_1: | |
a02f8f48 | 978 | host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK; |
61bfbdb8 LPC |
979 | break; |
980 | case MMC_BUS_WIDTH_4: | |
a02f8f48 | 981 | host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK; |
61bfbdb8 LPC |
982 | host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; |
983 | break; | |
a02f8f48 ZY |
984 | case MMC_BUS_WIDTH_8: |
985 | host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK; | |
986 | host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_8BIT; | |
987 | break; | |
61bfbdb8 LPC |
988 | default: |
989 | break; | |
990 | } | |
991 | } | |
992 | ||
61bfbdb8 LPC |
993 | static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) |
994 | { | |
995 | struct jz4740_mmc_host *host = mmc_priv(mmc); | |
996 | jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); | |
997 | } | |
998 | ||
152b5245 PC |
999 | static int jz4740_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) |
1000 | { | |
1001 | int ret; | |
1002 | ||
1003 | /* vqmmc regulator is available */ | |
1004 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
1005 | ret = mmc_regulator_set_vqmmc(mmc, ios); | |
1006 | return ret < 0 ? ret : 0; | |
1007 | } | |
1008 | ||
1009 | /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ | |
1010 | if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) | |
1011 | return 0; | |
1012 | ||
1013 | return -EINVAL; | |
1014 | } | |
1015 | ||
61bfbdb8 LPC |
1016 | static const struct mmc_host_ops jz4740_mmc_ops = { |
1017 | .request = jz4740_mmc_request, | |
bb2f4592 AS |
1018 | .pre_req = jz4740_mmc_pre_request, |
1019 | .post_req = jz4740_mmc_post_request, | |
61bfbdb8 | 1020 | .set_ios = jz4740_mmc_set_ios, |
58e300af LPC |
1021 | .get_ro = mmc_gpio_get_ro, |
1022 | .get_cd = mmc_gpio_get_cd, | |
61bfbdb8 | 1023 | .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, |
152b5245 | 1024 | .start_signal_voltage_switch = jz4740_voltage_switch, |
61bfbdb8 LPC |
1025 | }; |
1026 | ||
61e11eba EG |
1027 | static const struct of_device_id jz4740_mmc_of_match[] = { |
1028 | { .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 }, | |
a0c938b5 | 1029 | { .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B }, |
2af2af99 | 1030 | { .compatible = "ingenic,jz4760-mmc", .data = (void *) JZ_MMC_JZ4760 }, |
d1c777ee | 1031 | { .compatible = "ingenic,jz4775-mmc", .data = (void *) JZ_MMC_JZ4780 }, |
6a78768a | 1032 | { .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 }, |
fea5fcc2 | 1033 | { .compatible = "ingenic,x1000-mmc", .data = (void *) JZ_MMC_X1000 }, |
61e11eba EG |
1034 | {}, |
1035 | }; | |
1036 | MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match); | |
1037 | ||
c3be1efd | 1038 | static int jz4740_mmc_probe(struct platform_device* pdev) |
61bfbdb8 LPC |
1039 | { |
1040 | int ret; | |
1041 | struct mmc_host *mmc; | |
1042 | struct jz4740_mmc_host *host; | |
61e11eba | 1043 | const struct of_device_id *match; |
61bfbdb8 LPC |
1044 | |
1045 | mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); | |
1046 | if (!mmc) { | |
1047 | dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); | |
1048 | return -ENOMEM; | |
1049 | } | |
1050 | ||
1051 | host = mmc_priv(mmc); | |
61bfbdb8 | 1052 | |
61e11eba EG |
1053 | match = of_match_device(jz4740_mmc_of_match, &pdev->dev); |
1054 | if (match) { | |
1055 | host->version = (enum jz4740_mmc_version)match->data; | |
61e11eba EG |
1056 | } else { |
1057 | /* JZ4740 should be the only one using legacy probe */ | |
1058 | host->version = JZ_MMC_JZ4740; | |
61e11eba EG |
1059 | } |
1060 | ||
05395527 PC |
1061 | ret = mmc_of_parse(mmc); |
1062 | if (ret) { | |
295208a6 | 1063 | dev_err_probe(&pdev->dev, ret, "could not parse device properties\n"); |
05395527 PC |
1064 | goto err_free_host; |
1065 | } | |
1066 | ||
1067 | mmc_regulator_get_supply(mmc); | |
1068 | ||
61bfbdb8 LPC |
1069 | host->irq = platform_get_irq(pdev, 0); |
1070 | if (host->irq < 0) { | |
1071 | ret = host->irq; | |
61bfbdb8 LPC |
1072 | goto err_free_host; |
1073 | } | |
1074 | ||
017d84bd | 1075 | host->clk = devm_clk_get(&pdev->dev, "mmc"); |
3119cbda JI |
1076 | if (IS_ERR(host->clk)) { |
1077 | ret = PTR_ERR(host->clk); | |
61bfbdb8 LPC |
1078 | dev_err(&pdev->dev, "Failed to get mmc clock\n"); |
1079 | goto err_free_host; | |
1080 | } | |
1081 | ||
7ca27a6f AS |
1082 | host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1083 | host->base = devm_ioremap_resource(&pdev->dev, host->mem_res); | |
3e7e8c18 WY |
1084 | if (IS_ERR(host->base)) { |
1085 | ret = PTR_ERR(host->base); | |
017d84bd | 1086 | goto err_free_host; |
61bfbdb8 LPC |
1087 | } |
1088 | ||
61bfbdb8 | 1089 | mmc->ops = &jz4740_mmc_ops; |
61e11eba EG |
1090 | if (!mmc->f_max) |
1091 | mmc->f_max = JZ_MMC_CLK_RATE; | |
3f18c504 PC |
1092 | |
1093 | /* | |
1094 | * There seems to be a problem with this driver on the JZ4760 and | |
1095 | * JZ4760B SoCs. There, when using the maximum rate supported (50 MHz), | |
1096 | * the communication fails with many SD cards. | |
1097 | * Until this bug is sorted out, limit the maximum rate to 24 MHz. | |
1098 | */ | |
1099 | if (host->version == JZ_MMC_JZ4760 && mmc->f_max > JZ_MMC_CLK_RATE) | |
1100 | mmc->f_max = JZ_MMC_CLK_RATE; | |
1101 | ||
61e11eba | 1102 | mmc->f_min = mmc->f_max / 128; |
61bfbdb8 | 1103 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
61bfbdb8 | 1104 | |
d422f8b9 UH |
1105 | /* |
1106 | * We use a fixed timeout of 5s, hence inform the core about it. A | |
1107 | * future improvement should instead respect the cmd->busy_timeout. | |
1108 | */ | |
1109 | mmc->max_busy_timeout = JZ_MMC_REQ_TIMEOUT_MS; | |
1110 | ||
61bfbdb8 LPC |
1111 | mmc->max_blk_size = (1 << 10) - 1; |
1112 | mmc->max_blk_count = (1 << 15) - 1; | |
1113 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1114 | ||
a36274e0 | 1115 | mmc->max_segs = 128; |
61bfbdb8 LPC |
1116 | mmc->max_seg_size = mmc->max_req_size; |
1117 | ||
1118 | host->mmc = mmc; | |
1119 | host->pdev = pdev; | |
1120 | spin_lock_init(&host->lock); | |
6a78768a | 1121 | host->irq_mask = ~0; |
61bfbdb8 | 1122 | |
436a3cfd ZLK |
1123 | jz4740_mmc_reset(host); |
1124 | ||
61bfbdb8 LPC |
1125 | ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, |
1126 | dev_name(&pdev->dev), host); | |
1127 | if (ret) { | |
1128 | dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); | |
0f6f3235 | 1129 | goto err_free_host; |
61bfbdb8 LPC |
1130 | } |
1131 | ||
61bfbdb8 | 1132 | jz4740_mmc_clock_disable(host); |
2ee4f620 | 1133 | timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0); |
61bfbdb8 | 1134 | |
7e8466e2 PC |
1135 | ret = jz4740_mmc_acquire_dma_channels(host); |
1136 | if (ret == -EPROBE_DEFER) | |
1137 | goto err_free_irq; | |
1138 | host->use_dma = !ret; | |
7ca27a6f | 1139 | |
61bfbdb8 LPC |
1140 | platform_set_drvdata(pdev, host); |
1141 | ret = mmc_add_host(mmc); | |
1142 | ||
1143 | if (ret) { | |
1144 | dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); | |
7e8466e2 | 1145 | goto err_release_dma; |
61bfbdb8 | 1146 | } |
fea5fcc2 | 1147 | dev_info(&pdev->dev, "Ingenic SD/MMC card driver registered\n"); |
61bfbdb8 | 1148 | |
7ca27a6f AS |
1149 | dev_info(&pdev->dev, "Using %s, %d-bit mode\n", |
1150 | host->use_dma ? "DMA" : "PIO", | |
a02f8f48 ZY |
1151 | (mmc->caps & MMC_CAP_8_BIT_DATA) ? 8 : |
1152 | ((mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1)); | |
7ca27a6f | 1153 | |
61bfbdb8 LPC |
1154 | return 0; |
1155 | ||
7e8466e2 PC |
1156 | err_release_dma: |
1157 | if (host->use_dma) | |
1158 | jz4740_mmc_release_dma_channels(host); | |
61bfbdb8 LPC |
1159 | err_free_irq: |
1160 | free_irq(host->irq, host); | |
61bfbdb8 | 1161 | err_free_host: |
61bfbdb8 LPC |
1162 | mmc_free_host(mmc); |
1163 | ||
1164 | return ret; | |
1165 | } | |
1166 | ||
6e0ee714 | 1167 | static int jz4740_mmc_remove(struct platform_device *pdev) |
61bfbdb8 LPC |
1168 | { |
1169 | struct jz4740_mmc_host *host = platform_get_drvdata(pdev); | |
1170 | ||
1171 | del_timer_sync(&host->timeout_timer); | |
1172 | jz4740_mmc_set_irq_enabled(host, 0xff, false); | |
1173 | jz4740_mmc_reset(host); | |
1174 | ||
1175 | mmc_remove_host(host->mmc); | |
1176 | ||
1177 | free_irq(host->irq, host); | |
61bfbdb8 | 1178 | |
7ca27a6f AS |
1179 | if (host->use_dma) |
1180 | jz4740_mmc_release_dma_channels(host); | |
1181 | ||
61bfbdb8 LPC |
1182 | mmc_free_host(host->mmc); |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
e0d64ecc | 1187 | static int jz4740_mmc_suspend(struct device *dev) |
61bfbdb8 | 1188 | { |
fa5ed6bc | 1189 | return pinctrl_pm_select_sleep_state(dev); |
61bfbdb8 LPC |
1190 | } |
1191 | ||
e0d64ecc | 1192 | static int jz4740_mmc_resume(struct device *dev) |
61bfbdb8 | 1193 | { |
a62ff540 | 1194 | return pinctrl_select_default_state(dev); |
61bfbdb8 LPC |
1195 | } |
1196 | ||
52cc1d7f PC |
1197 | static DEFINE_SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend, |
1198 | jz4740_mmc_resume); | |
61bfbdb8 LPC |
1199 | |
1200 | static struct platform_driver jz4740_mmc_driver = { | |
1201 | .probe = jz4740_mmc_probe, | |
0433c143 | 1202 | .remove = jz4740_mmc_remove, |
61bfbdb8 LPC |
1203 | .driver = { |
1204 | .name = "jz4740-mmc", | |
21b2cec6 | 1205 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
61e11eba | 1206 | .of_match_table = of_match_ptr(jz4740_mmc_of_match), |
e0d64ecc | 1207 | .pm = pm_sleep_ptr(&jz4740_mmc_pm_ops), |
61bfbdb8 LPC |
1208 | }, |
1209 | }; | |
1210 | ||
d1f81a64 | 1211 | module_platform_driver(jz4740_mmc_driver); |
61bfbdb8 LPC |
1212 | |
1213 | MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); | |
1214 | MODULE_LICENSE("GPL"); | |
1215 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); |