[linux-2.6-block.git] / drivers / mmc / host / dw_mmc-zx.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * ZX Specific Extensions for Synopsys DW Multimedia Card Interface driver
 *
 * Copyright (C) 2016, Linaro Ltd.
 * Copyright (C) 2016, ZTE Corp.
 */

#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
#include "dw_mmc-zx.h"

struct dw_mci_zx_priv_data {
	struct regmap	*sysc_base;
};

enum delay_type {
	DELAY_TYPE_READ,	/* read dqs delay */
	DELAY_TYPE_CLK,		/* clk sample delay */
};

static int dw_mci_zx_emmc_set_delay(struct dw_mci *host, unsigned int delay,
				    enum delay_type dflag)
{
	struct dw_mci_zx_priv_data *priv = host->priv;
	struct regmap *sysc_base = priv->sysc_base;
	unsigned int clksel;
	unsigned int loop = 1000;
	int ret;

	if (!sysc_base)
		return -EINVAL;

	ret = regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
				 PARA_HALF_CLK_MODE | PARA_DLL_BYPASS_MODE |
				 PARA_PHASE_DET_SEL_MASK |
				 PARA_DLL_LOCK_NUM_MASK |
				 DLL_REG_SET | PARA_DLL_START_MASK,
				 PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4));
	if (ret)
		return ret;

	ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel);
	if (ret)
		return ret;

	if (dflag == DELAY_TYPE_CLK) {
		clksel &= ~CLK_SAMP_DELAY_MASK;
		clksel |= CLK_SAMP_DELAY(delay);
	} else {
		clksel &= ~READ_DQS_DELAY_MASK;
		clksel |= READ_DQS_DELAY(delay);
	}

	regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel);
	regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
			   PARA_DLL_START_MASK | PARA_DLL_LOCK_NUM_MASK |
			   DLL_REG_SET,
			   PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4) |
			   DLL_REG_SET);

	do {
		ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel);
		if (ret)
			return ret;

	} while (--loop && !(clksel & ZX_DLL_LOCKED));

	if (!loop) {
		dev_err(host->dev, "Error: %s dll lock fail\n", __func__);
		return -EIO;
	}

	return 0;
}

static int dw_mci_zx_emmc_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
{
	struct dw_mci *host = slot->host;
	struct mmc_host *mmc = slot->mmc;
	int ret, len = 0, start = 0, end = 0, delay, best = 0;

	for (delay = 1; delay < 128; delay++) {
		ret = dw_mci_zx_emmc_set_delay(host, delay, DELAY_TYPE_CLK);
		if (!ret && mmc_send_tuning(mmc, opcode, NULL)) {
			if (start >= 0) {
				end = delay - 1;
				/* check and update longest good range */
				if ((end - start) > len) {
					best = (start + end) >> 1;
					len = end - start;
				}
			}
			start = -1;
			end = 0;
			continue;
		}
		if (start < 0)
			start = delay;
	}

	if (start >= 0) {
		end = delay - 1;
		if ((end - start) > len) {
			best = (start + end) >> 1;
			len = end - start;
		}
	}
	if (best < 0)
		return -EIO;

	dev_info(host->dev, "%s best range: start %d end %d\n", __func__,
		 start, end);
	return dw_mci_zx_emmc_set_delay(host, best, DELAY_TYPE_CLK);
}

static int dw_mci_zx_prepare_hs400_tuning(struct dw_mci *host,
					  struct mmc_ios *ios)
{
	int ret;

	/* config phase shift as 90 degree */
	ret = dw_mci_zx_emmc_set_delay(host, 32, DELAY_TYPE_READ);
	if (ret < 0)
		return -EIO;

	return 0;
}

static int dw_mci_zx_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
{
	struct dw_mci *host = slot->host;

	if (host->verid == 0x290a) /* only for emmc */
		return dw_mci_zx_emmc_execute_tuning(slot, opcode);
	/* TODO: Add 0x210a dedicated tuning for sd/sdio */

	return 0;
}

static int dw_mci_zx_parse_dt(struct dw_mci *host)
{
	struct device_node *np = host->dev->of_node;
	struct device_node *node;
	struct dw_mci_zx_priv_data *priv;
	struct regmap *sysc_base;
	int ret;

	/* syscon is needed only by emmc */
	node = of_parse_phandle(np, "zte,aon-syscon", 0);
	if (node) {
		sysc_base = syscon_node_to_regmap(node);
		of_node_put(node);

		if (IS_ERR(sysc_base)) {
			ret = PTR_ERR(sysc_base);
			if (ret != -EPROBE_DEFER)
				dev_err(host->dev, "Can't get syscon: %d\n",
					ret);
			return ret;
		}
	} else {
		return 0;
	}

	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;
	priv->sysc_base = sysc_base;
	host->priv = priv;

	return 0;
}

static unsigned long zx_dwmmc_caps[3] = {
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
};

static const struct dw_mci_drv_data zx_drv_data = {
	.caps			= zx_dwmmc_caps,
	.num_caps		= ARRAY_SIZE(zx_dwmmc_caps),
	.execute_tuning		= dw_mci_zx_execute_tuning,
	.prepare_hs400_tuning	= dw_mci_zx_prepare_hs400_tuning,
	.parse_dt               = dw_mci_zx_parse_dt,
};

static const struct of_device_id dw_mci_zx_match[] = {
	{ .compatible = "zte,zx296718-dw-mshc", .data = &zx_drv_data},
	{},
};
MODULE_DEVICE_TABLE(of, dw_mci_zx_match);

static int dw_mci_zx_probe(struct platform_device *pdev)
{
	const struct dw_mci_drv_data *drv_data;
	const struct of_device_id *match;

	match = of_match_node(dw_mci_zx_match, pdev->dev.of_node);
	drv_data = match->data;

	return dw_mci_pltfm_register(pdev, drv_data);
}

static const struct dev_pm_ops dw_mci_zx_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				pm_runtime_force_resume)
	SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
			   dw_mci_runtime_resume,
			   NULL)
};

static struct platform_driver dw_mci_zx_pltfm_driver = {
	.probe		= dw_mci_zx_probe,
	.remove		= dw_mci_pltfm_remove,
	.driver		= {
		.name		= "dwmmc_zx",
		.of_match_table	= dw_mci_zx_match,
		.pm		= &dw_mci_zx_dev_pm_ops,
	},
};

module_platform_driver(dw_mci_zx_pltfm_driver);

MODULE_DESCRIPTION("ZTE emmc/sd driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
a8c643ad JN	2	/*
	3	* ZX Specific Extensions for Synopsys DW Multimedia Card Interface driver
	4	*
	5	* Copyright (C) 2016, Linaro Ltd.
	6	* Copyright (C) 2016, ZTE Corp.
a8c643ad JN	7	*/
	8
	9	#include <linux/clk.h>
	10	#include <linux/mfd/syscon.h>
	11	#include <linux/mmc/host.h>
	12	#include <linux/mmc/mmc.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/pm_runtime.h>
	17	#include <linux/regmap.h>
	18	#include <linux/slab.h>
	19
	20	#include "dw_mmc.h"
	21	#include "dw_mmc-pltfm.h"
	22	#include "dw_mmc-zx.h"
	23
	24	struct dw_mci_zx_priv_data {
	25	struct regmap *sysc_base;
	26	};
	27
	28	enum delay_type {
	29	DELAY_TYPE_READ, /* read dqs delay */
	30	DELAY_TYPE_CLK, /* clk sample delay */
	31	};
	32
	33	static int dw_mci_zx_emmc_set_delay(struct dw_mci *host, unsigned int delay,
	34	enum delay_type dflag)
	35	{
	36	struct dw_mci_zx_priv_data *priv = host->priv;
	37	struct regmap *sysc_base = priv->sysc_base;
	38	unsigned int clksel;
	39	unsigned int loop = 1000;
	40	int ret;
	41
	42	if (!sysc_base)
	43	return -EINVAL;
	44
	45	ret = regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
	46	PARA_HALF_CLK_MODE \| PARA_DLL_BYPASS_MODE \|
	47	PARA_PHASE_DET_SEL_MASK \|
	48	PARA_DLL_LOCK_NUM_MASK \|
	49	DLL_REG_SET \| PARA_DLL_START_MASK,
	50	PARA_DLL_START(4) \| PARA_DLL_LOCK_NUM(4));
	51	if (ret)
	52	return ret;
	53
	54	ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel);
	55	if (ret)
	56	return ret;
	57
	58	if (dflag == DELAY_TYPE_CLK) {
	59	clksel &= ~CLK_SAMP_DELAY_MASK;
	60	clksel \|= CLK_SAMP_DELAY(delay);
	61	} else {
	62	clksel &= ~READ_DQS_DELAY_MASK;
	63	clksel \|= READ_DQS_DELAY(delay);
	64	}
	65
	66	regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel);
	67	regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
	68	PARA_DLL_START_MASK \| PARA_DLL_LOCK_NUM_MASK \|
	69	DLL_REG_SET,
	70	PARA_DLL_START(4) \| PARA_DLL_LOCK_NUM(4) \|
71	DLL_REG_SET);
72
73	do {
74	ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel);
75	if (ret)
76	return ret;
77
78	} while (--loop && !(clksel & ZX_DLL_LOCKED));
79
80	if (!loop) {
81	dev_err(host->dev, "Error: %s dll lock fail\n", __func__);
82	return -EIO;
83	}
84
85	return 0;
86	}
87
88	static int dw_mci_zx_emmc_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
89	{
90	struct dw_mci *host = slot->host;
91	struct mmc_host *mmc = slot->mmc;
92	int ret, len = 0, start = 0, end = 0, delay, best = 0;
93
94	for (delay = 1; delay < 128; delay++) {
95	ret = dw_mci_zx_emmc_set_delay(host, delay, DELAY_TYPE_CLK);
96	if (!ret && mmc_send_tuning(mmc, opcode, NULL)) {
97	if (start >= 0) {
98	end = delay - 1;
99	/* check and update longest good range */
100	if ((end - start) > len) {
101	best = (start + end) >> 1;
102	len = end - start;
103	}
104	}
105	start = -1;
106	end = 0;
107	continue;
108	}
109	if (start < 0)
110	start = delay;
111	}
112
113	if (start >= 0) {
114	end = delay - 1;
115	if ((end - start) > len) {
116	best = (start + end) >> 1;
117	len = end - start;
118	}
119	}
120	if (best < 0)
121	return -EIO;
122
123	dev_info(host->dev, "%s best range: start %d end %d\n", __func__,
124	start, end);
125	return dw_mci_zx_emmc_set_delay(host, best, DELAY_TYPE_CLK);
126	}
127
128	static int dw_mci_zx_prepare_hs400_tuning(struct dw_mci *host,
129	struct mmc_ios *ios)
130	{
131	int ret;
132
133	/* config phase shift as 90 degree */
134	ret = dw_mci_zx_emmc_set_delay(host, 32, DELAY_TYPE_READ);
135	if (ret < 0)
136	return -EIO;
137
138	return 0;
139	}
140
141	static int dw_mci_zx_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
142	{
143	struct dw_mci *host = slot->host;
144
145	if (host->verid == 0x290a) /* only for emmc */
146	return dw_mci_zx_emmc_execute_tuning(slot, opcode);
147	/* TODO: Add 0x210a dedicated tuning for sd/sdio */
148
149	return 0;
150	}
151
152	static int dw_mci_zx_parse_dt(struct dw_mci *host)
153	{
154	struct device_node *np = host->dev->of_node;
155	struct device_node *node;
156	struct dw_mci_zx_priv_data *priv;
157	struct regmap *sysc_base;
158	int ret;
159
160	/* syscon is needed only by emmc */
161	node = of_parse_phandle(np, "zte,aon-syscon", 0);
162	if (node) {
163	sysc_base = syscon_node_to_regmap(node);
164	of_node_put(node);
165
166	if (IS_ERR(sysc_base)) {
167	ret = PTR_ERR(sysc_base);
168	if (ret != -EPROBE_DEFER)
169	dev_err(host->dev, "Can't get syscon: %d\n",
170	ret);
171	return ret;
172	}
173	} else {
174	return 0;
175	}
176
177	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
178	if (!priv)
179	return -ENOMEM;
180	priv->sysc_base = sysc_base;
181	host->priv = priv;
182
183	return 0;
184	}
185
186	static unsigned long zx_dwmmc_caps[3] = {
187	MMC_CAP_CMD23,
188	MMC_CAP_CMD23,
189	MMC_CAP_CMD23,
190	};
191
192	static const struct dw_mci_drv_data zx_drv_data = {
193	.caps = zx_dwmmc_caps,
0d84b9e5	194	.num_caps = ARRAY_SIZE(zx_dwmmc_caps),
a8c643ad JN	195	.execute_tuning = dw_mci_zx_execute_tuning,
	196	.prepare_hs400_tuning = dw_mci_zx_prepare_hs400_tuning,
	197	.parse_dt = dw_mci_zx_parse_dt,
	198	};
	199
	200	static const struct of_device_id dw_mci_zx_match[] = {
	201	{ .compatible = "zte,zx296718-dw-mshc", .data = &zx_drv_data},
	202	{},
	203	};
	204	MODULE_DEVICE_TABLE(of, dw_mci_zx_match);
	205
	206	static int dw_mci_zx_probe(struct platform_device *pdev)
	207	{
	208	const struct dw_mci_drv_data *drv_data;
	209	const struct of_device_id *match;
	210
	211	match = of_match_node(dw_mci_zx_match, pdev->dev.of_node);
	212	drv_data = match->data;
	213
	214	return dw_mci_pltfm_register(pdev, drv_data);
	215	}
	216
	217	static const struct dev_pm_ops dw_mci_zx_dev_pm_ops = {
	218	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	219	pm_runtime_force_resume)
	220	SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
	221	dw_mci_runtime_resume,
	222	NULL)
	223	};
	224
	225	static struct platform_driver dw_mci_zx_pltfm_driver = {
	226	.probe = dw_mci_zx_probe,
	227	.remove = dw_mci_pltfm_remove,
	228	.driver = {
	229	.name = "dwmmc_zx",
	230	.of_match_table = dw_mci_zx_match,
	231	.pm = &dw_mci_zx_dev_pm_ops,
	232	},
	233	};
	234
	235	module_platform_driver(dw_mci_zx_pltfm_driver);
	236
	237	MODULE_DESCRIPTION("ZTE emmc/sd driver");
	238	MODULE_LICENSE("GPL v2");