[linux-2.6-block.git] / drivers / mmc / host / dw_mmc-exynos.c

/*
 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
 *
 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/mmc/host.h>
#include <linux/mmc/dw_mmc.h>
#include <linux/of.h>
#include <linux/of_gpio.h>

#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"

#define NUM_PINS(x)			(x + 2)

#define SDMMC_CLKSEL			0x09C
#define SDMMC_CLKSEL_CCLK_SAMPLE(x)	(((x) & 7) << 0)
#define SDMMC_CLKSEL_CCLK_DRIVE(x)	(((x) & 7) << 16)
#define SDMMC_CLKSEL_CCLK_DIVIDER(x)	(((x) & 7) << 24)
#define SDMMC_CLKSEL_GET_DRV_WD3(x)	(((x) >> 16) & 0x7)
#define SDMMC_CLKSEL_TIMING(x, y, z)	(SDMMC_CLKSEL_CCLK_SAMPLE(x) |	\
					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\
					SDMMC_CLKSEL_CCLK_DIVIDER(z))
#define SDMMC_CLKSEL_WAKEUP_INT		BIT(11)

#define EXYNOS4210_FIXED_CIU_CLK_DIV	2
#define EXYNOS4412_FIXED_CIU_CLK_DIV	4

/* Variations in Exynos specific dw-mshc controller */
enum dw_mci_exynos_type {
	DW_MCI_TYPE_EXYNOS4210,
	DW_MCI_TYPE_EXYNOS4412,
	DW_MCI_TYPE_EXYNOS5250,
	DW_MCI_TYPE_EXYNOS5420,
};

/* Exynos implementation specific driver private data */
struct dw_mci_exynos_priv_data {
	enum dw_mci_exynos_type		ctrl_type;
	u8				ciu_div;
	u32				sdr_timing;
	u32				ddr_timing;
};

static struct dw_mci_exynos_compatible {
	char				*compatible;
	enum dw_mci_exynos_type		ctrl_type;
} exynos_compat[] = {
	{
		.compatible	= "samsung,exynos4210-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4210,
	}, {
		.compatible	= "samsung,exynos4412-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4412,
	}, {
		.compatible	= "samsung,exynos5250-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5250,
	}, {
		.compatible	= "samsung,exynos5420-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420,
	},
};

static int dw_mci_exynos_priv_init(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	return 0;
}

static int dw_mci_exynos_setup_clock(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420)
		host->bus_hz /= (priv->ciu_div + 1);
	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
		host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
		host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int dw_mci_exynos_suspend(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	return dw_mci_suspend(host);
}

static int dw_mci_exynos_resume(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	return dw_mci_resume(host);
}

/**
 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
 *
 * On exynos5420 there is a silicon errata that will sometimes leave the
 * WAKEUP_INT bit in the CLKSEL register asserted.  This bit is 1 to indicate
 * that it fired and we can clear it by writing a 1 back.  Clear it to prevent
 * interrupts from going off constantly.
 *
 * We run this code on all exynos variants because it doesn't hurt.
 */

static int dw_mci_exynos_resume_noirq(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);
	u32 clksel;

	clksel = mci_readl(host, CLKSEL);
	if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
		mci_writel(host, CLKSEL, clksel);

	return 0;
}
#else
#define dw_mci_exynos_suspend		NULL
#define dw_mci_exynos_resume		NULL
#define dw_mci_exynos_resume_noirq	NULL
#endif /* CONFIG_PM_SLEEP */

static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
{
	/*
	 * Exynos4412 and Exynos5250 extends the use of CMD register with the
	 * use of bit 29 (which is reserved on standard MSHC controllers) for
	 * optionally bypassing the HOLD register for command and data. The
	 * HOLD register should be bypassed in case there is no phase shift
	 * applied on CMD/DATA that is sent to the card.
	 */
	if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
}

static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (ios->timing == MMC_TIMING_UHS_DDR50)
		mci_writel(host, CLKSEL, priv->ddr_timing);
	else
		mci_writel(host, CLKSEL, priv->sdr_timing);
}

static int dw_mci_exynos_parse_dt(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv;
	struct device_node *np = host->dev->of_node;
	u32 timing[2];
	u32 div = 0;
	int idx;
	int ret;

	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(host->dev, "mem alloc failed for private data\n");
		return -ENOMEM;
	}

	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
		if (of_device_is_compatible(np, exynos_compat[idx].compatible))
			priv->ctrl_type = exynos_compat[idx].ctrl_type;
	}

	of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
	priv->ciu_div = div;

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-sdr-timing", timing, 2);
	if (ret)
		return ret;

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-ddr-timing", timing, 2);
	if (ret)
		return ret;

	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
	host->priv = priv;
	return 0;
}

/* Common capabilities of Exynos4/Exynos5 SoC */
static unsigned long exynos_dwmmc_caps[4] = {
	MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
		MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
};

static const struct dw_mci_drv_data exynos_drv_data = {
	.caps			= exynos_dwmmc_caps,
	.init			= dw_mci_exynos_priv_init,
	.setup_clock		= dw_mci_exynos_setup_clock,
	.prepare_command	= dw_mci_exynos_prepare_command,
	.set_ios		= dw_mci_exynos_set_ios,
	.parse_dt		= dw_mci_exynos_parse_dt,
};

static const struct of_device_id dw_mci_exynos_match[] = {
	{ .compatible = "samsung,exynos4412-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5250-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5420-dw-mshc",
			.data = &exynos_drv_data, },
	{},
};
MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);

static int dw_mci_exynos_probe(struct platform_device *pdev)
{
	const struct dw_mci_drv_data *drv_data;
	const struct of_device_id *match;

	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	drv_data = match->data;
	return dw_mci_pltfm_register(pdev, drv_data);
}

const struct dev_pm_ops dw_mci_exynos_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	.resume_noirq = dw_mci_exynos_resume_noirq,
	.thaw_noirq = dw_mci_exynos_resume_noirq,
	.restore_noirq = dw_mci_exynos_resume_noirq,
};

static struct platform_driver dw_mci_exynos_pltfm_driver = {
	.probe		= dw_mci_exynos_probe,
	.remove		= __exit_p(dw_mci_pltfm_remove),
	.driver		= {
		.name		= "dwmmc_exynos",
		.of_match_table	= dw_mci_exynos_match,
		.pm		= &dw_mci_exynos_pmops,
	},
};

module_platform_driver(dw_mci_exynos_pltfm_driver);

MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dwmmc-exynos");
Commit	Line	Data
c3665006 TA	1	/*
	2	* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
	3	*
	4	* Copyright (C) 2012, Samsung Electronics Co., Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/clk.h>
	15	#include <linux/mmc/host.h>
	16	#include <linux/mmc/dw_mmc.h>
	17	#include <linux/of.h>
	18	#include <linux/of_gpio.h>
	19
	20	#include "dw_mmc.h"
	21	#include "dw_mmc-pltfm.h"
	22
	23	#define NUM_PINS(x) (x + 2)
	24
	25	#define SDMMC_CLKSEL 0x09C
	26	#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
	27	#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
	28	#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
	29	#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
	30	#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) \| \
	31	SDMMC_CLKSEL_CCLK_DRIVE(y) \| \
	32	SDMMC_CLKSEL_CCLK_DIVIDER(z))
e2c63599	33	#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
c3665006	34
c3665006 TA	35	#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
	36	#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
	37
	38	/* Variations in Exynos specific dw-mshc controller */
	39	enum dw_mci_exynos_type {
	40	DW_MCI_TYPE_EXYNOS4210,
	41	DW_MCI_TYPE_EXYNOS4412,
	42	DW_MCI_TYPE_EXYNOS5250,
00fd041b	43	DW_MCI_TYPE_EXYNOS5420,
c3665006 TA	44	};
	45
	46	/* Exynos implementation specific driver private data */
	47	struct dw_mci_exynos_priv_data {
	48	enum dw_mci_exynos_type ctrl_type;
	49	u8 ciu_div;
	50	u32 sdr_timing;
	51	u32 ddr_timing;
	52	};
	53
	54	static struct dw_mci_exynos_compatible {
	55	char *compatible;
	56	enum dw_mci_exynos_type ctrl_type;
	57	} exynos_compat[] = {
	58	{
	59	.compatible = "samsung,exynos4210-dw-mshc",
	60	.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
	61	}, {
	62	.compatible = "samsung,exynos4412-dw-mshc",
	63	.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
	64	}, {
	65	.compatible = "samsung,exynos5250-dw-mshc",
	66	.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
00fd041b YK	67	}, {
	68	.compatible = "samsung,exynos5420-dw-mshc",
	69	.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
c3665006 TA	70	},
	71	};
	72
	73	static int dw_mci_exynos_priv_init(struct dw_mci *host)
	74	{
e6c784ed	75	struct dw_mci_exynos_priv_data *priv = host->priv;
c3665006	76
c3665006 TA	77	return 0;
	78	}
	79
	80	static int dw_mci_exynos_setup_clock(struct dw_mci *host)
	81	{
	82	struct dw_mci_exynos_priv_data *priv = host->priv;
	83
00fd041b YK	84	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 \|\|
00fd041b YK	85	priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420)
c3665006 TA	86	host->bus_hz /= (priv->ciu_div + 1);
	87	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
	88	host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
	89	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
	90	host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
	91
	92	return 0;
	93	}
	94
e2c63599 DA	95	#ifdef CONFIG_PM_SLEEP
	96	static int dw_mci_exynos_suspend(struct device *dev)
	97	{
	98	struct dw_mci *host = dev_get_drvdata(dev);
	99
	100	return dw_mci_suspend(host);
	101	}
	102
	103	static int dw_mci_exynos_resume(struct device *dev)
	104	{
	105	struct dw_mci *host = dev_get_drvdata(dev);
	106
	107	return dw_mci_resume(host);
	108	}
	109
	110	/**
	111	* dw_mci_exynos_resume_noirq - Exynos-specific resume code
	112	*
	113	* On exynos5420 there is a silicon errata that will sometimes leave the
	114	* WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
	115	* that it fired and we can clear it by writing a 1 back. Clear it to prevent
	116	* interrupts from going off constantly.
	117	*
	118	* We run this code on all exynos variants because it doesn't hurt.
	119	*/
	120
	121	static int dw_mci_exynos_resume_noirq(struct device *dev)
	122	{
	123	struct dw_mci *host = dev_get_drvdata(dev);
	124	u32 clksel;
	125
	126	clksel = mci_readl(host, CLKSEL);
	127	if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
	128	mci_writel(host, CLKSEL, clksel);
	129
	130	return 0;
	131	}
	132	#else
	133	#define dw_mci_exynos_suspend NULL
	134	#define dw_mci_exynos_resume NULL
	135	#define dw_mci_exynos_resume_noirq NULL
	136	#endif /* CONFIG_PM_SLEEP */
	137
c3665006 TA	138	static void dw_mci_exynos_prepare_command(struct dw_mci host, u32 cmdr)
	139	{
	140	/*
	141	* Exynos4412 and Exynos5250 extends the use of CMD register with the
	142	* use of bit 29 (which is reserved on standard MSHC controllers) for
	143	* optionally bypassing the HOLD register for command and data. The
	144	* HOLD register should be bypassed in case there is no phase shift
	145	* applied on CMD/DATA that is sent to the card.
	146	*/
	147	if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
	148	*cmdr \|= SDMMC_CMD_USE_HOLD_REG;
	149	}
	150
	151	static void dw_mci_exynos_set_ios(struct dw_mci host, struct mmc_ios ios)
	152	{
	153	struct dw_mci_exynos_priv_data *priv = host->priv;
	154
	155	if (ios->timing == MMC_TIMING_UHS_DDR50)
	156	mci_writel(host, CLKSEL, priv->ddr_timing);
	157	else
	158	mci_writel(host, CLKSEL, priv->sdr_timing);
	159	}
	160
	161	static int dw_mci_exynos_parse_dt(struct dw_mci *host)
	162	{
e6c784ed	163	struct dw_mci_exynos_priv_data *priv;
c3665006 TA	164	struct device_node *np = host->dev->of_node;
	165	u32 timing[2];
	166	u32 div = 0;
e6c784ed	167	int idx;
c3665006 TA	168	int ret;
c3665006 TA	169
e6c784ed YK	170	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	171	if (!priv) {
	172	dev_err(host->dev, "mem alloc failed for private data\n");
	173	return -ENOMEM;
	174	}
	175
	176	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
	177	if (of_device_is_compatible(np, exynos_compat[idx].compatible))
	178	priv->ctrl_type = exynos_compat[idx].ctrl_type;
	179	}
	180
c3665006 TA	181	of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
	182	priv->ciu_div = div;
	183
	184	ret = of_property_read_u32_array(np,
	185	"samsung,dw-mshc-sdr-timing", timing, 2);
	186	if (ret)
	187	return ret;
	188
c3665006 TA	189	ret = of_property_read_u32_array(np,
	190	"samsung,dw-mshc-ddr-timing", timing, 2);
	191	if (ret)
	192	return ret;
	193
e6c784ed	194	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
c3665006	195	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
e6c784ed	196	host->priv = priv;
c3665006 TA	197	return 0;
	198	}
	199
0f6e73d0 DK	200	/* Common capabilities of Exynos4/Exynos5 SoC */
0f6e73d0 DK	201	static unsigned long exynos_dwmmc_caps[4] = {
c3665006 TA	202	MMC_CAP_UHS_DDR50 \| MMC_CAP_1_8V_DDR \|
	203	MMC_CAP_8_BIT_DATA \| MMC_CAP_CMD23,
	204	MMC_CAP_CMD23,
	205	MMC_CAP_CMD23,
	206	MMC_CAP_CMD23,
	207	};
	208
0f6e73d0 DK	209	static const struct dw_mci_drv_data exynos_drv_data = {
0f6e73d0 DK	210	.caps = exynos_dwmmc_caps,
c3665006 TA	211	.init = dw_mci_exynos_priv_init,
	212	.setup_clock = dw_mci_exynos_setup_clock,
	213	.prepare_command = dw_mci_exynos_prepare_command,
	214	.set_ios = dw_mci_exynos_set_ios,
	215	.parse_dt = dw_mci_exynos_parse_dt,
c3665006 TA	216	};
	217
	218	static const struct of_device_id dw_mci_exynos_match[] = {
0f6e73d0 DK	219	{ .compatible = "samsung,exynos4412-dw-mshc",
0f6e73d0 DK	220	.data = &exynos_drv_data, },
c3665006	221	{ .compatible = "samsung,exynos5250-dw-mshc",
0f6e73d0	222	.data = &exynos_drv_data, },
00fd041b YK	223	{ .compatible = "samsung,exynos5420-dw-mshc",
00fd041b YK	224	.data = &exynos_drv_data, },
c3665006 TA	225	{},
c3665006 TA	226	};
517cb9f1	227	MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
c3665006	228
9665f7f2	229	static int dw_mci_exynos_probe(struct platform_device *pdev)
c3665006	230	{
8e2b36ea	231	const struct dw_mci_drv_data *drv_data;
c3665006 TA	232	const struct of_device_id *match;
	233
	234	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	235	drv_data = match->data;
	236	return dw_mci_pltfm_register(pdev, drv_data);
	237	}
	238
e2c63599 DA	239	const struct dev_pm_ops dw_mci_exynos_pmops = {
	240	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	241	.resume_noirq = dw_mci_exynos_resume_noirq,
	242	.thaw_noirq = dw_mci_exynos_resume_noirq,
	243	.restore_noirq = dw_mci_exynos_resume_noirq,
	244	};
	245
c3665006 TA	246	static struct platform_driver dw_mci_exynos_pltfm_driver = {
	247	.probe = dw_mci_exynos_probe,
	248	.remove = __exit_p(dw_mci_pltfm_remove),
	249	.driver = {
	250	.name = "dwmmc_exynos",
20183d50	251	.of_match_table = dw_mci_exynos_match,
e2c63599	252	.pm = &dw_mci_exynos_pmops,
c3665006 TA	253	},
	254	};
	255
	256	module_platform_driver(dw_mci_exynos_pltfm_driver);
	257
	258	MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
	259	MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
	260	MODULE_LICENSE("GPL v2");
	261	MODULE_ALIAS("platform:dwmmc-exynos");