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b4cff454 VB |
1 | /* |
2 | * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver | |
3 | * | |
4 | * Copyright (C) 2006 Texas Instruments. | |
5 | * Original author: Purushotam Kumar | |
6 | * Copyright (C) 2009 David Brownell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/mmc/host.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/mmc/mmc.h> | |
34 | ||
35 | #include <mach/mmc.h> | |
36 | #include <mach/edma.h> | |
37 | ||
38 | /* | |
39 | * Register Definitions | |
40 | */ | |
41 | #define DAVINCI_MMCCTL 0x00 /* Control Register */ | |
42 | #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ | |
43 | #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ | |
44 | #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ | |
45 | #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ | |
46 | #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ | |
47 | #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ | |
48 | #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ | |
49 | #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ | |
50 | #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ | |
51 | #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ | |
52 | #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ | |
53 | #define DAVINCI_MMCCMD 0x30 /* Command Register */ | |
54 | #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ | |
55 | #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ | |
56 | #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ | |
57 | #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ | |
58 | #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ | |
59 | #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ | |
60 | #define DAVINCI_MMCETOK 0x4C | |
61 | #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ | |
62 | #define DAVINCI_MMCCKC 0x54 | |
63 | #define DAVINCI_MMCTORC 0x58 | |
64 | #define DAVINCI_MMCTODC 0x5C | |
65 | #define DAVINCI_MMCBLNC 0x60 | |
66 | #define DAVINCI_SDIOCTL 0x64 | |
67 | #define DAVINCI_SDIOST0 0x68 | |
68 | #define DAVINCI_SDIOEN 0x6C | |
69 | #define DAVINCI_SDIOST 0x70 | |
70 | #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ | |
71 | ||
72 | /* DAVINCI_MMCCTL definitions */ | |
73 | #define MMCCTL_DATRST (1 << 0) | |
74 | #define MMCCTL_CMDRST (1 << 1) | |
75 | #define MMCCTL_WIDTH_4_BIT (1 << 2) | |
76 | #define MMCCTL_DATEG_DISABLED (0 << 6) | |
77 | #define MMCCTL_DATEG_RISING (1 << 6) | |
78 | #define MMCCTL_DATEG_FALLING (2 << 6) | |
79 | #define MMCCTL_DATEG_BOTH (3 << 6) | |
80 | #define MMCCTL_PERMDR_LE (0 << 9) | |
81 | #define MMCCTL_PERMDR_BE (1 << 9) | |
82 | #define MMCCTL_PERMDX_LE (0 << 10) | |
83 | #define MMCCTL_PERMDX_BE (1 << 10) | |
84 | ||
85 | /* DAVINCI_MMCCLK definitions */ | |
86 | #define MMCCLK_CLKEN (1 << 8) | |
87 | #define MMCCLK_CLKRT_MASK (0xFF << 0) | |
88 | ||
89 | /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ | |
90 | #define MMCST0_DATDNE BIT(0) /* data done */ | |
91 | #define MMCST0_BSYDNE BIT(1) /* busy done */ | |
92 | #define MMCST0_RSPDNE BIT(2) /* command done */ | |
93 | #define MMCST0_TOUTRD BIT(3) /* data read timeout */ | |
94 | #define MMCST0_TOUTRS BIT(4) /* command response timeout */ | |
95 | #define MMCST0_CRCWR BIT(5) /* data write CRC error */ | |
96 | #define MMCST0_CRCRD BIT(6) /* data read CRC error */ | |
97 | #define MMCST0_CRCRS BIT(7) /* command response CRC error */ | |
98 | #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ | |
99 | #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ | |
100 | #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ | |
101 | #define MMCST0_TRNDNE BIT(12) /* transfer done */ | |
102 | ||
103 | /* DAVINCI_MMCST1 definitions */ | |
104 | #define MMCST1_BUSY (1 << 0) | |
105 | ||
106 | /* DAVINCI_MMCCMD definitions */ | |
107 | #define MMCCMD_CMD_MASK (0x3F << 0) | |
108 | #define MMCCMD_PPLEN (1 << 7) | |
109 | #define MMCCMD_BSYEXP (1 << 8) | |
110 | #define MMCCMD_RSPFMT_MASK (3 << 9) | |
111 | #define MMCCMD_RSPFMT_NONE (0 << 9) | |
112 | #define MMCCMD_RSPFMT_R1456 (1 << 9) | |
113 | #define MMCCMD_RSPFMT_R2 (2 << 9) | |
114 | #define MMCCMD_RSPFMT_R3 (3 << 9) | |
115 | #define MMCCMD_DTRW (1 << 11) | |
116 | #define MMCCMD_STRMTP (1 << 12) | |
117 | #define MMCCMD_WDATX (1 << 13) | |
118 | #define MMCCMD_INITCK (1 << 14) | |
119 | #define MMCCMD_DCLR (1 << 15) | |
120 | #define MMCCMD_DMATRIG (1 << 16) | |
121 | ||
122 | /* DAVINCI_MMCFIFOCTL definitions */ | |
123 | #define MMCFIFOCTL_FIFORST (1 << 0) | |
124 | #define MMCFIFOCTL_FIFODIR_WR (1 << 1) | |
125 | #define MMCFIFOCTL_FIFODIR_RD (0 << 1) | |
126 | #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ | |
127 | #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ | |
128 | #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ | |
129 | #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ | |
130 | #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ | |
131 | ||
132 | ||
133 | /* MMCSD Init clock in Hz in opendrain mode */ | |
134 | #define MMCSD_INIT_CLOCK 200000 | |
135 | ||
136 | /* | |
137 | * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, | |
138 | * and we handle up to NR_SG segments. MMC_BLOCK_BOUNCE kicks in only | |
139 | * for drivers with max_hw_segs == 1, making the segments bigger (64KB) | |
140 | * than the page or two that's otherwise typical. NR_SG == 16 gives at | |
141 | * least the same throughput boost, using EDMA transfer linkage instead | |
142 | * of spending CPU time copying pages. | |
143 | */ | |
144 | #define MAX_CCNT ((1 << 16) - 1) | |
145 | ||
146 | #define NR_SG 16 | |
147 | ||
148 | static unsigned rw_threshold = 32; | |
149 | module_param(rw_threshold, uint, S_IRUGO); | |
150 | MODULE_PARM_DESC(rw_threshold, | |
151 | "Read/Write threshold. Default = 32"); | |
152 | ||
153 | static unsigned __initdata use_dma = 1; | |
154 | module_param(use_dma, uint, 0); | |
155 | MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); | |
156 | ||
157 | struct mmc_davinci_host { | |
158 | struct mmc_command *cmd; | |
159 | struct mmc_data *data; | |
160 | struct mmc_host *mmc; | |
161 | struct clk *clk; | |
162 | unsigned int mmc_input_clk; | |
163 | void __iomem *base; | |
164 | struct resource *mem_res; | |
165 | int irq; | |
166 | unsigned char bus_mode; | |
167 | ||
168 | #define DAVINCI_MMC_DATADIR_NONE 0 | |
169 | #define DAVINCI_MMC_DATADIR_READ 1 | |
170 | #define DAVINCI_MMC_DATADIR_WRITE 2 | |
171 | unsigned char data_dir; | |
172 | ||
173 | /* buffer is used during PIO of one scatterlist segment, and | |
174 | * is updated along with buffer_bytes_left. bytes_left applies | |
175 | * to all N blocks of the PIO transfer. | |
176 | */ | |
177 | u8 *buffer; | |
178 | u32 buffer_bytes_left; | |
179 | u32 bytes_left; | |
180 | ||
3d348aaf | 181 | u32 rxdma, txdma; |
b4cff454 VB |
182 | bool use_dma; |
183 | bool do_dma; | |
184 | ||
185 | /* Scatterlist DMA uses one or more parameter RAM entries: | |
186 | * the main one (associated with rxdma or txdma) plus zero or | |
187 | * more links. The entries for a given transfer differ only | |
188 | * by memory buffer (address, length) and link field. | |
189 | */ | |
190 | struct edmacc_param tx_template; | |
191 | struct edmacc_param rx_template; | |
192 | unsigned n_link; | |
3d348aaf | 193 | u32 links[NR_SG - 1]; |
b4cff454 VB |
194 | |
195 | /* For PIO we walk scatterlists one segment at a time. */ | |
196 | unsigned int sg_len; | |
197 | struct scatterlist *sg; | |
198 | ||
199 | /* Version of the MMC/SD controller */ | |
200 | u8 version; | |
201 | /* for ns in one cycle calculation */ | |
202 | unsigned ns_in_one_cycle; | |
203 | }; | |
204 | ||
205 | ||
206 | /* PIO only */ | |
207 | static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) | |
208 | { | |
209 | host->buffer_bytes_left = sg_dma_len(host->sg); | |
210 | host->buffer = sg_virt(host->sg); | |
211 | if (host->buffer_bytes_left > host->bytes_left) | |
212 | host->buffer_bytes_left = host->bytes_left; | |
213 | } | |
214 | ||
215 | static void davinci_fifo_data_trans(struct mmc_davinci_host *host, | |
216 | unsigned int n) | |
217 | { | |
218 | u8 *p; | |
219 | unsigned int i; | |
220 | ||
221 | if (host->buffer_bytes_left == 0) { | |
222 | host->sg = sg_next(host->data->sg); | |
223 | mmc_davinci_sg_to_buf(host); | |
224 | } | |
225 | ||
226 | p = host->buffer; | |
227 | if (n > host->buffer_bytes_left) | |
228 | n = host->buffer_bytes_left; | |
229 | host->buffer_bytes_left -= n; | |
230 | host->bytes_left -= n; | |
231 | ||
232 | /* NOTE: we never transfer more than rw_threshold bytes | |
233 | * to/from the fifo here; there's no I/O overlap. | |
234 | * This also assumes that access width( i.e. ACCWD) is 4 bytes | |
235 | */ | |
236 | if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { | |
237 | for (i = 0; i < (n >> 2); i++) { | |
238 | writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); | |
239 | p = p + 4; | |
240 | } | |
241 | if (n & 3) { | |
242 | iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); | |
243 | p = p + (n & 3); | |
244 | } | |
245 | } else { | |
246 | for (i = 0; i < (n >> 2); i++) { | |
247 | *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); | |
248 | p = p + 4; | |
249 | } | |
250 | if (n & 3) { | |
251 | ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); | |
252 | p = p + (n & 3); | |
253 | } | |
254 | } | |
255 | host->buffer = p; | |
256 | } | |
257 | ||
258 | static void mmc_davinci_start_command(struct mmc_davinci_host *host, | |
259 | struct mmc_command *cmd) | |
260 | { | |
261 | u32 cmd_reg = 0; | |
262 | u32 im_val; | |
263 | ||
264 | dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", | |
265 | cmd->opcode, cmd->arg, | |
266 | ({ char *s; | |
267 | switch (mmc_resp_type(cmd)) { | |
268 | case MMC_RSP_R1: | |
269 | s = ", R1/R5/R6/R7 response"; | |
270 | break; | |
271 | case MMC_RSP_R1B: | |
272 | s = ", R1b response"; | |
273 | break; | |
274 | case MMC_RSP_R2: | |
275 | s = ", R2 response"; | |
276 | break; | |
277 | case MMC_RSP_R3: | |
278 | s = ", R3/R4 response"; | |
279 | break; | |
280 | default: | |
281 | s = ", (R? response)"; | |
282 | break; | |
283 | }; s; })); | |
284 | host->cmd = cmd; | |
285 | ||
286 | switch (mmc_resp_type(cmd)) { | |
287 | case MMC_RSP_R1B: | |
288 | /* There's some spec confusion about when R1B is | |
289 | * allowed, but if the card doesn't issue a BUSY | |
290 | * then it's harmless for us to allow it. | |
291 | */ | |
292 | cmd_reg |= MMCCMD_BSYEXP; | |
293 | /* FALLTHROUGH */ | |
294 | case MMC_RSP_R1: /* 48 bits, CRC */ | |
295 | cmd_reg |= MMCCMD_RSPFMT_R1456; | |
296 | break; | |
297 | case MMC_RSP_R2: /* 136 bits, CRC */ | |
298 | cmd_reg |= MMCCMD_RSPFMT_R2; | |
299 | break; | |
300 | case MMC_RSP_R3: /* 48 bits, no CRC */ | |
301 | cmd_reg |= MMCCMD_RSPFMT_R3; | |
302 | break; | |
303 | default: | |
304 | cmd_reg |= MMCCMD_RSPFMT_NONE; | |
305 | dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", | |
306 | mmc_resp_type(cmd)); | |
307 | break; | |
308 | } | |
309 | ||
310 | /* Set command index */ | |
311 | cmd_reg |= cmd->opcode; | |
312 | ||
313 | /* Enable EDMA transfer triggers */ | |
314 | if (host->do_dma) | |
315 | cmd_reg |= MMCCMD_DMATRIG; | |
316 | ||
317 | if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && | |
318 | host->data_dir == DAVINCI_MMC_DATADIR_READ) | |
319 | cmd_reg |= MMCCMD_DMATRIG; | |
320 | ||
321 | /* Setting whether command involves data transfer or not */ | |
322 | if (cmd->data) | |
323 | cmd_reg |= MMCCMD_WDATX; | |
324 | ||
325 | /* Setting whether stream or block transfer */ | |
326 | if (cmd->flags & MMC_DATA_STREAM) | |
327 | cmd_reg |= MMCCMD_STRMTP; | |
328 | ||
329 | /* Setting whether data read or write */ | |
330 | if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) | |
331 | cmd_reg |= MMCCMD_DTRW; | |
332 | ||
333 | if (host->bus_mode == MMC_BUSMODE_PUSHPULL) | |
334 | cmd_reg |= MMCCMD_PPLEN; | |
335 | ||
336 | /* set Command timeout */ | |
337 | writel(0x1FFF, host->base + DAVINCI_MMCTOR); | |
338 | ||
339 | /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ | |
340 | im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; | |
341 | if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { | |
342 | im_val |= MMCST0_DATDNE | MMCST0_CRCWR; | |
343 | ||
344 | if (!host->do_dma) | |
345 | im_val |= MMCST0_DXRDY; | |
346 | } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { | |
347 | im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; | |
348 | ||
349 | if (!host->do_dma) | |
350 | im_val |= MMCST0_DRRDY; | |
351 | } | |
352 | ||
353 | /* | |
354 | * Before non-DMA WRITE commands the controller needs priming: | |
355 | * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size | |
356 | */ | |
357 | if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) | |
358 | davinci_fifo_data_trans(host, rw_threshold); | |
359 | ||
360 | writel(cmd->arg, host->base + DAVINCI_MMCARGHL); | |
361 | writel(cmd_reg, host->base + DAVINCI_MMCCMD); | |
362 | writel(im_val, host->base + DAVINCI_MMCIM); | |
363 | } | |
364 | ||
365 | /*----------------------------------------------------------------------*/ | |
366 | ||
367 | /* DMA infrastructure */ | |
368 | ||
369 | static void davinci_abort_dma(struct mmc_davinci_host *host) | |
370 | { | |
371 | int sync_dev; | |
372 | ||
373 | if (host->data_dir == DAVINCI_MMC_DATADIR_READ) | |
374 | sync_dev = host->rxdma; | |
375 | else | |
376 | sync_dev = host->txdma; | |
377 | ||
378 | edma_stop(sync_dev); | |
379 | edma_clean_channel(sync_dev); | |
380 | } | |
381 | ||
382 | static void | |
383 | mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data); | |
384 | ||
385 | static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data) | |
386 | { | |
387 | if (DMA_COMPLETE != ch_status) { | |
388 | struct mmc_davinci_host *host = data; | |
389 | ||
390 | /* Currently means: DMA Event Missed, or "null" transfer | |
391 | * request was seen. In the future, TC errors (like bad | |
392 | * addresses) might be presented too. | |
393 | */ | |
394 | dev_warn(mmc_dev(host->mmc), "DMA %s error\n", | |
395 | (host->data->flags & MMC_DATA_WRITE) | |
396 | ? "write" : "read"); | |
397 | host->data->error = -EIO; | |
398 | mmc_davinci_xfer_done(host, host->data); | |
399 | } | |
400 | } | |
401 | ||
402 | /* Set up tx or rx template, to be modified and updated later */ | |
403 | static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host, | |
404 | bool tx, struct edmacc_param *template) | |
405 | { | |
406 | unsigned sync_dev; | |
407 | const u16 acnt = 4; | |
408 | const u16 bcnt = rw_threshold >> 2; | |
409 | const u16 ccnt = 0; | |
410 | u32 src_port = 0; | |
411 | u32 dst_port = 0; | |
412 | s16 src_bidx, dst_bidx; | |
413 | s16 src_cidx, dst_cidx; | |
414 | ||
415 | /* | |
416 | * A-B Sync transfer: each DMA request is for one "frame" of | |
417 | * rw_threshold bytes, broken into "acnt"-size chunks repeated | |
418 | * "bcnt" times. Each segment needs "ccnt" such frames; since | |
419 | * we tell the block layer our mmc->max_seg_size limit, we can | |
420 | * trust (later) that it's within bounds. | |
421 | * | |
422 | * The FIFOs are read/written in 4-byte chunks (acnt == 4) and | |
423 | * EDMA will optimize memory operations to use larger bursts. | |
424 | */ | |
425 | if (tx) { | |
426 | sync_dev = host->txdma; | |
427 | ||
428 | /* src_prt, ccnt, and link to be set up later */ | |
429 | src_bidx = acnt; | |
430 | src_cidx = acnt * bcnt; | |
431 | ||
432 | dst_port = host->mem_res->start + DAVINCI_MMCDXR; | |
433 | dst_bidx = 0; | |
434 | dst_cidx = 0; | |
435 | } else { | |
436 | sync_dev = host->rxdma; | |
437 | ||
438 | src_port = host->mem_res->start + DAVINCI_MMCDRR; | |
439 | src_bidx = 0; | |
440 | src_cidx = 0; | |
441 | ||
442 | /* dst_prt, ccnt, and link to be set up later */ | |
443 | dst_bidx = acnt; | |
444 | dst_cidx = acnt * bcnt; | |
445 | } | |
446 | ||
447 | /* | |
448 | * We can't use FIFO mode for the FIFOs because MMC FIFO addresses | |
449 | * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT | |
450 | * parameter is ignored. | |
451 | */ | |
452 | edma_set_src(sync_dev, src_port, INCR, W8BIT); | |
453 | edma_set_dest(sync_dev, dst_port, INCR, W8BIT); | |
454 | ||
455 | edma_set_src_index(sync_dev, src_bidx, src_cidx); | |
456 | edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); | |
457 | ||
458 | edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); | |
459 | ||
460 | edma_read_slot(sync_dev, template); | |
461 | ||
462 | /* don't bother with irqs or chaining */ | |
463 | template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; | |
464 | } | |
465 | ||
466 | static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host, | |
467 | struct mmc_data *data) | |
468 | { | |
469 | struct edmacc_param *template; | |
470 | int channel, slot; | |
471 | unsigned link; | |
472 | struct scatterlist *sg; | |
473 | unsigned sg_len; | |
474 | unsigned bytes_left = host->bytes_left; | |
475 | const unsigned shift = ffs(rw_threshold) - 1;; | |
476 | ||
477 | if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { | |
478 | template = &host->tx_template; | |
479 | channel = host->txdma; | |
480 | } else { | |
481 | template = &host->rx_template; | |
482 | channel = host->rxdma; | |
483 | } | |
484 | ||
485 | /* We know sg_len and ccnt will never be out of range because | |
486 | * we told the mmc layer which in turn tells the block layer | |
487 | * to ensure that it only hands us one scatterlist segment | |
488 | * per EDMA PARAM entry. Update the PARAM | |
489 | * entries needed for each segment of this scatterlist. | |
490 | */ | |
491 | for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len; | |
492 | sg_len-- != 0 && bytes_left; | |
493 | sg = sg_next(sg), slot = host->links[link++]) { | |
494 | u32 buf = sg_dma_address(sg); | |
495 | unsigned count = sg_dma_len(sg); | |
496 | ||
497 | template->link_bcntrld = sg_len | |
498 | ? (EDMA_CHAN_SLOT(host->links[link]) << 5) | |
499 | : 0xffff; | |
500 | ||
501 | if (count > bytes_left) | |
502 | count = bytes_left; | |
503 | bytes_left -= count; | |
504 | ||
505 | if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) | |
506 | template->src = buf; | |
507 | else | |
508 | template->dst = buf; | |
509 | template->ccnt = count >> shift; | |
510 | ||
511 | edma_write_slot(slot, template); | |
512 | } | |
513 | ||
514 | if (host->version == MMC_CTLR_VERSION_2) | |
515 | edma_clear_event(channel); | |
516 | ||
517 | edma_start(channel); | |
518 | } | |
519 | ||
520 | static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, | |
521 | struct mmc_data *data) | |
522 | { | |
523 | int i; | |
524 | int mask = rw_threshold - 1; | |
525 | ||
526 | host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
527 | ((data->flags & MMC_DATA_WRITE) | |
528 | ? DMA_TO_DEVICE | |
529 | : DMA_FROM_DEVICE)); | |
530 | ||
531 | /* no individual DMA segment should need a partial FIFO */ | |
532 | for (i = 0; i < host->sg_len; i++) { | |
533 | if (sg_dma_len(data->sg + i) & mask) { | |
534 | dma_unmap_sg(mmc_dev(host->mmc), | |
535 | data->sg, data->sg_len, | |
536 | (data->flags & MMC_DATA_WRITE) | |
537 | ? DMA_TO_DEVICE | |
538 | : DMA_FROM_DEVICE); | |
539 | return -1; | |
540 | } | |
541 | } | |
542 | ||
543 | host->do_dma = 1; | |
544 | mmc_davinci_send_dma_request(host, data); | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
549 | static void __init_or_module | |
550 | davinci_release_dma_channels(struct mmc_davinci_host *host) | |
551 | { | |
552 | unsigned i; | |
553 | ||
554 | if (!host->use_dma) | |
555 | return; | |
556 | ||
557 | for (i = 0; i < host->n_link; i++) | |
558 | edma_free_slot(host->links[i]); | |
559 | ||
560 | edma_free_channel(host->txdma); | |
561 | edma_free_channel(host->rxdma); | |
562 | } | |
563 | ||
564 | static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) | |
565 | { | |
566 | int r, i; | |
567 | ||
568 | /* Acquire master DMA write channel */ | |
569 | r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host, | |
570 | EVENTQ_DEFAULT); | |
571 | if (r < 0) { | |
572 | dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", | |
573 | "tx", r); | |
574 | return r; | |
575 | } | |
576 | mmc_davinci_dma_setup(host, true, &host->tx_template); | |
577 | ||
578 | /* Acquire master DMA read channel */ | |
579 | r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host, | |
580 | EVENTQ_DEFAULT); | |
581 | if (r < 0) { | |
582 | dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", | |
583 | "rx", r); | |
584 | goto free_master_write; | |
585 | } | |
586 | mmc_davinci_dma_setup(host, false, &host->rx_template); | |
587 | ||
588 | /* Allocate parameter RAM slots, which will later be bound to a | |
589 | * channel as needed to handle a scatterlist. | |
590 | */ | |
591 | for (i = 0; i < ARRAY_SIZE(host->links); i++) { | |
592 | r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); | |
593 | if (r < 0) { | |
594 | dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n", | |
595 | r); | |
596 | break; | |
597 | } | |
598 | host->links[i] = r; | |
599 | } | |
600 | host->n_link = i; | |
601 | ||
602 | return 0; | |
603 | ||
604 | free_master_write: | |
605 | edma_free_channel(host->txdma); | |
606 | ||
607 | return r; | |
608 | } | |
609 | ||
610 | /*----------------------------------------------------------------------*/ | |
611 | ||
612 | static void | |
613 | mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) | |
614 | { | |
615 | int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; | |
616 | int timeout; | |
617 | struct mmc_data *data = req->data; | |
618 | ||
619 | if (host->version == MMC_CTLR_VERSION_2) | |
620 | fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; | |
621 | ||
622 | host->data = data; | |
623 | if (data == NULL) { | |
624 | host->data_dir = DAVINCI_MMC_DATADIR_NONE; | |
625 | writel(0, host->base + DAVINCI_MMCBLEN); | |
626 | writel(0, host->base + DAVINCI_MMCNBLK); | |
627 | return; | |
628 | } | |
629 | ||
630 | dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n", | |
631 | (data->flags & MMC_DATA_STREAM) ? "stream" : "block", | |
632 | (data->flags & MMC_DATA_WRITE) ? "write" : "read", | |
633 | data->blocks, data->blksz); | |
634 | dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", | |
635 | data->timeout_clks, data->timeout_ns); | |
636 | timeout = data->timeout_clks + | |
637 | (data->timeout_ns / host->ns_in_one_cycle); | |
638 | if (timeout > 0xffff) | |
639 | timeout = 0xffff; | |
640 | ||
641 | writel(timeout, host->base + DAVINCI_MMCTOD); | |
642 | writel(data->blocks, host->base + DAVINCI_MMCNBLK); | |
643 | writel(data->blksz, host->base + DAVINCI_MMCBLEN); | |
644 | ||
645 | /* Configure the FIFO */ | |
646 | switch (data->flags & MMC_DATA_WRITE) { | |
647 | case MMC_DATA_WRITE: | |
648 | host->data_dir = DAVINCI_MMC_DATADIR_WRITE; | |
649 | writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, | |
650 | host->base + DAVINCI_MMCFIFOCTL); | |
651 | writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, | |
652 | host->base + DAVINCI_MMCFIFOCTL); | |
653 | break; | |
654 | ||
655 | default: | |
656 | host->data_dir = DAVINCI_MMC_DATADIR_READ; | |
657 | writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, | |
658 | host->base + DAVINCI_MMCFIFOCTL); | |
659 | writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, | |
660 | host->base + DAVINCI_MMCFIFOCTL); | |
661 | break; | |
662 | } | |
663 | ||
664 | host->buffer = NULL; | |
665 | host->bytes_left = data->blocks * data->blksz; | |
666 | ||
667 | /* For now we try to use DMA whenever we won't need partial FIFO | |
668 | * reads or writes, either for the whole transfer (as tested here) | |
669 | * or for any individual scatterlist segment (tested when we call | |
670 | * start_dma_transfer). | |
671 | * | |
672 | * While we *could* change that, unusual block sizes are rarely | |
673 | * used. The occasional fallback to PIO should't hurt. | |
674 | */ | |
675 | if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 | |
676 | && mmc_davinci_start_dma_transfer(host, data) == 0) { | |
677 | /* zero this to ensure we take no PIO paths */ | |
678 | host->bytes_left = 0; | |
679 | } else { | |
680 | /* Revert to CPU Copy */ | |
681 | host->sg_len = data->sg_len; | |
682 | host->sg = host->data->sg; | |
683 | mmc_davinci_sg_to_buf(host); | |
684 | } | |
685 | } | |
686 | ||
687 | static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) | |
688 | { | |
689 | struct mmc_davinci_host *host = mmc_priv(mmc); | |
690 | unsigned long timeout = jiffies + msecs_to_jiffies(900); | |
691 | u32 mmcst1 = 0; | |
692 | ||
693 | /* Card may still be sending BUSY after a previous operation, | |
694 | * typically some kind of write. If so, we can't proceed yet. | |
695 | */ | |
696 | while (time_before(jiffies, timeout)) { | |
697 | mmcst1 = readl(host->base + DAVINCI_MMCST1); | |
698 | if (!(mmcst1 & MMCST1_BUSY)) | |
699 | break; | |
700 | cpu_relax(); | |
701 | } | |
702 | if (mmcst1 & MMCST1_BUSY) { | |
703 | dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); | |
704 | req->cmd->error = -ETIMEDOUT; | |
705 | mmc_request_done(mmc, req); | |
706 | return; | |
707 | } | |
708 | ||
709 | host->do_dma = 0; | |
710 | mmc_davinci_prepare_data(host, req); | |
711 | mmc_davinci_start_command(host, req->cmd); | |
712 | } | |
713 | ||
714 | static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, | |
715 | unsigned int mmc_req_freq) | |
716 | { | |
717 | unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; | |
718 | ||
719 | mmc_pclk = host->mmc_input_clk; | |
720 | if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) | |
721 | mmc_push_pull_divisor = ((unsigned int)mmc_pclk | |
722 | / (2 * mmc_req_freq)) - 1; | |
723 | else | |
724 | mmc_push_pull_divisor = 0; | |
725 | ||
726 | mmc_freq = (unsigned int)mmc_pclk | |
727 | / (2 * (mmc_push_pull_divisor + 1)); | |
728 | ||
729 | if (mmc_freq > mmc_req_freq) | |
730 | mmc_push_pull_divisor = mmc_push_pull_divisor + 1; | |
731 | /* Convert ns to clock cycles */ | |
732 | if (mmc_req_freq <= 400000) | |
733 | host->ns_in_one_cycle = (1000000) / (((mmc_pclk | |
734 | / (2 * (mmc_push_pull_divisor + 1)))/1000)); | |
735 | else | |
736 | host->ns_in_one_cycle = (1000000) / (((mmc_pclk | |
737 | / (2 * (mmc_push_pull_divisor + 1)))/1000000)); | |
738 | ||
739 | return mmc_push_pull_divisor; | |
740 | } | |
741 | ||
742 | static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
743 | { | |
744 | unsigned int open_drain_freq = 0, mmc_pclk = 0; | |
745 | unsigned int mmc_push_pull_freq = 0; | |
746 | struct mmc_davinci_host *host = mmc_priv(mmc); | |
747 | ||
748 | mmc_pclk = host->mmc_input_clk; | |
749 | dev_dbg(mmc_dev(host->mmc), | |
750 | "clock %dHz busmode %d powermode %d Vdd %04x\n", | |
751 | ios->clock, ios->bus_mode, ios->power_mode, | |
752 | ios->vdd); | |
753 | if (ios->bus_width == MMC_BUS_WIDTH_4) { | |
754 | dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); | |
755 | writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_WIDTH_4_BIT, | |
756 | host->base + DAVINCI_MMCCTL); | |
757 | } else { | |
758 | dev_dbg(mmc_dev(host->mmc), "Disabling 4 bit mode\n"); | |
759 | writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_WIDTH_4_BIT, | |
760 | host->base + DAVINCI_MMCCTL); | |
761 | } | |
762 | ||
763 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { | |
764 | u32 temp; | |
765 | ||
766 | /* Ignoring the init clock value passed for fixing the inter | |
767 | * operability with different cards. | |
768 | */ | |
769 | open_drain_freq = ((unsigned int)mmc_pclk | |
770 | / (2 * MMCSD_INIT_CLOCK)) - 1; | |
771 | ||
772 | if (open_drain_freq > 0xFF) | |
773 | open_drain_freq = 0xFF; | |
774 | ||
775 | temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; | |
776 | temp |= open_drain_freq; | |
777 | writel(temp, host->base + DAVINCI_MMCCLK); | |
778 | ||
779 | /* Convert ns to clock cycles */ | |
780 | host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); | |
781 | } else { | |
782 | u32 temp; | |
783 | mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); | |
784 | ||
785 | if (mmc_push_pull_freq > 0xFF) | |
786 | mmc_push_pull_freq = 0xFF; | |
787 | ||
788 | temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; | |
789 | writel(temp, host->base + DAVINCI_MMCCLK); | |
790 | ||
791 | udelay(10); | |
792 | ||
793 | temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; | |
794 | temp |= mmc_push_pull_freq; | |
795 | writel(temp, host->base + DAVINCI_MMCCLK); | |
796 | ||
797 | writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); | |
798 | ||
799 | udelay(10); | |
800 | } | |
801 | ||
802 | host->bus_mode = ios->bus_mode; | |
803 | if (ios->power_mode == MMC_POWER_UP) { | |
804 | unsigned long timeout = jiffies + msecs_to_jiffies(50); | |
805 | bool lose = true; | |
806 | ||
807 | /* Send clock cycles, poll completion */ | |
808 | writel(0, host->base + DAVINCI_MMCARGHL); | |
809 | writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); | |
810 | while (time_before(jiffies, timeout)) { | |
811 | u32 tmp = readl(host->base + DAVINCI_MMCST0); | |
812 | ||
813 | if (tmp & MMCST0_RSPDNE) { | |
814 | lose = false; | |
815 | break; | |
816 | } | |
817 | cpu_relax(); | |
818 | } | |
819 | if (lose) | |
820 | dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); | |
821 | } | |
822 | ||
823 | /* FIXME on power OFF, reset things ... */ | |
824 | } | |
825 | ||
826 | static void | |
827 | mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) | |
828 | { | |
829 | host->data = NULL; | |
830 | ||
831 | if (host->do_dma) { | |
832 | davinci_abort_dma(host); | |
833 | ||
834 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
835 | (data->flags & MMC_DATA_WRITE) | |
836 | ? DMA_TO_DEVICE | |
837 | : DMA_FROM_DEVICE); | |
838 | host->do_dma = false; | |
839 | } | |
840 | host->data_dir = DAVINCI_MMC_DATADIR_NONE; | |
841 | ||
842 | if (!data->stop || (host->cmd && host->cmd->error)) { | |
843 | mmc_request_done(host->mmc, data->mrq); | |
844 | writel(0, host->base + DAVINCI_MMCIM); | |
845 | } else | |
846 | mmc_davinci_start_command(host, data->stop); | |
847 | } | |
848 | ||
849 | static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, | |
850 | struct mmc_command *cmd) | |
851 | { | |
852 | host->cmd = NULL; | |
853 | ||
854 | if (cmd->flags & MMC_RSP_PRESENT) { | |
855 | if (cmd->flags & MMC_RSP_136) { | |
856 | /* response type 2 */ | |
857 | cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); | |
858 | cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); | |
859 | cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); | |
860 | cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); | |
861 | } else { | |
862 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
863 | cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); | |
864 | } | |
865 | } | |
866 | ||
867 | if (host->data == NULL || cmd->error) { | |
868 | if (cmd->error == -ETIMEDOUT) | |
869 | cmd->mrq->cmd->retries = 0; | |
870 | mmc_request_done(host->mmc, cmd->mrq); | |
871 | writel(0, host->base + DAVINCI_MMCIM); | |
872 | } | |
873 | } | |
874 | ||
875 | static void | |
876 | davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) | |
877 | { | |
878 | u32 temp; | |
879 | ||
880 | /* reset command and data state machines */ | |
881 | temp = readl(host->base + DAVINCI_MMCCTL); | |
882 | writel(temp | MMCCTL_CMDRST | MMCCTL_DATRST, | |
883 | host->base + DAVINCI_MMCCTL); | |
884 | ||
885 | temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); | |
886 | udelay(10); | |
887 | writel(temp, host->base + DAVINCI_MMCCTL); | |
888 | } | |
889 | ||
890 | static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) | |
891 | { | |
892 | struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; | |
893 | unsigned int status, qstatus; | |
894 | int end_command = 0; | |
895 | int end_transfer = 0; | |
896 | struct mmc_data *data = host->data; | |
897 | ||
898 | if (host->cmd == NULL && host->data == NULL) { | |
899 | status = readl(host->base + DAVINCI_MMCST0); | |
900 | dev_dbg(mmc_dev(host->mmc), | |
901 | "Spurious interrupt 0x%04x\n", status); | |
902 | /* Disable the interrupt from mmcsd */ | |
903 | writel(0, host->base + DAVINCI_MMCIM); | |
904 | return IRQ_NONE; | |
905 | } | |
906 | ||
907 | status = readl(host->base + DAVINCI_MMCST0); | |
908 | qstatus = status; | |
909 | ||
910 | /* handle FIFO first when using PIO for data. | |
911 | * bytes_left will decrease to zero as I/O progress and status will | |
912 | * read zero over iteration because this controller status | |
913 | * register(MMCST0) reports any status only once and it is cleared | |
914 | * by read. So, it is not unbouned loop even in the case of | |
915 | * non-dma. | |
916 | */ | |
917 | while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { | |
918 | davinci_fifo_data_trans(host, rw_threshold); | |
919 | status = readl(host->base + DAVINCI_MMCST0); | |
920 | if (!status) | |
921 | break; | |
922 | qstatus |= status; | |
923 | } | |
924 | ||
925 | if (qstatus & MMCST0_DATDNE) { | |
926 | /* All blocks sent/received, and CRC checks passed */ | |
927 | if (data != NULL) { | |
928 | if ((host->do_dma == 0) && (host->bytes_left > 0)) { | |
929 | /* if datasize < rw_threshold | |
930 | * no RX ints are generated | |
931 | */ | |
932 | davinci_fifo_data_trans(host, host->bytes_left); | |
933 | } | |
934 | end_transfer = 1; | |
935 | data->bytes_xfered = data->blocks * data->blksz; | |
936 | } else { | |
937 | dev_err(mmc_dev(host->mmc), | |
938 | "DATDNE with no host->data\n"); | |
939 | } | |
940 | } | |
941 | ||
942 | if (qstatus & MMCST0_TOUTRD) { | |
943 | /* Read data timeout */ | |
944 | data->error = -ETIMEDOUT; | |
945 | end_transfer = 1; | |
946 | ||
947 | dev_dbg(mmc_dev(host->mmc), | |
948 | "read data timeout, status %x\n", | |
949 | qstatus); | |
950 | ||
951 | davinci_abort_data(host, data); | |
952 | } | |
953 | ||
954 | if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { | |
955 | /* Data CRC error */ | |
956 | data->error = -EILSEQ; | |
957 | end_transfer = 1; | |
958 | ||
959 | /* NOTE: this controller uses CRCWR to report both CRC | |
960 | * errors and timeouts (on writes). MMCDRSP values are | |
961 | * only weakly documented, but 0x9f was clearly a timeout | |
962 | * case and the two three-bit patterns in various SD specs | |
963 | * (101, 010) aren't part of it ... | |
964 | */ | |
965 | if (qstatus & MMCST0_CRCWR) { | |
966 | u32 temp = readb(host->base + DAVINCI_MMCDRSP); | |
967 | ||
968 | if (temp == 0x9f) | |
969 | data->error = -ETIMEDOUT; | |
970 | } | |
971 | dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", | |
972 | (qstatus & MMCST0_CRCWR) ? "write" : "read", | |
973 | (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); | |
974 | ||
975 | davinci_abort_data(host, data); | |
976 | } | |
977 | ||
978 | if (qstatus & MMCST0_TOUTRS) { | |
979 | /* Command timeout */ | |
980 | if (host->cmd) { | |
981 | dev_dbg(mmc_dev(host->mmc), | |
982 | "CMD%d timeout, status %x\n", | |
983 | host->cmd->opcode, qstatus); | |
984 | host->cmd->error = -ETIMEDOUT; | |
985 | if (data) { | |
986 | end_transfer = 1; | |
987 | davinci_abort_data(host, data); | |
988 | } else | |
989 | end_command = 1; | |
990 | } | |
991 | } | |
992 | ||
993 | if (qstatus & MMCST0_CRCRS) { | |
994 | /* Command CRC error */ | |
995 | dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); | |
996 | if (host->cmd) { | |
997 | host->cmd->error = -EILSEQ; | |
998 | end_command = 1; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | if (qstatus & MMCST0_RSPDNE) { | |
1003 | /* End of command phase */ | |
1004 | end_command = (int) host->cmd; | |
1005 | } | |
1006 | ||
1007 | if (end_command) | |
1008 | mmc_davinci_cmd_done(host, host->cmd); | |
1009 | if (end_transfer) | |
1010 | mmc_davinci_xfer_done(host, data); | |
1011 | return IRQ_HANDLED; | |
1012 | } | |
1013 | ||
1014 | static int mmc_davinci_get_cd(struct mmc_host *mmc) | |
1015 | { | |
1016 | struct platform_device *pdev = to_platform_device(mmc->parent); | |
1017 | struct davinci_mmc_config *config = pdev->dev.platform_data; | |
1018 | ||
1019 | if (!config || !config->get_cd) | |
1020 | return -ENOSYS; | |
1021 | return config->get_cd(pdev->id); | |
1022 | } | |
1023 | ||
1024 | static int mmc_davinci_get_ro(struct mmc_host *mmc) | |
1025 | { | |
1026 | struct platform_device *pdev = to_platform_device(mmc->parent); | |
1027 | struct davinci_mmc_config *config = pdev->dev.platform_data; | |
1028 | ||
1029 | if (!config || !config->get_ro) | |
1030 | return -ENOSYS; | |
1031 | return config->get_ro(pdev->id); | |
1032 | } | |
1033 | ||
1034 | static struct mmc_host_ops mmc_davinci_ops = { | |
1035 | .request = mmc_davinci_request, | |
1036 | .set_ios = mmc_davinci_set_ios, | |
1037 | .get_cd = mmc_davinci_get_cd, | |
1038 | .get_ro = mmc_davinci_get_ro, | |
1039 | }; | |
1040 | ||
1041 | /*----------------------------------------------------------------------*/ | |
1042 | ||
1043 | static void __init init_mmcsd_host(struct mmc_davinci_host *host) | |
1044 | { | |
1045 | /* DAT line portion is diabled and in reset state */ | |
1046 | writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_DATRST, | |
1047 | host->base + DAVINCI_MMCCTL); | |
1048 | ||
1049 | /* CMD line portion is diabled and in reset state */ | |
1050 | writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_CMDRST, | |
1051 | host->base + DAVINCI_MMCCTL); | |
1052 | ||
1053 | udelay(10); | |
1054 | ||
1055 | writel(0, host->base + DAVINCI_MMCCLK); | |
1056 | writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); | |
1057 | ||
1058 | writel(0x1FFF, host->base + DAVINCI_MMCTOR); | |
1059 | writel(0xFFFF, host->base + DAVINCI_MMCTOD); | |
1060 | ||
1061 | writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_DATRST, | |
1062 | host->base + DAVINCI_MMCCTL); | |
1063 | writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_CMDRST, | |
1064 | host->base + DAVINCI_MMCCTL); | |
1065 | ||
1066 | udelay(10); | |
1067 | } | |
1068 | ||
1069 | static int __init davinci_mmcsd_probe(struct platform_device *pdev) | |
1070 | { | |
1071 | struct davinci_mmc_config *pdata = pdev->dev.platform_data; | |
1072 | struct mmc_davinci_host *host = NULL; | |
1073 | struct mmc_host *mmc = NULL; | |
1074 | struct resource *r, *mem = NULL; | |
1075 | int ret = 0, irq = 0; | |
1076 | size_t mem_size; | |
1077 | ||
1078 | /* REVISIT: when we're fully converted, fail if pdata is NULL */ | |
1079 | ||
1080 | ret = -ENODEV; | |
1081 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1082 | irq = platform_get_irq(pdev, 0); | |
1083 | if (!r || irq == NO_IRQ) | |
1084 | goto out; | |
1085 | ||
1086 | ret = -EBUSY; | |
1087 | mem_size = resource_size(r); | |
1088 | mem = request_mem_region(r->start, mem_size, pdev->name); | |
1089 | if (!mem) | |
1090 | goto out; | |
1091 | ||
1092 | ret = -ENOMEM; | |
1093 | mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); | |
1094 | if (!mmc) | |
1095 | goto out; | |
1096 | ||
1097 | host = mmc_priv(mmc); | |
1098 | host->mmc = mmc; /* Important */ | |
1099 | ||
1100 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1101 | if (!r) | |
1102 | goto out; | |
1103 | host->rxdma = r->start; | |
1104 | ||
1105 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1106 | if (!r) | |
1107 | goto out; | |
1108 | host->txdma = r->start; | |
1109 | ||
1110 | host->mem_res = mem; | |
1111 | host->base = ioremap(mem->start, mem_size); | |
1112 | if (!host->base) | |
1113 | goto out; | |
1114 | ||
1115 | ret = -ENXIO; | |
1116 | host->clk = clk_get(&pdev->dev, "MMCSDCLK"); | |
1117 | if (IS_ERR(host->clk)) { | |
1118 | ret = PTR_ERR(host->clk); | |
1119 | goto out; | |
1120 | } | |
1121 | clk_enable(host->clk); | |
1122 | host->mmc_input_clk = clk_get_rate(host->clk); | |
1123 | ||
1124 | init_mmcsd_host(host); | |
1125 | ||
1126 | host->use_dma = use_dma; | |
1127 | host->irq = irq; | |
1128 | ||
1129 | if (host->use_dma && davinci_acquire_dma_channels(host) != 0) | |
1130 | host->use_dma = 0; | |
1131 | ||
1132 | /* REVISIT: someday, support IRQ-driven card detection. */ | |
1133 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
1134 | ||
1135 | if (!pdata || pdata->wires == 4 || pdata->wires == 0) | |
1136 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1137 | ||
1138 | host->version = pdata->version; | |
1139 | ||
1140 | mmc->ops = &mmc_davinci_ops; | |
1141 | mmc->f_min = 312500; | |
1142 | mmc->f_max = 25000000; | |
1143 | if (pdata && pdata->max_freq) | |
1144 | mmc->f_max = pdata->max_freq; | |
1145 | if (pdata && pdata->caps) | |
1146 | mmc->caps |= pdata->caps; | |
1147 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
1148 | ||
1149 | /* With no iommu coalescing pages, each phys_seg is a hw_seg. | |
1150 | * Each hw_seg uses one EDMA parameter RAM slot, always one | |
1151 | * channel and then usually some linked slots. | |
1152 | */ | |
1153 | mmc->max_hw_segs = 1 + host->n_link; | |
1154 | mmc->max_phys_segs = mmc->max_hw_segs; | |
1155 | ||
1156 | /* EDMA limit per hw segment (one or two MBytes) */ | |
1157 | mmc->max_seg_size = MAX_CCNT * rw_threshold; | |
1158 | ||
1159 | /* MMC/SD controller limits for multiblock requests */ | |
1160 | mmc->max_blk_size = 4095; /* BLEN is 12 bits */ | |
1161 | mmc->max_blk_count = 65535; /* NBLK is 16 bits */ | |
1162 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1163 | ||
1164 | dev_dbg(mmc_dev(host->mmc), "max_phys_segs=%d\n", mmc->max_phys_segs); | |
1165 | dev_dbg(mmc_dev(host->mmc), "max_hw_segs=%d\n", mmc->max_hw_segs); | |
1166 | dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); | |
1167 | dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); | |
1168 | dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); | |
1169 | ||
1170 | platform_set_drvdata(pdev, host); | |
1171 | ||
1172 | ret = mmc_add_host(mmc); | |
1173 | if (ret < 0) | |
1174 | goto out; | |
1175 | ||
1176 | ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host); | |
1177 | if (ret) | |
1178 | goto out; | |
1179 | ||
1180 | rename_region(mem, mmc_hostname(mmc)); | |
1181 | ||
1182 | dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", | |
1183 | host->use_dma ? "DMA" : "PIO", | |
1184 | (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); | |
1185 | ||
1186 | return 0; | |
1187 | ||
1188 | out: | |
1189 | if (host) { | |
1190 | davinci_release_dma_channels(host); | |
1191 | ||
1192 | if (host->clk) { | |
1193 | clk_disable(host->clk); | |
1194 | clk_put(host->clk); | |
1195 | } | |
1196 | ||
1197 | if (host->base) | |
1198 | iounmap(host->base); | |
1199 | } | |
1200 | ||
1201 | if (mmc) | |
1202 | mmc_free_host(mmc); | |
1203 | ||
1204 | if (mem) | |
1205 | release_resource(mem); | |
1206 | ||
1207 | dev_dbg(&pdev->dev, "probe err %d\n", ret); | |
1208 | ||
1209 | return ret; | |
1210 | } | |
1211 | ||
1212 | static int __exit davinci_mmcsd_remove(struct platform_device *pdev) | |
1213 | { | |
1214 | struct mmc_davinci_host *host = platform_get_drvdata(pdev); | |
1215 | ||
1216 | platform_set_drvdata(pdev, NULL); | |
1217 | if (host) { | |
1218 | mmc_remove_host(host->mmc); | |
1219 | free_irq(host->irq, host); | |
1220 | ||
1221 | davinci_release_dma_channels(host); | |
1222 | ||
1223 | clk_disable(host->clk); | |
1224 | clk_put(host->clk); | |
1225 | ||
1226 | iounmap(host->base); | |
1227 | ||
1228 | release_resource(host->mem_res); | |
1229 | ||
1230 | mmc_free_host(host->mmc); | |
1231 | } | |
1232 | ||
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | #ifdef CONFIG_PM | |
1237 | static int davinci_mmcsd_suspend(struct platform_device *pdev, pm_message_t msg) | |
1238 | { | |
1239 | struct mmc_davinci_host *host = platform_get_drvdata(pdev); | |
1240 | ||
1241 | return mmc_suspend_host(host->mmc, msg); | |
1242 | } | |
1243 | ||
1244 | static int davinci_mmcsd_resume(struct platform_device *pdev) | |
1245 | { | |
1246 | struct mmc_davinci_host *host = platform_get_drvdata(pdev); | |
1247 | ||
1248 | return mmc_resume_host(host->mmc); | |
1249 | } | |
1250 | #else | |
1251 | #define davinci_mmcsd_suspend NULL | |
1252 | #define davinci_mmcsd_resume NULL | |
1253 | #endif | |
1254 | ||
1255 | static struct platform_driver davinci_mmcsd_driver = { | |
1256 | .driver = { | |
1257 | .name = "davinci_mmc", | |
1258 | .owner = THIS_MODULE, | |
1259 | }, | |
1260 | .remove = __exit_p(davinci_mmcsd_remove), | |
1261 | .suspend = davinci_mmcsd_suspend, | |
1262 | .resume = davinci_mmcsd_resume, | |
1263 | }; | |
1264 | ||
1265 | static int __init davinci_mmcsd_init(void) | |
1266 | { | |
1267 | return platform_driver_probe(&davinci_mmcsd_driver, | |
1268 | davinci_mmcsd_probe); | |
1269 | } | |
1270 | module_init(davinci_mmcsd_init); | |
1271 | ||
1272 | static void __exit davinci_mmcsd_exit(void) | |
1273 | { | |
1274 | platform_driver_unregister(&davinci_mmcsd_driver); | |
1275 | } | |
1276 | module_exit(davinci_mmcsd_exit); | |
1277 | ||
1278 | MODULE_AUTHOR("Texas Instruments India"); | |
1279 | MODULE_LICENSE("GPL"); | |
1280 | MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); | |
1281 |