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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
[linux-block.git] / drivers / mmc / host / atmel-mci.c
CommitLineData
7d2be074
HS		 1/*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/blkdev.h>
11#include <linux/clk.h>
deec9ae3 12#include <linux/debugfs.h>
7d2be074 13#include <linux/device.h>
65e8b083
HS		 14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
fbfca4b8 16#include <linux/err.h>
3c26e170 17#include <linux/gpio.h>
7d2be074
HS		 18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/scatterlist.h>
deec9ae3 24#include <linux/seq_file.h>
5a0e3ad6 25#include <linux/slab.h>
deec9ae3 26#include <linux/stat.h>
7d2be074
HS		 27
28#include <linux/mmc/host.h>
2f1d7918 29#include <linux/mmc/sdio.h>
2635d1ba
NF		 30
31#include <mach/atmel-mci.h>
c42aa775 32#include <linux/atmel-mci.h>
796211b7 33#include <linux/atmel_pdc.h>
7d2be074 34
7d2be074
HS		 35#include <asm/io.h>
36#include <asm/unaligned.h>
37
04d699c3 38#include <mach/cpu.h>
3663b736 39#include <mach/board.h>
7d2be074
HS		 40
41#include "atmel-mci-regs.h"
42
2c96a293 43#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
65e8b083 44#define ATMCI_DMA_THRESHOLD 16
7d2be074
HS		 45
46enum {
47 EVENT_CMD_COMPLETE = 0,
7d2be074 48 EVENT_XFER_COMPLETE,
c06ad258
HS		 49 EVENT_DATA_COMPLETE,
50 EVENT_DATA_ERROR,
51};
52
53enum atmel_mci_state {
965ebf33
HS		 54 STATE_IDLE = 0,
55 STATE_SENDING_CMD,
c06ad258
HS		 56 STATE_SENDING_DATA,
57 STATE_DATA_BUSY,
58 STATE_SENDING_STOP,
59 STATE_DATA_ERROR,
7d2be074
HS		 60};
61
796211b7
LD		 62enum atmci_xfer_dir {
63 XFER_RECEIVE = 0,
64 XFER_TRANSMIT,
65};
66
67enum atmci_pdc_buf {
68 PDC_FIRST_BUF = 0,
69 PDC_SECOND_BUF,
70};
71
72struct atmel_mci_caps {
73 bool has_dma;
74 bool has_pdc;
75 bool has_cfg_reg;
76 bool has_cstor_reg;
77 bool has_highspeed;
78 bool has_rwproof;
79};
80
65e8b083 81struct atmel_mci_dma {
65e8b083
HS		 82 struct dma_chan *chan;
83 struct dma_async_tx_descriptor *data_desc;
65e8b083
HS		 84};
85
965ebf33
HS		 86/**
87 * struct atmel_mci - MMC controller state shared between all slots
88 * @lock: Spinlock protecting the queue and associated data.
89 * @regs: Pointer to MMIO registers.
796211b7 90 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
965ebf33
HS		 91 * @pio_offset: Offset into the current scatterlist entry.
92 * @cur_slot: The slot which is currently using the controller.
93 * @mrq: The request currently being processed on @cur_slot,
94 * or NULL if the controller is idle.
95 * @cmd: The command currently being sent to the card, or NULL.
96 * @data: The data currently being transferred, or NULL if no data
97 * transfer is in progress.
796211b7 98 * @data_size: just data->blocks * data->blksz.
65e8b083
HS		 99 * @dma: DMA client state.
100 * @data_chan: DMA channel being used for the current data transfer.
965ebf33
HS		 101 * @cmd_status: Snapshot of SR taken upon completion of the current
102 * command. Only valid when EVENT_CMD_COMPLETE is pending.
103 * @data_status: Snapshot of SR taken upon completion of the current
104 * data transfer. Only valid when EVENT_DATA_COMPLETE or
105 * EVENT_DATA_ERROR is pending.
106 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
107 * to be sent.
108 * @tasklet: Tasklet running the request state machine.
109 * @pending_events: Bitmask of events flagged by the interrupt handler
110 * to be processed by the tasklet.
111 * @completed_events: Bitmask of events which the state machine has
112 * processed.
113 * @state: Tasklet state.
114 * @queue: List of slots waiting for access to the controller.
115 * @need_clock_update: Update the clock rate before the next request.
116 * @need_reset: Reset controller before next request.
117 * @mode_reg: Value of the MR register.
74791a2d 118 * @cfg_reg: Value of the CFG register.
965ebf33
HS		 119 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
120 * rate and timeout calculations.
121 * @mapbase: Physical address of the MMIO registers.
122 * @mck: The peripheral bus clock hooked up to the MMC controller.
123 * @pdev: Platform device associated with the MMC controller.
124 * @slot: Slots sharing this MMC controller.
796211b7
LD		 125 * @caps: MCI capabilities depending on MCI version.
126 * @prepare_data: function to setup MCI before data transfer which
127 * depends on MCI capabilities.
128 * @submit_data: function to start data transfer which depends on MCI
129 * capabilities.
130 * @stop_transfer: function to stop data transfer which depends on MCI
131 * capabilities.
965ebf33
HS		 132 *
133 * Locking
134 * =======
135 *
136 * @lock is a softirq-safe spinlock protecting @queue as well as
137 * @cur_slot, @mrq and @state. These must always be updated
138 * at the same time while holding @lock.
139 *
140 * @lock also protects mode_reg and need_clock_update since these are
141 * used to synchronize mode register updates with the queue
142 * processing.
143 *
144 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
145 * and must always be written at the same time as the slot is added to
146 * @queue.
147 *
148 * @pending_events and @completed_events are accessed using atomic bit
149 * operations, so they don't need any locking.
150 *
151 * None of the fields touched by the interrupt handler need any
152 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
153 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
154 * interrupts must be disabled and @data_status updated with a
155 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
25985edc 156 * CMDRDY interrupt must be disabled and @cmd_status updated with a
965ebf33
HS		 157 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
158 * bytes_xfered field of @data must be written. This is ensured by
159 * using barriers.
160 */
7d2be074 161struct atmel_mci {
965ebf33 162 spinlock_t lock;
7d2be074
HS		 163 void __iomem *regs;
164
165 struct scatterlist *sg;
166 unsigned int pio_offset;
167
965ebf33 168 struct atmel_mci_slot *cur_slot;
7d2be074
HS		 169 struct mmc_request *mrq;
170 struct mmc_command *cmd;
171 struct mmc_data *data;
796211b7 172 unsigned int data_size;
7d2be074 173
65e8b083
HS		 174 struct atmel_mci_dma dma;
175 struct dma_chan *data_chan;
176
7d2be074
HS		 177 u32 cmd_status;
178 u32 data_status;
7d2be074
HS		 179 u32 stop_cmdr;
180
7d2be074
HS		 181 struct tasklet_struct tasklet;
182 unsigned long pending_events;
183 unsigned long completed_events;
c06ad258 184 enum atmel_mci_state state;
965ebf33 185 struct list_head queue;
7d2be074 186
965ebf33
HS		 187 bool need_clock_update;
188 bool need_reset;
189 u32 mode_reg;
74791a2d 190 u32 cfg_reg;
7d2be074
HS		 191 unsigned long bus_hz;
192 unsigned long mapbase;
193 struct clk *mck;
194 struct platform_device *pdev;
965ebf33 195
2c96a293 196 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
796211b7
LD		 197
198 struct atmel_mci_caps caps;
199
200 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
201 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
202 void (*stop_transfer)(struct atmel_mci *host);
965ebf33
HS		 203};
204
205/**
206 * struct atmel_mci_slot - MMC slot state
207 * @mmc: The mmc_host representing this slot.
208 * @host: The MMC controller this slot is using.
209 * @sdc_reg: Value of SDCR to be written before using this slot.
88ff82ed 210 * @sdio_irq: SDIO irq mask for this slot.
965ebf33
HS		 211 * @mrq: mmc_request currently being processed or waiting to be
212 * processed, or NULL when the slot is idle.
213 * @queue_node: List node for placing this node in the @queue list of
214 * &struct atmel_mci.
215 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
216 * @flags: Random state bits associated with the slot.
217 * @detect_pin: GPIO pin used for card detection, or negative if not
218 * available.
219 * @wp_pin: GPIO pin used for card write protect sending, or negative
220 * if not available.
1c1452be 221 * @detect_is_active_high: The state of the detect pin when it is active.
965ebf33
HS		 222 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
223 */
224struct atmel_mci_slot {
225 struct mmc_host *mmc;
226 struct atmel_mci *host;
227
228 u32 sdc_reg;
88ff82ed 229 u32 sdio_irq;
965ebf33
HS		 230
231 struct mmc_request *mrq;
232 struct list_head queue_node;
233
234 unsigned int clock;
235 unsigned long flags;
236#define ATMCI_CARD_PRESENT 0
237#define ATMCI_CARD_NEED_INIT 1
238#define ATMCI_SHUTDOWN 2
5c2f2b9b 239#define ATMCI_SUSPENDED 3
965ebf33
HS		 240
241 int detect_pin;
242 int wp_pin;
1c1452be 243 bool detect_is_active_high;
965ebf33
HS		 244
245 struct timer_list detect_timer;
7d2be074
HS		 246};
247
7d2be074
HS		 248#define atmci_test_and_clear_pending(host, event) \
249 test_and_clear_bit(event, &host->pending_events)
7d2be074
HS		 250#define atmci_set_completed(host, event) \
251 set_bit(event, &host->completed_events)
252#define atmci_set_pending(host, event) \
253 set_bit(event, &host->pending_events)
7d2be074 254
deec9ae3
HS		 255/*
256 * The debugfs stuff below is mostly optimized away when
257 * CONFIG_DEBUG_FS is not set.
258 */
259static int atmci_req_show(struct seq_file *s, void *v)
260{
965ebf33
HS		 261 struct atmel_mci_slot *slot = s->private;
262 struct mmc_request *mrq;
deec9ae3
HS		 263 struct mmc_command *cmd;
264 struct mmc_command *stop;
265 struct mmc_data *data;
266
267 /* Make sure we get a consistent snapshot */
965ebf33
HS		 268 spin_lock_bh(&slot->host->lock);
269 mrq = slot->mrq;
deec9ae3
HS		 270
271 if (mrq) {
272 cmd = mrq->cmd;
273 data = mrq->data;
274 stop = mrq->stop;
275
276 if (cmd)
277 seq_printf(s,
278 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
279 cmd->opcode, cmd->arg, cmd->flags,
280 cmd->resp[0], cmd->resp[1], cmd->resp[2],
d586ebbb 281 cmd->resp[3], cmd->error);
deec9ae3
HS		 282 if (data)
283 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
284 data->bytes_xfered, data->blocks,
285 data->blksz, data->flags, data->error);
286 if (stop)
287 seq_printf(s,
288 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
289 stop->opcode, stop->arg, stop->flags,
290 stop->resp[0], stop->resp[1], stop->resp[2],
d586ebbb 291 stop->resp[3], stop->error);
deec9ae3
HS		 292 }
293
965ebf33 294 spin_unlock_bh(&slot->host->lock);
deec9ae3
HS		 295
296 return 0;
297}
298
299static int atmci_req_open(struct inode *inode, struct file *file)
300{
301 return single_open(file, atmci_req_show, inode->i_private);
302}
303
304static const struct file_operations atmci_req_fops = {
305 .owner = THIS_MODULE,
306 .open = atmci_req_open,
307 .read = seq_read,
308 .llseek = seq_lseek,
309 .release = single_release,
310};
311
312static void atmci_show_status_reg(struct seq_file *s,
313 const char *regname, u32 value)
314{
315 static const char *sr_bit[] = {
316 [0] = "CMDRDY",
317 [1] = "RXRDY",
318 [2] = "TXRDY",
319 [3] = "BLKE",
320 [4] = "DTIP",
321 [5] = "NOTBUSY",
04d699c3
RE		 322 [6] = "ENDRX",
323 [7] = "ENDTX",
deec9ae3
HS		 324 [8] = "SDIOIRQA",
325 [9] = "SDIOIRQB",
04d699c3
RE		 326 [12] = "SDIOWAIT",
327 [14] = "RXBUFF",
328 [15] = "TXBUFE",
deec9ae3
HS		 329 [16] = "RINDE",
330 [17] = "RDIRE",
331 [18] = "RCRCE",
332 [19] = "RENDE",
333 [20] = "RTOE",
334 [21] = "DCRCE",
335 [22] = "DTOE",
04d699c3
RE		 336 [23] = "CSTOE",
337 [24] = "BLKOVRE",
338 [25] = "DMADONE",
339 [26] = "FIFOEMPTY",
340 [27] = "XFRDONE",
deec9ae3
HS		 341 [30] = "OVRE",
342 [31] = "UNRE",
343 };
344 unsigned int i;
345
346 seq_printf(s, "%s:\t0x%08x", regname, value);
347 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
348 if (value & (1 << i)) {
349 if (sr_bit[i])
350 seq_printf(s, " %s", sr_bit[i]);
351 else
352 seq_puts(s, " UNKNOWN");
353 }
354 }
355 seq_putc(s, '\n');
356}
357
358static int atmci_regs_show(struct seq_file *s, void *v)
359{
360 struct atmel_mci *host = s->private;
361 u32 *buf;
362
2c96a293 363 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
deec9ae3
HS		 364 if (!buf)
365 return -ENOMEM;
366
965ebf33
HS		 367 /*
368 * Grab a more or less consistent snapshot. Note that we're
369 * not disabling interrupts, so IMR and SR may not be
370 * consistent.
371 */
372 spin_lock_bh(&host->lock);
87e60f2b 373 clk_enable(host->mck);
2c96a293 374 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
87e60f2b 375 clk_disable(host->mck);
965ebf33 376 spin_unlock_bh(&host->lock);
deec9ae3
HS		 377
378 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
2c96a293
LD		 379 buf[ATMCI_MR / 4],
380 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
381 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "",
382 buf[ATMCI_MR / 4] & 0xff);
383 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
384 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
385 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
deec9ae3 386 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
2c96a293
LD		 387 buf[ATMCI_BLKR / 4],
388 buf[ATMCI_BLKR / 4] & 0xffff,
389 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
796211b7 390 if (host->caps.has_cstor_reg)
2c96a293 391 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
deec9ae3
HS		 392
393 /* Don't read RSPR and RDR; it will consume the data there */
394
2c96a293
LD		 395 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
396 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
deec9ae3 397
796211b7 398 if (host->caps.has_dma) {
74791a2d
NF		 399 u32 val;
400
2c96a293 401 val = buf[ATMCI_DMA / 4];
74791a2d
NF		 402 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
403 val, val & 3,
404 ((val >> 4) & 3) ?
405 1 << (((val >> 4) & 3) + 1) : 1,
2c96a293 406 val & ATMCI_DMAEN ? " DMAEN" : "");
796211b7
LD		 407 }
408 if (host->caps.has_cfg_reg) {
409 u32 val;
74791a2d 410
2c96a293 411 val = buf[ATMCI_CFG / 4];
74791a2d
NF		 412 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
413 val,
2c96a293
LD		 414 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
415 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
416 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
417 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
74791a2d
NF		 418 }
419
b17339a1
HS		 420 kfree(buf);
421
deec9ae3
HS		 422 return 0;
423}
424
425static int atmci_regs_open(struct inode *inode, struct file *file)
426{
427 return single_open(file, atmci_regs_show, inode->i_private);
428}
429
430static const struct file_operations atmci_regs_fops = {
431 .owner = THIS_MODULE,
432 .open = atmci_regs_open,
433 .read = seq_read,
434 .llseek = seq_lseek,
435 .release = single_release,
436};
437
965ebf33 438static void atmci_init_debugfs(struct atmel_mci_slot *slot)
deec9ae3 439{
965ebf33
HS		 440 struct mmc_host *mmc = slot->mmc;
441 struct atmel_mci *host = slot->host;
442 struct dentry *root;
443 struct dentry *node;
deec9ae3 444
deec9ae3
HS		 445 root = mmc->debugfs_root;
446 if (!root)
447 return;
448
449 node = debugfs_create_file("regs", S_IRUSR, root, host,
450 &atmci_regs_fops);
451 if (IS_ERR(node))
452 return;
453 if (!node)
454 goto err;
455
965ebf33 456 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
deec9ae3
HS		 457 if (!node)
458 goto err;
459
c06ad258
HS		 460 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
461 if (!node)
462 goto err;
463
deec9ae3
HS		 464 node = debugfs_create_x32("pending_events", S_IRUSR, root,
465 (u32 *)&host->pending_events);
466 if (!node)
467 goto err;
468
469 node = debugfs_create_x32("completed_events", S_IRUSR, root,
470 (u32 *)&host->completed_events);
471 if (!node)
472 goto err;
473
474 return;
475
476err:
965ebf33 477 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
deec9ae3 478}
7d2be074 479
2c96a293 480static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
7d2be074
HS		 481 unsigned int ns)
482{
483 return (ns * (host->bus_hz / 1000000) + 999) / 1000;
484}
485
486static void atmci_set_timeout(struct atmel_mci *host,
965ebf33 487 struct atmel_mci_slot *slot, struct mmc_data *data)
7d2be074
HS		 488{
489 static unsigned dtomul_to_shift[] = {
490 0, 4, 7, 8, 10, 12, 16, 20
491 };
492 unsigned timeout;
493 unsigned dtocyc;
494 unsigned dtomul;
495
2c96a293
LD		 496 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
497 + data->timeout_clks;
7d2be074
HS		 498
499 for (dtomul = 0; dtomul < 8; dtomul++) {
500 unsigned shift = dtomul_to_shift[dtomul];
501 dtocyc = (timeout + (1 << shift) - 1) >> shift;
502 if (dtocyc < 15)
503 break;
504 }
505
506 if (dtomul >= 8) {
507 dtomul = 7;
508 dtocyc = 15;
509 }
510
965ebf33 511 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
7d2be074 512 dtocyc << dtomul_to_shift[dtomul]);
03fc9a7f 513 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
7d2be074
HS		 514}
515
516/*
517 * Return mask with command flags to be enabled for this command.
518 */
519static u32 atmci_prepare_command(struct mmc_host *mmc,
520 struct mmc_command *cmd)
521{
522 struct mmc_data *data;
523 u32 cmdr;
524
525 cmd->error = -EINPROGRESS;
526
2c96a293 527 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
7d2be074
HS		 528
529 if (cmd->flags & MMC_RSP_PRESENT) {
530 if (cmd->flags & MMC_RSP_136)
2c96a293 531 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
7d2be074 532 else
2c96a293 533 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
7d2be074
HS		 534 }
535
536 /*
537 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
538 * it's too difficult to determine whether this is an ACMD or
539 * not. Better make it 64.
540 */
2c96a293 541 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
7d2be074
HS		 542
543 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
2c96a293 544 cmdr |= ATMCI_CMDR_OPDCMD;
7d2be074
HS		 545
546 data = cmd->data;
547 if (data) {
2c96a293 548 cmdr |= ATMCI_CMDR_START_XFER;
2f1d7918
NF		 549
550 if (cmd->opcode == SD_IO_RW_EXTENDED) {
2c96a293 551 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
2f1d7918
NF		 552 } else {
553 if (data->flags & MMC_DATA_STREAM)
2c96a293 554 cmdr |= ATMCI_CMDR_STREAM;
2f1d7918 555 else if (data->blocks > 1)
2c96a293 556 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
2f1d7918 557 else
2c96a293 558 cmdr |= ATMCI_CMDR_BLOCK;
2f1d7918 559 }
7d2be074
HS		 560
561 if (data->flags & MMC_DATA_READ)
2c96a293 562 cmdr |= ATMCI_CMDR_TRDIR_READ;
7d2be074
HS		 563 }
564
565 return cmdr;
566}
567
11d1488b 568static void atmci_send_command(struct atmel_mci *host,
965ebf33 569 struct mmc_command *cmd, u32 cmd_flags)
7d2be074 570{
7d2be074
HS		 571 WARN_ON(host->cmd);
572 host->cmd = cmd;
573
965ebf33 574 dev_vdbg(&host->pdev->dev,
7d2be074
HS		 575 "start command: ARGR=0x%08x CMDR=0x%08x\n",
576 cmd->arg, cmd_flags);
577
03fc9a7f
LD		 578 atmci_writel(host, ATMCI_ARGR, cmd->arg);
579 atmci_writel(host, ATMCI_CMDR, cmd_flags);
7d2be074
HS		 580}
581
2c96a293 582static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
7d2be074 583{
11d1488b 584 atmci_send_command(host, data->stop, host->stop_cmdr);
03fc9a7f 585 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
7d2be074
HS		 586}
587
796211b7
LD		 588/*
589 * Configure given PDC buffer taking care of alignement issues.
590 * Update host->data_size and host->sg.
591 */
592static void atmci_pdc_set_single_buf(struct atmel_mci *host,
593 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
594{
595 u32 pointer_reg, counter_reg;
596
597 if (dir == XFER_RECEIVE) {
598 pointer_reg = ATMEL_PDC_RPR;
599 counter_reg = ATMEL_PDC_RCR;
600 } else {
601 pointer_reg = ATMEL_PDC_TPR;
602 counter_reg = ATMEL_PDC_TCR;
603 }
604
605 if (buf_nb == PDC_SECOND_BUF) {
1ebbe3d3
LD		 606 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
607 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
796211b7
LD		 608 }
609
610 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
341fa4c3 611 if (host->data_size <= sg_dma_len(host->sg)) {
796211b7
LD		 612 if (host->data_size & 0x3) {
613 /* If size is different from modulo 4, transfer bytes */
614 atmci_writel(host, counter_reg, host->data_size);
615 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
616 } else {
617 /* Else transfer 32-bits words */
618 atmci_writel(host, counter_reg, host->data_size / 4);
619 }
620 host->data_size = 0;
621 } else {
622 /* We assume the size of a page is 32-bits aligned */
341fa4c3
LD		 623 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
624 host->data_size -= sg_dma_len(host->sg);
796211b7
LD		 625 if (host->data_size)
626 host->sg = sg_next(host->sg);
627 }
628}
629
630/*
631 * Configure PDC buffer according to the data size ie configuring one or two
632 * buffers. Don't use this function if you want to configure only the second
633 * buffer. In this case, use atmci_pdc_set_single_buf.
634 */
635static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
65e8b083 636{
796211b7
LD		 637 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
638 if (host->data_size)
639 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
640}
641
642/*
643 * Unmap sg lists, called when transfer is finished.
644 */
645static void atmci_pdc_cleanup(struct atmel_mci *host)
646{
647 struct mmc_data *data = host->data;
65e8b083 648
009a891b 649 if (data)
796211b7
LD		 650 dma_unmap_sg(&host->pdev->dev,
651 data->sg, data->sg_len,
652 ((data->flags & MMC_DATA_WRITE)
653 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
65e8b083
HS		 654}
655
796211b7
LD		 656/*
657 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
658 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
659 * interrupt needed for both transfer directions.
660 */
661static void atmci_pdc_complete(struct atmel_mci *host)
65e8b083 662{
796211b7
LD		 663 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
664 atmci_pdc_cleanup(host);
65e8b083 665
796211b7
LD		 666 /*
667 * If the card was removed, data will be NULL. No point trying
668 * to send the stop command or waiting for NBUSY in this case.
669 */
670 if (host->data) {
65e8b083 671 atmci_set_pending(host, EVENT_XFER_COMPLETE);
796211b7 672 tasklet_schedule(&host->tasklet);
03fc9a7f 673 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083
HS		 674 }
675}
676
796211b7
LD		 677static void atmci_dma_cleanup(struct atmel_mci *host)
678{
679 struct mmc_data *data = host->data;
680
681 if (data)
682 dma_unmap_sg(host->dma.chan->device->dev,
683 data->sg, data->sg_len,
684 ((data->flags & MMC_DATA_WRITE)
685 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
686}
687
688/*
689 * This function is called by the DMA driver from tasklet context.
690 */
65e8b083
HS		 691static void atmci_dma_complete(void *arg)
692{
693 struct atmel_mci *host = arg;
694 struct mmc_data *data = host->data;
695
696 dev_vdbg(&host->pdev->dev, "DMA complete\n");
697
796211b7 698 if (host->caps.has_dma)
74791a2d 699 /* Disable DMA hardware handshaking on MCI */
03fc9a7f 700 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
74791a2d 701
65e8b083
HS		 702 atmci_dma_cleanup(host);
703
704 /*
705 * If the card was removed, data will be NULL. No point trying
706 * to send the stop command or waiting for NBUSY in this case.
707 */
708 if (data) {
709 atmci_set_pending(host, EVENT_XFER_COMPLETE);
710 tasklet_schedule(&host->tasklet);
711
712 /*
713 * Regardless of what the documentation says, we have
714 * to wait for NOTBUSY even after block read
715 * operations.
716 *
717 * When the DMA transfer is complete, the controller
718 * may still be reading the CRC from the card, i.e.
719 * the data transfer is still in progress and we
720 * haven't seen all the potential error bits yet.
721 *
722 * The interrupt handler will schedule a different
723 * tasklet to finish things up when the data transfer
724 * is completely done.
725 *
726 * We may not complete the mmc request here anyway
727 * because the mmc layer may call back and cause us to
728 * violate the "don't submit new operations from the
729 * completion callback" rule of the dma engine
730 * framework.
731 */
03fc9a7f 732 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083
HS		 733 }
734}
735
796211b7
LD		 736/*
737 * Returns a mask of interrupt flags to be enabled after the whole
738 * request has been prepared.
739 */
740static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
741{
742 u32 iflags;
743
744 data->error = -EINPROGRESS;
745
746 host->sg = data->sg;
747 host->data = data;
748 host->data_chan = NULL;
749
750 iflags = ATMCI_DATA_ERROR_FLAGS;
751
752 /*
753 * Errata: MMC data write operation with less than 12
754 * bytes is impossible.
755 *
756 * Errata: MCI Transmit Data Register (TDR) FIFO
757 * corruption when length is not multiple of 4.
758 */
759 if (data->blocks * data->blksz < 12
760 || (data->blocks * data->blksz) & 3)
761 host->need_reset = true;
762
763 host->pio_offset = 0;
764 if (data->flags & MMC_DATA_READ)
765 iflags |= ATMCI_RXRDY;
766 else
767 iflags |= ATMCI_TXRDY;
768
769 return iflags;
770}
771
772/*
773 * Set interrupt flags and set block length into the MCI mode register even
774 * if this value is also accessible in the MCI block register. It seems to be
775 * necessary before the High Speed MCI version. It also map sg and configure
776 * PDC registers.
777 */
778static u32
779atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
780{
781 u32 iflags, tmp;
782 unsigned int sg_len;
783 enum dma_data_direction dir;
784
785 data->error = -EINPROGRESS;
786
787 host->data = data;
788 host->sg = data->sg;
789 iflags = ATMCI_DATA_ERROR_FLAGS;
790
791 /* Enable pdc mode */
792 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
793
794 if (data->flags & MMC_DATA_READ) {
795 dir = DMA_FROM_DEVICE;
796 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
797 } else {
798 dir = DMA_TO_DEVICE;
799 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE;
800 }
801
802 /* Set BLKLEN */
803 tmp = atmci_readl(host, ATMCI_MR);
804 tmp &= 0x0000ffff;
805 tmp |= ATMCI_BLKLEN(data->blksz);
806 atmci_writel(host, ATMCI_MR, tmp);
807
808 /* Configure PDC */
809 host->data_size = data->blocks * data->blksz;
810 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
796211b7
LD		 811 if (host->data_size)
812 atmci_pdc_set_both_buf(host,
813 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
814
815 return iflags;
816}
817
818static u32
74791a2d 819atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
65e8b083
HS		 820{
821 struct dma_chan *chan;
822 struct dma_async_tx_descriptor *desc;
823 struct scatterlist *sg;
824 unsigned int i;
825 enum dma_data_direction direction;
05f5799c 826 enum dma_transfer_direction slave_dirn;
657a77fa 827 unsigned int sglen;
796211b7
LD		 828 u32 iflags;
829
830 data->error = -EINPROGRESS;
831
832 WARN_ON(host->data);
833 host->sg = NULL;
834 host->data = data;
835
836 iflags = ATMCI_DATA_ERROR_FLAGS;
65e8b083
HS		 837
838 /*
839 * We don't do DMA on "complex" transfers, i.e. with
840 * non-word-aligned buffers or lengths. Also, we don't bother
841 * with all the DMA setup overhead for short transfers.
842 */
796211b7
LD		 843 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
844 return atmci_prepare_data(host, data);
65e8b083 845 if (data->blksz & 3)
796211b7 846 return atmci_prepare_data(host, data);
65e8b083
HS		 847
848 for_each_sg(data->sg, sg, data->sg_len, i) {
849 if (sg->offset & 3 || sg->length & 3)
796211b7 850 return atmci_prepare_data(host, data);
65e8b083
HS		 851 }
852
853 /* If we don't have a channel, we can't do DMA */
854 chan = host->dma.chan;
6f49a57a 855 if (chan)
65e8b083 856 host->data_chan = chan;
65e8b083
HS		 857
858 if (!chan)
859 return -ENODEV;
860
796211b7 861 if (host->caps.has_dma)
03fc9a7f 862 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN);
74791a2d 863
05f5799c 864 if (data->flags & MMC_DATA_READ) {
65e8b083 865 direction = DMA_FROM_DEVICE;
05f5799c
VK		 866 slave_dirn = DMA_DEV_TO_MEM;
867 } else {
65e8b083 868 direction = DMA_TO_DEVICE;
05f5799c
VK		 869 slave_dirn = DMA_MEM_TO_DEV;
870 }
65e8b083 871
266ac3f2 872 sglen = dma_map_sg(chan->device->dev, data->sg,
796211b7 873 data->sg_len, direction);
88ce4db3 874
65e8b083 875 desc = chan->device->device_prep_slave_sg(chan,
05f5799c 876 data->sg, sglen, slave_dirn,
65e8b083
HS		 877 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
878 if (!desc)
657a77fa 879 goto unmap_exit;
65e8b083
HS		 880
881 host->dma.data_desc = desc;
882 desc->callback = atmci_dma_complete;
883 desc->callback_param = host;
65e8b083 884
796211b7 885 return iflags;
657a77fa 886unmap_exit:
88ce4db3 887 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
657a77fa 888 return -ENOMEM;
65e8b083
HS		 889}
890
796211b7
LD		 891static void
892atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
893{
894 return;
895}
896
897/*
898 * Start PDC according to transfer direction.
899 */
900static void
901atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
902{
903 if (data->flags & MMC_DATA_READ)
904 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
905 else
906 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
907}
908
909static void
910atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
74791a2d
NF		 911{
912 struct dma_chan *chan = host->data_chan;
913 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
914
915 if (chan) {
5328906a
LW		 916 dmaengine_submit(desc);
917 dma_async_issue_pending(chan);
74791a2d
NF		 918 }
919}
920
796211b7 921static void atmci_stop_transfer(struct atmel_mci *host)
65e8b083 922{
65e8b083 923 atmci_set_pending(host, EVENT_XFER_COMPLETE);
03fc9a7f 924 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083
HS		 925}
926
7d2be074 927/*
796211b7 928 * Stop data transfer because error(s) occured.
7d2be074 929 */
796211b7 930static void atmci_stop_transfer_pdc(struct atmel_mci *host)
7d2be074 931{
796211b7
LD		 932 atmci_set_pending(host, EVENT_XFER_COMPLETE);
933 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
934}
965ebf33 935
796211b7
LD		 936static void atmci_stop_transfer_dma(struct atmel_mci *host)
937{
938 struct dma_chan *chan = host->data_chan;
965ebf33 939
796211b7
LD		 940 if (chan) {
941 dmaengine_terminate_all(chan);
942 atmci_dma_cleanup(host);
943 } else {
944 /* Data transfer was stopped by the interrupt handler */
945 atmci_set_pending(host, EVENT_XFER_COMPLETE);
946 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083 947 }
7d2be074
HS		 948}
949
796211b7
LD		 950/*
951 * Start a request: prepare data if needed, prepare the command and activate
952 * interrupts.
953 */
965ebf33
HS		 954static void atmci_start_request(struct atmel_mci *host,
955 struct atmel_mci_slot *slot)
7d2be074 956{
965ebf33 957 struct mmc_request *mrq;
7d2be074 958 struct mmc_command *cmd;
965ebf33 959 struct mmc_data *data;
7d2be074 960 u32 iflags;
965ebf33 961 u32 cmdflags;
7d2be074 962
965ebf33
HS		 963 mrq = slot->mrq;
964 host->cur_slot = slot;
7d2be074 965 host->mrq = mrq;
965ebf33 966
7d2be074
HS		 967 host->pending_events = 0;
968 host->completed_events = 0;
ca55f46e 969 host->data_status = 0;
7d2be074 970
965ebf33 971 if (host->need_reset) {
18ee684b
LD		 972 iflags = atmci_readl(host, ATMCI_IMR);
973 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
03fc9a7f
LD		 974 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
975 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
976 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 977 if (host->caps.has_cfg_reg)
03fc9a7f 978 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
18ee684b 979 atmci_writel(host, ATMCI_IER, iflags);
965ebf33
HS		 980 host->need_reset = false;
981 }
03fc9a7f 982 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
965ebf33 983
03fc9a7f 984 iflags = atmci_readl(host, ATMCI_IMR);
2c96a293 985 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
965ebf33
HS		 986 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
987 iflags);
988
989 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
990 /* Send init sequence (74 clock cycles) */
03fc9a7f
LD		 991 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
992 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
965ebf33
HS		 993 cpu_relax();
994 }
74791a2d 995 iflags = 0;
7d2be074
HS		 996 data = mrq->data;
997 if (data) {
965ebf33 998 atmci_set_timeout(host, slot, data);
a252e3e3
HS		 999
1000 /* Must set block count/size before sending command */
03fc9a7f 1001 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
2c96a293 1002 | ATMCI_BLKLEN(data->blksz));
965ebf33 1003 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
2c96a293 1004 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
74791a2d 1005
796211b7 1006 iflags |= host->prepare_data(host, data);
7d2be074
HS		 1007 }
1008
2c96a293 1009 iflags |= ATMCI_CMDRDY;
7d2be074 1010 cmd = mrq->cmd;
965ebf33 1011 cmdflags = atmci_prepare_command(slot->mmc, cmd);
11d1488b 1012 atmci_send_command(host, cmd, cmdflags);
7d2be074
HS		 1013
1014 if (data)
796211b7 1015 host->submit_data(host, data);
7d2be074
HS		 1016
1017 if (mrq->stop) {
965ebf33 1018 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
2c96a293 1019 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
7d2be074 1020 if (!(data->flags & MMC_DATA_WRITE))
2c96a293 1021 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
7d2be074 1022 if (data->flags & MMC_DATA_STREAM)
2c96a293 1023 host->stop_cmdr |= ATMCI_CMDR_STREAM;
7d2be074 1024 else
2c96a293 1025 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
7d2be074
HS		 1026 }
1027
1028 /*
1029 * We could have enabled interrupts earlier, but I suspect
1030 * that would open up a nice can of interesting race
1031 * conditions (e.g. command and data complete, but stop not
1032 * prepared yet.)
1033 */
03fc9a7f 1034 atmci_writel(host, ATMCI_IER, iflags);
965ebf33 1035}
7d2be074 1036
965ebf33
HS		 1037static void atmci_queue_request(struct atmel_mci *host,
1038 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1039{
1040 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1041 host->state);
1042
1043 spin_lock_bh(&host->lock);
1044 slot->mrq = mrq;
1045 if (host->state == STATE_IDLE) {
1046 host->state = STATE_SENDING_CMD;
1047 atmci_start_request(host, slot);
1048 } else {
1049 list_add_tail(&slot->queue_node, &host->queue);
1050 }
1051 spin_unlock_bh(&host->lock);
1052}
7d2be074 1053
965ebf33
HS		 1054static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1055{
1056 struct atmel_mci_slot *slot = mmc_priv(mmc);
1057 struct atmel_mci *host = slot->host;
1058 struct mmc_data *data;
1059
1060 WARN_ON(slot->mrq);
1061
1062 /*
1063 * We may "know" the card is gone even though there's still an
1064 * electrical connection. If so, we really need to communicate
1065 * this to the MMC core since there won't be any more
1066 * interrupts as the card is completely removed. Otherwise,
1067 * the MMC core might believe the card is still there even
1068 * though the card was just removed very slowly.
1069 */
1070 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1071 mrq->cmd->error = -ENOMEDIUM;
1072 mmc_request_done(mmc, mrq);
1073 return;
1074 }
1075
1076 /* We don't support multiple blocks of weird lengths. */
1077 data = mrq->data;
1078 if (data && data->blocks > 1 && data->blksz & 3) {
1079 mrq->cmd->error = -EINVAL;
1080 mmc_request_done(mmc, mrq);
1081 }
1082
1083 atmci_queue_request(host, slot, mrq);
7d2be074
HS		 1084}
1085
1086static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1087{
965ebf33
HS		 1088 struct atmel_mci_slot *slot = mmc_priv(mmc);
1089 struct atmel_mci *host = slot->host;
1090 unsigned int i;
7d2be074 1091
2c96a293 1092 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
945533b5
HS		 1093 switch (ios->bus_width) {
1094 case MMC_BUS_WIDTH_1:
2c96a293 1095 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
945533b5
HS		 1096 break;
1097 case MMC_BUS_WIDTH_4:
2c96a293 1098 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
945533b5
HS		 1099 break;
1100 }
1101
7d2be074 1102 if (ios->clock) {
965ebf33 1103 unsigned int clock_min = ~0U;
7d2be074
HS		 1104 u32 clkdiv;
1105
965ebf33
HS		 1106 spin_lock_bh(&host->lock);
1107 if (!host->mode_reg) {
945533b5 1108 clk_enable(host->mck);
03fc9a7f
LD		 1109 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1110 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
796211b7 1111 if (host->caps.has_cfg_reg)
03fc9a7f 1112 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
965ebf33 1113 }
945533b5 1114
965ebf33
HS		 1115 /*
1116 * Use mirror of ios->clock to prevent race with mmc
1117 * core ios update when finding the minimum.
1118 */
1119 slot->clock = ios->clock;
2c96a293 1120 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
965ebf33
HS		 1121 if (host->slot[i] && host->slot[i]->clock
1122 && host->slot[i]->clock < clock_min)
1123 clock_min = host->slot[i]->clock;
1124 }
1125
1126 /* Calculate clock divider */
1127 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
7d2be074
HS		 1128 if (clkdiv > 255) {
1129 dev_warn(&mmc->class_dev,
1130 "clock %u too slow; using %lu\n",
965ebf33 1131 clock_min, host->bus_hz / (2 * 256));
7d2be074
HS		 1132 clkdiv = 255;
1133 }
1134
2c96a293 1135 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
04d699c3 1136
965ebf33
HS		 1137 /*
1138 * WRPROOF and RDPROOF prevent overruns/underruns by
1139 * stopping the clock when the FIFO is full/empty.
1140 * This state is not expected to last for long.
1141 */
796211b7 1142 if (host->caps.has_rwproof)
2c96a293 1143 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
7d2be074 1144
796211b7 1145 if (host->caps.has_cfg_reg) {
99ddffd8
NF		 1146 /* setup High Speed mode in relation with card capacity */
1147 if (ios->timing == MMC_TIMING_SD_HS)
2c96a293 1148 host->cfg_reg |= ATMCI_CFG_HSMODE;
99ddffd8 1149 else
2c96a293 1150 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
99ddffd8
NF		 1151 }
1152
1153 if (list_empty(&host->queue)) {
03fc9a7f 1154 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1155 if (host->caps.has_cfg_reg)
03fc9a7f 1156 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
99ddffd8 1157 } else {
965ebf33 1158 host->need_clock_update = true;
99ddffd8 1159 }
965ebf33
HS		 1160
1161 spin_unlock_bh(&host->lock);
945533b5 1162 } else {
965ebf33
HS		 1163 bool any_slot_active = false;
1164
1165 spin_lock_bh(&host->lock);
1166 slot->clock = 0;
2c96a293 1167 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
965ebf33
HS		 1168 if (host->slot[i] && host->slot[i]->clock) {
1169 any_slot_active = true;
1170 break;
1171 }
945533b5 1172 }
965ebf33 1173 if (!any_slot_active) {
03fc9a7f 1174 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
965ebf33 1175 if (host->mode_reg) {
03fc9a7f 1176 atmci_readl(host, ATMCI_MR);
965ebf33
HS		 1177 clk_disable(host->mck);
1178 }
1179 host->mode_reg = 0;
1180 }
1181 spin_unlock_bh(&host->lock);
7d2be074
HS		 1182 }
1183
1184 switch (ios->power_mode) {
965ebf33
HS		 1185 case MMC_POWER_UP:
1186 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1187 break;
7d2be074
HS		 1188 default:
1189 /*
1190 * TODO: None of the currently available AVR32-based
1191 * boards allow MMC power to be turned off. Implement
1192 * power control when this can be tested properly.
965ebf33
HS		 1193 *
1194 * We also need to hook this into the clock management
1195 * somehow so that newly inserted cards aren't
1196 * subjected to a fast clock before we have a chance
1197 * to figure out what the maximum rate is. Currently,
1198 * there's no way to avoid this, and there never will
1199 * be for boards that don't support power control.
7d2be074
HS		 1200 */
1201 break;
1202 }
1203}
1204
1205static int atmci_get_ro(struct mmc_host *mmc)
1206{
965ebf33
HS		 1207 int read_only = -ENOSYS;
1208 struct atmel_mci_slot *slot = mmc_priv(mmc);
7d2be074 1209
965ebf33
HS		 1210 if (gpio_is_valid(slot->wp_pin)) {
1211 read_only = gpio_get_value(slot->wp_pin);
7d2be074
HS		 1212 dev_dbg(&mmc->class_dev, "card is %s\n",
1213 read_only ? "read-only" : "read-write");
7d2be074
HS		 1214 }
1215
1216 return read_only;
1217}
1218
965ebf33
HS		 1219static int atmci_get_cd(struct mmc_host *mmc)
1220{
1221 int present = -ENOSYS;
1222 struct atmel_mci_slot *slot = mmc_priv(mmc);
1223
1224 if (gpio_is_valid(slot->detect_pin)) {
1c1452be
JL		 1225 present = !(gpio_get_value(slot->detect_pin) ^
1226 slot->detect_is_active_high);
965ebf33
HS		 1227 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1228 present ? "" : "not ");
1229 }
1230
1231 return present;
1232}
1233
88ff82ed
AG		 1234static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1235{
1236 struct atmel_mci_slot *slot = mmc_priv(mmc);
1237 struct atmel_mci *host = slot->host;
1238
1239 if (enable)
03fc9a7f 1240 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
88ff82ed 1241 else
03fc9a7f 1242 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
88ff82ed
AG		 1243}
1244
965ebf33 1245static const struct mmc_host_ops atmci_ops = {
7d2be074
HS		 1246 .request = atmci_request,
1247 .set_ios = atmci_set_ios,
1248 .get_ro = atmci_get_ro,
965ebf33 1249 .get_cd = atmci_get_cd,
88ff82ed 1250 .enable_sdio_irq = atmci_enable_sdio_irq,
7d2be074
HS		 1251};
1252
965ebf33
HS		 1253/* Called with host->lock held */
1254static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1255 __releases(&host->lock)
1256 __acquires(&host->lock)
1257{
1258 struct atmel_mci_slot *slot = NULL;
1259 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1260
1261 WARN_ON(host->cmd || host->data);
1262
1263 /*
1264 * Update the MMC clock rate if necessary. This may be
1265 * necessary if set_ios() is called when a different slot is
25985edc 1266 * busy transferring data.
965ebf33 1267 */
99ddffd8 1268 if (host->need_clock_update) {
03fc9a7f 1269 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1270 if (host->caps.has_cfg_reg)
03fc9a7f 1271 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
99ddffd8 1272 }
965ebf33
HS		 1273
1274 host->cur_slot->mrq = NULL;
1275 host->mrq = NULL;
1276 if (!list_empty(&host->queue)) {
1277 slot = list_entry(host->queue.next,
1278 struct atmel_mci_slot, queue_node);
1279 list_del(&slot->queue_node);
1280 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1281 mmc_hostname(slot->mmc));
1282 host->state = STATE_SENDING_CMD;
1283 atmci_start_request(host, slot);
1284 } else {
1285 dev_vdbg(&host->pdev->dev, "list empty\n");
1286 host->state = STATE_IDLE;
1287 }
1288
1289 spin_unlock(&host->lock);
1290 mmc_request_done(prev_mmc, mrq);
1291 spin_lock(&host->lock);
1292}
1293
7d2be074 1294static void atmci_command_complete(struct atmel_mci *host,
c06ad258 1295 struct mmc_command *cmd)
7d2be074 1296{
c06ad258
HS		 1297 u32 status = host->cmd_status;
1298
7d2be074 1299 /* Read the response from the card (up to 16 bytes) */
03fc9a7f
LD		 1300 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1301 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1302 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1303 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
7d2be074 1304
2c96a293 1305 if (status & ATMCI_RTOE)
7d2be074 1306 cmd->error = -ETIMEDOUT;
2c96a293 1307 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
7d2be074 1308 cmd->error = -EILSEQ;
2c96a293 1309 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
7d2be074
HS		 1310 cmd->error = -EIO;
1311 else
1312 cmd->error = 0;
1313
1314 if (cmd->error) {
965ebf33 1315 dev_dbg(&host->pdev->dev,
7d2be074
HS		 1316 "command error: status=0x%08x\n", status);
1317
1318 if (cmd->data) {
796211b7 1319 host->stop_transfer(host);
009a891b 1320 host->data = NULL;
03fc9a7f 1321 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY
2c96a293 1322 | ATMCI_TXRDY | ATMCI_RXRDY
7d2be074
HS		 1323 | ATMCI_DATA_ERROR_FLAGS);
1324 }
1325 }
1326}
1327
1328static void atmci_detect_change(unsigned long data)
1329{
965ebf33
HS		 1330 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1331 bool present;
1332 bool present_old;
7d2be074
HS		 1333
1334 /*
965ebf33
HS		 1335 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1336 * freeing the interrupt. We must not re-enable the interrupt
1337 * if it has been freed, and if we're shutting down, it
1338 * doesn't really matter whether the card is present or not.
7d2be074
HS		 1339 */
1340 smp_rmb();
965ebf33 1341 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
7d2be074
HS		 1342 return;
1343
965ebf33 1344 enable_irq(gpio_to_irq(slot->detect_pin));
1c1452be
JL		 1345 present = !(gpio_get_value(slot->detect_pin) ^
1346 slot->detect_is_active_high);
965ebf33 1347 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
7d2be074 1348
965ebf33
HS		 1349 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1350 present, present_old);
7d2be074 1351
965ebf33
HS		 1352 if (present != present_old) {
1353 struct atmel_mci *host = slot->host;
1354 struct mmc_request *mrq;
1355
1356 dev_dbg(&slot->mmc->class_dev, "card %s\n",
7d2be074 1357 present ? "inserted" : "removed");
7d2be074 1358
965ebf33
HS		 1359 spin_lock(&host->lock);
1360
1361 if (!present)
1362 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1363 else
1364 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
7d2be074
HS		 1365
1366 /* Clean up queue if present */
965ebf33 1367 mrq = slot->mrq;
7d2be074 1368 if (mrq) {
965ebf33
HS		 1369 if (mrq == host->mrq) {
1370 /*
1371 * Reset controller to terminate any ongoing
1372 * commands or data transfers.
1373 */
03fc9a7f
LD		 1374 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1375 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1376 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1377 if (host->caps.has_cfg_reg)
03fc9a7f 1378 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
965ebf33
HS		 1379
1380 host->data = NULL;
1381 host->cmd = NULL;
1382
1383 switch (host->state) {
1384 case STATE_IDLE:
c06ad258 1385 break;
965ebf33
HS		 1386 case STATE_SENDING_CMD:
1387 mrq->cmd->error = -ENOMEDIUM;
1388 if (!mrq->data)
1389 break;
1390 /* fall through */
1391 case STATE_SENDING_DATA:
c06ad258 1392 mrq->data->error = -ENOMEDIUM;
796211b7 1393 host->stop_transfer(host);
c06ad258 1394 break;
965ebf33
HS		 1395 case STATE_DATA_BUSY:
1396 case STATE_DATA_ERROR:
1397 if (mrq->data->error == -EINPROGRESS)
1398 mrq->data->error = -ENOMEDIUM;
1399 if (!mrq->stop)
1400 break;
1401 /* fall through */
1402 case STATE_SENDING_STOP:
1403 mrq->stop->error = -ENOMEDIUM;
1404 break;
1405 }
7d2be074 1406
965ebf33
HS		 1407 atmci_request_end(host, mrq);
1408 } else {
1409 list_del(&slot->queue_node);
1410 mrq->cmd->error = -ENOMEDIUM;
1411 if (mrq->data)
1412 mrq->data->error = -ENOMEDIUM;
1413 if (mrq->stop)
1414 mrq->stop->error = -ENOMEDIUM;
1415
1416 spin_unlock(&host->lock);
1417 mmc_request_done(slot->mmc, mrq);
1418 spin_lock(&host->lock);
1419 }
7d2be074 1420 }
965ebf33 1421 spin_unlock(&host->lock);
7d2be074 1422
965ebf33 1423 mmc_detect_change(slot->mmc, 0);
7d2be074
HS		 1424 }
1425}
1426
1427static void atmci_tasklet_func(unsigned long priv)
1428{
965ebf33 1429 struct atmel_mci *host = (struct atmel_mci *)priv;
7d2be074
HS		 1430 struct mmc_request *mrq = host->mrq;
1431 struct mmc_data *data = host->data;
c06ad258
HS		 1432 struct mmc_command *cmd = host->cmd;
1433 enum atmel_mci_state state = host->state;
1434 enum atmel_mci_state prev_state;
1435 u32 status;
1436
965ebf33
HS		 1437 spin_lock(&host->lock);
1438
c06ad258 1439 state = host->state;
7d2be074 1440
965ebf33 1441 dev_vdbg(&host->pdev->dev,
c06ad258
HS		 1442 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1443 state, host->pending_events, host->completed_events,
03fc9a7f 1444 atmci_readl(host, ATMCI_IMR));
7d2be074 1445
c06ad258
HS		 1446 do {
1447 prev_state = state;
7d2be074 1448
c06ad258 1449 switch (state) {
965ebf33
HS		 1450 case STATE_IDLE:
1451 break;
1452
c06ad258
HS		 1453 case STATE_SENDING_CMD:
1454 if (!atmci_test_and_clear_pending(host,
1455 EVENT_CMD_COMPLETE))
1456 break;
7d2be074 1457
c06ad258
HS		 1458 host->cmd = NULL;
1459 atmci_set_completed(host, EVENT_CMD_COMPLETE);
1460 atmci_command_complete(host, mrq->cmd);
1461 if (!mrq->data || cmd->error) {
965ebf33
HS		 1462 atmci_request_end(host, host->mrq);
1463 goto unlock;
c06ad258 1464 }
7d2be074 1465
c06ad258
HS		 1466 prev_state = state = STATE_SENDING_DATA;
1467 /* fall through */
7d2be074 1468
c06ad258
HS		 1469 case STATE_SENDING_DATA:
1470 if (atmci_test_and_clear_pending(host,
1471 EVENT_DATA_ERROR)) {
796211b7 1472 host->stop_transfer(host);
c06ad258 1473 if (data->stop)
2c96a293 1474 atmci_send_stop_cmd(host, data);
c06ad258
HS		 1475 state = STATE_DATA_ERROR;
1476 break;
1477 }
7d2be074 1478
c06ad258
HS		 1479 if (!atmci_test_and_clear_pending(host,
1480 EVENT_XFER_COMPLETE))
1481 break;
7d2be074 1482
c06ad258
HS		 1483 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1484 prev_state = state = STATE_DATA_BUSY;
1485 /* fall through */
7d2be074 1486
c06ad258
HS		 1487 case STATE_DATA_BUSY:
1488 if (!atmci_test_and_clear_pending(host,
1489 EVENT_DATA_COMPLETE))
1490 break;
1491
1492 host->data = NULL;
1493 atmci_set_completed(host, EVENT_DATA_COMPLETE);
1494 status = host->data_status;
1495 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
2c96a293 1496 if (status & ATMCI_DTOE) {
965ebf33 1497 dev_dbg(&host->pdev->dev,
c06ad258
HS		 1498 "data timeout error\n");
1499 data->error = -ETIMEDOUT;
2c96a293 1500 } else if (status & ATMCI_DCRCE) {
965ebf33 1501 dev_dbg(&host->pdev->dev,
c06ad258
HS		 1502 "data CRC error\n");
1503 data->error = -EILSEQ;
1504 } else {
965ebf33 1505 dev_dbg(&host->pdev->dev,
c06ad258
HS		 1506 "data FIFO error (status=%08x)\n",
1507 status);
1508 data->error = -EIO;
1509 }
1510 } else {
1511 data->bytes_xfered = data->blocks * data->blksz;
1512 data->error = 0;
03fc9a7f 1513 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS);
c06ad258
HS		 1514 }
1515
1516 if (!data->stop) {
965ebf33
HS		 1517 atmci_request_end(host, host->mrq);
1518 goto unlock;
c06ad258 1519 }
7d2be074 1520
c06ad258
HS		 1521 prev_state = state = STATE_SENDING_STOP;
1522 if (!data->error)
2c96a293 1523 atmci_send_stop_cmd(host, data);
c06ad258
HS		 1524 /* fall through */
1525
1526 case STATE_SENDING_STOP:
1527 if (!atmci_test_and_clear_pending(host,
1528 EVENT_CMD_COMPLETE))
1529 break;
1530
1531 host->cmd = NULL;
1532 atmci_command_complete(host, mrq->stop);
965ebf33
HS		 1533 atmci_request_end(host, host->mrq);
1534 goto unlock;
c06ad258
HS		 1535
1536 case STATE_DATA_ERROR:
1537 if (!atmci_test_and_clear_pending(host,
1538 EVENT_XFER_COMPLETE))
1539 break;
1540
1541 state = STATE_DATA_BUSY;
1542 break;
1543 }
1544 } while (state != prev_state);
1545
1546 host->state = state;
965ebf33
HS		 1547
1548unlock:
1549 spin_unlock(&host->lock);
7d2be074
HS		 1550}
1551
1552static void atmci_read_data_pio(struct atmel_mci *host)
1553{
1554 struct scatterlist *sg = host->sg;
1555 void *buf = sg_virt(sg);
1556 unsigned int offset = host->pio_offset;
1557 struct mmc_data *data = host->data;
1558 u32 value;
1559 u32 status;
1560 unsigned int nbytes = 0;
1561
1562 do {
03fc9a7f 1563 value = atmci_readl(host, ATMCI_RDR);
7d2be074
HS		 1564 if (likely(offset + 4 <= sg->length)) {
1565 put_unaligned(value, (u32 *)(buf + offset));
1566
1567 offset += 4;
1568 nbytes += 4;
1569
1570 if (offset == sg->length) {
5e7184ae 1571 flush_dcache_page(sg_page(sg));
7d2be074
HS		 1572 host->sg = sg = sg_next(sg);
1573 if (!sg)
1574 goto done;
1575
1576 offset = 0;
1577 buf = sg_virt(sg);
1578 }
1579 } else {
1580 unsigned int remaining = sg->length - offset;
1581 memcpy(buf + offset, &value, remaining);
1582 nbytes += remaining;
1583
1584 flush_dcache_page(sg_page(sg));
1585 host->sg = sg = sg_next(sg);
1586 if (!sg)
1587 goto done;
1588
1589 offset = 4 - remaining;
1590 buf = sg_virt(sg);
1591 memcpy(buf, (u8 *)&value + remaining, offset);
1592 nbytes += offset;
1593 }
1594
03fc9a7f 1595 status = atmci_readl(host, ATMCI_SR);
7d2be074 1596 if (status & ATMCI_DATA_ERROR_FLAGS) {
03fc9a7f 1597 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
7d2be074
HS		 1598 | ATMCI_DATA_ERROR_FLAGS));
1599 host->data_status = status;
965ebf33
HS		 1600 data->bytes_xfered += nbytes;
1601 smp_wmb();
7d2be074
HS		 1602 atmci_set_pending(host, EVENT_DATA_ERROR);
1603 tasklet_schedule(&host->tasklet);
965ebf33 1604 return;
7d2be074 1605 }
2c96a293 1606 } while (status & ATMCI_RXRDY);
7d2be074
HS		 1607
1608 host->pio_offset = offset;
1609 data->bytes_xfered += nbytes;
1610
1611 return;
1612
1613done:
03fc9a7f
LD		 1614 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1615 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
7d2be074 1616 data->bytes_xfered += nbytes;
965ebf33 1617 smp_wmb();
c06ad258 1618 atmci_set_pending(host, EVENT_XFER_COMPLETE);
7d2be074
HS		 1619}
1620
1621static void atmci_write_data_pio(struct atmel_mci *host)
1622{
1623 struct scatterlist *sg = host->sg;
1624 void *buf = sg_virt(sg);
1625 unsigned int offset = host->pio_offset;
1626 struct mmc_data *data = host->data;
1627 u32 value;
1628 u32 status;
1629 unsigned int nbytes = 0;
1630
1631 do {
1632 if (likely(offset + 4 <= sg->length)) {
1633 value = get_unaligned((u32 *)(buf + offset));
03fc9a7f 1634 atmci_writel(host, ATMCI_TDR, value);
7d2be074
HS		 1635
1636 offset += 4;
1637 nbytes += 4;
1638 if (offset == sg->length) {
1639 host->sg = sg = sg_next(sg);
1640 if (!sg)
1641 goto done;
1642
1643 offset = 0;
1644 buf = sg_virt(sg);
1645 }
1646 } else {
1647 unsigned int remaining = sg->length - offset;
1648
1649 value = 0;
1650 memcpy(&value, buf + offset, remaining);
1651 nbytes += remaining;
1652
1653 host->sg = sg = sg_next(sg);
1654 if (!sg) {
03fc9a7f 1655 atmci_writel(host, ATMCI_TDR, value);
7d2be074
HS		 1656 goto done;
1657 }
1658
1659 offset = 4 - remaining;
1660 buf = sg_virt(sg);
1661 memcpy((u8 *)&value + remaining, buf, offset);
03fc9a7f 1662 atmci_writel(host, ATMCI_TDR, value);
7d2be074
HS		 1663 nbytes += offset;
1664 }
1665
03fc9a7f 1666 status = atmci_readl(host, ATMCI_SR);
7d2be074 1667 if (status & ATMCI_DATA_ERROR_FLAGS) {
03fc9a7f 1668 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
7d2be074
HS		 1669 | ATMCI_DATA_ERROR_FLAGS));
1670 host->data_status = status;
965ebf33
HS		 1671 data->bytes_xfered += nbytes;
1672 smp_wmb();
7d2be074
HS		 1673 atmci_set_pending(host, EVENT_DATA_ERROR);
1674 tasklet_schedule(&host->tasklet);
965ebf33 1675 return;
7d2be074 1676 }
2c96a293 1677 } while (status & ATMCI_TXRDY);
7d2be074
HS		 1678
1679 host->pio_offset = offset;
1680 data->bytes_xfered += nbytes;
1681
1682 return;
1683
1684done:
03fc9a7f
LD		 1685 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1686 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
7d2be074 1687 data->bytes_xfered += nbytes;
965ebf33 1688 smp_wmb();
c06ad258 1689 atmci_set_pending(host, EVENT_XFER_COMPLETE);
7d2be074
HS		 1690}
1691
965ebf33 1692static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
7d2be074 1693{
03fc9a7f 1694 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
7d2be074 1695
c06ad258 1696 host->cmd_status = status;
965ebf33 1697 smp_wmb();
c06ad258 1698 atmci_set_pending(host, EVENT_CMD_COMPLETE);
7d2be074
HS		 1699 tasklet_schedule(&host->tasklet);
1700}
1701
88ff82ed
AG		 1702static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1703{
1704 int i;
1705
2c96a293 1706 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
88ff82ed
AG		 1707 struct atmel_mci_slot *slot = host->slot[i];
1708 if (slot && (status & slot->sdio_irq)) {
1709 mmc_signal_sdio_irq(slot->mmc);
1710 }
1711 }
1712}
1713
1714
7d2be074
HS		 1715static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1716{
965ebf33 1717 struct atmel_mci *host = dev_id;
7d2be074
HS		 1718 u32 status, mask, pending;
1719 unsigned int pass_count = 0;
1720
7d2be074 1721 do {
03fc9a7f
LD		 1722 status = atmci_readl(host, ATMCI_SR);
1723 mask = atmci_readl(host, ATMCI_IMR);
7d2be074
HS		 1724 pending = status & mask;
1725 if (!pending)
1726 break;
1727
1728 if (pending & ATMCI_DATA_ERROR_FLAGS) {
03fc9a7f 1729 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2c96a293 1730 | ATMCI_RXRDY | ATMCI_TXRDY);
03fc9a7f 1731 pending &= atmci_readl(host, ATMCI_IMR);
965ebf33 1732
7d2be074 1733 host->data_status = status;
965ebf33 1734 smp_wmb();
7d2be074
HS		 1735 atmci_set_pending(host, EVENT_DATA_ERROR);
1736 tasklet_schedule(&host->tasklet);
1737 }
796211b7 1738
796211b7
LD		 1739 if (pending & ATMCI_TXBUFE) {
1740 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
7e8ba228 1741 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
796211b7
LD		 1742 /*
1743 * We can receive this interruption before having configured
1744 * the second pdc buffer, so we need to reconfigure first and
1745 * second buffers again
1746 */
1747 if (host->data_size) {
1748 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
7e8ba228 1749 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
796211b7
LD		 1750 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
1751 } else {
1752 atmci_pdc_complete(host);
1753 }
7e8ba228
LD		 1754 } else if (pending & ATMCI_ENDTX) {
1755 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
796211b7
LD		 1756
1757 if (host->data_size) {
1758 atmci_pdc_set_single_buf(host,
7e8ba228
LD		 1759 XFER_TRANSMIT, PDC_SECOND_BUF);
1760 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
796211b7
LD		 1761 }
1762 }
1763
1764 if (pending & ATMCI_RXBUFF) {
1765 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
7e8ba228 1766 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
796211b7
LD		 1767 /*
1768 * We can receive this interruption before having configured
1769 * the second pdc buffer, so we need to reconfigure first and
1770 * second buffers again
1771 */
1772 if (host->data_size) {
1773 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
7e8ba228 1774 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
796211b7
LD		 1775 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
1776 } else {
1777 atmci_pdc_complete(host);
1778 }
7e8ba228
LD		 1779 } else if (pending & ATMCI_ENDRX) {
1780 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1781
1782 if (host->data_size) {
1783 atmci_pdc_set_single_buf(host,
1784 XFER_RECEIVE, PDC_SECOND_BUF);
1785 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1786 }
796211b7
LD		 1787 }
1788
7e8ba228 1789
2c96a293 1790 if (pending & ATMCI_NOTBUSY) {
03fc9a7f 1791 atmci_writel(host, ATMCI_IDR,
2c96a293 1792 ATMCI_DATA_ERROR_FLAGS | ATMCI_NOTBUSY);
ca55f46e
HS		 1793 if (!host->data_status)
1794 host->data_status = status;
965ebf33 1795 smp_wmb();
7d2be074
HS		 1796 atmci_set_pending(host, EVENT_DATA_COMPLETE);
1797 tasklet_schedule(&host->tasklet);
1798 }
2c96a293 1799 if (pending & ATMCI_RXRDY)
7d2be074 1800 atmci_read_data_pio(host);
2c96a293 1801 if (pending & ATMCI_TXRDY)
7d2be074
HS		 1802 atmci_write_data_pio(host);
1803
2c96a293 1804 if (pending & ATMCI_CMDRDY)
965ebf33 1805 atmci_cmd_interrupt(host, status);
88ff82ed 1806
2c96a293 1807 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
88ff82ed
AG		 1808 atmci_sdio_interrupt(host, status);
1809
7d2be074
HS		 1810 } while (pass_count++ < 5);
1811
7d2be074
HS		 1812 return pass_count ? IRQ_HANDLED : IRQ_NONE;
1813}
1814
1815static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
1816{
965ebf33 1817 struct atmel_mci_slot *slot = dev_id;
7d2be074
HS		 1818
1819 /*
1820 * Disable interrupts until the pin has stabilized and check
1821 * the state then. Use mod_timer() since we may be in the
1822 * middle of the timer routine when this interrupt triggers.
1823 */
1824 disable_irq_nosync(irq);
965ebf33 1825 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
7d2be074
HS		 1826
1827 return IRQ_HANDLED;
1828}
1829
965ebf33
HS		 1830static int __init atmci_init_slot(struct atmel_mci *host,
1831 struct mci_slot_pdata *slot_data, unsigned int id,
88ff82ed 1832 u32 sdc_reg, u32 sdio_irq)
965ebf33
HS		 1833{
1834 struct mmc_host *mmc;
1835 struct atmel_mci_slot *slot;
1836
1837 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
1838 if (!mmc)
1839 return -ENOMEM;
1840
1841 slot = mmc_priv(mmc);
1842 slot->mmc = mmc;
1843 slot->host = host;
1844 slot->detect_pin = slot_data->detect_pin;
1845 slot->wp_pin = slot_data->wp_pin;
1c1452be 1846 slot->detect_is_active_high = slot_data->detect_is_active_high;
965ebf33 1847 slot->sdc_reg = sdc_reg;
88ff82ed 1848 slot->sdio_irq = sdio_irq;
965ebf33
HS		 1849
1850 mmc->ops = &atmci_ops;
1851 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
1852 mmc->f_max = host->bus_hz / 2;
1853 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
88ff82ed
AG		 1854 if (sdio_irq)
1855 mmc->caps |= MMC_CAP_SDIO_IRQ;
796211b7 1856 if (host->caps.has_highspeed)
99ddffd8 1857 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
965ebf33
HS		 1858 if (slot_data->bus_width >= 4)
1859 mmc->caps |= MMC_CAP_4_BIT_DATA;
1860
a36274e0 1861 mmc->max_segs = 64;
965ebf33
HS		 1862 mmc->max_req_size = 32768 * 512;
1863 mmc->max_blk_size = 32768;
1864 mmc->max_blk_count = 512;
1865
1866 /* Assume card is present initially */
1867 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1868 if (gpio_is_valid(slot->detect_pin)) {
1869 if (gpio_request(slot->detect_pin, "mmc_detect")) {
1870 dev_dbg(&mmc->class_dev, "no detect pin available\n");
1871 slot->detect_pin = -EBUSY;
1c1452be
JL		 1872 } else if (gpio_get_value(slot->detect_pin) ^
1873 slot->detect_is_active_high) {
965ebf33
HS		 1874 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1875 }
1876 }
1877
1878 if (!gpio_is_valid(slot->detect_pin))
1879 mmc->caps |= MMC_CAP_NEEDS_POLL;
1880
1881 if (gpio_is_valid(slot->wp_pin)) {
1882 if (gpio_request(slot->wp_pin, "mmc_wp")) {
1883 dev_dbg(&mmc->class_dev, "no WP pin available\n");
1884 slot->wp_pin = -EBUSY;
1885 }
1886 }
1887
1888 host->slot[id] = slot;
1889 mmc_add_host(mmc);
1890
1891 if (gpio_is_valid(slot->detect_pin)) {
1892 int ret;
1893
1894 setup_timer(&slot->detect_timer, atmci_detect_change,
1895 (unsigned long)slot);
1896
1897 ret = request_irq(gpio_to_irq(slot->detect_pin),
1898 atmci_detect_interrupt,
1899 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1900 "mmc-detect", slot);
1901 if (ret) {
1902 dev_dbg(&mmc->class_dev,
1903 "could not request IRQ %d for detect pin\n",
1904 gpio_to_irq(slot->detect_pin));
1905 gpio_free(slot->detect_pin);
1906 slot->detect_pin = -EBUSY;
1907 }
1908 }
1909
1910 atmci_init_debugfs(slot);
1911
1912 return 0;
1913}
1914
1915static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
1916 unsigned int id)
1917{
1918 /* Debugfs stuff is cleaned up by mmc core */
1919
1920 set_bit(ATMCI_SHUTDOWN, &slot->flags);
1921 smp_wmb();
1922
1923 mmc_remove_host(slot->mmc);
1924
1925 if (gpio_is_valid(slot->detect_pin)) {
1926 int pin = slot->detect_pin;
1927
1928 free_irq(gpio_to_irq(pin), slot);
1929 del_timer_sync(&slot->detect_timer);
1930 gpio_free(pin);
1931 }
1932 if (gpio_is_valid(slot->wp_pin))
1933 gpio_free(slot->wp_pin);
1934
1935 slot->host->slot[id] = NULL;
1936 mmc_free_host(slot->mmc);
1937}
1938
2c96a293 1939static bool atmci_filter(struct dma_chan *chan, void *slave)
74465b4f 1940{
2635d1ba 1941 struct mci_dma_data *sl = slave;
74465b4f 1942
2635d1ba
NF		 1943 if (sl && find_slave_dev(sl) == chan->device->dev) {
1944 chan->private = slave_data_ptr(sl);
7dd60251 1945 return true;
2635d1ba 1946 } else {
7dd60251 1947 return false;
2635d1ba 1948 }
74465b4f 1949}
2635d1ba 1950
ef878198 1951static bool atmci_configure_dma(struct atmel_mci *host)
2635d1ba
NF		 1952{
1953 struct mci_platform_data *pdata;
1954
1955 if (host == NULL)
ef878198 1956 return false;
2635d1ba
NF		 1957
1958 pdata = host->pdev->dev.platform_data;
1959
1960 if (pdata && find_slave_dev(pdata->dma_slave)) {
1961 dma_cap_mask_t mask;
1962
1963 setup_dma_addr(pdata->dma_slave,
2c96a293
LD		 1964 host->mapbase + ATMCI_TDR,
1965 host->mapbase + ATMCI_RDR);
2635d1ba
NF		 1966
1967 /* Try to grab a DMA channel */
1968 dma_cap_zero(mask);
1969 dma_cap_set(DMA_SLAVE, mask);
1970 host->dma.chan =
2c96a293 1971 dma_request_channel(mask, atmci_filter, pdata->dma_slave);
2635d1ba 1972 }
ef878198
LD		 1973 if (!host->dma.chan) {
1974 dev_warn(&host->pdev->dev, "no DMA channel available\n");
1975 return false;
1976 } else {
74791a2d
NF		 1977 dev_info(&host->pdev->dev,
1978 "Using %s for DMA transfers\n",
1979 dma_chan_name(host->dma.chan));
ef878198
LD		 1980 return true;
1981 }
2635d1ba 1982}
796211b7
LD		 1983
1984static inline unsigned int atmci_get_version(struct atmel_mci *host)
1985{
1986 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
1987}
1988
1989/*
1990 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
1991 * HSMCI provides DMA support and a new config register but no more supports
1992 * PDC.
1993 */
1994static void __init atmci_get_cap(struct atmel_mci *host)
1995{
1996 unsigned int version;
1997
1998 version = atmci_get_version(host);
1999 dev_info(&host->pdev->dev,
2000 "version: 0x%x\n", version);
2001
2002 host->caps.has_dma = 0;
2003 host->caps.has_pdc = 0;
2004 host->caps.has_cfg_reg = 0;
2005 host->caps.has_cstor_reg = 0;
2006 host->caps.has_highspeed = 0;
2007 host->caps.has_rwproof = 0;
2008
2009 /* keep only major version number */
2010 switch (version & 0xf00) {
2011 case 0x100:
2012 case 0x200:
2013 host->caps.has_pdc = 1;
2014 host->caps.has_rwproof = 1;
2015 break;
2016 case 0x300:
2017 case 0x400:
2018 case 0x500:
2019#ifdef CONFIG_AT_HDMAC
2020 host->caps.has_dma = 1;
2635d1ba 2021#else
796211b7
LD		 2022 host->caps.has_dma = 0;
2023 dev_info(&host->pdev->dev,
2024 "has dma capability but dma engine is not selected, then use pio\n");
74465b4f 2025#endif
796211b7
LD		 2026 host->caps.has_cfg_reg = 1;
2027 host->caps.has_cstor_reg = 1;
2028 host->caps.has_highspeed = 1;
2029 host->caps.has_rwproof = 1;
2030 break;
2031 default:
2032 dev_warn(&host->pdev->dev,
2033 "Unmanaged mci version, set minimum capabilities\n");
2034 break;
2035 }
2036}
74465b4f 2037
7d2be074
HS		 2038static int __init atmci_probe(struct platform_device *pdev)
2039{
2040 struct mci_platform_data *pdata;
965ebf33
HS		 2041 struct atmel_mci *host;
2042 struct resource *regs;
2043 unsigned int nr_slots;
2044 int irq;
2045 int ret;
7d2be074
HS		 2046
2047 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2048 if (!regs)
2049 return -ENXIO;
2050 pdata = pdev->dev.platform_data;
2051 if (!pdata)
2052 return -ENXIO;
2053 irq = platform_get_irq(pdev, 0);
2054 if (irq < 0)
2055 return irq;
2056
965ebf33
HS		 2057 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2058 if (!host)
7d2be074
HS		 2059 return -ENOMEM;
2060
7d2be074 2061 host->pdev = pdev;
965ebf33
HS		 2062 spin_lock_init(&host->lock);
2063 INIT_LIST_HEAD(&host->queue);
7d2be074
HS		 2064
2065 host->mck = clk_get(&pdev->dev, "mci_clk");
2066 if (IS_ERR(host->mck)) {
2067 ret = PTR_ERR(host->mck);
2068 goto err_clk_get;
2069 }
2070
2071 ret = -ENOMEM;
e8e3f6ca 2072 host->regs = ioremap(regs->start, resource_size(regs));
7d2be074
HS		 2073 if (!host->regs)
2074 goto err_ioremap;
2075
2076 clk_enable(host->mck);
03fc9a7f 2077 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
7d2be074
HS		 2078 host->bus_hz = clk_get_rate(host->mck);
2079 clk_disable(host->mck);
2080
2081 host->mapbase = regs->start;
2082
965ebf33 2083 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
7d2be074 2084
89c8aa20 2085 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
7d2be074
HS		 2086 if (ret)
2087 goto err_request_irq;
2088
796211b7
LD		 2089 /* Get MCI capabilities and set operations according to it */
2090 atmci_get_cap(host);
ef878198 2091 if (host->caps.has_dma && atmci_configure_dma(host)) {
796211b7
LD		 2092 host->prepare_data = &atmci_prepare_data_dma;
2093 host->submit_data = &atmci_submit_data_dma;
2094 host->stop_transfer = &atmci_stop_transfer_dma;
2095 } else if (host->caps.has_pdc) {
2096 dev_info(&pdev->dev, "using PDC\n");
2097 host->prepare_data = &atmci_prepare_data_pdc;
2098 host->submit_data = &atmci_submit_data_pdc;
2099 host->stop_transfer = &atmci_stop_transfer_pdc;
2100 } else {
ef878198 2101 dev_info(&pdev->dev, "using PIO\n");
796211b7
LD		 2102 host->prepare_data = &atmci_prepare_data;
2103 host->submit_data = &atmci_submit_data;
2104 host->stop_transfer = &atmci_stop_transfer;
2105 }
2106
7d2be074
HS		 2107 platform_set_drvdata(pdev, host);
2108
965ebf33
HS		 2109 /* We need at least one slot to succeed */
2110 nr_slots = 0;
2111 ret = -ENODEV;
2112 if (pdata->slot[0].bus_width) {
2113 ret = atmci_init_slot(host, &pdata->slot[0],
2c96a293 2114 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
965ebf33
HS		 2115 if (!ret)
2116 nr_slots++;
2117 }
2118 if (pdata->slot[1].bus_width) {
2119 ret = atmci_init_slot(host, &pdata->slot[1],
2c96a293 2120 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
965ebf33
HS		 2121 if (!ret)
2122 nr_slots++;
7d2be074
HS		 2123 }
2124
04d699c3
RE		 2125 if (!nr_slots) {
2126 dev_err(&pdev->dev, "init failed: no slot defined\n");
965ebf33 2127 goto err_init_slot;
04d699c3 2128 }
7d2be074 2129
965ebf33
HS		 2130 dev_info(&pdev->dev,
2131 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2132 host->mapbase, irq, nr_slots);
deec9ae3 2133
7d2be074
HS		 2134 return 0;
2135
965ebf33 2136err_init_slot:
74465b4f
DW		 2137 if (host->dma.chan)
2138 dma_release_channel(host->dma.chan);
965ebf33 2139 free_irq(irq, host);
7d2be074
HS		 2140err_request_irq:
2141 iounmap(host->regs);
2142err_ioremap:
2143 clk_put(host->mck);
2144err_clk_get:
965ebf33 2145 kfree(host);
7d2be074
HS		 2146 return ret;
2147}
2148
2149static int __exit atmci_remove(struct platform_device *pdev)
2150{
965ebf33
HS		 2151 struct atmel_mci *host = platform_get_drvdata(pdev);
2152 unsigned int i;
7d2be074
HS		 2153
2154 platform_set_drvdata(pdev, NULL);
2155
2c96a293 2156 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
965ebf33
HS		 2157 if (host->slot[i])
2158 atmci_cleanup_slot(host->slot[i], i);
2159 }
7d2be074 2160
965ebf33 2161 clk_enable(host->mck);
03fc9a7f
LD		 2162 atmci_writel(host, ATMCI_IDR, ~0UL);
2163 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2164 atmci_readl(host, ATMCI_SR);
965ebf33 2165 clk_disable(host->mck);
7d2be074 2166
65e8b083 2167#ifdef CONFIG_MMC_ATMELMCI_DMA
74465b4f
DW		 2168 if (host->dma.chan)
2169 dma_release_channel(host->dma.chan);
65e8b083
HS		 2170#endif
2171
965ebf33
HS		 2172 free_irq(platform_get_irq(pdev, 0), host);
2173 iounmap(host->regs);
7d2be074 2174
965ebf33
HS		 2175 clk_put(host->mck);
2176 kfree(host);
7d2be074 2177
7d2be074
HS		 2178 return 0;
2179}
2180
5c2f2b9b
NF		 2181#ifdef CONFIG_PM
2182static int atmci_suspend(struct device *dev)
2183{
2184 struct atmel_mci *host = dev_get_drvdata(dev);
2185 int i;
2186
2c96a293 2187 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
5c2f2b9b
NF		 2188 struct atmel_mci_slot *slot = host->slot[i];
2189 int ret;
2190
2191 if (!slot)
2192 continue;
2193 ret = mmc_suspend_host(slot->mmc);
2194 if (ret < 0) {
2195 while (--i >= 0) {
2196 slot = host->slot[i];
2197 if (slot
2198 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2199 mmc_resume_host(host->slot[i]->mmc);
2200 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2201 }
2202 }
2203 return ret;
2204 } else {
2205 set_bit(ATMCI_SUSPENDED, &slot->flags);
2206 }
2207 }
2208
2209 return 0;
2210}
2211
2212static int atmci_resume(struct device *dev)
2213{
2214 struct atmel_mci *host = dev_get_drvdata(dev);
2215 int i;
2216 int ret = 0;
2217
2c96a293 2218 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
5c2f2b9b
NF		 2219 struct atmel_mci_slot *slot = host->slot[i];
2220 int err;
2221
2222 slot = host->slot[i];
2223 if (!slot)
2224 continue;
2225 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2226 continue;
2227 err = mmc_resume_host(slot->mmc);
2228 if (err < 0)
2229 ret = err;
2230 else
2231 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2232 }
2233
2234 return ret;
2235}
2236static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2237#define ATMCI_PM_OPS (&atmci_pm)
2238#else
2239#define ATMCI_PM_OPS NULL
2240#endif
2241
7d2be074
HS		 2242static struct platform_driver atmci_driver = {
2243 .remove = __exit_p(atmci_remove),
2244 .driver = {
2245 .name = "atmel_mci",
5c2f2b9b 2246 .pm = ATMCI_PM_OPS,
7d2be074
HS		 2247 },
2248};
2249
2250static int __init atmci_init(void)
2251{
2252 return platform_driver_probe(&atmci_driver, atmci_probe);
2253}
2254
2255static void __exit atmci_exit(void)
2256{
2257 platform_driver_unregister(&atmci_driver);
2258}
2259
74465b4f 2260late_initcall(atmci_init); /* try to load after dma driver when built-in */
7d2be074
HS		 2261module_exit(atmci_exit);
2262
2263MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
e05503ef 2264MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
7d2be074 2265MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)