Commit | Line | Data |
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7d2be074 HS |
1 | /* |
2 | * Atmel MultiMedia Card Interface driver | |
3 | * | |
4 | * Copyright (C) 2004-2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/blkdev.h> | |
11 | #include <linux/clk.h> | |
deec9ae3 | 12 | #include <linux/debugfs.h> |
7d2be074 | 13 | #include <linux/device.h> |
65e8b083 HS |
14 | #include <linux/dmaengine.h> |
15 | #include <linux/dma-mapping.h> | |
fbfca4b8 | 16 | #include <linux/err.h> |
3c26e170 | 17 | #include <linux/gpio.h> |
7d2be074 HS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/scatterlist.h> | |
deec9ae3 | 24 | #include <linux/seq_file.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
deec9ae3 | 26 | #include <linux/stat.h> |
7d2be074 HS |
27 | |
28 | #include <linux/mmc/host.h> | |
2635d1ba NF |
29 | |
30 | #include <mach/atmel-mci.h> | |
c42aa775 | 31 | #include <linux/atmel-mci.h> |
7d2be074 | 32 | |
7d2be074 HS |
33 | #include <asm/io.h> |
34 | #include <asm/unaligned.h> | |
35 | ||
04d699c3 | 36 | #include <mach/cpu.h> |
3663b736 | 37 | #include <mach/board.h> |
7d2be074 HS |
38 | |
39 | #include "atmel-mci-regs.h" | |
40 | ||
41 | #define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE) | |
65e8b083 | 42 | #define ATMCI_DMA_THRESHOLD 16 |
7d2be074 HS |
43 | |
44 | enum { | |
45 | EVENT_CMD_COMPLETE = 0, | |
7d2be074 | 46 | EVENT_XFER_COMPLETE, |
c06ad258 HS |
47 | EVENT_DATA_COMPLETE, |
48 | EVENT_DATA_ERROR, | |
49 | }; | |
50 | ||
51 | enum atmel_mci_state { | |
965ebf33 HS |
52 | STATE_IDLE = 0, |
53 | STATE_SENDING_CMD, | |
c06ad258 HS |
54 | STATE_SENDING_DATA, |
55 | STATE_DATA_BUSY, | |
56 | STATE_SENDING_STOP, | |
57 | STATE_DATA_ERROR, | |
7d2be074 HS |
58 | }; |
59 | ||
65e8b083 HS |
60 | struct atmel_mci_dma { |
61 | #ifdef CONFIG_MMC_ATMELMCI_DMA | |
65e8b083 HS |
62 | struct dma_chan *chan; |
63 | struct dma_async_tx_descriptor *data_desc; | |
64 | #endif | |
65 | }; | |
66 | ||
965ebf33 HS |
67 | /** |
68 | * struct atmel_mci - MMC controller state shared between all slots | |
69 | * @lock: Spinlock protecting the queue and associated data. | |
70 | * @regs: Pointer to MMIO registers. | |
71 | * @sg: Scatterlist entry currently being processed by PIO code, if any. | |
72 | * @pio_offset: Offset into the current scatterlist entry. | |
73 | * @cur_slot: The slot which is currently using the controller. | |
74 | * @mrq: The request currently being processed on @cur_slot, | |
75 | * or NULL if the controller is idle. | |
76 | * @cmd: The command currently being sent to the card, or NULL. | |
77 | * @data: The data currently being transferred, or NULL if no data | |
78 | * transfer is in progress. | |
65e8b083 HS |
79 | * @dma: DMA client state. |
80 | * @data_chan: DMA channel being used for the current data transfer. | |
965ebf33 HS |
81 | * @cmd_status: Snapshot of SR taken upon completion of the current |
82 | * command. Only valid when EVENT_CMD_COMPLETE is pending. | |
83 | * @data_status: Snapshot of SR taken upon completion of the current | |
84 | * data transfer. Only valid when EVENT_DATA_COMPLETE or | |
85 | * EVENT_DATA_ERROR is pending. | |
86 | * @stop_cmdr: Value to be loaded into CMDR when the stop command is | |
87 | * to be sent. | |
88 | * @tasklet: Tasklet running the request state machine. | |
89 | * @pending_events: Bitmask of events flagged by the interrupt handler | |
90 | * to be processed by the tasklet. | |
91 | * @completed_events: Bitmask of events which the state machine has | |
92 | * processed. | |
93 | * @state: Tasklet state. | |
94 | * @queue: List of slots waiting for access to the controller. | |
95 | * @need_clock_update: Update the clock rate before the next request. | |
96 | * @need_reset: Reset controller before next request. | |
97 | * @mode_reg: Value of the MR register. | |
74791a2d | 98 | * @cfg_reg: Value of the CFG register. |
965ebf33 HS |
99 | * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus |
100 | * rate and timeout calculations. | |
101 | * @mapbase: Physical address of the MMIO registers. | |
102 | * @mck: The peripheral bus clock hooked up to the MMC controller. | |
103 | * @pdev: Platform device associated with the MMC controller. | |
104 | * @slot: Slots sharing this MMC controller. | |
105 | * | |
106 | * Locking | |
107 | * ======= | |
108 | * | |
109 | * @lock is a softirq-safe spinlock protecting @queue as well as | |
110 | * @cur_slot, @mrq and @state. These must always be updated | |
111 | * at the same time while holding @lock. | |
112 | * | |
113 | * @lock also protects mode_reg and need_clock_update since these are | |
114 | * used to synchronize mode register updates with the queue | |
115 | * processing. | |
116 | * | |
117 | * The @mrq field of struct atmel_mci_slot is also protected by @lock, | |
118 | * and must always be written at the same time as the slot is added to | |
119 | * @queue. | |
120 | * | |
121 | * @pending_events and @completed_events are accessed using atomic bit | |
122 | * operations, so they don't need any locking. | |
123 | * | |
124 | * None of the fields touched by the interrupt handler need any | |
125 | * locking. However, ordering is important: Before EVENT_DATA_ERROR or | |
126 | * EVENT_DATA_COMPLETE is set in @pending_events, all data-related | |
127 | * interrupts must be disabled and @data_status updated with a | |
128 | * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the | |
129 | * CMDRDY interupt must be disabled and @cmd_status updated with a | |
130 | * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the | |
131 | * bytes_xfered field of @data must be written. This is ensured by | |
132 | * using barriers. | |
133 | */ | |
7d2be074 | 134 | struct atmel_mci { |
965ebf33 | 135 | spinlock_t lock; |
7d2be074 HS |
136 | void __iomem *regs; |
137 | ||
138 | struct scatterlist *sg; | |
139 | unsigned int pio_offset; | |
140 | ||
965ebf33 | 141 | struct atmel_mci_slot *cur_slot; |
7d2be074 HS |
142 | struct mmc_request *mrq; |
143 | struct mmc_command *cmd; | |
144 | struct mmc_data *data; | |
145 | ||
65e8b083 HS |
146 | struct atmel_mci_dma dma; |
147 | struct dma_chan *data_chan; | |
148 | ||
7d2be074 HS |
149 | u32 cmd_status; |
150 | u32 data_status; | |
7d2be074 HS |
151 | u32 stop_cmdr; |
152 | ||
7d2be074 HS |
153 | struct tasklet_struct tasklet; |
154 | unsigned long pending_events; | |
155 | unsigned long completed_events; | |
c06ad258 | 156 | enum atmel_mci_state state; |
965ebf33 | 157 | struct list_head queue; |
7d2be074 | 158 | |
965ebf33 HS |
159 | bool need_clock_update; |
160 | bool need_reset; | |
161 | u32 mode_reg; | |
74791a2d | 162 | u32 cfg_reg; |
7d2be074 HS |
163 | unsigned long bus_hz; |
164 | unsigned long mapbase; | |
165 | struct clk *mck; | |
166 | struct platform_device *pdev; | |
965ebf33 HS |
167 | |
168 | struct atmel_mci_slot *slot[ATMEL_MCI_MAX_NR_SLOTS]; | |
169 | }; | |
170 | ||
171 | /** | |
172 | * struct atmel_mci_slot - MMC slot state | |
173 | * @mmc: The mmc_host representing this slot. | |
174 | * @host: The MMC controller this slot is using. | |
175 | * @sdc_reg: Value of SDCR to be written before using this slot. | |
176 | * @mrq: mmc_request currently being processed or waiting to be | |
177 | * processed, or NULL when the slot is idle. | |
178 | * @queue_node: List node for placing this node in the @queue list of | |
179 | * &struct atmel_mci. | |
180 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. | |
181 | * @flags: Random state bits associated with the slot. | |
182 | * @detect_pin: GPIO pin used for card detection, or negative if not | |
183 | * available. | |
184 | * @wp_pin: GPIO pin used for card write protect sending, or negative | |
185 | * if not available. | |
1c1452be | 186 | * @detect_is_active_high: The state of the detect pin when it is active. |
965ebf33 HS |
187 | * @detect_timer: Timer used for debouncing @detect_pin interrupts. |
188 | */ | |
189 | struct atmel_mci_slot { | |
190 | struct mmc_host *mmc; | |
191 | struct atmel_mci *host; | |
192 | ||
193 | u32 sdc_reg; | |
194 | ||
195 | struct mmc_request *mrq; | |
196 | struct list_head queue_node; | |
197 | ||
198 | unsigned int clock; | |
199 | unsigned long flags; | |
200 | #define ATMCI_CARD_PRESENT 0 | |
201 | #define ATMCI_CARD_NEED_INIT 1 | |
202 | #define ATMCI_SHUTDOWN 2 | |
203 | ||
204 | int detect_pin; | |
205 | int wp_pin; | |
1c1452be | 206 | bool detect_is_active_high; |
965ebf33 HS |
207 | |
208 | struct timer_list detect_timer; | |
7d2be074 HS |
209 | }; |
210 | ||
7d2be074 HS |
211 | #define atmci_test_and_clear_pending(host, event) \ |
212 | test_and_clear_bit(event, &host->pending_events) | |
7d2be074 HS |
213 | #define atmci_set_completed(host, event) \ |
214 | set_bit(event, &host->completed_events) | |
215 | #define atmci_set_pending(host, event) \ | |
216 | set_bit(event, &host->pending_events) | |
7d2be074 | 217 | |
04d699c3 RE |
218 | /* |
219 | * Enable or disable features/registers based on | |
220 | * whether the processor supports them | |
221 | */ | |
222 | static bool mci_has_rwproof(void) | |
223 | { | |
224 | if (cpu_is_at91sam9261() || cpu_is_at91rm9200()) | |
225 | return false; | |
226 | else | |
227 | return true; | |
228 | } | |
229 | ||
74791a2d NF |
230 | /* |
231 | * The new MCI2 module isn't 100% compatible with the old MCI module, | |
232 | * and it has a few nice features which we want to use... | |
233 | */ | |
234 | static inline bool atmci_is_mci2(void) | |
235 | { | |
236 | if (cpu_is_at91sam9g45()) | |
237 | return true; | |
238 | ||
239 | return false; | |
240 | } | |
241 | ||
242 | ||
deec9ae3 HS |
243 | /* |
244 | * The debugfs stuff below is mostly optimized away when | |
245 | * CONFIG_DEBUG_FS is not set. | |
246 | */ | |
247 | static int atmci_req_show(struct seq_file *s, void *v) | |
248 | { | |
965ebf33 HS |
249 | struct atmel_mci_slot *slot = s->private; |
250 | struct mmc_request *mrq; | |
deec9ae3 HS |
251 | struct mmc_command *cmd; |
252 | struct mmc_command *stop; | |
253 | struct mmc_data *data; | |
254 | ||
255 | /* Make sure we get a consistent snapshot */ | |
965ebf33 HS |
256 | spin_lock_bh(&slot->host->lock); |
257 | mrq = slot->mrq; | |
deec9ae3 HS |
258 | |
259 | if (mrq) { | |
260 | cmd = mrq->cmd; | |
261 | data = mrq->data; | |
262 | stop = mrq->stop; | |
263 | ||
264 | if (cmd) | |
265 | seq_printf(s, | |
266 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
267 | cmd->opcode, cmd->arg, cmd->flags, | |
268 | cmd->resp[0], cmd->resp[1], cmd->resp[2], | |
269 | cmd->resp[2], cmd->error); | |
270 | if (data) | |
271 | seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", | |
272 | data->bytes_xfered, data->blocks, | |
273 | data->blksz, data->flags, data->error); | |
274 | if (stop) | |
275 | seq_printf(s, | |
276 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
277 | stop->opcode, stop->arg, stop->flags, | |
278 | stop->resp[0], stop->resp[1], stop->resp[2], | |
279 | stop->resp[2], stop->error); | |
280 | } | |
281 | ||
965ebf33 | 282 | spin_unlock_bh(&slot->host->lock); |
deec9ae3 HS |
283 | |
284 | return 0; | |
285 | } | |
286 | ||
287 | static int atmci_req_open(struct inode *inode, struct file *file) | |
288 | { | |
289 | return single_open(file, atmci_req_show, inode->i_private); | |
290 | } | |
291 | ||
292 | static const struct file_operations atmci_req_fops = { | |
293 | .owner = THIS_MODULE, | |
294 | .open = atmci_req_open, | |
295 | .read = seq_read, | |
296 | .llseek = seq_lseek, | |
297 | .release = single_release, | |
298 | }; | |
299 | ||
300 | static void atmci_show_status_reg(struct seq_file *s, | |
301 | const char *regname, u32 value) | |
302 | { | |
303 | static const char *sr_bit[] = { | |
304 | [0] = "CMDRDY", | |
305 | [1] = "RXRDY", | |
306 | [2] = "TXRDY", | |
307 | [3] = "BLKE", | |
308 | [4] = "DTIP", | |
309 | [5] = "NOTBUSY", | |
04d699c3 RE |
310 | [6] = "ENDRX", |
311 | [7] = "ENDTX", | |
deec9ae3 HS |
312 | [8] = "SDIOIRQA", |
313 | [9] = "SDIOIRQB", | |
04d699c3 RE |
314 | [12] = "SDIOWAIT", |
315 | [14] = "RXBUFF", | |
316 | [15] = "TXBUFE", | |
deec9ae3 HS |
317 | [16] = "RINDE", |
318 | [17] = "RDIRE", | |
319 | [18] = "RCRCE", | |
320 | [19] = "RENDE", | |
321 | [20] = "RTOE", | |
322 | [21] = "DCRCE", | |
323 | [22] = "DTOE", | |
04d699c3 RE |
324 | [23] = "CSTOE", |
325 | [24] = "BLKOVRE", | |
326 | [25] = "DMADONE", | |
327 | [26] = "FIFOEMPTY", | |
328 | [27] = "XFRDONE", | |
deec9ae3 HS |
329 | [30] = "OVRE", |
330 | [31] = "UNRE", | |
331 | }; | |
332 | unsigned int i; | |
333 | ||
334 | seq_printf(s, "%s:\t0x%08x", regname, value); | |
335 | for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { | |
336 | if (value & (1 << i)) { | |
337 | if (sr_bit[i]) | |
338 | seq_printf(s, " %s", sr_bit[i]); | |
339 | else | |
340 | seq_puts(s, " UNKNOWN"); | |
341 | } | |
342 | } | |
343 | seq_putc(s, '\n'); | |
344 | } | |
345 | ||
346 | static int atmci_regs_show(struct seq_file *s, void *v) | |
347 | { | |
348 | struct atmel_mci *host = s->private; | |
349 | u32 *buf; | |
350 | ||
351 | buf = kmalloc(MCI_REGS_SIZE, GFP_KERNEL); | |
352 | if (!buf) | |
353 | return -ENOMEM; | |
354 | ||
965ebf33 HS |
355 | /* |
356 | * Grab a more or less consistent snapshot. Note that we're | |
357 | * not disabling interrupts, so IMR and SR may not be | |
358 | * consistent. | |
359 | */ | |
360 | spin_lock_bh(&host->lock); | |
87e60f2b | 361 | clk_enable(host->mck); |
deec9ae3 | 362 | memcpy_fromio(buf, host->regs, MCI_REGS_SIZE); |
87e60f2b | 363 | clk_disable(host->mck); |
965ebf33 | 364 | spin_unlock_bh(&host->lock); |
deec9ae3 HS |
365 | |
366 | seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n", | |
367 | buf[MCI_MR / 4], | |
368 | buf[MCI_MR / 4] & MCI_MR_RDPROOF ? " RDPROOF" : "", | |
369 | buf[MCI_MR / 4] & MCI_MR_WRPROOF ? " WRPROOF" : "", | |
370 | buf[MCI_MR / 4] & 0xff); | |
371 | seq_printf(s, "DTOR:\t0x%08x\n", buf[MCI_DTOR / 4]); | |
372 | seq_printf(s, "SDCR:\t0x%08x\n", buf[MCI_SDCR / 4]); | |
373 | seq_printf(s, "ARGR:\t0x%08x\n", buf[MCI_ARGR / 4]); | |
374 | seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", | |
375 | buf[MCI_BLKR / 4], | |
376 | buf[MCI_BLKR / 4] & 0xffff, | |
377 | (buf[MCI_BLKR / 4] >> 16) & 0xffff); | |
74791a2d NF |
378 | if (atmci_is_mci2()) |
379 | seq_printf(s, "CSTOR:\t0x%08x\n", buf[MCI_CSTOR / 4]); | |
deec9ae3 HS |
380 | |
381 | /* Don't read RSPR and RDR; it will consume the data there */ | |
382 | ||
383 | atmci_show_status_reg(s, "SR", buf[MCI_SR / 4]); | |
384 | atmci_show_status_reg(s, "IMR", buf[MCI_IMR / 4]); | |
385 | ||
74791a2d NF |
386 | if (atmci_is_mci2()) { |
387 | u32 val; | |
388 | ||
389 | val = buf[MCI_DMA / 4]; | |
390 | seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", | |
391 | val, val & 3, | |
392 | ((val >> 4) & 3) ? | |
393 | 1 << (((val >> 4) & 3) + 1) : 1, | |
394 | val & MCI_DMAEN ? " DMAEN" : ""); | |
395 | ||
396 | val = buf[MCI_CFG / 4]; | |
397 | seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", | |
398 | val, | |
399 | val & MCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", | |
400 | val & MCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", | |
401 | val & MCI_CFG_HSMODE ? " HSMODE" : "", | |
402 | val & MCI_CFG_LSYNC ? " LSYNC" : ""); | |
403 | } | |
404 | ||
b17339a1 HS |
405 | kfree(buf); |
406 | ||
deec9ae3 HS |
407 | return 0; |
408 | } | |
409 | ||
410 | static int atmci_regs_open(struct inode *inode, struct file *file) | |
411 | { | |
412 | return single_open(file, atmci_regs_show, inode->i_private); | |
413 | } | |
414 | ||
415 | static const struct file_operations atmci_regs_fops = { | |
416 | .owner = THIS_MODULE, | |
417 | .open = atmci_regs_open, | |
418 | .read = seq_read, | |
419 | .llseek = seq_lseek, | |
420 | .release = single_release, | |
421 | }; | |
422 | ||
965ebf33 | 423 | static void atmci_init_debugfs(struct atmel_mci_slot *slot) |
deec9ae3 | 424 | { |
965ebf33 HS |
425 | struct mmc_host *mmc = slot->mmc; |
426 | struct atmel_mci *host = slot->host; | |
427 | struct dentry *root; | |
428 | struct dentry *node; | |
deec9ae3 | 429 | |
deec9ae3 HS |
430 | root = mmc->debugfs_root; |
431 | if (!root) | |
432 | return; | |
433 | ||
434 | node = debugfs_create_file("regs", S_IRUSR, root, host, | |
435 | &atmci_regs_fops); | |
436 | if (IS_ERR(node)) | |
437 | return; | |
438 | if (!node) | |
439 | goto err; | |
440 | ||
965ebf33 | 441 | node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); |
deec9ae3 HS |
442 | if (!node) |
443 | goto err; | |
444 | ||
c06ad258 HS |
445 | node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); |
446 | if (!node) | |
447 | goto err; | |
448 | ||
deec9ae3 HS |
449 | node = debugfs_create_x32("pending_events", S_IRUSR, root, |
450 | (u32 *)&host->pending_events); | |
451 | if (!node) | |
452 | goto err; | |
453 | ||
454 | node = debugfs_create_x32("completed_events", S_IRUSR, root, | |
455 | (u32 *)&host->completed_events); | |
456 | if (!node) | |
457 | goto err; | |
458 | ||
459 | return; | |
460 | ||
461 | err: | |
965ebf33 | 462 | dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); |
deec9ae3 | 463 | } |
7d2be074 | 464 | |
7d2be074 HS |
465 | static inline unsigned int ns_to_clocks(struct atmel_mci *host, |
466 | unsigned int ns) | |
467 | { | |
468 | return (ns * (host->bus_hz / 1000000) + 999) / 1000; | |
469 | } | |
470 | ||
471 | static void atmci_set_timeout(struct atmel_mci *host, | |
965ebf33 | 472 | struct atmel_mci_slot *slot, struct mmc_data *data) |
7d2be074 HS |
473 | { |
474 | static unsigned dtomul_to_shift[] = { | |
475 | 0, 4, 7, 8, 10, 12, 16, 20 | |
476 | }; | |
477 | unsigned timeout; | |
478 | unsigned dtocyc; | |
479 | unsigned dtomul; | |
480 | ||
481 | timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks; | |
482 | ||
483 | for (dtomul = 0; dtomul < 8; dtomul++) { | |
484 | unsigned shift = dtomul_to_shift[dtomul]; | |
485 | dtocyc = (timeout + (1 << shift) - 1) >> shift; | |
486 | if (dtocyc < 15) | |
487 | break; | |
488 | } | |
489 | ||
490 | if (dtomul >= 8) { | |
491 | dtomul = 7; | |
492 | dtocyc = 15; | |
493 | } | |
494 | ||
965ebf33 | 495 | dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", |
7d2be074 HS |
496 | dtocyc << dtomul_to_shift[dtomul]); |
497 | mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc))); | |
498 | } | |
499 | ||
500 | /* | |
501 | * Return mask with command flags to be enabled for this command. | |
502 | */ | |
503 | static u32 atmci_prepare_command(struct mmc_host *mmc, | |
504 | struct mmc_command *cmd) | |
505 | { | |
506 | struct mmc_data *data; | |
507 | u32 cmdr; | |
508 | ||
509 | cmd->error = -EINPROGRESS; | |
510 | ||
511 | cmdr = MCI_CMDR_CMDNB(cmd->opcode); | |
512 | ||
513 | if (cmd->flags & MMC_RSP_PRESENT) { | |
514 | if (cmd->flags & MMC_RSP_136) | |
515 | cmdr |= MCI_CMDR_RSPTYP_136BIT; | |
516 | else | |
517 | cmdr |= MCI_CMDR_RSPTYP_48BIT; | |
518 | } | |
519 | ||
520 | /* | |
521 | * This should really be MAXLAT_5 for CMD2 and ACMD41, but | |
522 | * it's too difficult to determine whether this is an ACMD or | |
523 | * not. Better make it 64. | |
524 | */ | |
525 | cmdr |= MCI_CMDR_MAXLAT_64CYC; | |
526 | ||
527 | if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) | |
528 | cmdr |= MCI_CMDR_OPDCMD; | |
529 | ||
530 | data = cmd->data; | |
531 | if (data) { | |
532 | cmdr |= MCI_CMDR_START_XFER; | |
533 | if (data->flags & MMC_DATA_STREAM) | |
534 | cmdr |= MCI_CMDR_STREAM; | |
535 | else if (data->blocks > 1) | |
536 | cmdr |= MCI_CMDR_MULTI_BLOCK; | |
537 | else | |
538 | cmdr |= MCI_CMDR_BLOCK; | |
539 | ||
540 | if (data->flags & MMC_DATA_READ) | |
541 | cmdr |= MCI_CMDR_TRDIR_READ; | |
542 | } | |
543 | ||
544 | return cmdr; | |
545 | } | |
546 | ||
547 | static void atmci_start_command(struct atmel_mci *host, | |
965ebf33 | 548 | struct mmc_command *cmd, u32 cmd_flags) |
7d2be074 | 549 | { |
7d2be074 HS |
550 | WARN_ON(host->cmd); |
551 | host->cmd = cmd; | |
552 | ||
965ebf33 | 553 | dev_vdbg(&host->pdev->dev, |
7d2be074 HS |
554 | "start command: ARGR=0x%08x CMDR=0x%08x\n", |
555 | cmd->arg, cmd_flags); | |
556 | ||
557 | mci_writel(host, ARGR, cmd->arg); | |
558 | mci_writel(host, CMDR, cmd_flags); | |
559 | } | |
560 | ||
965ebf33 | 561 | static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) |
7d2be074 | 562 | { |
7d2be074 HS |
563 | atmci_start_command(host, data->stop, host->stop_cmdr); |
564 | mci_writel(host, IER, MCI_CMDRDY); | |
565 | } | |
566 | ||
65e8b083 HS |
567 | #ifdef CONFIG_MMC_ATMELMCI_DMA |
568 | static void atmci_dma_cleanup(struct atmel_mci *host) | |
569 | { | |
570 | struct mmc_data *data = host->data; | |
571 | ||
009a891b NF |
572 | if (data) |
573 | dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, | |
574 | ((data->flags & MMC_DATA_WRITE) | |
575 | ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); | |
65e8b083 HS |
576 | } |
577 | ||
578 | static void atmci_stop_dma(struct atmel_mci *host) | |
579 | { | |
580 | struct dma_chan *chan = host->data_chan; | |
581 | ||
582 | if (chan) { | |
583 | chan->device->device_terminate_all(chan); | |
584 | atmci_dma_cleanup(host); | |
585 | } else { | |
586 | /* Data transfer was stopped by the interrupt handler */ | |
587 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | |
588 | mci_writel(host, IER, MCI_NOTBUSY); | |
589 | } | |
590 | } | |
591 | ||
592 | /* This function is called by the DMA driver from tasklet context. */ | |
593 | static void atmci_dma_complete(void *arg) | |
594 | { | |
595 | struct atmel_mci *host = arg; | |
596 | struct mmc_data *data = host->data; | |
597 | ||
598 | dev_vdbg(&host->pdev->dev, "DMA complete\n"); | |
599 | ||
74791a2d NF |
600 | if (atmci_is_mci2()) |
601 | /* Disable DMA hardware handshaking on MCI */ | |
602 | mci_writel(host, DMA, mci_readl(host, DMA) & ~MCI_DMAEN); | |
603 | ||
65e8b083 HS |
604 | atmci_dma_cleanup(host); |
605 | ||
606 | /* | |
607 | * If the card was removed, data will be NULL. No point trying | |
608 | * to send the stop command or waiting for NBUSY in this case. | |
609 | */ | |
610 | if (data) { | |
611 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | |
612 | tasklet_schedule(&host->tasklet); | |
613 | ||
614 | /* | |
615 | * Regardless of what the documentation says, we have | |
616 | * to wait for NOTBUSY even after block read | |
617 | * operations. | |
618 | * | |
619 | * When the DMA transfer is complete, the controller | |
620 | * may still be reading the CRC from the card, i.e. | |
621 | * the data transfer is still in progress and we | |
622 | * haven't seen all the potential error bits yet. | |
623 | * | |
624 | * The interrupt handler will schedule a different | |
625 | * tasklet to finish things up when the data transfer | |
626 | * is completely done. | |
627 | * | |
628 | * We may not complete the mmc request here anyway | |
629 | * because the mmc layer may call back and cause us to | |
630 | * violate the "don't submit new operations from the | |
631 | * completion callback" rule of the dma engine | |
632 | * framework. | |
633 | */ | |
634 | mci_writel(host, IER, MCI_NOTBUSY); | |
635 | } | |
636 | } | |
637 | ||
638 | static int | |
74791a2d | 639 | atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) |
65e8b083 HS |
640 | { |
641 | struct dma_chan *chan; | |
642 | struct dma_async_tx_descriptor *desc; | |
643 | struct scatterlist *sg; | |
644 | unsigned int i; | |
645 | enum dma_data_direction direction; | |
657a77fa | 646 | unsigned int sglen; |
65e8b083 HS |
647 | |
648 | /* | |
649 | * We don't do DMA on "complex" transfers, i.e. with | |
650 | * non-word-aligned buffers or lengths. Also, we don't bother | |
651 | * with all the DMA setup overhead for short transfers. | |
652 | */ | |
653 | if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) | |
654 | return -EINVAL; | |
655 | if (data->blksz & 3) | |
656 | return -EINVAL; | |
657 | ||
658 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
659 | if (sg->offset & 3 || sg->length & 3) | |
660 | return -EINVAL; | |
661 | } | |
662 | ||
663 | /* If we don't have a channel, we can't do DMA */ | |
664 | chan = host->dma.chan; | |
6f49a57a | 665 | if (chan) |
65e8b083 | 666 | host->data_chan = chan; |
65e8b083 HS |
667 | |
668 | if (!chan) | |
669 | return -ENODEV; | |
670 | ||
74791a2d NF |
671 | if (atmci_is_mci2()) |
672 | mci_writel(host, DMA, MCI_DMA_CHKSIZE(3) | MCI_DMAEN); | |
673 | ||
65e8b083 HS |
674 | if (data->flags & MMC_DATA_READ) |
675 | direction = DMA_FROM_DEVICE; | |
676 | else | |
677 | direction = DMA_TO_DEVICE; | |
678 | ||
657a77fa AN |
679 | sglen = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, direction); |
680 | if (sglen != data->sg_len) | |
681 | goto unmap_exit; | |
65e8b083 HS |
682 | desc = chan->device->device_prep_slave_sg(chan, |
683 | data->sg, data->sg_len, direction, | |
684 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
685 | if (!desc) | |
657a77fa | 686 | goto unmap_exit; |
65e8b083 HS |
687 | |
688 | host->dma.data_desc = desc; | |
689 | desc->callback = atmci_dma_complete; | |
690 | desc->callback_param = host; | |
65e8b083 HS |
691 | |
692 | return 0; | |
657a77fa AN |
693 | unmap_exit: |
694 | dma_unmap_sg(&host->pdev->dev, data->sg, sglen, direction); | |
695 | return -ENOMEM; | |
65e8b083 HS |
696 | } |
697 | ||
74791a2d NF |
698 | static void atmci_submit_data(struct atmel_mci *host) |
699 | { | |
700 | struct dma_chan *chan = host->data_chan; | |
701 | struct dma_async_tx_descriptor *desc = host->dma.data_desc; | |
702 | ||
703 | if (chan) { | |
704 | desc->tx_submit(desc); | |
705 | chan->device->device_issue_pending(chan); | |
706 | } | |
707 | } | |
708 | ||
65e8b083 HS |
709 | #else /* CONFIG_MMC_ATMELMCI_DMA */ |
710 | ||
74791a2d | 711 | static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) |
65e8b083 HS |
712 | { |
713 | return -ENOSYS; | |
714 | } | |
715 | ||
74791a2d NF |
716 | static void atmci_submit_data(struct atmel_mci *host) {} |
717 | ||
65e8b083 HS |
718 | static void atmci_stop_dma(struct atmel_mci *host) |
719 | { | |
720 | /* Data transfer was stopped by the interrupt handler */ | |
721 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | |
722 | mci_writel(host, IER, MCI_NOTBUSY); | |
723 | } | |
724 | ||
725 | #endif /* CONFIG_MMC_ATMELMCI_DMA */ | |
726 | ||
7d2be074 HS |
727 | /* |
728 | * Returns a mask of interrupt flags to be enabled after the whole | |
729 | * request has been prepared. | |
730 | */ | |
74791a2d | 731 | static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) |
7d2be074 | 732 | { |
965ebf33 | 733 | u32 iflags; |
7d2be074 HS |
734 | |
735 | data->error = -EINPROGRESS; | |
736 | ||
737 | WARN_ON(host->data); | |
738 | host->sg = NULL; | |
739 | host->data = data; | |
740 | ||
7d2be074 | 741 | iflags = ATMCI_DATA_ERROR_FLAGS; |
74791a2d | 742 | if (atmci_prepare_data_dma(host, data)) { |
65e8b083 | 743 | host->data_chan = NULL; |
965ebf33 | 744 | |
65e8b083 HS |
745 | /* |
746 | * Errata: MMC data write operation with less than 12 | |
747 | * bytes is impossible. | |
748 | * | |
749 | * Errata: MCI Transmit Data Register (TDR) FIFO | |
750 | * corruption when length is not multiple of 4. | |
751 | */ | |
752 | if (data->blocks * data->blksz < 12 | |
753 | || (data->blocks * data->blksz) & 3) | |
754 | host->need_reset = true; | |
965ebf33 | 755 | |
65e8b083 HS |
756 | host->sg = data->sg; |
757 | host->pio_offset = 0; | |
758 | if (data->flags & MMC_DATA_READ) | |
759 | iflags |= MCI_RXRDY; | |
760 | else | |
761 | iflags |= MCI_TXRDY; | |
762 | } | |
7d2be074 HS |
763 | |
764 | return iflags; | |
765 | } | |
766 | ||
965ebf33 HS |
767 | static void atmci_start_request(struct atmel_mci *host, |
768 | struct atmel_mci_slot *slot) | |
7d2be074 | 769 | { |
965ebf33 | 770 | struct mmc_request *mrq; |
7d2be074 | 771 | struct mmc_command *cmd; |
965ebf33 | 772 | struct mmc_data *data; |
7d2be074 | 773 | u32 iflags; |
965ebf33 | 774 | u32 cmdflags; |
7d2be074 | 775 | |
965ebf33 HS |
776 | mrq = slot->mrq; |
777 | host->cur_slot = slot; | |
7d2be074 | 778 | host->mrq = mrq; |
965ebf33 | 779 | |
7d2be074 HS |
780 | host->pending_events = 0; |
781 | host->completed_events = 0; | |
ca55f46e | 782 | host->data_status = 0; |
7d2be074 | 783 | |
965ebf33 HS |
784 | if (host->need_reset) { |
785 | mci_writel(host, CR, MCI_CR_SWRST); | |
786 | mci_writel(host, CR, MCI_CR_MCIEN); | |
787 | mci_writel(host, MR, host->mode_reg); | |
74791a2d NF |
788 | if (atmci_is_mci2()) |
789 | mci_writel(host, CFG, host->cfg_reg); | |
965ebf33 HS |
790 | host->need_reset = false; |
791 | } | |
792 | mci_writel(host, SDCR, slot->sdc_reg); | |
793 | ||
794 | iflags = mci_readl(host, IMR); | |
795 | if (iflags) | |
796 | dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", | |
797 | iflags); | |
798 | ||
799 | if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { | |
800 | /* Send init sequence (74 clock cycles) */ | |
801 | mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT); | |
802 | while (!(mci_readl(host, SR) & MCI_CMDRDY)) | |
803 | cpu_relax(); | |
804 | } | |
74791a2d | 805 | iflags = 0; |
7d2be074 HS |
806 | data = mrq->data; |
807 | if (data) { | |
965ebf33 | 808 | atmci_set_timeout(host, slot, data); |
a252e3e3 HS |
809 | |
810 | /* Must set block count/size before sending command */ | |
811 | mci_writel(host, BLKR, MCI_BCNT(data->blocks) | |
812 | | MCI_BLKLEN(data->blksz)); | |
965ebf33 HS |
813 | dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", |
814 | MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz)); | |
74791a2d NF |
815 | |
816 | iflags |= atmci_prepare_data(host, data); | |
7d2be074 HS |
817 | } |
818 | ||
74791a2d | 819 | iflags |= MCI_CMDRDY; |
7d2be074 | 820 | cmd = mrq->cmd; |
965ebf33 | 821 | cmdflags = atmci_prepare_command(slot->mmc, cmd); |
7d2be074 HS |
822 | atmci_start_command(host, cmd, cmdflags); |
823 | ||
824 | if (data) | |
74791a2d | 825 | atmci_submit_data(host); |
7d2be074 HS |
826 | |
827 | if (mrq->stop) { | |
965ebf33 | 828 | host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); |
7d2be074 HS |
829 | host->stop_cmdr |= MCI_CMDR_STOP_XFER; |
830 | if (!(data->flags & MMC_DATA_WRITE)) | |
831 | host->stop_cmdr |= MCI_CMDR_TRDIR_READ; | |
832 | if (data->flags & MMC_DATA_STREAM) | |
833 | host->stop_cmdr |= MCI_CMDR_STREAM; | |
834 | else | |
835 | host->stop_cmdr |= MCI_CMDR_MULTI_BLOCK; | |
836 | } | |
837 | ||
838 | /* | |
839 | * We could have enabled interrupts earlier, but I suspect | |
840 | * that would open up a nice can of interesting race | |
841 | * conditions (e.g. command and data complete, but stop not | |
842 | * prepared yet.) | |
843 | */ | |
844 | mci_writel(host, IER, iflags); | |
965ebf33 | 845 | } |
7d2be074 | 846 | |
965ebf33 HS |
847 | static void atmci_queue_request(struct atmel_mci *host, |
848 | struct atmel_mci_slot *slot, struct mmc_request *mrq) | |
849 | { | |
850 | dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", | |
851 | host->state); | |
852 | ||
853 | spin_lock_bh(&host->lock); | |
854 | slot->mrq = mrq; | |
855 | if (host->state == STATE_IDLE) { | |
856 | host->state = STATE_SENDING_CMD; | |
857 | atmci_start_request(host, slot); | |
858 | } else { | |
859 | list_add_tail(&slot->queue_node, &host->queue); | |
860 | } | |
861 | spin_unlock_bh(&host->lock); | |
862 | } | |
7d2be074 | 863 | |
965ebf33 HS |
864 | static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
865 | { | |
866 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
867 | struct atmel_mci *host = slot->host; | |
868 | struct mmc_data *data; | |
869 | ||
870 | WARN_ON(slot->mrq); | |
871 | ||
872 | /* | |
873 | * We may "know" the card is gone even though there's still an | |
874 | * electrical connection. If so, we really need to communicate | |
875 | * this to the MMC core since there won't be any more | |
876 | * interrupts as the card is completely removed. Otherwise, | |
877 | * the MMC core might believe the card is still there even | |
878 | * though the card was just removed very slowly. | |
879 | */ | |
880 | if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { | |
881 | mrq->cmd->error = -ENOMEDIUM; | |
882 | mmc_request_done(mmc, mrq); | |
883 | return; | |
884 | } | |
885 | ||
886 | /* We don't support multiple blocks of weird lengths. */ | |
887 | data = mrq->data; | |
888 | if (data && data->blocks > 1 && data->blksz & 3) { | |
889 | mrq->cmd->error = -EINVAL; | |
890 | mmc_request_done(mmc, mrq); | |
891 | } | |
892 | ||
893 | atmci_queue_request(host, slot, mrq); | |
7d2be074 HS |
894 | } |
895 | ||
896 | static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
897 | { | |
965ebf33 HS |
898 | struct atmel_mci_slot *slot = mmc_priv(mmc); |
899 | struct atmel_mci *host = slot->host; | |
900 | unsigned int i; | |
7d2be074 | 901 | |
965ebf33 | 902 | slot->sdc_reg &= ~MCI_SDCBUS_MASK; |
945533b5 HS |
903 | switch (ios->bus_width) { |
904 | case MMC_BUS_WIDTH_1: | |
965ebf33 | 905 | slot->sdc_reg |= MCI_SDCBUS_1BIT; |
945533b5 HS |
906 | break; |
907 | case MMC_BUS_WIDTH_4: | |
32ab83a5 | 908 | slot->sdc_reg |= MCI_SDCBUS_4BIT; |
945533b5 HS |
909 | break; |
910 | } | |
911 | ||
7d2be074 | 912 | if (ios->clock) { |
965ebf33 | 913 | unsigned int clock_min = ~0U; |
7d2be074 HS |
914 | u32 clkdiv; |
915 | ||
965ebf33 HS |
916 | spin_lock_bh(&host->lock); |
917 | if (!host->mode_reg) { | |
945533b5 | 918 | clk_enable(host->mck); |
965ebf33 HS |
919 | mci_writel(host, CR, MCI_CR_SWRST); |
920 | mci_writel(host, CR, MCI_CR_MCIEN); | |
74791a2d NF |
921 | if (atmci_is_mci2()) |
922 | mci_writel(host, CFG, host->cfg_reg); | |
965ebf33 | 923 | } |
945533b5 | 924 | |
965ebf33 HS |
925 | /* |
926 | * Use mirror of ios->clock to prevent race with mmc | |
927 | * core ios update when finding the minimum. | |
928 | */ | |
929 | slot->clock = ios->clock; | |
930 | for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { | |
931 | if (host->slot[i] && host->slot[i]->clock | |
932 | && host->slot[i]->clock < clock_min) | |
933 | clock_min = host->slot[i]->clock; | |
934 | } | |
935 | ||
936 | /* Calculate clock divider */ | |
937 | clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; | |
7d2be074 HS |
938 | if (clkdiv > 255) { |
939 | dev_warn(&mmc->class_dev, | |
940 | "clock %u too slow; using %lu\n", | |
965ebf33 | 941 | clock_min, host->bus_hz / (2 * 256)); |
7d2be074 HS |
942 | clkdiv = 255; |
943 | } | |
944 | ||
04d699c3 RE |
945 | host->mode_reg = MCI_MR_CLKDIV(clkdiv); |
946 | ||
965ebf33 HS |
947 | /* |
948 | * WRPROOF and RDPROOF prevent overruns/underruns by | |
949 | * stopping the clock when the FIFO is full/empty. | |
950 | * This state is not expected to last for long. | |
951 | */ | |
04d699c3 RE |
952 | if (mci_has_rwproof()) |
953 | host->mode_reg |= (MCI_MR_WRPROOF | MCI_MR_RDPROOF); | |
7d2be074 | 954 | |
965ebf33 HS |
955 | if (list_empty(&host->queue)) |
956 | mci_writel(host, MR, host->mode_reg); | |
957 | else | |
958 | host->need_clock_update = true; | |
959 | ||
960 | spin_unlock_bh(&host->lock); | |
945533b5 | 961 | } else { |
965ebf33 HS |
962 | bool any_slot_active = false; |
963 | ||
964 | spin_lock_bh(&host->lock); | |
965 | slot->clock = 0; | |
966 | for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { | |
967 | if (host->slot[i] && host->slot[i]->clock) { | |
968 | any_slot_active = true; | |
969 | break; | |
970 | } | |
945533b5 | 971 | } |
965ebf33 HS |
972 | if (!any_slot_active) { |
973 | mci_writel(host, CR, MCI_CR_MCIDIS); | |
974 | if (host->mode_reg) { | |
975 | mci_readl(host, MR); | |
976 | clk_disable(host->mck); | |
977 | } | |
978 | host->mode_reg = 0; | |
979 | } | |
980 | spin_unlock_bh(&host->lock); | |
7d2be074 HS |
981 | } |
982 | ||
983 | switch (ios->power_mode) { | |
965ebf33 HS |
984 | case MMC_POWER_UP: |
985 | set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); | |
986 | break; | |
7d2be074 HS |
987 | default: |
988 | /* | |
989 | * TODO: None of the currently available AVR32-based | |
990 | * boards allow MMC power to be turned off. Implement | |
991 | * power control when this can be tested properly. | |
965ebf33 HS |
992 | * |
993 | * We also need to hook this into the clock management | |
994 | * somehow so that newly inserted cards aren't | |
995 | * subjected to a fast clock before we have a chance | |
996 | * to figure out what the maximum rate is. Currently, | |
997 | * there's no way to avoid this, and there never will | |
998 | * be for boards that don't support power control. | |
7d2be074 HS |
999 | */ |
1000 | break; | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | static int atmci_get_ro(struct mmc_host *mmc) | |
1005 | { | |
965ebf33 HS |
1006 | int read_only = -ENOSYS; |
1007 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
7d2be074 | 1008 | |
965ebf33 HS |
1009 | if (gpio_is_valid(slot->wp_pin)) { |
1010 | read_only = gpio_get_value(slot->wp_pin); | |
7d2be074 HS |
1011 | dev_dbg(&mmc->class_dev, "card is %s\n", |
1012 | read_only ? "read-only" : "read-write"); | |
7d2be074 HS |
1013 | } |
1014 | ||
1015 | return read_only; | |
1016 | } | |
1017 | ||
965ebf33 HS |
1018 | static int atmci_get_cd(struct mmc_host *mmc) |
1019 | { | |
1020 | int present = -ENOSYS; | |
1021 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1022 | ||
1023 | if (gpio_is_valid(slot->detect_pin)) { | |
1c1452be JL |
1024 | present = !(gpio_get_value(slot->detect_pin) ^ |
1025 | slot->detect_is_active_high); | |
965ebf33 HS |
1026 | dev_dbg(&mmc->class_dev, "card is %spresent\n", |
1027 | present ? "" : "not "); | |
1028 | } | |
1029 | ||
1030 | return present; | |
1031 | } | |
1032 | ||
1033 | static const struct mmc_host_ops atmci_ops = { | |
7d2be074 HS |
1034 | .request = atmci_request, |
1035 | .set_ios = atmci_set_ios, | |
1036 | .get_ro = atmci_get_ro, | |
965ebf33 | 1037 | .get_cd = atmci_get_cd, |
7d2be074 HS |
1038 | }; |
1039 | ||
965ebf33 HS |
1040 | /* Called with host->lock held */ |
1041 | static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) | |
1042 | __releases(&host->lock) | |
1043 | __acquires(&host->lock) | |
1044 | { | |
1045 | struct atmel_mci_slot *slot = NULL; | |
1046 | struct mmc_host *prev_mmc = host->cur_slot->mmc; | |
1047 | ||
1048 | WARN_ON(host->cmd || host->data); | |
1049 | ||
1050 | /* | |
1051 | * Update the MMC clock rate if necessary. This may be | |
1052 | * necessary if set_ios() is called when a different slot is | |
1053 | * busy transfering data. | |
1054 | */ | |
1055 | if (host->need_clock_update) | |
1056 | mci_writel(host, MR, host->mode_reg); | |
1057 | ||
1058 | host->cur_slot->mrq = NULL; | |
1059 | host->mrq = NULL; | |
1060 | if (!list_empty(&host->queue)) { | |
1061 | slot = list_entry(host->queue.next, | |
1062 | struct atmel_mci_slot, queue_node); | |
1063 | list_del(&slot->queue_node); | |
1064 | dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", | |
1065 | mmc_hostname(slot->mmc)); | |
1066 | host->state = STATE_SENDING_CMD; | |
1067 | atmci_start_request(host, slot); | |
1068 | } else { | |
1069 | dev_vdbg(&host->pdev->dev, "list empty\n"); | |
1070 | host->state = STATE_IDLE; | |
1071 | } | |
1072 | ||
1073 | spin_unlock(&host->lock); | |
1074 | mmc_request_done(prev_mmc, mrq); | |
1075 | spin_lock(&host->lock); | |
1076 | } | |
1077 | ||
7d2be074 | 1078 | static void atmci_command_complete(struct atmel_mci *host, |
c06ad258 | 1079 | struct mmc_command *cmd) |
7d2be074 | 1080 | { |
c06ad258 HS |
1081 | u32 status = host->cmd_status; |
1082 | ||
7d2be074 HS |
1083 | /* Read the response from the card (up to 16 bytes) */ |
1084 | cmd->resp[0] = mci_readl(host, RSPR); | |
1085 | cmd->resp[1] = mci_readl(host, RSPR); | |
1086 | cmd->resp[2] = mci_readl(host, RSPR); | |
1087 | cmd->resp[3] = mci_readl(host, RSPR); | |
1088 | ||
1089 | if (status & MCI_RTOE) | |
1090 | cmd->error = -ETIMEDOUT; | |
1091 | else if ((cmd->flags & MMC_RSP_CRC) && (status & MCI_RCRCE)) | |
1092 | cmd->error = -EILSEQ; | |
1093 | else if (status & (MCI_RINDE | MCI_RDIRE | MCI_RENDE)) | |
1094 | cmd->error = -EIO; | |
1095 | else | |
1096 | cmd->error = 0; | |
1097 | ||
1098 | if (cmd->error) { | |
965ebf33 | 1099 | dev_dbg(&host->pdev->dev, |
7d2be074 HS |
1100 | "command error: status=0x%08x\n", status); |
1101 | ||
1102 | if (cmd->data) { | |
65e8b083 | 1103 | atmci_stop_dma(host); |
009a891b | 1104 | host->data = NULL; |
7d2be074 HS |
1105 | mci_writel(host, IDR, MCI_NOTBUSY |
1106 | | MCI_TXRDY | MCI_RXRDY | |
1107 | | ATMCI_DATA_ERROR_FLAGS); | |
1108 | } | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | static void atmci_detect_change(unsigned long data) | |
1113 | { | |
965ebf33 HS |
1114 | struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; |
1115 | bool present; | |
1116 | bool present_old; | |
7d2be074 HS |
1117 | |
1118 | /* | |
965ebf33 HS |
1119 | * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before |
1120 | * freeing the interrupt. We must not re-enable the interrupt | |
1121 | * if it has been freed, and if we're shutting down, it | |
1122 | * doesn't really matter whether the card is present or not. | |
7d2be074 HS |
1123 | */ |
1124 | smp_rmb(); | |
965ebf33 | 1125 | if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) |
7d2be074 HS |
1126 | return; |
1127 | ||
965ebf33 | 1128 | enable_irq(gpio_to_irq(slot->detect_pin)); |
1c1452be JL |
1129 | present = !(gpio_get_value(slot->detect_pin) ^ |
1130 | slot->detect_is_active_high); | |
965ebf33 | 1131 | present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); |
7d2be074 | 1132 | |
965ebf33 HS |
1133 | dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", |
1134 | present, present_old); | |
7d2be074 | 1135 | |
965ebf33 HS |
1136 | if (present != present_old) { |
1137 | struct atmel_mci *host = slot->host; | |
1138 | struct mmc_request *mrq; | |
1139 | ||
1140 | dev_dbg(&slot->mmc->class_dev, "card %s\n", | |
7d2be074 | 1141 | present ? "inserted" : "removed"); |
7d2be074 | 1142 | |
965ebf33 HS |
1143 | spin_lock(&host->lock); |
1144 | ||
1145 | if (!present) | |
1146 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
1147 | else | |
1148 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
7d2be074 HS |
1149 | |
1150 | /* Clean up queue if present */ | |
965ebf33 | 1151 | mrq = slot->mrq; |
7d2be074 | 1152 | if (mrq) { |
965ebf33 HS |
1153 | if (mrq == host->mrq) { |
1154 | /* | |
1155 | * Reset controller to terminate any ongoing | |
1156 | * commands or data transfers. | |
1157 | */ | |
1158 | mci_writel(host, CR, MCI_CR_SWRST); | |
1159 | mci_writel(host, CR, MCI_CR_MCIEN); | |
1160 | mci_writel(host, MR, host->mode_reg); | |
74791a2d NF |
1161 | if (atmci_is_mci2()) |
1162 | mci_writel(host, CFG, host->cfg_reg); | |
965ebf33 HS |
1163 | |
1164 | host->data = NULL; | |
1165 | host->cmd = NULL; | |
1166 | ||
1167 | switch (host->state) { | |
1168 | case STATE_IDLE: | |
c06ad258 | 1169 | break; |
965ebf33 HS |
1170 | case STATE_SENDING_CMD: |
1171 | mrq->cmd->error = -ENOMEDIUM; | |
1172 | if (!mrq->data) | |
1173 | break; | |
1174 | /* fall through */ | |
1175 | case STATE_SENDING_DATA: | |
c06ad258 | 1176 | mrq->data->error = -ENOMEDIUM; |
65e8b083 | 1177 | atmci_stop_dma(host); |
c06ad258 | 1178 | break; |
965ebf33 HS |
1179 | case STATE_DATA_BUSY: |
1180 | case STATE_DATA_ERROR: | |
1181 | if (mrq->data->error == -EINPROGRESS) | |
1182 | mrq->data->error = -ENOMEDIUM; | |
1183 | if (!mrq->stop) | |
1184 | break; | |
1185 | /* fall through */ | |
1186 | case STATE_SENDING_STOP: | |
1187 | mrq->stop->error = -ENOMEDIUM; | |
1188 | break; | |
1189 | } | |
7d2be074 | 1190 | |
965ebf33 HS |
1191 | atmci_request_end(host, mrq); |
1192 | } else { | |
1193 | list_del(&slot->queue_node); | |
1194 | mrq->cmd->error = -ENOMEDIUM; | |
1195 | if (mrq->data) | |
1196 | mrq->data->error = -ENOMEDIUM; | |
1197 | if (mrq->stop) | |
1198 | mrq->stop->error = -ENOMEDIUM; | |
1199 | ||
1200 | spin_unlock(&host->lock); | |
1201 | mmc_request_done(slot->mmc, mrq); | |
1202 | spin_lock(&host->lock); | |
1203 | } | |
7d2be074 | 1204 | } |
965ebf33 | 1205 | spin_unlock(&host->lock); |
7d2be074 | 1206 | |
965ebf33 | 1207 | mmc_detect_change(slot->mmc, 0); |
7d2be074 HS |
1208 | } |
1209 | } | |
1210 | ||
1211 | static void atmci_tasklet_func(unsigned long priv) | |
1212 | { | |
965ebf33 | 1213 | struct atmel_mci *host = (struct atmel_mci *)priv; |
7d2be074 HS |
1214 | struct mmc_request *mrq = host->mrq; |
1215 | struct mmc_data *data = host->data; | |
c06ad258 HS |
1216 | struct mmc_command *cmd = host->cmd; |
1217 | enum atmel_mci_state state = host->state; | |
1218 | enum atmel_mci_state prev_state; | |
1219 | u32 status; | |
1220 | ||
965ebf33 HS |
1221 | spin_lock(&host->lock); |
1222 | ||
c06ad258 | 1223 | state = host->state; |
7d2be074 | 1224 | |
965ebf33 | 1225 | dev_vdbg(&host->pdev->dev, |
c06ad258 HS |
1226 | "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", |
1227 | state, host->pending_events, host->completed_events, | |
7d2be074 HS |
1228 | mci_readl(host, IMR)); |
1229 | ||
c06ad258 HS |
1230 | do { |
1231 | prev_state = state; | |
7d2be074 | 1232 | |
c06ad258 | 1233 | switch (state) { |
965ebf33 HS |
1234 | case STATE_IDLE: |
1235 | break; | |
1236 | ||
c06ad258 HS |
1237 | case STATE_SENDING_CMD: |
1238 | if (!atmci_test_and_clear_pending(host, | |
1239 | EVENT_CMD_COMPLETE)) | |
1240 | break; | |
7d2be074 | 1241 | |
c06ad258 HS |
1242 | host->cmd = NULL; |
1243 | atmci_set_completed(host, EVENT_CMD_COMPLETE); | |
1244 | atmci_command_complete(host, mrq->cmd); | |
1245 | if (!mrq->data || cmd->error) { | |
965ebf33 HS |
1246 | atmci_request_end(host, host->mrq); |
1247 | goto unlock; | |
c06ad258 | 1248 | } |
7d2be074 | 1249 | |
c06ad258 HS |
1250 | prev_state = state = STATE_SENDING_DATA; |
1251 | /* fall through */ | |
7d2be074 | 1252 | |
c06ad258 HS |
1253 | case STATE_SENDING_DATA: |
1254 | if (atmci_test_and_clear_pending(host, | |
1255 | EVENT_DATA_ERROR)) { | |
65e8b083 | 1256 | atmci_stop_dma(host); |
c06ad258 | 1257 | if (data->stop) |
965ebf33 | 1258 | send_stop_cmd(host, data); |
c06ad258 HS |
1259 | state = STATE_DATA_ERROR; |
1260 | break; | |
1261 | } | |
7d2be074 | 1262 | |
c06ad258 HS |
1263 | if (!atmci_test_and_clear_pending(host, |
1264 | EVENT_XFER_COMPLETE)) | |
1265 | break; | |
7d2be074 | 1266 | |
c06ad258 HS |
1267 | atmci_set_completed(host, EVENT_XFER_COMPLETE); |
1268 | prev_state = state = STATE_DATA_BUSY; | |
1269 | /* fall through */ | |
7d2be074 | 1270 | |
c06ad258 HS |
1271 | case STATE_DATA_BUSY: |
1272 | if (!atmci_test_and_clear_pending(host, | |
1273 | EVENT_DATA_COMPLETE)) | |
1274 | break; | |
1275 | ||
1276 | host->data = NULL; | |
1277 | atmci_set_completed(host, EVENT_DATA_COMPLETE); | |
1278 | status = host->data_status; | |
1279 | if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) { | |
1280 | if (status & MCI_DTOE) { | |
965ebf33 | 1281 | dev_dbg(&host->pdev->dev, |
c06ad258 HS |
1282 | "data timeout error\n"); |
1283 | data->error = -ETIMEDOUT; | |
1284 | } else if (status & MCI_DCRCE) { | |
965ebf33 | 1285 | dev_dbg(&host->pdev->dev, |
c06ad258 HS |
1286 | "data CRC error\n"); |
1287 | data->error = -EILSEQ; | |
1288 | } else { | |
965ebf33 | 1289 | dev_dbg(&host->pdev->dev, |
c06ad258 HS |
1290 | "data FIFO error (status=%08x)\n", |
1291 | status); | |
1292 | data->error = -EIO; | |
1293 | } | |
1294 | } else { | |
1295 | data->bytes_xfered = data->blocks * data->blksz; | |
1296 | data->error = 0; | |
1297 | } | |
1298 | ||
1299 | if (!data->stop) { | |
965ebf33 HS |
1300 | atmci_request_end(host, host->mrq); |
1301 | goto unlock; | |
c06ad258 | 1302 | } |
7d2be074 | 1303 | |
c06ad258 HS |
1304 | prev_state = state = STATE_SENDING_STOP; |
1305 | if (!data->error) | |
965ebf33 | 1306 | send_stop_cmd(host, data); |
c06ad258 HS |
1307 | /* fall through */ |
1308 | ||
1309 | case STATE_SENDING_STOP: | |
1310 | if (!atmci_test_and_clear_pending(host, | |
1311 | EVENT_CMD_COMPLETE)) | |
1312 | break; | |
1313 | ||
1314 | host->cmd = NULL; | |
1315 | atmci_command_complete(host, mrq->stop); | |
965ebf33 HS |
1316 | atmci_request_end(host, host->mrq); |
1317 | goto unlock; | |
c06ad258 HS |
1318 | |
1319 | case STATE_DATA_ERROR: | |
1320 | if (!atmci_test_and_clear_pending(host, | |
1321 | EVENT_XFER_COMPLETE)) | |
1322 | break; | |
1323 | ||
1324 | state = STATE_DATA_BUSY; | |
1325 | break; | |
1326 | } | |
1327 | } while (state != prev_state); | |
1328 | ||
1329 | host->state = state; | |
965ebf33 HS |
1330 | |
1331 | unlock: | |
1332 | spin_unlock(&host->lock); | |
7d2be074 HS |
1333 | } |
1334 | ||
1335 | static void atmci_read_data_pio(struct atmel_mci *host) | |
1336 | { | |
1337 | struct scatterlist *sg = host->sg; | |
1338 | void *buf = sg_virt(sg); | |
1339 | unsigned int offset = host->pio_offset; | |
1340 | struct mmc_data *data = host->data; | |
1341 | u32 value; | |
1342 | u32 status; | |
1343 | unsigned int nbytes = 0; | |
1344 | ||
1345 | do { | |
1346 | value = mci_readl(host, RDR); | |
1347 | if (likely(offset + 4 <= sg->length)) { | |
1348 | put_unaligned(value, (u32 *)(buf + offset)); | |
1349 | ||
1350 | offset += 4; | |
1351 | nbytes += 4; | |
1352 | ||
1353 | if (offset == sg->length) { | |
5e7184ae | 1354 | flush_dcache_page(sg_page(sg)); |
7d2be074 HS |
1355 | host->sg = sg = sg_next(sg); |
1356 | if (!sg) | |
1357 | goto done; | |
1358 | ||
1359 | offset = 0; | |
1360 | buf = sg_virt(sg); | |
1361 | } | |
1362 | } else { | |
1363 | unsigned int remaining = sg->length - offset; | |
1364 | memcpy(buf + offset, &value, remaining); | |
1365 | nbytes += remaining; | |
1366 | ||
1367 | flush_dcache_page(sg_page(sg)); | |
1368 | host->sg = sg = sg_next(sg); | |
1369 | if (!sg) | |
1370 | goto done; | |
1371 | ||
1372 | offset = 4 - remaining; | |
1373 | buf = sg_virt(sg); | |
1374 | memcpy(buf, (u8 *)&value + remaining, offset); | |
1375 | nbytes += offset; | |
1376 | } | |
1377 | ||
1378 | status = mci_readl(host, SR); | |
1379 | if (status & ATMCI_DATA_ERROR_FLAGS) { | |
1380 | mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY | |
1381 | | ATMCI_DATA_ERROR_FLAGS)); | |
1382 | host->data_status = status; | |
965ebf33 HS |
1383 | data->bytes_xfered += nbytes; |
1384 | smp_wmb(); | |
7d2be074 HS |
1385 | atmci_set_pending(host, EVENT_DATA_ERROR); |
1386 | tasklet_schedule(&host->tasklet); | |
965ebf33 | 1387 | return; |
7d2be074 HS |
1388 | } |
1389 | } while (status & MCI_RXRDY); | |
1390 | ||
1391 | host->pio_offset = offset; | |
1392 | data->bytes_xfered += nbytes; | |
1393 | ||
1394 | return; | |
1395 | ||
1396 | done: | |
1397 | mci_writel(host, IDR, MCI_RXRDY); | |
1398 | mci_writel(host, IER, MCI_NOTBUSY); | |
1399 | data->bytes_xfered += nbytes; | |
965ebf33 | 1400 | smp_wmb(); |
c06ad258 | 1401 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
1402 | } |
1403 | ||
1404 | static void atmci_write_data_pio(struct atmel_mci *host) | |
1405 | { | |
1406 | struct scatterlist *sg = host->sg; | |
1407 | void *buf = sg_virt(sg); | |
1408 | unsigned int offset = host->pio_offset; | |
1409 | struct mmc_data *data = host->data; | |
1410 | u32 value; | |
1411 | u32 status; | |
1412 | unsigned int nbytes = 0; | |
1413 | ||
1414 | do { | |
1415 | if (likely(offset + 4 <= sg->length)) { | |
1416 | value = get_unaligned((u32 *)(buf + offset)); | |
1417 | mci_writel(host, TDR, value); | |
1418 | ||
1419 | offset += 4; | |
1420 | nbytes += 4; | |
1421 | if (offset == sg->length) { | |
1422 | host->sg = sg = sg_next(sg); | |
1423 | if (!sg) | |
1424 | goto done; | |
1425 | ||
1426 | offset = 0; | |
1427 | buf = sg_virt(sg); | |
1428 | } | |
1429 | } else { | |
1430 | unsigned int remaining = sg->length - offset; | |
1431 | ||
1432 | value = 0; | |
1433 | memcpy(&value, buf + offset, remaining); | |
1434 | nbytes += remaining; | |
1435 | ||
1436 | host->sg = sg = sg_next(sg); | |
1437 | if (!sg) { | |
1438 | mci_writel(host, TDR, value); | |
1439 | goto done; | |
1440 | } | |
1441 | ||
1442 | offset = 4 - remaining; | |
1443 | buf = sg_virt(sg); | |
1444 | memcpy((u8 *)&value + remaining, buf, offset); | |
1445 | mci_writel(host, TDR, value); | |
1446 | nbytes += offset; | |
1447 | } | |
1448 | ||
1449 | status = mci_readl(host, SR); | |
1450 | if (status & ATMCI_DATA_ERROR_FLAGS) { | |
1451 | mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY | |
1452 | | ATMCI_DATA_ERROR_FLAGS)); | |
1453 | host->data_status = status; | |
965ebf33 HS |
1454 | data->bytes_xfered += nbytes; |
1455 | smp_wmb(); | |
7d2be074 HS |
1456 | atmci_set_pending(host, EVENT_DATA_ERROR); |
1457 | tasklet_schedule(&host->tasklet); | |
965ebf33 | 1458 | return; |
7d2be074 HS |
1459 | } |
1460 | } while (status & MCI_TXRDY); | |
1461 | ||
1462 | host->pio_offset = offset; | |
1463 | data->bytes_xfered += nbytes; | |
1464 | ||
1465 | return; | |
1466 | ||
1467 | done: | |
1468 | mci_writel(host, IDR, MCI_TXRDY); | |
1469 | mci_writel(host, IER, MCI_NOTBUSY); | |
1470 | data->bytes_xfered += nbytes; | |
965ebf33 | 1471 | smp_wmb(); |
c06ad258 | 1472 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
1473 | } |
1474 | ||
965ebf33 | 1475 | static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status) |
7d2be074 | 1476 | { |
7d2be074 HS |
1477 | mci_writel(host, IDR, MCI_CMDRDY); |
1478 | ||
c06ad258 | 1479 | host->cmd_status = status; |
965ebf33 | 1480 | smp_wmb(); |
c06ad258 | 1481 | atmci_set_pending(host, EVENT_CMD_COMPLETE); |
7d2be074 HS |
1482 | tasklet_schedule(&host->tasklet); |
1483 | } | |
1484 | ||
1485 | static irqreturn_t atmci_interrupt(int irq, void *dev_id) | |
1486 | { | |
965ebf33 | 1487 | struct atmel_mci *host = dev_id; |
7d2be074 HS |
1488 | u32 status, mask, pending; |
1489 | unsigned int pass_count = 0; | |
1490 | ||
7d2be074 HS |
1491 | do { |
1492 | status = mci_readl(host, SR); | |
1493 | mask = mci_readl(host, IMR); | |
1494 | pending = status & mask; | |
1495 | if (!pending) | |
1496 | break; | |
1497 | ||
1498 | if (pending & ATMCI_DATA_ERROR_FLAGS) { | |
1499 | mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS | |
1500 | | MCI_RXRDY | MCI_TXRDY); | |
1501 | pending &= mci_readl(host, IMR); | |
965ebf33 | 1502 | |
7d2be074 | 1503 | host->data_status = status; |
965ebf33 | 1504 | smp_wmb(); |
7d2be074 HS |
1505 | atmci_set_pending(host, EVENT_DATA_ERROR); |
1506 | tasklet_schedule(&host->tasklet); | |
1507 | } | |
1508 | if (pending & MCI_NOTBUSY) { | |
c06ad258 HS |
1509 | mci_writel(host, IDR, |
1510 | ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY); | |
ca55f46e HS |
1511 | if (!host->data_status) |
1512 | host->data_status = status; | |
965ebf33 | 1513 | smp_wmb(); |
7d2be074 HS |
1514 | atmci_set_pending(host, EVENT_DATA_COMPLETE); |
1515 | tasklet_schedule(&host->tasklet); | |
1516 | } | |
1517 | if (pending & MCI_RXRDY) | |
1518 | atmci_read_data_pio(host); | |
1519 | if (pending & MCI_TXRDY) | |
1520 | atmci_write_data_pio(host); | |
1521 | ||
1522 | if (pending & MCI_CMDRDY) | |
965ebf33 | 1523 | atmci_cmd_interrupt(host, status); |
7d2be074 HS |
1524 | } while (pass_count++ < 5); |
1525 | ||
7d2be074 HS |
1526 | return pass_count ? IRQ_HANDLED : IRQ_NONE; |
1527 | } | |
1528 | ||
1529 | static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) | |
1530 | { | |
965ebf33 | 1531 | struct atmel_mci_slot *slot = dev_id; |
7d2be074 HS |
1532 | |
1533 | /* | |
1534 | * Disable interrupts until the pin has stabilized and check | |
1535 | * the state then. Use mod_timer() since we may be in the | |
1536 | * middle of the timer routine when this interrupt triggers. | |
1537 | */ | |
1538 | disable_irq_nosync(irq); | |
965ebf33 | 1539 | mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); |
7d2be074 HS |
1540 | |
1541 | return IRQ_HANDLED; | |
1542 | } | |
1543 | ||
965ebf33 HS |
1544 | static int __init atmci_init_slot(struct atmel_mci *host, |
1545 | struct mci_slot_pdata *slot_data, unsigned int id, | |
1546 | u32 sdc_reg) | |
1547 | { | |
1548 | struct mmc_host *mmc; | |
1549 | struct atmel_mci_slot *slot; | |
1550 | ||
1551 | mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); | |
1552 | if (!mmc) | |
1553 | return -ENOMEM; | |
1554 | ||
1555 | slot = mmc_priv(mmc); | |
1556 | slot->mmc = mmc; | |
1557 | slot->host = host; | |
1558 | slot->detect_pin = slot_data->detect_pin; | |
1559 | slot->wp_pin = slot_data->wp_pin; | |
1c1452be | 1560 | slot->detect_is_active_high = slot_data->detect_is_active_high; |
965ebf33 HS |
1561 | slot->sdc_reg = sdc_reg; |
1562 | ||
1563 | mmc->ops = &atmci_ops; | |
1564 | mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); | |
1565 | mmc->f_max = host->bus_hz / 2; | |
1566 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
1567 | if (slot_data->bus_width >= 4) | |
1568 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1569 | ||
1570 | mmc->max_hw_segs = 64; | |
1571 | mmc->max_phys_segs = 64; | |
1572 | mmc->max_req_size = 32768 * 512; | |
1573 | mmc->max_blk_size = 32768; | |
1574 | mmc->max_blk_count = 512; | |
1575 | ||
1576 | /* Assume card is present initially */ | |
1577 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
1578 | if (gpio_is_valid(slot->detect_pin)) { | |
1579 | if (gpio_request(slot->detect_pin, "mmc_detect")) { | |
1580 | dev_dbg(&mmc->class_dev, "no detect pin available\n"); | |
1581 | slot->detect_pin = -EBUSY; | |
1c1452be JL |
1582 | } else if (gpio_get_value(slot->detect_pin) ^ |
1583 | slot->detect_is_active_high) { | |
965ebf33 HS |
1584 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); |
1585 | } | |
1586 | } | |
1587 | ||
1588 | if (!gpio_is_valid(slot->detect_pin)) | |
1589 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
1590 | ||
1591 | if (gpio_is_valid(slot->wp_pin)) { | |
1592 | if (gpio_request(slot->wp_pin, "mmc_wp")) { | |
1593 | dev_dbg(&mmc->class_dev, "no WP pin available\n"); | |
1594 | slot->wp_pin = -EBUSY; | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | host->slot[id] = slot; | |
1599 | mmc_add_host(mmc); | |
1600 | ||
1601 | if (gpio_is_valid(slot->detect_pin)) { | |
1602 | int ret; | |
1603 | ||
1604 | setup_timer(&slot->detect_timer, atmci_detect_change, | |
1605 | (unsigned long)slot); | |
1606 | ||
1607 | ret = request_irq(gpio_to_irq(slot->detect_pin), | |
1608 | atmci_detect_interrupt, | |
1609 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | |
1610 | "mmc-detect", slot); | |
1611 | if (ret) { | |
1612 | dev_dbg(&mmc->class_dev, | |
1613 | "could not request IRQ %d for detect pin\n", | |
1614 | gpio_to_irq(slot->detect_pin)); | |
1615 | gpio_free(slot->detect_pin); | |
1616 | slot->detect_pin = -EBUSY; | |
1617 | } | |
1618 | } | |
1619 | ||
1620 | atmci_init_debugfs(slot); | |
1621 | ||
1622 | return 0; | |
1623 | } | |
1624 | ||
1625 | static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot, | |
1626 | unsigned int id) | |
1627 | { | |
1628 | /* Debugfs stuff is cleaned up by mmc core */ | |
1629 | ||
1630 | set_bit(ATMCI_SHUTDOWN, &slot->flags); | |
1631 | smp_wmb(); | |
1632 | ||
1633 | mmc_remove_host(slot->mmc); | |
1634 | ||
1635 | if (gpio_is_valid(slot->detect_pin)) { | |
1636 | int pin = slot->detect_pin; | |
1637 | ||
1638 | free_irq(gpio_to_irq(pin), slot); | |
1639 | del_timer_sync(&slot->detect_timer); | |
1640 | gpio_free(pin); | |
1641 | } | |
1642 | if (gpio_is_valid(slot->wp_pin)) | |
1643 | gpio_free(slot->wp_pin); | |
1644 | ||
1645 | slot->host->slot[id] = NULL; | |
1646 | mmc_free_host(slot->mmc); | |
1647 | } | |
1648 | ||
74465b4f | 1649 | #ifdef CONFIG_MMC_ATMELMCI_DMA |
7dd60251 | 1650 | static bool filter(struct dma_chan *chan, void *slave) |
74465b4f | 1651 | { |
2635d1ba | 1652 | struct mci_dma_data *sl = slave; |
74465b4f | 1653 | |
2635d1ba NF |
1654 | if (sl && find_slave_dev(sl) == chan->device->dev) { |
1655 | chan->private = slave_data_ptr(sl); | |
7dd60251 | 1656 | return true; |
2635d1ba | 1657 | } else { |
7dd60251 | 1658 | return false; |
2635d1ba | 1659 | } |
74465b4f | 1660 | } |
2635d1ba NF |
1661 | |
1662 | static void atmci_configure_dma(struct atmel_mci *host) | |
1663 | { | |
1664 | struct mci_platform_data *pdata; | |
1665 | ||
1666 | if (host == NULL) | |
1667 | return; | |
1668 | ||
1669 | pdata = host->pdev->dev.platform_data; | |
1670 | ||
1671 | if (pdata && find_slave_dev(pdata->dma_slave)) { | |
1672 | dma_cap_mask_t mask; | |
1673 | ||
1674 | setup_dma_addr(pdata->dma_slave, | |
1675 | host->mapbase + MCI_TDR, | |
1676 | host->mapbase + MCI_RDR); | |
1677 | ||
1678 | /* Try to grab a DMA channel */ | |
1679 | dma_cap_zero(mask); | |
1680 | dma_cap_set(DMA_SLAVE, mask); | |
1681 | host->dma.chan = | |
1682 | dma_request_channel(mask, filter, pdata->dma_slave); | |
1683 | } | |
1684 | if (!host->dma.chan) | |
1685 | dev_notice(&host->pdev->dev, "DMA not available, using PIO\n"); | |
74791a2d NF |
1686 | else |
1687 | dev_info(&host->pdev->dev, | |
1688 | "Using %s for DMA transfers\n", | |
1689 | dma_chan_name(host->dma.chan)); | |
2635d1ba NF |
1690 | } |
1691 | #else | |
1692 | static void atmci_configure_dma(struct atmel_mci *host) {} | |
74465b4f DW |
1693 | #endif |
1694 | ||
7d2be074 HS |
1695 | static int __init atmci_probe(struct platform_device *pdev) |
1696 | { | |
1697 | struct mci_platform_data *pdata; | |
965ebf33 HS |
1698 | struct atmel_mci *host; |
1699 | struct resource *regs; | |
1700 | unsigned int nr_slots; | |
1701 | int irq; | |
1702 | int ret; | |
7d2be074 HS |
1703 | |
1704 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1705 | if (!regs) | |
1706 | return -ENXIO; | |
1707 | pdata = pdev->dev.platform_data; | |
1708 | if (!pdata) | |
1709 | return -ENXIO; | |
1710 | irq = platform_get_irq(pdev, 0); | |
1711 | if (irq < 0) | |
1712 | return irq; | |
1713 | ||
965ebf33 HS |
1714 | host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL); |
1715 | if (!host) | |
7d2be074 HS |
1716 | return -ENOMEM; |
1717 | ||
7d2be074 | 1718 | host->pdev = pdev; |
965ebf33 HS |
1719 | spin_lock_init(&host->lock); |
1720 | INIT_LIST_HEAD(&host->queue); | |
7d2be074 HS |
1721 | |
1722 | host->mck = clk_get(&pdev->dev, "mci_clk"); | |
1723 | if (IS_ERR(host->mck)) { | |
1724 | ret = PTR_ERR(host->mck); | |
1725 | goto err_clk_get; | |
1726 | } | |
1727 | ||
1728 | ret = -ENOMEM; | |
1729 | host->regs = ioremap(regs->start, regs->end - regs->start + 1); | |
1730 | if (!host->regs) | |
1731 | goto err_ioremap; | |
1732 | ||
1733 | clk_enable(host->mck); | |
1734 | mci_writel(host, CR, MCI_CR_SWRST); | |
1735 | host->bus_hz = clk_get_rate(host->mck); | |
1736 | clk_disable(host->mck); | |
1737 | ||
1738 | host->mapbase = regs->start; | |
1739 | ||
965ebf33 | 1740 | tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); |
7d2be074 | 1741 | |
89c8aa20 | 1742 | ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); |
7d2be074 HS |
1743 | if (ret) |
1744 | goto err_request_irq; | |
1745 | ||
2635d1ba | 1746 | atmci_configure_dma(host); |
65e8b083 | 1747 | |
7d2be074 HS |
1748 | platform_set_drvdata(pdev, host); |
1749 | ||
965ebf33 HS |
1750 | /* We need at least one slot to succeed */ |
1751 | nr_slots = 0; | |
1752 | ret = -ENODEV; | |
1753 | if (pdata->slot[0].bus_width) { | |
1754 | ret = atmci_init_slot(host, &pdata->slot[0], | |
ebb1fea9 | 1755 | 0, MCI_SDCSEL_SLOT_A); |
965ebf33 HS |
1756 | if (!ret) |
1757 | nr_slots++; | |
1758 | } | |
1759 | if (pdata->slot[1].bus_width) { | |
1760 | ret = atmci_init_slot(host, &pdata->slot[1], | |
ebb1fea9 | 1761 | 1, MCI_SDCSEL_SLOT_B); |
965ebf33 HS |
1762 | if (!ret) |
1763 | nr_slots++; | |
7d2be074 HS |
1764 | } |
1765 | ||
04d699c3 RE |
1766 | if (!nr_slots) { |
1767 | dev_err(&pdev->dev, "init failed: no slot defined\n"); | |
965ebf33 | 1768 | goto err_init_slot; |
04d699c3 | 1769 | } |
7d2be074 | 1770 | |
965ebf33 HS |
1771 | dev_info(&pdev->dev, |
1772 | "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", | |
1773 | host->mapbase, irq, nr_slots); | |
deec9ae3 | 1774 | |
7d2be074 HS |
1775 | return 0; |
1776 | ||
965ebf33 | 1777 | err_init_slot: |
65e8b083 | 1778 | #ifdef CONFIG_MMC_ATMELMCI_DMA |
74465b4f DW |
1779 | if (host->dma.chan) |
1780 | dma_release_channel(host->dma.chan); | |
65e8b083 | 1781 | #endif |
965ebf33 | 1782 | free_irq(irq, host); |
7d2be074 HS |
1783 | err_request_irq: |
1784 | iounmap(host->regs); | |
1785 | err_ioremap: | |
1786 | clk_put(host->mck); | |
1787 | err_clk_get: | |
965ebf33 | 1788 | kfree(host); |
7d2be074 HS |
1789 | return ret; |
1790 | } | |
1791 | ||
1792 | static int __exit atmci_remove(struct platform_device *pdev) | |
1793 | { | |
965ebf33 HS |
1794 | struct atmel_mci *host = platform_get_drvdata(pdev); |
1795 | unsigned int i; | |
7d2be074 HS |
1796 | |
1797 | platform_set_drvdata(pdev, NULL); | |
1798 | ||
965ebf33 HS |
1799 | for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { |
1800 | if (host->slot[i]) | |
1801 | atmci_cleanup_slot(host->slot[i], i); | |
1802 | } | |
7d2be074 | 1803 | |
965ebf33 HS |
1804 | clk_enable(host->mck); |
1805 | mci_writel(host, IDR, ~0UL); | |
1806 | mci_writel(host, CR, MCI_CR_MCIDIS); | |
1807 | mci_readl(host, SR); | |
1808 | clk_disable(host->mck); | |
7d2be074 | 1809 | |
65e8b083 | 1810 | #ifdef CONFIG_MMC_ATMELMCI_DMA |
74465b4f DW |
1811 | if (host->dma.chan) |
1812 | dma_release_channel(host->dma.chan); | |
65e8b083 HS |
1813 | #endif |
1814 | ||
965ebf33 HS |
1815 | free_irq(platform_get_irq(pdev, 0), host); |
1816 | iounmap(host->regs); | |
7d2be074 | 1817 | |
965ebf33 HS |
1818 | clk_put(host->mck); |
1819 | kfree(host); | |
7d2be074 | 1820 | |
7d2be074 HS |
1821 | return 0; |
1822 | } | |
1823 | ||
1824 | static struct platform_driver atmci_driver = { | |
1825 | .remove = __exit_p(atmci_remove), | |
1826 | .driver = { | |
1827 | .name = "atmel_mci", | |
1828 | }, | |
1829 | }; | |
1830 | ||
1831 | static int __init atmci_init(void) | |
1832 | { | |
1833 | return platform_driver_probe(&atmci_driver, atmci_probe); | |
1834 | } | |
1835 | ||
1836 | static void __exit atmci_exit(void) | |
1837 | { | |
1838 | platform_driver_unregister(&atmci_driver); | |
1839 | } | |
1840 | ||
74465b4f | 1841 | late_initcall(atmci_init); /* try to load after dma driver when built-in */ |
7d2be074 HS |
1842 | module_exit(atmci_exit); |
1843 | ||
1844 | MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); | |
1845 | MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>"); | |
1846 | MODULE_LICENSE("GPL v2"); |