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7d2be074 HS |
1 | /* |
2 | * Atmel MultiMedia Card Interface driver | |
3 | * | |
4 | * Copyright (C) 2004-2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/blkdev.h> | |
11 | #include <linux/clk.h> | |
deec9ae3 | 12 | #include <linux/debugfs.h> |
7d2be074 | 13 | #include <linux/device.h> |
65e8b083 HS |
14 | #include <linux/dmaengine.h> |
15 | #include <linux/dma-mapping.h> | |
fbfca4b8 | 16 | #include <linux/err.h> |
3c26e170 | 17 | #include <linux/gpio.h> |
7d2be074 HS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
7bca646e | 20 | #include <linux/io.h> |
7d2be074 HS |
21 | #include <linux/ioport.h> |
22 | #include <linux/module.h> | |
e919fd20 LD |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | |
25 | #include <linux/of_gpio.h> | |
7d2be074 HS |
26 | #include <linux/platform_device.h> |
27 | #include <linux/scatterlist.h> | |
deec9ae3 | 28 | #include <linux/seq_file.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
deec9ae3 | 30 | #include <linux/stat.h> |
e2b35f3d | 31 | #include <linux/types.h> |
7d2be074 HS |
32 | |
33 | #include <linux/mmc/host.h> | |
2f1d7918 | 34 | #include <linux/mmc/sdio.h> |
2635d1ba | 35 | |
c42aa775 | 36 | #include <linux/atmel-mci.h> |
796211b7 | 37 | #include <linux/atmel_pdc.h> |
ae552ab0 WY |
38 | #include <linux/pm.h> |
39 | #include <linux/pm_runtime.h> | |
b5b64fa6 | 40 | #include <linux/pinctrl/consumer.h> |
7d2be074 | 41 | |
bf614c7a | 42 | #include <asm/cacheflush.h> |
7d2be074 HS |
43 | #include <asm/io.h> |
44 | #include <asm/unaligned.h> | |
45 | ||
ec8fc9cf | 46 | /* |
47 | * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors | |
48 | * Registers and bitfields marked with [2] are only available in MCI2 | |
49 | */ | |
50 | ||
51 | /* MCI Register Definitions */ | |
52 | #define ATMCI_CR 0x0000 /* Control */ | |
53 | #define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */ | |
54 | #define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */ | |
55 | #define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */ | |
56 | #define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */ | |
57 | #define ATMCI_CR_SWRST BIT(7) /* Software Reset */ | |
58 | #define ATMCI_MR 0x0004 /* Mode */ | |
59 | #define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */ | |
60 | #define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */ | |
61 | #define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */ | |
62 | #define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */ | |
63 | #define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */ | |
64 | #define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */ | |
65 | #define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */ | |
66 | #define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */ | |
67 | #define ATMCI_DTOR 0x0008 /* Data Timeout */ | |
68 | #define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */ | |
69 | #define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */ | |
70 | #define ATMCI_SDCR 0x000c /* SD Card / SDIO */ | |
71 | #define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */ | |
72 | #define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */ | |
73 | #define ATMCI_SDCSEL_MASK (3 << 0) | |
74 | #define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */ | |
75 | #define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */ | |
76 | #define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */ | |
77 | #define ATMCI_SDCBUS_MASK (3 << 6) | |
78 | #define ATMCI_ARGR 0x0010 /* Command Argument */ | |
79 | #define ATMCI_CMDR 0x0014 /* Command */ | |
80 | #define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */ | |
81 | #define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */ | |
82 | #define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */ | |
83 | #define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */ | |
84 | #define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */ | |
85 | #define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */ | |
86 | #define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */ | |
87 | #define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */ | |
88 | #define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */ | |
89 | #define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */ | |
90 | #define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */ | |
91 | #define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */ | |
92 | #define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */ | |
93 | #define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */ | |
94 | #define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */ | |
95 | #define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */ | |
96 | #define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */ | |
97 | #define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */ | |
98 | #define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */ | |
99 | #define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */ | |
100 | #define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */ | |
101 | #define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */ | |
102 | #define ATMCI_BLKR 0x0018 /* Block */ | |
103 | #define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */ | |
104 | #define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */ | |
105 | #define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */ | |
106 | #define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */ | |
107 | #define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */ | |
108 | #define ATMCI_RSPR 0x0020 /* Response 0 */ | |
109 | #define ATMCI_RSPR1 0x0024 /* Response 1 */ | |
110 | #define ATMCI_RSPR2 0x0028 /* Response 2 */ | |
111 | #define ATMCI_RSPR3 0x002c /* Response 3 */ | |
112 | #define ATMCI_RDR 0x0030 /* Receive Data */ | |
113 | #define ATMCI_TDR 0x0034 /* Transmit Data */ | |
114 | #define ATMCI_SR 0x0040 /* Status */ | |
115 | #define ATMCI_IER 0x0044 /* Interrupt Enable */ | |
116 | #define ATMCI_IDR 0x0048 /* Interrupt Disable */ | |
117 | #define ATMCI_IMR 0x004c /* Interrupt Mask */ | |
118 | #define ATMCI_CMDRDY BIT(0) /* Command Ready */ | |
119 | #define ATMCI_RXRDY BIT(1) /* Receiver Ready */ | |
120 | #define ATMCI_TXRDY BIT(2) /* Transmitter Ready */ | |
121 | #define ATMCI_BLKE BIT(3) /* Data Block Ended */ | |
122 | #define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */ | |
123 | #define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */ | |
124 | #define ATMCI_ENDRX BIT(6) /* End of RX Buffer */ | |
125 | #define ATMCI_ENDTX BIT(7) /* End of TX Buffer */ | |
126 | #define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */ | |
127 | #define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */ | |
128 | #define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */ | |
129 | #define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */ | |
130 | #define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */ | |
131 | #define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */ | |
132 | #define ATMCI_RINDE BIT(16) /* Response Index Error */ | |
133 | #define ATMCI_RDIRE BIT(17) /* Response Direction Error */ | |
134 | #define ATMCI_RCRCE BIT(18) /* Response CRC Error */ | |
135 | #define ATMCI_RENDE BIT(19) /* Response End Bit Error */ | |
136 | #define ATMCI_RTOE BIT(20) /* Response Time-Out Error */ | |
137 | #define ATMCI_DCRCE BIT(21) /* Data CRC Error */ | |
138 | #define ATMCI_DTOE BIT(22) /* Data Time-Out Error */ | |
139 | #define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */ | |
140 | #define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */ | |
141 | #define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */ | |
142 | #define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */ | |
143 | #define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */ | |
144 | #define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */ | |
145 | #define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */ | |
146 | #define ATMCI_OVRE BIT(30) /* RX Overrun Error */ | |
147 | #define ATMCI_UNRE BIT(31) /* TX Underrun Error */ | |
148 | #define ATMCI_DMA 0x0050 /* DMA Configuration[2] */ | |
149 | #define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */ | |
150 | #define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */ | |
151 | #define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */ | |
152 | #define ATMCI_CFG 0x0054 /* Configuration[2] */ | |
153 | #define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */ | |
154 | #define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */ | |
155 | #define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */ | |
156 | #define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */ | |
157 | #define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */ | |
158 | #define ATMCI_WP_EN BIT(0) /* WP Enable */ | |
159 | #define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */ | |
160 | #define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */ | |
161 | #define ATMCI_GET_WP_VS(x) ((x) & 0x0f) | |
162 | #define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff) | |
163 | #define ATMCI_VERSION 0x00FC /* Version */ | |
164 | #define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */ | |
165 | ||
166 | /* This is not including the FIFO Aperture on MCI2 */ | |
167 | #define ATMCI_REGS_SIZE 0x100 | |
168 | ||
169 | /* Register access macros */ | |
170 | #define atmci_readl(port, reg) \ | |
171 | __raw_readl((port)->regs + reg) | |
172 | #define atmci_writel(port, reg, value) \ | |
173 | __raw_writel((value), (port)->regs + reg) | |
174 | ||
175 | /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */ | |
176 | #ifdef CONFIG_AVR32 | |
177 | # define ATMCI_PDC_CONNECTED 0 | |
178 | #else | |
179 | # define ATMCI_PDC_CONNECTED 1 | |
180 | #endif | |
181 | ||
ae552ab0 WY |
182 | #define AUTOSUSPEND_DELAY 50 |
183 | ||
2c96a293 | 184 | #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE) |
65e8b083 | 185 | #define ATMCI_DMA_THRESHOLD 16 |
7d2be074 HS |
186 | |
187 | enum { | |
f5177547 | 188 | EVENT_CMD_RDY = 0, |
7d2be074 | 189 | EVENT_XFER_COMPLETE, |
f5177547 | 190 | EVENT_NOTBUSY, |
c06ad258 HS |
191 | EVENT_DATA_ERROR, |
192 | }; | |
193 | ||
194 | enum atmel_mci_state { | |
965ebf33 HS |
195 | STATE_IDLE = 0, |
196 | STATE_SENDING_CMD, | |
f5177547 LD |
197 | STATE_DATA_XFER, |
198 | STATE_WAITING_NOTBUSY, | |
c06ad258 | 199 | STATE_SENDING_STOP, |
f5177547 | 200 | STATE_END_REQUEST, |
7d2be074 HS |
201 | }; |
202 | ||
796211b7 LD |
203 | enum atmci_xfer_dir { |
204 | XFER_RECEIVE = 0, | |
205 | XFER_TRANSMIT, | |
206 | }; | |
207 | ||
208 | enum atmci_pdc_buf { | |
209 | PDC_FIRST_BUF = 0, | |
210 | PDC_SECOND_BUF, | |
211 | }; | |
212 | ||
213 | struct atmel_mci_caps { | |
ccdfe612 | 214 | bool has_dma_conf_reg; |
796211b7 LD |
215 | bool has_pdc; |
216 | bool has_cfg_reg; | |
217 | bool has_cstor_reg; | |
218 | bool has_highspeed; | |
219 | bool has_rwproof; | |
faf8180b | 220 | bool has_odd_clk_div; |
24011f34 LD |
221 | bool has_bad_data_ordering; |
222 | bool need_reset_after_xfer; | |
223 | bool need_blksz_mul_4; | |
077d4073 | 224 | bool need_notbusy_for_read_ops; |
796211b7 LD |
225 | }; |
226 | ||
65e8b083 | 227 | struct atmel_mci_dma { |
65e8b083 HS |
228 | struct dma_chan *chan; |
229 | struct dma_async_tx_descriptor *data_desc; | |
65e8b083 HS |
230 | }; |
231 | ||
965ebf33 HS |
232 | /** |
233 | * struct atmel_mci - MMC controller state shared between all slots | |
234 | * @lock: Spinlock protecting the queue and associated data. | |
235 | * @regs: Pointer to MMIO registers. | |
796211b7 | 236 | * @sg: Scatterlist entry currently being processed by PIO or PDC code. |
965ebf33 | 237 | * @pio_offset: Offset into the current scatterlist entry. |
7a90dcc2 LD |
238 | * @buffer: Buffer used if we don't have the r/w proof capability. We |
239 | * don't have the time to switch pdc buffers so we have to use only | |
240 | * one buffer for the full transaction. | |
241 | * @buf_size: size of the buffer. | |
242 | * @phys_buf_addr: buffer address needed for pdc. | |
965ebf33 HS |
243 | * @cur_slot: The slot which is currently using the controller. |
244 | * @mrq: The request currently being processed on @cur_slot, | |
245 | * or NULL if the controller is idle. | |
246 | * @cmd: The command currently being sent to the card, or NULL. | |
247 | * @data: The data currently being transferred, or NULL if no data | |
248 | * transfer is in progress. | |
796211b7 | 249 | * @data_size: just data->blocks * data->blksz. |
65e8b083 HS |
250 | * @dma: DMA client state. |
251 | * @data_chan: DMA channel being used for the current data transfer. | |
965ebf33 HS |
252 | * @cmd_status: Snapshot of SR taken upon completion of the current |
253 | * command. Only valid when EVENT_CMD_COMPLETE is pending. | |
254 | * @data_status: Snapshot of SR taken upon completion of the current | |
255 | * data transfer. Only valid when EVENT_DATA_COMPLETE or | |
256 | * EVENT_DATA_ERROR is pending. | |
257 | * @stop_cmdr: Value to be loaded into CMDR when the stop command is | |
258 | * to be sent. | |
259 | * @tasklet: Tasklet running the request state machine. | |
260 | * @pending_events: Bitmask of events flagged by the interrupt handler | |
261 | * to be processed by the tasklet. | |
262 | * @completed_events: Bitmask of events which the state machine has | |
263 | * processed. | |
264 | * @state: Tasklet state. | |
265 | * @queue: List of slots waiting for access to the controller. | |
266 | * @need_clock_update: Update the clock rate before the next request. | |
267 | * @need_reset: Reset controller before next request. | |
24011f34 | 268 | * @timer: Timer to balance the data timeout error flag which cannot rise. |
965ebf33 | 269 | * @mode_reg: Value of the MR register. |
74791a2d | 270 | * @cfg_reg: Value of the CFG register. |
965ebf33 HS |
271 | * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus |
272 | * rate and timeout calculations. | |
273 | * @mapbase: Physical address of the MMIO registers. | |
274 | * @mck: The peripheral bus clock hooked up to the MMC controller. | |
275 | * @pdev: Platform device associated with the MMC controller. | |
276 | * @slot: Slots sharing this MMC controller. | |
796211b7 LD |
277 | * @caps: MCI capabilities depending on MCI version. |
278 | * @prepare_data: function to setup MCI before data transfer which | |
279 | * depends on MCI capabilities. | |
280 | * @submit_data: function to start data transfer which depends on MCI | |
281 | * capabilities. | |
282 | * @stop_transfer: function to stop data transfer which depends on MCI | |
283 | * capabilities. | |
965ebf33 HS |
284 | * |
285 | * Locking | |
286 | * ======= | |
287 | * | |
288 | * @lock is a softirq-safe spinlock protecting @queue as well as | |
289 | * @cur_slot, @mrq and @state. These must always be updated | |
290 | * at the same time while holding @lock. | |
291 | * | |
292 | * @lock also protects mode_reg and need_clock_update since these are | |
293 | * used to synchronize mode register updates with the queue | |
294 | * processing. | |
295 | * | |
296 | * The @mrq field of struct atmel_mci_slot is also protected by @lock, | |
297 | * and must always be written at the same time as the slot is added to | |
298 | * @queue. | |
299 | * | |
300 | * @pending_events and @completed_events are accessed using atomic bit | |
301 | * operations, so they don't need any locking. | |
302 | * | |
303 | * None of the fields touched by the interrupt handler need any | |
304 | * locking. However, ordering is important: Before EVENT_DATA_ERROR or | |
305 | * EVENT_DATA_COMPLETE is set in @pending_events, all data-related | |
306 | * interrupts must be disabled and @data_status updated with a | |
307 | * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the | |
25985edc | 308 | * CMDRDY interrupt must be disabled and @cmd_status updated with a |
965ebf33 HS |
309 | * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the |
310 | * bytes_xfered field of @data must be written. This is ensured by | |
311 | * using barriers. | |
312 | */ | |
7d2be074 | 313 | struct atmel_mci { |
965ebf33 | 314 | spinlock_t lock; |
7d2be074 HS |
315 | void __iomem *regs; |
316 | ||
317 | struct scatterlist *sg; | |
bdbc5d0c | 318 | unsigned int sg_len; |
7d2be074 | 319 | unsigned int pio_offset; |
7a90dcc2 LD |
320 | unsigned int *buffer; |
321 | unsigned int buf_size; | |
322 | dma_addr_t buf_phys_addr; | |
7d2be074 | 323 | |
965ebf33 | 324 | struct atmel_mci_slot *cur_slot; |
7d2be074 HS |
325 | struct mmc_request *mrq; |
326 | struct mmc_command *cmd; | |
327 | struct mmc_data *data; | |
796211b7 | 328 | unsigned int data_size; |
7d2be074 | 329 | |
65e8b083 HS |
330 | struct atmel_mci_dma dma; |
331 | struct dma_chan *data_chan; | |
e2b35f3d | 332 | struct dma_slave_config dma_conf; |
65e8b083 | 333 | |
7d2be074 HS |
334 | u32 cmd_status; |
335 | u32 data_status; | |
7d2be074 HS |
336 | u32 stop_cmdr; |
337 | ||
7d2be074 HS |
338 | struct tasklet_struct tasklet; |
339 | unsigned long pending_events; | |
340 | unsigned long completed_events; | |
c06ad258 | 341 | enum atmel_mci_state state; |
965ebf33 | 342 | struct list_head queue; |
7d2be074 | 343 | |
965ebf33 HS |
344 | bool need_clock_update; |
345 | bool need_reset; | |
24011f34 | 346 | struct timer_list timer; |
965ebf33 | 347 | u32 mode_reg; |
74791a2d | 348 | u32 cfg_reg; |
7d2be074 HS |
349 | unsigned long bus_hz; |
350 | unsigned long mapbase; | |
351 | struct clk *mck; | |
352 | struct platform_device *pdev; | |
965ebf33 | 353 | |
2c96a293 | 354 | struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; |
796211b7 LD |
355 | |
356 | struct atmel_mci_caps caps; | |
357 | ||
358 | u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data); | |
359 | void (*submit_data)(struct atmel_mci *host, struct mmc_data *data); | |
360 | void (*stop_transfer)(struct atmel_mci *host); | |
965ebf33 HS |
361 | }; |
362 | ||
363 | /** | |
364 | * struct atmel_mci_slot - MMC slot state | |
365 | * @mmc: The mmc_host representing this slot. | |
366 | * @host: The MMC controller this slot is using. | |
367 | * @sdc_reg: Value of SDCR to be written before using this slot. | |
88ff82ed | 368 | * @sdio_irq: SDIO irq mask for this slot. |
965ebf33 HS |
369 | * @mrq: mmc_request currently being processed or waiting to be |
370 | * processed, or NULL when the slot is idle. | |
371 | * @queue_node: List node for placing this node in the @queue list of | |
372 | * &struct atmel_mci. | |
373 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. | |
374 | * @flags: Random state bits associated with the slot. | |
375 | * @detect_pin: GPIO pin used for card detection, or negative if not | |
376 | * available. | |
377 | * @wp_pin: GPIO pin used for card write protect sending, or negative | |
378 | * if not available. | |
1c1452be | 379 | * @detect_is_active_high: The state of the detect pin when it is active. |
965ebf33 HS |
380 | * @detect_timer: Timer used for debouncing @detect_pin interrupts. |
381 | */ | |
382 | struct atmel_mci_slot { | |
383 | struct mmc_host *mmc; | |
384 | struct atmel_mci *host; | |
385 | ||
386 | u32 sdc_reg; | |
88ff82ed | 387 | u32 sdio_irq; |
965ebf33 HS |
388 | |
389 | struct mmc_request *mrq; | |
390 | struct list_head queue_node; | |
391 | ||
392 | unsigned int clock; | |
393 | unsigned long flags; | |
394 | #define ATMCI_CARD_PRESENT 0 | |
395 | #define ATMCI_CARD_NEED_INIT 1 | |
396 | #define ATMCI_SHUTDOWN 2 | |
397 | ||
398 | int detect_pin; | |
399 | int wp_pin; | |
1c1452be | 400 | bool detect_is_active_high; |
965ebf33 HS |
401 | |
402 | struct timer_list detect_timer; | |
7d2be074 HS |
403 | }; |
404 | ||
7d2be074 HS |
405 | #define atmci_test_and_clear_pending(host, event) \ |
406 | test_and_clear_bit(event, &host->pending_events) | |
7d2be074 HS |
407 | #define atmci_set_completed(host, event) \ |
408 | set_bit(event, &host->completed_events) | |
409 | #define atmci_set_pending(host, event) \ | |
410 | set_bit(event, &host->pending_events) | |
7d2be074 | 411 | |
deec9ae3 HS |
412 | /* |
413 | * The debugfs stuff below is mostly optimized away when | |
414 | * CONFIG_DEBUG_FS is not set. | |
415 | */ | |
416 | static int atmci_req_show(struct seq_file *s, void *v) | |
417 | { | |
965ebf33 HS |
418 | struct atmel_mci_slot *slot = s->private; |
419 | struct mmc_request *mrq; | |
deec9ae3 HS |
420 | struct mmc_command *cmd; |
421 | struct mmc_command *stop; | |
422 | struct mmc_data *data; | |
423 | ||
424 | /* Make sure we get a consistent snapshot */ | |
965ebf33 HS |
425 | spin_lock_bh(&slot->host->lock); |
426 | mrq = slot->mrq; | |
deec9ae3 HS |
427 | |
428 | if (mrq) { | |
429 | cmd = mrq->cmd; | |
430 | data = mrq->data; | |
431 | stop = mrq->stop; | |
432 | ||
433 | if (cmd) | |
434 | seq_printf(s, | |
435 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
436 | cmd->opcode, cmd->arg, cmd->flags, | |
437 | cmd->resp[0], cmd->resp[1], cmd->resp[2], | |
d586ebbb | 438 | cmd->resp[3], cmd->error); |
deec9ae3 HS |
439 | if (data) |
440 | seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", | |
441 | data->bytes_xfered, data->blocks, | |
442 | data->blksz, data->flags, data->error); | |
443 | if (stop) | |
444 | seq_printf(s, | |
445 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
446 | stop->opcode, stop->arg, stop->flags, | |
447 | stop->resp[0], stop->resp[1], stop->resp[2], | |
d586ebbb | 448 | stop->resp[3], stop->error); |
deec9ae3 HS |
449 | } |
450 | ||
965ebf33 | 451 | spin_unlock_bh(&slot->host->lock); |
deec9ae3 HS |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
456 | static int atmci_req_open(struct inode *inode, struct file *file) | |
457 | { | |
458 | return single_open(file, atmci_req_show, inode->i_private); | |
459 | } | |
460 | ||
461 | static const struct file_operations atmci_req_fops = { | |
462 | .owner = THIS_MODULE, | |
463 | .open = atmci_req_open, | |
464 | .read = seq_read, | |
465 | .llseek = seq_lseek, | |
466 | .release = single_release, | |
467 | }; | |
468 | ||
469 | static void atmci_show_status_reg(struct seq_file *s, | |
470 | const char *regname, u32 value) | |
471 | { | |
472 | static const char *sr_bit[] = { | |
473 | [0] = "CMDRDY", | |
474 | [1] = "RXRDY", | |
475 | [2] = "TXRDY", | |
476 | [3] = "BLKE", | |
477 | [4] = "DTIP", | |
478 | [5] = "NOTBUSY", | |
04d699c3 RE |
479 | [6] = "ENDRX", |
480 | [7] = "ENDTX", | |
deec9ae3 HS |
481 | [8] = "SDIOIRQA", |
482 | [9] = "SDIOIRQB", | |
04d699c3 RE |
483 | [12] = "SDIOWAIT", |
484 | [14] = "RXBUFF", | |
485 | [15] = "TXBUFE", | |
deec9ae3 HS |
486 | [16] = "RINDE", |
487 | [17] = "RDIRE", | |
488 | [18] = "RCRCE", | |
489 | [19] = "RENDE", | |
490 | [20] = "RTOE", | |
491 | [21] = "DCRCE", | |
492 | [22] = "DTOE", | |
04d699c3 RE |
493 | [23] = "CSTOE", |
494 | [24] = "BLKOVRE", | |
495 | [25] = "DMADONE", | |
496 | [26] = "FIFOEMPTY", | |
497 | [27] = "XFRDONE", | |
deec9ae3 HS |
498 | [30] = "OVRE", |
499 | [31] = "UNRE", | |
500 | }; | |
501 | unsigned int i; | |
502 | ||
503 | seq_printf(s, "%s:\t0x%08x", regname, value); | |
504 | for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { | |
505 | if (value & (1 << i)) { | |
506 | if (sr_bit[i]) | |
507 | seq_printf(s, " %s", sr_bit[i]); | |
508 | else | |
509 | seq_puts(s, " UNKNOWN"); | |
510 | } | |
511 | } | |
512 | seq_putc(s, '\n'); | |
513 | } | |
514 | ||
515 | static int atmci_regs_show(struct seq_file *s, void *v) | |
516 | { | |
517 | struct atmel_mci *host = s->private; | |
518 | u32 *buf; | |
b3894f26 BB |
519 | int ret = 0; |
520 | ||
deec9ae3 | 521 | |
2c96a293 | 522 | buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL); |
deec9ae3 HS |
523 | if (!buf) |
524 | return -ENOMEM; | |
525 | ||
ae552ab0 WY |
526 | pm_runtime_get_sync(&host->pdev->dev); |
527 | ||
965ebf33 HS |
528 | /* |
529 | * Grab a more or less consistent snapshot. Note that we're | |
530 | * not disabling interrupts, so IMR and SR may not be | |
531 | * consistent. | |
532 | */ | |
533 | spin_lock_bh(&host->lock); | |
2c96a293 | 534 | memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); |
965ebf33 | 535 | spin_unlock_bh(&host->lock); |
deec9ae3 | 536 | |
ae552ab0 WY |
537 | pm_runtime_mark_last_busy(&host->pdev->dev); |
538 | pm_runtime_put_autosuspend(&host->pdev->dev); | |
b3894f26 | 539 | |
8a4de07e | 540 | seq_printf(s, "MR:\t0x%08x%s%s ", |
2c96a293 LD |
541 | buf[ATMCI_MR / 4], |
542 | buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "", | |
8a4de07e NF |
543 | buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : ""); |
544 | if (host->caps.has_odd_clk_div) | |
545 | seq_printf(s, "{CLKDIV,CLKODD}=%u\n", | |
546 | ((buf[ATMCI_MR / 4] & 0xff) << 1) | |
547 | | ((buf[ATMCI_MR / 4] >> 16) & 1)); | |
548 | else | |
549 | seq_printf(s, "CLKDIV=%u\n", | |
550 | (buf[ATMCI_MR / 4] & 0xff)); | |
2c96a293 LD |
551 | seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]); |
552 | seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]); | |
553 | seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]); | |
deec9ae3 | 554 | seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", |
2c96a293 LD |
555 | buf[ATMCI_BLKR / 4], |
556 | buf[ATMCI_BLKR / 4] & 0xffff, | |
557 | (buf[ATMCI_BLKR / 4] >> 16) & 0xffff); | |
796211b7 | 558 | if (host->caps.has_cstor_reg) |
2c96a293 | 559 | seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]); |
deec9ae3 HS |
560 | |
561 | /* Don't read RSPR and RDR; it will consume the data there */ | |
562 | ||
2c96a293 LD |
563 | atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); |
564 | atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]); | |
deec9ae3 | 565 | |
ccdfe612 | 566 | if (host->caps.has_dma_conf_reg) { |
74791a2d NF |
567 | u32 val; |
568 | ||
2c96a293 | 569 | val = buf[ATMCI_DMA / 4]; |
74791a2d NF |
570 | seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", |
571 | val, val & 3, | |
572 | ((val >> 4) & 3) ? | |
573 | 1 << (((val >> 4) & 3) + 1) : 1, | |
2c96a293 | 574 | val & ATMCI_DMAEN ? " DMAEN" : ""); |
796211b7 LD |
575 | } |
576 | if (host->caps.has_cfg_reg) { | |
577 | u32 val; | |
74791a2d | 578 | |
2c96a293 | 579 | val = buf[ATMCI_CFG / 4]; |
74791a2d NF |
580 | seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", |
581 | val, | |
2c96a293 LD |
582 | val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", |
583 | val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", | |
584 | val & ATMCI_CFG_HSMODE ? " HSMODE" : "", | |
585 | val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); | |
74791a2d NF |
586 | } |
587 | ||
b17339a1 HS |
588 | kfree(buf); |
589 | ||
b3894f26 | 590 | return ret; |
deec9ae3 HS |
591 | } |
592 | ||
593 | static int atmci_regs_open(struct inode *inode, struct file *file) | |
594 | { | |
595 | return single_open(file, atmci_regs_show, inode->i_private); | |
596 | } | |
597 | ||
598 | static const struct file_operations atmci_regs_fops = { | |
599 | .owner = THIS_MODULE, | |
600 | .open = atmci_regs_open, | |
601 | .read = seq_read, | |
602 | .llseek = seq_lseek, | |
603 | .release = single_release, | |
604 | }; | |
605 | ||
965ebf33 | 606 | static void atmci_init_debugfs(struct atmel_mci_slot *slot) |
deec9ae3 | 607 | { |
965ebf33 HS |
608 | struct mmc_host *mmc = slot->mmc; |
609 | struct atmel_mci *host = slot->host; | |
610 | struct dentry *root; | |
611 | struct dentry *node; | |
deec9ae3 | 612 | |
deec9ae3 HS |
613 | root = mmc->debugfs_root; |
614 | if (!root) | |
615 | return; | |
616 | ||
617 | node = debugfs_create_file("regs", S_IRUSR, root, host, | |
618 | &atmci_regs_fops); | |
619 | if (IS_ERR(node)) | |
620 | return; | |
621 | if (!node) | |
622 | goto err; | |
623 | ||
965ebf33 | 624 | node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); |
deec9ae3 HS |
625 | if (!node) |
626 | goto err; | |
627 | ||
c06ad258 HS |
628 | node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); |
629 | if (!node) | |
630 | goto err; | |
631 | ||
deec9ae3 HS |
632 | node = debugfs_create_x32("pending_events", S_IRUSR, root, |
633 | (u32 *)&host->pending_events); | |
634 | if (!node) | |
635 | goto err; | |
636 | ||
637 | node = debugfs_create_x32("completed_events", S_IRUSR, root, | |
638 | (u32 *)&host->completed_events); | |
639 | if (!node) | |
640 | goto err; | |
641 | ||
642 | return; | |
643 | ||
644 | err: | |
965ebf33 | 645 | dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); |
deec9ae3 | 646 | } |
7d2be074 | 647 | |
e919fd20 LD |
648 | #if defined(CONFIG_OF) |
649 | static const struct of_device_id atmci_dt_ids[] = { | |
650 | { .compatible = "atmel,hsmci" }, | |
651 | { /* sentinel */ } | |
652 | }; | |
653 | ||
654 | MODULE_DEVICE_TABLE(of, atmci_dt_ids); | |
655 | ||
c3be1efd | 656 | static struct mci_platform_data* |
e919fd20 LD |
657 | atmci_of_init(struct platform_device *pdev) |
658 | { | |
659 | struct device_node *np = pdev->dev.of_node; | |
660 | struct device_node *cnp; | |
661 | struct mci_platform_data *pdata; | |
662 | u32 slot_id; | |
663 | ||
664 | if (!np) { | |
665 | dev_err(&pdev->dev, "device node not found\n"); | |
666 | return ERR_PTR(-EINVAL); | |
667 | } | |
668 | ||
669 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
670 | if (!pdata) { | |
671 | dev_err(&pdev->dev, "could not allocate memory for pdata\n"); | |
672 | return ERR_PTR(-ENOMEM); | |
673 | } | |
674 | ||
675 | for_each_child_of_node(np, cnp) { | |
676 | if (of_property_read_u32(cnp, "reg", &slot_id)) { | |
677 | dev_warn(&pdev->dev, "reg property is missing for %s\n", | |
678 | cnp->full_name); | |
679 | continue; | |
680 | } | |
681 | ||
682 | if (slot_id >= ATMCI_MAX_NR_SLOTS) { | |
683 | dev_warn(&pdev->dev, "can't have more than %d slots\n", | |
684 | ATMCI_MAX_NR_SLOTS); | |
685 | break; | |
686 | } | |
687 | ||
688 | if (of_property_read_u32(cnp, "bus-width", | |
689 | &pdata->slot[slot_id].bus_width)) | |
690 | pdata->slot[slot_id].bus_width = 1; | |
691 | ||
692 | pdata->slot[slot_id].detect_pin = | |
693 | of_get_named_gpio(cnp, "cd-gpios", 0); | |
694 | ||
695 | pdata->slot[slot_id].detect_is_active_high = | |
696 | of_property_read_bool(cnp, "cd-inverted"); | |
697 | ||
76d55564 TK |
698 | pdata->slot[slot_id].non_removable = |
699 | of_property_read_bool(cnp, "non-removable"); | |
700 | ||
e919fd20 LD |
701 | pdata->slot[slot_id].wp_pin = |
702 | of_get_named_gpio(cnp, "wp-gpios", 0); | |
703 | } | |
704 | ||
705 | return pdata; | |
706 | } | |
707 | #else /* CONFIG_OF */ | |
708 | static inline struct mci_platform_data* | |
709 | atmci_of_init(struct platform_device *dev) | |
710 | { | |
711 | return ERR_PTR(-EINVAL); | |
712 | } | |
713 | #endif | |
714 | ||
7a90dcc2 LD |
715 | static inline unsigned int atmci_get_version(struct atmel_mci *host) |
716 | { | |
717 | return atmci_readl(host, ATMCI_VERSION) & 0x00000fff; | |
718 | } | |
719 | ||
447dc0d2 | 720 | /* |
721 | * Fix sconfig's burst size according to atmel MCI. We need to convert them as: | |
722 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
723 | * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2, | |
724 | * 8 -> 3, 16 -> 4. | |
725 | * | |
726 | * This can be done by finding most significant bit set. | |
727 | */ | |
728 | static inline unsigned int atmci_convert_chksize(struct atmel_mci *host, | |
729 | unsigned int maxburst) | |
730 | { | |
731 | unsigned int version = atmci_get_version(host); | |
732 | unsigned int offset = 2; | |
733 | ||
734 | if (version >= 0x600) | |
735 | offset = 1; | |
736 | ||
737 | if (maxburst > 1) | |
738 | return fls(maxburst) - offset; | |
739 | else | |
740 | return 0; | |
741 | } | |
742 | ||
24011f34 LD |
743 | static void atmci_timeout_timer(unsigned long data) |
744 | { | |
745 | struct atmel_mci *host; | |
746 | ||
747 | host = (struct atmel_mci *)data; | |
748 | ||
749 | dev_dbg(&host->pdev->dev, "software timeout\n"); | |
750 | ||
751 | if (host->mrq->cmd->data) { | |
752 | host->mrq->cmd->data->error = -ETIMEDOUT; | |
753 | host->data = NULL; | |
c1fa3426 LD |
754 | /* |
755 | * With some SDIO modules, sometimes DMA transfer hangs. If | |
756 | * stop_transfer() is not called then the DMA request is not | |
757 | * removed, following ones are queued and never computed. | |
758 | */ | |
759 | if (host->state == STATE_DATA_XFER) | |
760 | host->stop_transfer(host); | |
24011f34 LD |
761 | } else { |
762 | host->mrq->cmd->error = -ETIMEDOUT; | |
763 | host->cmd = NULL; | |
764 | } | |
765 | host->need_reset = 1; | |
766 | host->state = STATE_END_REQUEST; | |
767 | smp_wmb(); | |
768 | tasklet_schedule(&host->tasklet); | |
769 | } | |
770 | ||
2c96a293 | 771 | static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host, |
7d2be074 HS |
772 | unsigned int ns) |
773 | { | |
66292ad9 LD |
774 | /* |
775 | * It is easier here to use us instead of ns for the timeout, | |
776 | * it prevents from overflows during calculation. | |
777 | */ | |
778 | unsigned int us = DIV_ROUND_UP(ns, 1000); | |
779 | ||
780 | /* Maximum clock frequency is host->bus_hz/2 */ | |
781 | return us * (DIV_ROUND_UP(host->bus_hz, 2000000)); | |
7d2be074 HS |
782 | } |
783 | ||
784 | static void atmci_set_timeout(struct atmel_mci *host, | |
965ebf33 | 785 | struct atmel_mci_slot *slot, struct mmc_data *data) |
7d2be074 HS |
786 | { |
787 | static unsigned dtomul_to_shift[] = { | |
788 | 0, 4, 7, 8, 10, 12, 16, 20 | |
789 | }; | |
790 | unsigned timeout; | |
791 | unsigned dtocyc; | |
792 | unsigned dtomul; | |
793 | ||
2c96a293 LD |
794 | timeout = atmci_ns_to_clocks(host, data->timeout_ns) |
795 | + data->timeout_clks; | |
7d2be074 HS |
796 | |
797 | for (dtomul = 0; dtomul < 8; dtomul++) { | |
798 | unsigned shift = dtomul_to_shift[dtomul]; | |
799 | dtocyc = (timeout + (1 << shift) - 1) >> shift; | |
800 | if (dtocyc < 15) | |
801 | break; | |
802 | } | |
803 | ||
804 | if (dtomul >= 8) { | |
805 | dtomul = 7; | |
806 | dtocyc = 15; | |
807 | } | |
808 | ||
965ebf33 | 809 | dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", |
7d2be074 | 810 | dtocyc << dtomul_to_shift[dtomul]); |
03fc9a7f | 811 | atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc))); |
7d2be074 HS |
812 | } |
813 | ||
814 | /* | |
815 | * Return mask with command flags to be enabled for this command. | |
816 | */ | |
817 | static u32 atmci_prepare_command(struct mmc_host *mmc, | |
818 | struct mmc_command *cmd) | |
819 | { | |
820 | struct mmc_data *data; | |
821 | u32 cmdr; | |
822 | ||
823 | cmd->error = -EINPROGRESS; | |
824 | ||
2c96a293 | 825 | cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); |
7d2be074 HS |
826 | |
827 | if (cmd->flags & MMC_RSP_PRESENT) { | |
828 | if (cmd->flags & MMC_RSP_136) | |
2c96a293 | 829 | cmdr |= ATMCI_CMDR_RSPTYP_136BIT; |
7d2be074 | 830 | else |
2c96a293 | 831 | cmdr |= ATMCI_CMDR_RSPTYP_48BIT; |
7d2be074 HS |
832 | } |
833 | ||
834 | /* | |
835 | * This should really be MAXLAT_5 for CMD2 and ACMD41, but | |
836 | * it's too difficult to determine whether this is an ACMD or | |
837 | * not. Better make it 64. | |
838 | */ | |
2c96a293 | 839 | cmdr |= ATMCI_CMDR_MAXLAT_64CYC; |
7d2be074 HS |
840 | |
841 | if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) | |
2c96a293 | 842 | cmdr |= ATMCI_CMDR_OPDCMD; |
7d2be074 HS |
843 | |
844 | data = cmd->data; | |
845 | if (data) { | |
2c96a293 | 846 | cmdr |= ATMCI_CMDR_START_XFER; |
2f1d7918 NF |
847 | |
848 | if (cmd->opcode == SD_IO_RW_EXTENDED) { | |
2c96a293 | 849 | cmdr |= ATMCI_CMDR_SDIO_BLOCK; |
2f1d7918 | 850 | } else { |
fd551d94 | 851 | if (data->blocks > 1) |
2c96a293 | 852 | cmdr |= ATMCI_CMDR_MULTI_BLOCK; |
2f1d7918 | 853 | else |
2c96a293 | 854 | cmdr |= ATMCI_CMDR_BLOCK; |
2f1d7918 | 855 | } |
7d2be074 HS |
856 | |
857 | if (data->flags & MMC_DATA_READ) | |
2c96a293 | 858 | cmdr |= ATMCI_CMDR_TRDIR_READ; |
7d2be074 HS |
859 | } |
860 | ||
861 | return cmdr; | |
862 | } | |
863 | ||
11d1488b | 864 | static void atmci_send_command(struct atmel_mci *host, |
965ebf33 | 865 | struct mmc_command *cmd, u32 cmd_flags) |
7d2be074 | 866 | { |
7d2be074 HS |
867 | WARN_ON(host->cmd); |
868 | host->cmd = cmd; | |
869 | ||
965ebf33 | 870 | dev_vdbg(&host->pdev->dev, |
7d2be074 HS |
871 | "start command: ARGR=0x%08x CMDR=0x%08x\n", |
872 | cmd->arg, cmd_flags); | |
873 | ||
03fc9a7f LD |
874 | atmci_writel(host, ATMCI_ARGR, cmd->arg); |
875 | atmci_writel(host, ATMCI_CMDR, cmd_flags); | |
7d2be074 HS |
876 | } |
877 | ||
2c96a293 | 878 | static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) |
7d2be074 | 879 | { |
6801c41a | 880 | dev_dbg(&host->pdev->dev, "send stop command\n"); |
11d1488b | 881 | atmci_send_command(host, data->stop, host->stop_cmdr); |
03fc9a7f | 882 | atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); |
7d2be074 HS |
883 | } |
884 | ||
796211b7 LD |
885 | /* |
886 | * Configure given PDC buffer taking care of alignement issues. | |
887 | * Update host->data_size and host->sg. | |
888 | */ | |
889 | static void atmci_pdc_set_single_buf(struct atmel_mci *host, | |
890 | enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb) | |
891 | { | |
892 | u32 pointer_reg, counter_reg; | |
7a90dcc2 | 893 | unsigned int buf_size; |
796211b7 LD |
894 | |
895 | if (dir == XFER_RECEIVE) { | |
896 | pointer_reg = ATMEL_PDC_RPR; | |
897 | counter_reg = ATMEL_PDC_RCR; | |
898 | } else { | |
899 | pointer_reg = ATMEL_PDC_TPR; | |
900 | counter_reg = ATMEL_PDC_TCR; | |
901 | } | |
902 | ||
903 | if (buf_nb == PDC_SECOND_BUF) { | |
1ebbe3d3 LD |
904 | pointer_reg += ATMEL_PDC_SCND_BUF_OFF; |
905 | counter_reg += ATMEL_PDC_SCND_BUF_OFF; | |
796211b7 LD |
906 | } |
907 | ||
7a90dcc2 LD |
908 | if (!host->caps.has_rwproof) { |
909 | buf_size = host->buf_size; | |
910 | atmci_writel(host, pointer_reg, host->buf_phys_addr); | |
911 | } else { | |
912 | buf_size = sg_dma_len(host->sg); | |
913 | atmci_writel(host, pointer_reg, sg_dma_address(host->sg)); | |
914 | } | |
915 | ||
916 | if (host->data_size <= buf_size) { | |
796211b7 LD |
917 | if (host->data_size & 0x3) { |
918 | /* If size is different from modulo 4, transfer bytes */ | |
919 | atmci_writel(host, counter_reg, host->data_size); | |
920 | atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); | |
921 | } else { | |
922 | /* Else transfer 32-bits words */ | |
923 | atmci_writel(host, counter_reg, host->data_size / 4); | |
924 | } | |
925 | host->data_size = 0; | |
926 | } else { | |
927 | /* We assume the size of a page is 32-bits aligned */ | |
341fa4c3 LD |
928 | atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4); |
929 | host->data_size -= sg_dma_len(host->sg); | |
796211b7 LD |
930 | if (host->data_size) |
931 | host->sg = sg_next(host->sg); | |
932 | } | |
933 | } | |
934 | ||
935 | /* | |
936 | * Configure PDC buffer according to the data size ie configuring one or two | |
937 | * buffers. Don't use this function if you want to configure only the second | |
938 | * buffer. In this case, use atmci_pdc_set_single_buf. | |
939 | */ | |
940 | static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir) | |
65e8b083 | 941 | { |
796211b7 LD |
942 | atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF); |
943 | if (host->data_size) | |
944 | atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF); | |
945 | } | |
946 | ||
947 | /* | |
948 | * Unmap sg lists, called when transfer is finished. | |
949 | */ | |
950 | static void atmci_pdc_cleanup(struct atmel_mci *host) | |
951 | { | |
952 | struct mmc_data *data = host->data; | |
65e8b083 | 953 | |
009a891b | 954 | if (data) |
796211b7 LD |
955 | dma_unmap_sg(&host->pdev->dev, |
956 | data->sg, data->sg_len, | |
feeef096 | 957 | mmc_get_dma_dir(data)); |
65e8b083 HS |
958 | } |
959 | ||
796211b7 LD |
960 | /* |
961 | * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after | |
962 | * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY | |
963 | * interrupt needed for both transfer directions. | |
964 | */ | |
965 | static void atmci_pdc_complete(struct atmel_mci *host) | |
65e8b083 | 966 | { |
7a90dcc2 | 967 | int transfer_size = host->data->blocks * host->data->blksz; |
24011f34 | 968 | int i; |
7a90dcc2 | 969 | |
796211b7 | 970 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
7a90dcc2 LD |
971 | |
972 | if ((!host->caps.has_rwproof) | |
24011f34 LD |
973 | && (host->data->flags & MMC_DATA_READ)) { |
974 | if (host->caps.has_bad_data_ordering) | |
975 | for (i = 0; i < transfer_size; i++) | |
976 | host->buffer[i] = swab32(host->buffer[i]); | |
7a90dcc2 LD |
977 | sg_copy_from_buffer(host->data->sg, host->data->sg_len, |
978 | host->buffer, transfer_size); | |
24011f34 | 979 | } |
7a90dcc2 | 980 | |
796211b7 | 981 | atmci_pdc_cleanup(host); |
65e8b083 | 982 | |
6e9e4062 AB |
983 | dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__); |
984 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | |
985 | tasklet_schedule(&host->tasklet); | |
65e8b083 HS |
986 | } |
987 | ||
796211b7 LD |
988 | static void atmci_dma_cleanup(struct atmel_mci *host) |
989 | { | |
990 | struct mmc_data *data = host->data; | |
991 | ||
992 | if (data) | |
993 | dma_unmap_sg(host->dma.chan->device->dev, | |
994 | data->sg, data->sg_len, | |
feeef096 | 995 | mmc_get_dma_dir(data)); |
796211b7 LD |
996 | } |
997 | ||
998 | /* | |
999 | * This function is called by the DMA driver from tasklet context. | |
1000 | */ | |
65e8b083 HS |
1001 | static void atmci_dma_complete(void *arg) |
1002 | { | |
1003 | struct atmel_mci *host = arg; | |
1004 | struct mmc_data *data = host->data; | |
1005 | ||
1006 | dev_vdbg(&host->pdev->dev, "DMA complete\n"); | |
1007 | ||
ccdfe612 | 1008 | if (host->caps.has_dma_conf_reg) |
74791a2d | 1009 | /* Disable DMA hardware handshaking on MCI */ |
03fc9a7f | 1010 | atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN); |
74791a2d | 1011 | |
65e8b083 HS |
1012 | atmci_dma_cleanup(host); |
1013 | ||
1014 | /* | |
1015 | * If the card was removed, data will be NULL. No point trying | |
1016 | * to send the stop command or waiting for NBUSY in this case. | |
1017 | */ | |
1018 | if (data) { | |
6801c41a LD |
1019 | dev_dbg(&host->pdev->dev, |
1020 | "(%s) set pending xfer complete\n", __func__); | |
65e8b083 HS |
1021 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
1022 | tasklet_schedule(&host->tasklet); | |
1023 | ||
1024 | /* | |
1025 | * Regardless of what the documentation says, we have | |
1026 | * to wait for NOTBUSY even after block read | |
1027 | * operations. | |
1028 | * | |
1029 | * When the DMA transfer is complete, the controller | |
1030 | * may still be reading the CRC from the card, i.e. | |
1031 | * the data transfer is still in progress and we | |
1032 | * haven't seen all the potential error bits yet. | |
1033 | * | |
1034 | * The interrupt handler will schedule a different | |
1035 | * tasklet to finish things up when the data transfer | |
1036 | * is completely done. | |
1037 | * | |
1038 | * We may not complete the mmc request here anyway | |
1039 | * because the mmc layer may call back and cause us to | |
1040 | * violate the "don't submit new operations from the | |
1041 | * completion callback" rule of the dma engine | |
1042 | * framework. | |
1043 | */ | |
03fc9a7f | 1044 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
65e8b083 HS |
1045 | } |
1046 | } | |
1047 | ||
796211b7 LD |
1048 | /* |
1049 | * Returns a mask of interrupt flags to be enabled after the whole | |
1050 | * request has been prepared. | |
1051 | */ | |
1052 | static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) | |
1053 | { | |
1054 | u32 iflags; | |
1055 | ||
1056 | data->error = -EINPROGRESS; | |
1057 | ||
1058 | host->sg = data->sg; | |
bdbc5d0c | 1059 | host->sg_len = data->sg_len; |
796211b7 LD |
1060 | host->data = data; |
1061 | host->data_chan = NULL; | |
1062 | ||
1063 | iflags = ATMCI_DATA_ERROR_FLAGS; | |
1064 | ||
1065 | /* | |
1066 | * Errata: MMC data write operation with less than 12 | |
1067 | * bytes is impossible. | |
1068 | * | |
1069 | * Errata: MCI Transmit Data Register (TDR) FIFO | |
1070 | * corruption when length is not multiple of 4. | |
1071 | */ | |
1072 | if (data->blocks * data->blksz < 12 | |
1073 | || (data->blocks * data->blksz) & 3) | |
1074 | host->need_reset = true; | |
1075 | ||
1076 | host->pio_offset = 0; | |
1077 | if (data->flags & MMC_DATA_READ) | |
1078 | iflags |= ATMCI_RXRDY; | |
1079 | else | |
1080 | iflags |= ATMCI_TXRDY; | |
1081 | ||
1082 | return iflags; | |
1083 | } | |
1084 | ||
1085 | /* | |
1086 | * Set interrupt flags and set block length into the MCI mode register even | |
1087 | * if this value is also accessible in the MCI block register. It seems to be | |
1088 | * necessary before the High Speed MCI version. It also map sg and configure | |
1089 | * PDC registers. | |
1090 | */ | |
1091 | static u32 | |
1092 | atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) | |
1093 | { | |
1094 | u32 iflags, tmp; | |
1095 | unsigned int sg_len; | |
24011f34 | 1096 | int i; |
796211b7 LD |
1097 | |
1098 | data->error = -EINPROGRESS; | |
1099 | ||
1100 | host->data = data; | |
1101 | host->sg = data->sg; | |
1102 | iflags = ATMCI_DATA_ERROR_FLAGS; | |
1103 | ||
1104 | /* Enable pdc mode */ | |
1105 | atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); | |
1106 | ||
feeef096 | 1107 | if (data->flags & MMC_DATA_READ) |
796211b7 | 1108 | iflags |= ATMCI_ENDRX | ATMCI_RXBUFF; |
feeef096 | 1109 | else |
f5177547 | 1110 | iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE; |
796211b7 LD |
1111 | |
1112 | /* Set BLKLEN */ | |
1113 | tmp = atmci_readl(host, ATMCI_MR); | |
1114 | tmp &= 0x0000ffff; | |
1115 | tmp |= ATMCI_BLKLEN(data->blksz); | |
1116 | atmci_writel(host, ATMCI_MR, tmp); | |
1117 | ||
1118 | /* Configure PDC */ | |
1119 | host->data_size = data->blocks * data->blksz; | |
feeef096 HK |
1120 | sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, |
1121 | mmc_get_dma_dir(data)); | |
7a90dcc2 LD |
1122 | |
1123 | if ((!host->caps.has_rwproof) | |
24011f34 | 1124 | && (host->data->flags & MMC_DATA_WRITE)) { |
7a90dcc2 LD |
1125 | sg_copy_to_buffer(host->data->sg, host->data->sg_len, |
1126 | host->buffer, host->data_size); | |
24011f34 LD |
1127 | if (host->caps.has_bad_data_ordering) |
1128 | for (i = 0; i < host->data_size; i++) | |
1129 | host->buffer[i] = swab32(host->buffer[i]); | |
1130 | } | |
7a90dcc2 | 1131 | |
796211b7 | 1132 | if (host->data_size) |
feeef096 HK |
1133 | atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ? |
1134 | XFER_RECEIVE : XFER_TRANSMIT); | |
796211b7 LD |
1135 | return iflags; |
1136 | } | |
1137 | ||
1138 | static u32 | |
74791a2d | 1139 | atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) |
65e8b083 HS |
1140 | { |
1141 | struct dma_chan *chan; | |
1142 | struct dma_async_tx_descriptor *desc; | |
1143 | struct scatterlist *sg; | |
1144 | unsigned int i; | |
05f5799c | 1145 | enum dma_transfer_direction slave_dirn; |
657a77fa | 1146 | unsigned int sglen; |
693e5e20 | 1147 | u32 maxburst; |
796211b7 LD |
1148 | u32 iflags; |
1149 | ||
1150 | data->error = -EINPROGRESS; | |
1151 | ||
1152 | WARN_ON(host->data); | |
1153 | host->sg = NULL; | |
1154 | host->data = data; | |
1155 | ||
1156 | iflags = ATMCI_DATA_ERROR_FLAGS; | |
65e8b083 HS |
1157 | |
1158 | /* | |
1159 | * We don't do DMA on "complex" transfers, i.e. with | |
1160 | * non-word-aligned buffers or lengths. Also, we don't bother | |
1161 | * with all the DMA setup overhead for short transfers. | |
1162 | */ | |
796211b7 LD |
1163 | if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) |
1164 | return atmci_prepare_data(host, data); | |
65e8b083 | 1165 | if (data->blksz & 3) |
796211b7 | 1166 | return atmci_prepare_data(host, data); |
65e8b083 HS |
1167 | |
1168 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
1169 | if (sg->offset & 3 || sg->length & 3) | |
796211b7 | 1170 | return atmci_prepare_data(host, data); |
65e8b083 HS |
1171 | } |
1172 | ||
1173 | /* If we don't have a channel, we can't do DMA */ | |
1174 | chan = host->dma.chan; | |
6f49a57a | 1175 | if (chan) |
65e8b083 | 1176 | host->data_chan = chan; |
65e8b083 HS |
1177 | |
1178 | if (!chan) | |
1179 | return -ENODEV; | |
1180 | ||
05f5799c | 1181 | if (data->flags & MMC_DATA_READ) { |
e2b35f3d | 1182 | host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM; |
447dc0d2 | 1183 | maxburst = atmci_convert_chksize(host, |
1184 | host->dma_conf.src_maxburst); | |
05f5799c | 1185 | } else { |
e2b35f3d | 1186 | host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV; |
447dc0d2 | 1187 | maxburst = atmci_convert_chksize(host, |
1188 | host->dma_conf.dst_maxburst); | |
05f5799c | 1189 | } |
65e8b083 | 1190 | |
ccdfe612 H |
1191 | if (host->caps.has_dma_conf_reg) |
1192 | atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | | |
1193 | ATMCI_DMAEN); | |
693e5e20 | 1194 | |
266ac3f2 | 1195 | sglen = dma_map_sg(chan->device->dev, data->sg, |
feeef096 | 1196 | data->sg_len, mmc_get_dma_dir(data)); |
88ce4db3 | 1197 | |
e2b35f3d | 1198 | dmaengine_slave_config(chan, &host->dma_conf); |
16052827 | 1199 | desc = dmaengine_prep_slave_sg(chan, |
05f5799c | 1200 | data->sg, sglen, slave_dirn, |
65e8b083 HS |
1201 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1202 | if (!desc) | |
657a77fa | 1203 | goto unmap_exit; |
65e8b083 HS |
1204 | |
1205 | host->dma.data_desc = desc; | |
1206 | desc->callback = atmci_dma_complete; | |
1207 | desc->callback_param = host; | |
65e8b083 | 1208 | |
796211b7 | 1209 | return iflags; |
657a77fa | 1210 | unmap_exit: |
feeef096 HK |
1211 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, |
1212 | mmc_get_dma_dir(data)); | |
657a77fa | 1213 | return -ENOMEM; |
65e8b083 HS |
1214 | } |
1215 | ||
796211b7 LD |
1216 | static void |
1217 | atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) | |
1218 | { | |
1219 | return; | |
1220 | } | |
1221 | ||
1222 | /* | |
1223 | * Start PDC according to transfer direction. | |
1224 | */ | |
1225 | static void | |
1226 | atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data) | |
1227 | { | |
1228 | if (data->flags & MMC_DATA_READ) | |
1229 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); | |
1230 | else | |
1231 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); | |
1232 | } | |
1233 | ||
1234 | static void | |
1235 | atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) | |
74791a2d NF |
1236 | { |
1237 | struct dma_chan *chan = host->data_chan; | |
1238 | struct dma_async_tx_descriptor *desc = host->dma.data_desc; | |
1239 | ||
1240 | if (chan) { | |
5328906a LW |
1241 | dmaengine_submit(desc); |
1242 | dma_async_issue_pending(chan); | |
74791a2d NF |
1243 | } |
1244 | } | |
1245 | ||
796211b7 | 1246 | static void atmci_stop_transfer(struct atmel_mci *host) |
65e8b083 | 1247 | { |
6801c41a LD |
1248 | dev_dbg(&host->pdev->dev, |
1249 | "(%s) set pending xfer complete\n", __func__); | |
65e8b083 | 1250 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
03fc9a7f | 1251 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
65e8b083 HS |
1252 | } |
1253 | ||
7d2be074 | 1254 | /* |
7122bbb0 | 1255 | * Stop data transfer because error(s) occurred. |
7d2be074 | 1256 | */ |
796211b7 | 1257 | static void atmci_stop_transfer_pdc(struct atmel_mci *host) |
7d2be074 | 1258 | { |
f5177547 | 1259 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
796211b7 | 1260 | } |
965ebf33 | 1261 | |
796211b7 LD |
1262 | static void atmci_stop_transfer_dma(struct atmel_mci *host) |
1263 | { | |
1264 | struct dma_chan *chan = host->data_chan; | |
965ebf33 | 1265 | |
796211b7 LD |
1266 | if (chan) { |
1267 | dmaengine_terminate_all(chan); | |
1268 | atmci_dma_cleanup(host); | |
1269 | } else { | |
1270 | /* Data transfer was stopped by the interrupt handler */ | |
6801c41a LD |
1271 | dev_dbg(&host->pdev->dev, |
1272 | "(%s) set pending xfer complete\n", __func__); | |
796211b7 LD |
1273 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
1274 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
65e8b083 | 1275 | } |
7d2be074 HS |
1276 | } |
1277 | ||
796211b7 LD |
1278 | /* |
1279 | * Start a request: prepare data if needed, prepare the command and activate | |
1280 | * interrupts. | |
1281 | */ | |
965ebf33 HS |
1282 | static void atmci_start_request(struct atmel_mci *host, |
1283 | struct atmel_mci_slot *slot) | |
7d2be074 | 1284 | { |
965ebf33 | 1285 | struct mmc_request *mrq; |
7d2be074 | 1286 | struct mmc_command *cmd; |
965ebf33 | 1287 | struct mmc_data *data; |
7d2be074 | 1288 | u32 iflags; |
965ebf33 | 1289 | u32 cmdflags; |
7d2be074 | 1290 | |
965ebf33 HS |
1291 | mrq = slot->mrq; |
1292 | host->cur_slot = slot; | |
7d2be074 | 1293 | host->mrq = mrq; |
965ebf33 | 1294 | |
7d2be074 HS |
1295 | host->pending_events = 0; |
1296 | host->completed_events = 0; | |
f5177547 | 1297 | host->cmd_status = 0; |
ca55f46e | 1298 | host->data_status = 0; |
7d2be074 | 1299 | |
6801c41a LD |
1300 | dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode); |
1301 | ||
24011f34 | 1302 | if (host->need_reset || host->caps.need_reset_after_xfer) { |
18ee684b LD |
1303 | iflags = atmci_readl(host, ATMCI_IMR); |
1304 | iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB); | |
03fc9a7f LD |
1305 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
1306 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); | |
1307 | atmci_writel(host, ATMCI_MR, host->mode_reg); | |
796211b7 | 1308 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1309 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
18ee684b | 1310 | atmci_writel(host, ATMCI_IER, iflags); |
965ebf33 HS |
1311 | host->need_reset = false; |
1312 | } | |
03fc9a7f | 1313 | atmci_writel(host, ATMCI_SDCR, slot->sdc_reg); |
965ebf33 | 1314 | |
03fc9a7f | 1315 | iflags = atmci_readl(host, ATMCI_IMR); |
2c96a293 | 1316 | if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) |
f5177547 | 1317 | dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", |
965ebf33 HS |
1318 | iflags); |
1319 | ||
1320 | if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { | |
1321 | /* Send init sequence (74 clock cycles) */ | |
03fc9a7f LD |
1322 | atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT); |
1323 | while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY)) | |
965ebf33 HS |
1324 | cpu_relax(); |
1325 | } | |
74791a2d | 1326 | iflags = 0; |
7d2be074 HS |
1327 | data = mrq->data; |
1328 | if (data) { | |
965ebf33 | 1329 | atmci_set_timeout(host, slot, data); |
a252e3e3 HS |
1330 | |
1331 | /* Must set block count/size before sending command */ | |
03fc9a7f | 1332 | atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks) |
2c96a293 | 1333 | | ATMCI_BLKLEN(data->blksz)); |
965ebf33 | 1334 | dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", |
2c96a293 | 1335 | ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz)); |
74791a2d | 1336 | |
796211b7 | 1337 | iflags |= host->prepare_data(host, data); |
7d2be074 HS |
1338 | } |
1339 | ||
2c96a293 | 1340 | iflags |= ATMCI_CMDRDY; |
7d2be074 | 1341 | cmd = mrq->cmd; |
965ebf33 | 1342 | cmdflags = atmci_prepare_command(slot->mmc, cmd); |
66b512ed LD |
1343 | |
1344 | /* | |
1345 | * DMA transfer should be started before sending the command to avoid | |
1346 | * unexpected errors especially for read operations in SDIO mode. | |
1347 | * Unfortunately, in PDC mode, command has to be sent before starting | |
1348 | * the transfer. | |
1349 | */ | |
1350 | if (host->submit_data != &atmci_submit_data_dma) | |
1351 | atmci_send_command(host, cmd, cmdflags); | |
7d2be074 HS |
1352 | |
1353 | if (data) | |
796211b7 | 1354 | host->submit_data(host, data); |
7d2be074 | 1355 | |
66b512ed LD |
1356 | if (host->submit_data == &atmci_submit_data_dma) |
1357 | atmci_send_command(host, cmd, cmdflags); | |
1358 | ||
7d2be074 | 1359 | if (mrq->stop) { |
965ebf33 | 1360 | host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); |
2c96a293 | 1361 | host->stop_cmdr |= ATMCI_CMDR_STOP_XFER; |
7d2be074 | 1362 | if (!(data->flags & MMC_DATA_WRITE)) |
2c96a293 | 1363 | host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ; |
fd551d94 | 1364 | host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK; |
7d2be074 HS |
1365 | } |
1366 | ||
1367 | /* | |
1368 | * We could have enabled interrupts earlier, but I suspect | |
1369 | * that would open up a nice can of interesting race | |
1370 | * conditions (e.g. command and data complete, but stop not | |
1371 | * prepared yet.) | |
1372 | */ | |
03fc9a7f | 1373 | atmci_writel(host, ATMCI_IER, iflags); |
24011f34 LD |
1374 | |
1375 | mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); | |
965ebf33 | 1376 | } |
7d2be074 | 1377 | |
965ebf33 HS |
1378 | static void atmci_queue_request(struct atmel_mci *host, |
1379 | struct atmel_mci_slot *slot, struct mmc_request *mrq) | |
1380 | { | |
1381 | dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", | |
1382 | host->state); | |
1383 | ||
1384 | spin_lock_bh(&host->lock); | |
1385 | slot->mrq = mrq; | |
1386 | if (host->state == STATE_IDLE) { | |
1387 | host->state = STATE_SENDING_CMD; | |
1388 | atmci_start_request(host, slot); | |
1389 | } else { | |
6801c41a | 1390 | dev_dbg(&host->pdev->dev, "queue request\n"); |
965ebf33 HS |
1391 | list_add_tail(&slot->queue_node, &host->queue); |
1392 | } | |
1393 | spin_unlock_bh(&host->lock); | |
1394 | } | |
7d2be074 | 1395 | |
965ebf33 HS |
1396 | static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
1397 | { | |
1398 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1399 | struct atmel_mci *host = slot->host; | |
1400 | struct mmc_data *data; | |
1401 | ||
1402 | WARN_ON(slot->mrq); | |
6801c41a | 1403 | dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode); |
965ebf33 HS |
1404 | |
1405 | /* | |
1406 | * We may "know" the card is gone even though there's still an | |
1407 | * electrical connection. If so, we really need to communicate | |
1408 | * this to the MMC core since there won't be any more | |
1409 | * interrupts as the card is completely removed. Otherwise, | |
1410 | * the MMC core might believe the card is still there even | |
1411 | * though the card was just removed very slowly. | |
1412 | */ | |
1413 | if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { | |
1414 | mrq->cmd->error = -ENOMEDIUM; | |
1415 | mmc_request_done(mmc, mrq); | |
1416 | return; | |
1417 | } | |
1418 | ||
1419 | /* We don't support multiple blocks of weird lengths. */ | |
1420 | data = mrq->data; | |
1421 | if (data && data->blocks > 1 && data->blksz & 3) { | |
1422 | mrq->cmd->error = -EINVAL; | |
1423 | mmc_request_done(mmc, mrq); | |
1424 | } | |
1425 | ||
1426 | atmci_queue_request(host, slot, mrq); | |
7d2be074 HS |
1427 | } |
1428 | ||
1429 | static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1430 | { | |
965ebf33 HS |
1431 | struct atmel_mci_slot *slot = mmc_priv(mmc); |
1432 | struct atmel_mci *host = slot->host; | |
1433 | unsigned int i; | |
ae552ab0 | 1434 | |
2c96a293 | 1435 | slot->sdc_reg &= ~ATMCI_SDCBUS_MASK; |
945533b5 HS |
1436 | switch (ios->bus_width) { |
1437 | case MMC_BUS_WIDTH_1: | |
2c96a293 | 1438 | slot->sdc_reg |= ATMCI_SDCBUS_1BIT; |
945533b5 HS |
1439 | break; |
1440 | case MMC_BUS_WIDTH_4: | |
2c96a293 | 1441 | slot->sdc_reg |= ATMCI_SDCBUS_4BIT; |
945533b5 HS |
1442 | break; |
1443 | } | |
1444 | ||
7d2be074 | 1445 | if (ios->clock) { |
965ebf33 | 1446 | unsigned int clock_min = ~0U; |
60c8f783 | 1447 | int clkdiv; |
7d2be074 | 1448 | |
965ebf33 HS |
1449 | spin_lock_bh(&host->lock); |
1450 | if (!host->mode_reg) { | |
03fc9a7f LD |
1451 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
1452 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); | |
796211b7 | 1453 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1454 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
965ebf33 | 1455 | } |
945533b5 | 1456 | |
965ebf33 HS |
1457 | /* |
1458 | * Use mirror of ios->clock to prevent race with mmc | |
1459 | * core ios update when finding the minimum. | |
1460 | */ | |
1461 | slot->clock = ios->clock; | |
2c96a293 | 1462 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
965ebf33 HS |
1463 | if (host->slot[i] && host->slot[i]->clock |
1464 | && host->slot[i]->clock < clock_min) | |
1465 | clock_min = host->slot[i]->clock; | |
1466 | } | |
1467 | ||
1468 | /* Calculate clock divider */ | |
faf8180b LD |
1469 | if (host->caps.has_odd_clk_div) { |
1470 | clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; | |
60c8f783 LD |
1471 | if (clkdiv < 0) { |
1472 | dev_warn(&mmc->class_dev, | |
1473 | "clock %u too fast; using %lu\n", | |
1474 | clock_min, host->bus_hz / 2); | |
1475 | clkdiv = 0; | |
1476 | } else if (clkdiv > 511) { | |
faf8180b LD |
1477 | dev_warn(&mmc->class_dev, |
1478 | "clock %u too slow; using %lu\n", | |
1479 | clock_min, host->bus_hz / (511 + 2)); | |
1480 | clkdiv = 511; | |
1481 | } | |
1482 | host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) | |
1483 | | ATMCI_MR_CLKODD(clkdiv & 1); | |
1484 | } else { | |
1485 | clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; | |
1486 | if (clkdiv > 255) { | |
1487 | dev_warn(&mmc->class_dev, | |
1488 | "clock %u too slow; using %lu\n", | |
1489 | clock_min, host->bus_hz / (2 * 256)); | |
1490 | clkdiv = 255; | |
1491 | } | |
1492 | host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); | |
7d2be074 HS |
1493 | } |
1494 | ||
965ebf33 HS |
1495 | /* |
1496 | * WRPROOF and RDPROOF prevent overruns/underruns by | |
1497 | * stopping the clock when the FIFO is full/empty. | |
1498 | * This state is not expected to last for long. | |
1499 | */ | |
796211b7 | 1500 | if (host->caps.has_rwproof) |
2c96a293 | 1501 | host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); |
7d2be074 | 1502 | |
796211b7 | 1503 | if (host->caps.has_cfg_reg) { |
99ddffd8 NF |
1504 | /* setup High Speed mode in relation with card capacity */ |
1505 | if (ios->timing == MMC_TIMING_SD_HS) | |
2c96a293 | 1506 | host->cfg_reg |= ATMCI_CFG_HSMODE; |
99ddffd8 | 1507 | else |
2c96a293 | 1508 | host->cfg_reg &= ~ATMCI_CFG_HSMODE; |
99ddffd8 NF |
1509 | } |
1510 | ||
1511 | if (list_empty(&host->queue)) { | |
03fc9a7f | 1512 | atmci_writel(host, ATMCI_MR, host->mode_reg); |
796211b7 | 1513 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1514 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
99ddffd8 | 1515 | } else { |
965ebf33 | 1516 | host->need_clock_update = true; |
99ddffd8 | 1517 | } |
965ebf33 HS |
1518 | |
1519 | spin_unlock_bh(&host->lock); | |
945533b5 | 1520 | } else { |
965ebf33 HS |
1521 | bool any_slot_active = false; |
1522 | ||
1523 | spin_lock_bh(&host->lock); | |
1524 | slot->clock = 0; | |
2c96a293 | 1525 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
965ebf33 HS |
1526 | if (host->slot[i] && host->slot[i]->clock) { |
1527 | any_slot_active = true; | |
1528 | break; | |
1529 | } | |
945533b5 | 1530 | } |
965ebf33 | 1531 | if (!any_slot_active) { |
03fc9a7f | 1532 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); |
965ebf33 | 1533 | if (host->mode_reg) { |
03fc9a7f | 1534 | atmci_readl(host, ATMCI_MR); |
965ebf33 HS |
1535 | } |
1536 | host->mode_reg = 0; | |
1537 | } | |
1538 | spin_unlock_bh(&host->lock); | |
7d2be074 HS |
1539 | } |
1540 | ||
1541 | switch (ios->power_mode) { | |
9e7861f5 AB |
1542 | case MMC_POWER_OFF: |
1543 | if (!IS_ERR(mmc->supply.vmmc)) | |
1544 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
1545 | break; | |
965ebf33 HS |
1546 | case MMC_POWER_UP: |
1547 | set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); | |
9e7861f5 AB |
1548 | if (!IS_ERR(mmc->supply.vmmc)) |
1549 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); | |
965ebf33 | 1550 | break; |
7d2be074 HS |
1551 | default: |
1552 | /* | |
1553 | * TODO: None of the currently available AVR32-based | |
1554 | * boards allow MMC power to be turned off. Implement | |
1555 | * power control when this can be tested properly. | |
965ebf33 HS |
1556 | * |
1557 | * We also need to hook this into the clock management | |
1558 | * somehow so that newly inserted cards aren't | |
1559 | * subjected to a fast clock before we have a chance | |
1560 | * to figure out what the maximum rate is. Currently, | |
1561 | * there's no way to avoid this, and there never will | |
1562 | * be for boards that don't support power control. | |
7d2be074 HS |
1563 | */ |
1564 | break; | |
1565 | } | |
ae552ab0 | 1566 | |
7d2be074 HS |
1567 | } |
1568 | ||
1569 | static int atmci_get_ro(struct mmc_host *mmc) | |
1570 | { | |
965ebf33 HS |
1571 | int read_only = -ENOSYS; |
1572 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
7d2be074 | 1573 | |
965ebf33 HS |
1574 | if (gpio_is_valid(slot->wp_pin)) { |
1575 | read_only = gpio_get_value(slot->wp_pin); | |
7d2be074 HS |
1576 | dev_dbg(&mmc->class_dev, "card is %s\n", |
1577 | read_only ? "read-only" : "read-write"); | |
7d2be074 HS |
1578 | } |
1579 | ||
1580 | return read_only; | |
1581 | } | |
1582 | ||
965ebf33 HS |
1583 | static int atmci_get_cd(struct mmc_host *mmc) |
1584 | { | |
1585 | int present = -ENOSYS; | |
1586 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1587 | ||
1588 | if (gpio_is_valid(slot->detect_pin)) { | |
1c1452be JL |
1589 | present = !(gpio_get_value(slot->detect_pin) ^ |
1590 | slot->detect_is_active_high); | |
965ebf33 HS |
1591 | dev_dbg(&mmc->class_dev, "card is %spresent\n", |
1592 | present ? "" : "not "); | |
1593 | } | |
1594 | ||
1595 | return present; | |
1596 | } | |
1597 | ||
88ff82ed AG |
1598 | static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1599 | { | |
1600 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1601 | struct atmel_mci *host = slot->host; | |
1602 | ||
1603 | if (enable) | |
03fc9a7f | 1604 | atmci_writel(host, ATMCI_IER, slot->sdio_irq); |
88ff82ed | 1605 | else |
03fc9a7f | 1606 | atmci_writel(host, ATMCI_IDR, slot->sdio_irq); |
88ff82ed AG |
1607 | } |
1608 | ||
965ebf33 | 1609 | static const struct mmc_host_ops atmci_ops = { |
7d2be074 HS |
1610 | .request = atmci_request, |
1611 | .set_ios = atmci_set_ios, | |
1612 | .get_ro = atmci_get_ro, | |
965ebf33 | 1613 | .get_cd = atmci_get_cd, |
88ff82ed | 1614 | .enable_sdio_irq = atmci_enable_sdio_irq, |
7d2be074 HS |
1615 | }; |
1616 | ||
965ebf33 HS |
1617 | /* Called with host->lock held */ |
1618 | static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) | |
1619 | __releases(&host->lock) | |
1620 | __acquires(&host->lock) | |
1621 | { | |
1622 | struct atmel_mci_slot *slot = NULL; | |
1623 | struct mmc_host *prev_mmc = host->cur_slot->mmc; | |
1624 | ||
1625 | WARN_ON(host->cmd || host->data); | |
1626 | ||
1627 | /* | |
1628 | * Update the MMC clock rate if necessary. This may be | |
1629 | * necessary if set_ios() is called when a different slot is | |
25985edc | 1630 | * busy transferring data. |
965ebf33 | 1631 | */ |
99ddffd8 | 1632 | if (host->need_clock_update) { |
03fc9a7f | 1633 | atmci_writel(host, ATMCI_MR, host->mode_reg); |
796211b7 | 1634 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1635 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
99ddffd8 | 1636 | } |
965ebf33 HS |
1637 | |
1638 | host->cur_slot->mrq = NULL; | |
1639 | host->mrq = NULL; | |
1640 | if (!list_empty(&host->queue)) { | |
1641 | slot = list_entry(host->queue.next, | |
1642 | struct atmel_mci_slot, queue_node); | |
1643 | list_del(&slot->queue_node); | |
1644 | dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", | |
1645 | mmc_hostname(slot->mmc)); | |
1646 | host->state = STATE_SENDING_CMD; | |
1647 | atmci_start_request(host, slot); | |
1648 | } else { | |
1649 | dev_vdbg(&host->pdev->dev, "list empty\n"); | |
1650 | host->state = STATE_IDLE; | |
1651 | } | |
1652 | ||
24011f34 LD |
1653 | del_timer(&host->timer); |
1654 | ||
965ebf33 HS |
1655 | spin_unlock(&host->lock); |
1656 | mmc_request_done(prev_mmc, mrq); | |
1657 | spin_lock(&host->lock); | |
1658 | } | |
1659 | ||
7d2be074 | 1660 | static void atmci_command_complete(struct atmel_mci *host, |
c06ad258 | 1661 | struct mmc_command *cmd) |
7d2be074 | 1662 | { |
c06ad258 HS |
1663 | u32 status = host->cmd_status; |
1664 | ||
7d2be074 | 1665 | /* Read the response from the card (up to 16 bytes) */ |
03fc9a7f LD |
1666 | cmd->resp[0] = atmci_readl(host, ATMCI_RSPR); |
1667 | cmd->resp[1] = atmci_readl(host, ATMCI_RSPR); | |
1668 | cmd->resp[2] = atmci_readl(host, ATMCI_RSPR); | |
1669 | cmd->resp[3] = atmci_readl(host, ATMCI_RSPR); | |
7d2be074 | 1670 | |
2c96a293 | 1671 | if (status & ATMCI_RTOE) |
7d2be074 | 1672 | cmd->error = -ETIMEDOUT; |
2c96a293 | 1673 | else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE)) |
7d2be074 | 1674 | cmd->error = -EILSEQ; |
2c96a293 | 1675 | else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE)) |
7d2be074 | 1676 | cmd->error = -EIO; |
24011f34 LD |
1677 | else if (host->mrq->data && (host->mrq->data->blksz & 3)) { |
1678 | if (host->caps.need_blksz_mul_4) { | |
1679 | cmd->error = -EINVAL; | |
1680 | host->need_reset = 1; | |
1681 | } | |
1682 | } else | |
7d2be074 | 1683 | cmd->error = 0; |
7d2be074 HS |
1684 | } |
1685 | ||
1686 | static void atmci_detect_change(unsigned long data) | |
1687 | { | |
965ebf33 HS |
1688 | struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; |
1689 | bool present; | |
1690 | bool present_old; | |
7d2be074 HS |
1691 | |
1692 | /* | |
965ebf33 HS |
1693 | * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before |
1694 | * freeing the interrupt. We must not re-enable the interrupt | |
1695 | * if it has been freed, and if we're shutting down, it | |
1696 | * doesn't really matter whether the card is present or not. | |
7d2be074 HS |
1697 | */ |
1698 | smp_rmb(); | |
965ebf33 | 1699 | if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) |
7d2be074 HS |
1700 | return; |
1701 | ||
965ebf33 | 1702 | enable_irq(gpio_to_irq(slot->detect_pin)); |
1c1452be JL |
1703 | present = !(gpio_get_value(slot->detect_pin) ^ |
1704 | slot->detect_is_active_high); | |
965ebf33 | 1705 | present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); |
7d2be074 | 1706 | |
965ebf33 HS |
1707 | dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", |
1708 | present, present_old); | |
7d2be074 | 1709 | |
965ebf33 HS |
1710 | if (present != present_old) { |
1711 | struct atmel_mci *host = slot->host; | |
1712 | struct mmc_request *mrq; | |
1713 | ||
1714 | dev_dbg(&slot->mmc->class_dev, "card %s\n", | |
7d2be074 | 1715 | present ? "inserted" : "removed"); |
7d2be074 | 1716 | |
965ebf33 HS |
1717 | spin_lock(&host->lock); |
1718 | ||
1719 | if (!present) | |
1720 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
1721 | else | |
1722 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
7d2be074 HS |
1723 | |
1724 | /* Clean up queue if present */ | |
965ebf33 | 1725 | mrq = slot->mrq; |
7d2be074 | 1726 | if (mrq) { |
965ebf33 HS |
1727 | if (mrq == host->mrq) { |
1728 | /* | |
1729 | * Reset controller to terminate any ongoing | |
1730 | * commands or data transfers. | |
1731 | */ | |
03fc9a7f LD |
1732 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
1733 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); | |
1734 | atmci_writel(host, ATMCI_MR, host->mode_reg); | |
796211b7 | 1735 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1736 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
965ebf33 HS |
1737 | |
1738 | host->data = NULL; | |
1739 | host->cmd = NULL; | |
1740 | ||
1741 | switch (host->state) { | |
1742 | case STATE_IDLE: | |
c06ad258 | 1743 | break; |
965ebf33 HS |
1744 | case STATE_SENDING_CMD: |
1745 | mrq->cmd->error = -ENOMEDIUM; | |
f5177547 LD |
1746 | if (mrq->data) |
1747 | host->stop_transfer(host); | |
1748 | break; | |
1749 | case STATE_DATA_XFER: | |
c06ad258 | 1750 | mrq->data->error = -ENOMEDIUM; |
796211b7 | 1751 | host->stop_transfer(host); |
c06ad258 | 1752 | break; |
f5177547 LD |
1753 | case STATE_WAITING_NOTBUSY: |
1754 | mrq->data->error = -ENOMEDIUM; | |
1755 | break; | |
965ebf33 HS |
1756 | case STATE_SENDING_STOP: |
1757 | mrq->stop->error = -ENOMEDIUM; | |
1758 | break; | |
f5177547 LD |
1759 | case STATE_END_REQUEST: |
1760 | break; | |
965ebf33 | 1761 | } |
7d2be074 | 1762 | |
965ebf33 HS |
1763 | atmci_request_end(host, mrq); |
1764 | } else { | |
1765 | list_del(&slot->queue_node); | |
1766 | mrq->cmd->error = -ENOMEDIUM; | |
1767 | if (mrq->data) | |
1768 | mrq->data->error = -ENOMEDIUM; | |
1769 | if (mrq->stop) | |
1770 | mrq->stop->error = -ENOMEDIUM; | |
1771 | ||
1772 | spin_unlock(&host->lock); | |
1773 | mmc_request_done(slot->mmc, mrq); | |
1774 | spin_lock(&host->lock); | |
1775 | } | |
7d2be074 | 1776 | } |
965ebf33 | 1777 | spin_unlock(&host->lock); |
7d2be074 | 1778 | |
965ebf33 | 1779 | mmc_detect_change(slot->mmc, 0); |
7d2be074 HS |
1780 | } |
1781 | } | |
1782 | ||
1783 | static void atmci_tasklet_func(unsigned long priv) | |
1784 | { | |
965ebf33 | 1785 | struct atmel_mci *host = (struct atmel_mci *)priv; |
7d2be074 HS |
1786 | struct mmc_request *mrq = host->mrq; |
1787 | struct mmc_data *data = host->data; | |
c06ad258 HS |
1788 | enum atmel_mci_state state = host->state; |
1789 | enum atmel_mci_state prev_state; | |
1790 | u32 status; | |
1791 | ||
965ebf33 HS |
1792 | spin_lock(&host->lock); |
1793 | ||
c06ad258 | 1794 | state = host->state; |
7d2be074 | 1795 | |
965ebf33 | 1796 | dev_vdbg(&host->pdev->dev, |
c06ad258 HS |
1797 | "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", |
1798 | state, host->pending_events, host->completed_events, | |
03fc9a7f | 1799 | atmci_readl(host, ATMCI_IMR)); |
7d2be074 | 1800 | |
c06ad258 HS |
1801 | do { |
1802 | prev_state = state; | |
6801c41a | 1803 | dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state); |
7d2be074 | 1804 | |
c06ad258 | 1805 | switch (state) { |
965ebf33 HS |
1806 | case STATE_IDLE: |
1807 | break; | |
1808 | ||
c06ad258 | 1809 | case STATE_SENDING_CMD: |
f5177547 LD |
1810 | /* |
1811 | * Command has been sent, we are waiting for command | |
1812 | * ready. Then we have three next states possible: | |
1813 | * END_REQUEST by default, WAITING_NOTBUSY if it's a | |
1814 | * command needing it or DATA_XFER if there is data. | |
1815 | */ | |
6801c41a | 1816 | dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); |
c06ad258 | 1817 | if (!atmci_test_and_clear_pending(host, |
f5177547 | 1818 | EVENT_CMD_RDY)) |
c06ad258 | 1819 | break; |
7d2be074 | 1820 | |
6801c41a | 1821 | dev_dbg(&host->pdev->dev, "set completed cmd ready\n"); |
c06ad258 | 1822 | host->cmd = NULL; |
f5177547 | 1823 | atmci_set_completed(host, EVENT_CMD_RDY); |
c06ad258 | 1824 | atmci_command_complete(host, mrq->cmd); |
f5177547 | 1825 | if (mrq->data) { |
6801c41a LD |
1826 | dev_dbg(&host->pdev->dev, |
1827 | "command with data transfer"); | |
f5177547 LD |
1828 | /* |
1829 | * If there is a command error don't start | |
1830 | * data transfer. | |
1831 | */ | |
1832 | if (mrq->cmd->error) { | |
1833 | host->stop_transfer(host); | |
1834 | host->data = NULL; | |
1835 | atmci_writel(host, ATMCI_IDR, | |
1836 | ATMCI_TXRDY | ATMCI_RXRDY | |
1837 | | ATMCI_DATA_ERROR_FLAGS); | |
1838 | state = STATE_END_REQUEST; | |
1839 | } else | |
1840 | state = STATE_DATA_XFER; | |
1841 | } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) { | |
6801c41a LD |
1842 | dev_dbg(&host->pdev->dev, |
1843 | "command response need waiting notbusy"); | |
f5177547 LD |
1844 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
1845 | state = STATE_WAITING_NOTBUSY; | |
1846 | } else | |
1847 | state = STATE_END_REQUEST; | |
7d2be074 | 1848 | |
f5177547 | 1849 | break; |
7d2be074 | 1850 | |
f5177547 | 1851 | case STATE_DATA_XFER: |
c06ad258 HS |
1852 | if (atmci_test_and_clear_pending(host, |
1853 | EVENT_DATA_ERROR)) { | |
6801c41a | 1854 | dev_dbg(&host->pdev->dev, "set completed data error\n"); |
f5177547 LD |
1855 | atmci_set_completed(host, EVENT_DATA_ERROR); |
1856 | state = STATE_END_REQUEST; | |
c06ad258 HS |
1857 | break; |
1858 | } | |
7d2be074 | 1859 | |
f5177547 LD |
1860 | /* |
1861 | * A data transfer is in progress. The event expected | |
1862 | * to move to the next state depends of data transfer | |
1863 | * type (PDC or DMA). Once transfer done we can move | |
1864 | * to the next step which is WAITING_NOTBUSY in write | |
1865 | * case and directly SENDING_STOP in read case. | |
1866 | */ | |
6801c41a | 1867 | dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n"); |
c06ad258 HS |
1868 | if (!atmci_test_and_clear_pending(host, |
1869 | EVENT_XFER_COMPLETE)) | |
1870 | break; | |
7d2be074 | 1871 | |
6801c41a LD |
1872 | dev_dbg(&host->pdev->dev, |
1873 | "(%s) set completed xfer complete\n", | |
1874 | __func__); | |
c06ad258 | 1875 | atmci_set_completed(host, EVENT_XFER_COMPLETE); |
7d2be074 | 1876 | |
077d4073 LD |
1877 | if (host->caps.need_notbusy_for_read_ops || |
1878 | (host->data->flags & MMC_DATA_WRITE)) { | |
f5177547 LD |
1879 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
1880 | state = STATE_WAITING_NOTBUSY; | |
1881 | } else if (host->mrq->stop) { | |
1882 | atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); | |
1883 | atmci_send_stop_cmd(host, data); | |
1884 | state = STATE_SENDING_STOP; | |
c06ad258 | 1885 | } else { |
f5177547 | 1886 | host->data = NULL; |
c06ad258 HS |
1887 | data->bytes_xfered = data->blocks * data->blksz; |
1888 | data->error = 0; | |
f5177547 | 1889 | state = STATE_END_REQUEST; |
c06ad258 | 1890 | } |
f5177547 | 1891 | break; |
c06ad258 | 1892 | |
f5177547 LD |
1893 | case STATE_WAITING_NOTBUSY: |
1894 | /* | |
1895 | * We can be in the state for two reasons: a command | |
1896 | * requiring waiting not busy signal (stop command | |
1897 | * included) or a write operation. In the latest case, | |
1898 | * we need to send a stop command. | |
1899 | */ | |
6801c41a | 1900 | dev_dbg(&host->pdev->dev, "FSM: not busy?\n"); |
f5177547 LD |
1901 | if (!atmci_test_and_clear_pending(host, |
1902 | EVENT_NOTBUSY)) | |
1903 | break; | |
7d2be074 | 1904 | |
6801c41a | 1905 | dev_dbg(&host->pdev->dev, "set completed not busy\n"); |
f5177547 LD |
1906 | atmci_set_completed(host, EVENT_NOTBUSY); |
1907 | ||
1908 | if (host->data) { | |
1909 | /* | |
1910 | * For some commands such as CMD53, even if | |
1911 | * there is data transfer, there is no stop | |
1912 | * command to send. | |
1913 | */ | |
1914 | if (host->mrq->stop) { | |
1915 | atmci_writel(host, ATMCI_IER, | |
1916 | ATMCI_CMDRDY); | |
1917 | atmci_send_stop_cmd(host, data); | |
1918 | state = STATE_SENDING_STOP; | |
1919 | } else { | |
1920 | host->data = NULL; | |
1921 | data->bytes_xfered = data->blocks | |
1922 | * data->blksz; | |
1923 | data->error = 0; | |
1924 | state = STATE_END_REQUEST; | |
1925 | } | |
1926 | } else | |
1927 | state = STATE_END_REQUEST; | |
1928 | break; | |
c06ad258 HS |
1929 | |
1930 | case STATE_SENDING_STOP: | |
f5177547 LD |
1931 | /* |
1932 | * In this state, it is important to set host->data to | |
1933 | * NULL (which is tested in the waiting notbusy state) | |
1934 | * in order to go to the end request state instead of | |
1935 | * sending stop again. | |
1936 | */ | |
6801c41a | 1937 | dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); |
c06ad258 | 1938 | if (!atmci_test_and_clear_pending(host, |
f5177547 | 1939 | EVENT_CMD_RDY)) |
c06ad258 HS |
1940 | break; |
1941 | ||
6801c41a | 1942 | dev_dbg(&host->pdev->dev, "FSM: cmd ready\n"); |
c06ad258 | 1943 | host->cmd = NULL; |
f5177547 LD |
1944 | data->bytes_xfered = data->blocks * data->blksz; |
1945 | data->error = 0; | |
c06ad258 | 1946 | atmci_command_complete(host, mrq->stop); |
f5177547 LD |
1947 | if (mrq->stop->error) { |
1948 | host->stop_transfer(host); | |
1949 | atmci_writel(host, ATMCI_IDR, | |
1950 | ATMCI_TXRDY | ATMCI_RXRDY | |
1951 | | ATMCI_DATA_ERROR_FLAGS); | |
1952 | state = STATE_END_REQUEST; | |
1953 | } else { | |
1954 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
1955 | state = STATE_WAITING_NOTBUSY; | |
1956 | } | |
41b4e9a1 | 1957 | host->data = NULL; |
f5177547 | 1958 | break; |
c06ad258 | 1959 | |
f5177547 LD |
1960 | case STATE_END_REQUEST: |
1961 | atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY | |
1962 | | ATMCI_DATA_ERROR_FLAGS); | |
1963 | status = host->data_status; | |
1964 | if (unlikely(status)) { | |
1965 | host->stop_transfer(host); | |
1966 | host->data = NULL; | |
fbd986cd RG |
1967 | if (data) { |
1968 | if (status & ATMCI_DTOE) { | |
1969 | data->error = -ETIMEDOUT; | |
1970 | } else if (status & ATMCI_DCRCE) { | |
1971 | data->error = -EILSEQ; | |
1972 | } else { | |
1973 | data->error = -EIO; | |
1974 | } | |
f5177547 LD |
1975 | } |
1976 | } | |
c06ad258 | 1977 | |
f5177547 LD |
1978 | atmci_request_end(host, host->mrq); |
1979 | state = STATE_IDLE; | |
c06ad258 HS |
1980 | break; |
1981 | } | |
1982 | } while (state != prev_state); | |
1983 | ||
1984 | host->state = state; | |
965ebf33 | 1985 | |
965ebf33 | 1986 | spin_unlock(&host->lock); |
7d2be074 HS |
1987 | } |
1988 | ||
1989 | static void atmci_read_data_pio(struct atmel_mci *host) | |
1990 | { | |
1991 | struct scatterlist *sg = host->sg; | |
1992 | void *buf = sg_virt(sg); | |
1993 | unsigned int offset = host->pio_offset; | |
1994 | struct mmc_data *data = host->data; | |
1995 | u32 value; | |
1996 | u32 status; | |
1997 | unsigned int nbytes = 0; | |
1998 | ||
1999 | do { | |
03fc9a7f | 2000 | value = atmci_readl(host, ATMCI_RDR); |
7d2be074 HS |
2001 | if (likely(offset + 4 <= sg->length)) { |
2002 | put_unaligned(value, (u32 *)(buf + offset)); | |
2003 | ||
2004 | offset += 4; | |
2005 | nbytes += 4; | |
2006 | ||
2007 | if (offset == sg->length) { | |
5e7184ae | 2008 | flush_dcache_page(sg_page(sg)); |
7d2be074 | 2009 | host->sg = sg = sg_next(sg); |
bdbc5d0c TB |
2010 | host->sg_len--; |
2011 | if (!sg || !host->sg_len) | |
7d2be074 HS |
2012 | goto done; |
2013 | ||
2014 | offset = 0; | |
2015 | buf = sg_virt(sg); | |
2016 | } | |
2017 | } else { | |
2018 | unsigned int remaining = sg->length - offset; | |
2019 | memcpy(buf + offset, &value, remaining); | |
2020 | nbytes += remaining; | |
2021 | ||
2022 | flush_dcache_page(sg_page(sg)); | |
2023 | host->sg = sg = sg_next(sg); | |
bdbc5d0c TB |
2024 | host->sg_len--; |
2025 | if (!sg || !host->sg_len) | |
7d2be074 HS |
2026 | goto done; |
2027 | ||
2028 | offset = 4 - remaining; | |
2029 | buf = sg_virt(sg); | |
2030 | memcpy(buf, (u8 *)&value + remaining, offset); | |
2031 | nbytes += offset; | |
2032 | } | |
2033 | ||
03fc9a7f | 2034 | status = atmci_readl(host, ATMCI_SR); |
7d2be074 | 2035 | if (status & ATMCI_DATA_ERROR_FLAGS) { |
03fc9a7f | 2036 | atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY |
7d2be074 HS |
2037 | | ATMCI_DATA_ERROR_FLAGS)); |
2038 | host->data_status = status; | |
965ebf33 | 2039 | data->bytes_xfered += nbytes; |
965ebf33 | 2040 | return; |
7d2be074 | 2041 | } |
2c96a293 | 2042 | } while (status & ATMCI_RXRDY); |
7d2be074 HS |
2043 | |
2044 | host->pio_offset = offset; | |
2045 | data->bytes_xfered += nbytes; | |
2046 | ||
2047 | return; | |
2048 | ||
2049 | done: | |
03fc9a7f LD |
2050 | atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY); |
2051 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
7d2be074 | 2052 | data->bytes_xfered += nbytes; |
965ebf33 | 2053 | smp_wmb(); |
c06ad258 | 2054 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
2055 | } |
2056 | ||
2057 | static void atmci_write_data_pio(struct atmel_mci *host) | |
2058 | { | |
2059 | struct scatterlist *sg = host->sg; | |
2060 | void *buf = sg_virt(sg); | |
2061 | unsigned int offset = host->pio_offset; | |
2062 | struct mmc_data *data = host->data; | |
2063 | u32 value; | |
2064 | u32 status; | |
2065 | unsigned int nbytes = 0; | |
2066 | ||
2067 | do { | |
2068 | if (likely(offset + 4 <= sg->length)) { | |
2069 | value = get_unaligned((u32 *)(buf + offset)); | |
03fc9a7f | 2070 | atmci_writel(host, ATMCI_TDR, value); |
7d2be074 HS |
2071 | |
2072 | offset += 4; | |
2073 | nbytes += 4; | |
2074 | if (offset == sg->length) { | |
2075 | host->sg = sg = sg_next(sg); | |
bdbc5d0c TB |
2076 | host->sg_len--; |
2077 | if (!sg || !host->sg_len) | |
7d2be074 HS |
2078 | goto done; |
2079 | ||
2080 | offset = 0; | |
2081 | buf = sg_virt(sg); | |
2082 | } | |
2083 | } else { | |
2084 | unsigned int remaining = sg->length - offset; | |
2085 | ||
2086 | value = 0; | |
2087 | memcpy(&value, buf + offset, remaining); | |
2088 | nbytes += remaining; | |
2089 | ||
2090 | host->sg = sg = sg_next(sg); | |
bdbc5d0c TB |
2091 | host->sg_len--; |
2092 | if (!sg || !host->sg_len) { | |
03fc9a7f | 2093 | atmci_writel(host, ATMCI_TDR, value); |
7d2be074 HS |
2094 | goto done; |
2095 | } | |
2096 | ||
2097 | offset = 4 - remaining; | |
2098 | buf = sg_virt(sg); | |
2099 | memcpy((u8 *)&value + remaining, buf, offset); | |
03fc9a7f | 2100 | atmci_writel(host, ATMCI_TDR, value); |
7d2be074 HS |
2101 | nbytes += offset; |
2102 | } | |
2103 | ||
03fc9a7f | 2104 | status = atmci_readl(host, ATMCI_SR); |
7d2be074 | 2105 | if (status & ATMCI_DATA_ERROR_FLAGS) { |
03fc9a7f | 2106 | atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY |
7d2be074 HS |
2107 | | ATMCI_DATA_ERROR_FLAGS)); |
2108 | host->data_status = status; | |
965ebf33 | 2109 | data->bytes_xfered += nbytes; |
965ebf33 | 2110 | return; |
7d2be074 | 2111 | } |
2c96a293 | 2112 | } while (status & ATMCI_TXRDY); |
7d2be074 HS |
2113 | |
2114 | host->pio_offset = offset; | |
2115 | data->bytes_xfered += nbytes; | |
2116 | ||
2117 | return; | |
2118 | ||
2119 | done: | |
03fc9a7f LD |
2120 | atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY); |
2121 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
7d2be074 | 2122 | data->bytes_xfered += nbytes; |
965ebf33 | 2123 | smp_wmb(); |
c06ad258 | 2124 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
2125 | } |
2126 | ||
88ff82ed AG |
2127 | static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) |
2128 | { | |
2129 | int i; | |
2130 | ||
2c96a293 | 2131 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
88ff82ed AG |
2132 | struct atmel_mci_slot *slot = host->slot[i]; |
2133 | if (slot && (status & slot->sdio_irq)) { | |
2134 | mmc_signal_sdio_irq(slot->mmc); | |
2135 | } | |
2136 | } | |
2137 | } | |
2138 | ||
2139 | ||
7d2be074 HS |
2140 | static irqreturn_t atmci_interrupt(int irq, void *dev_id) |
2141 | { | |
965ebf33 | 2142 | struct atmel_mci *host = dev_id; |
7d2be074 HS |
2143 | u32 status, mask, pending; |
2144 | unsigned int pass_count = 0; | |
2145 | ||
7d2be074 | 2146 | do { |
03fc9a7f LD |
2147 | status = atmci_readl(host, ATMCI_SR); |
2148 | mask = atmci_readl(host, ATMCI_IMR); | |
7d2be074 HS |
2149 | pending = status & mask; |
2150 | if (!pending) | |
2151 | break; | |
2152 | ||
2153 | if (pending & ATMCI_DATA_ERROR_FLAGS) { | |
6801c41a | 2154 | dev_dbg(&host->pdev->dev, "IRQ: data error\n"); |
03fc9a7f | 2155 | atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS |
f5177547 LD |
2156 | | ATMCI_RXRDY | ATMCI_TXRDY |
2157 | | ATMCI_ENDRX | ATMCI_ENDTX | |
2158 | | ATMCI_RXBUFF | ATMCI_TXBUFE); | |
965ebf33 | 2159 | |
7d2be074 | 2160 | host->data_status = status; |
6801c41a | 2161 | dev_dbg(&host->pdev->dev, "set pending data error\n"); |
965ebf33 | 2162 | smp_wmb(); |
7d2be074 HS |
2163 | atmci_set_pending(host, EVENT_DATA_ERROR); |
2164 | tasklet_schedule(&host->tasklet); | |
2165 | } | |
796211b7 | 2166 | |
796211b7 | 2167 | if (pending & ATMCI_TXBUFE) { |
6801c41a | 2168 | dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n"); |
796211b7 | 2169 | atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); |
7e8ba228 | 2170 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); |
796211b7 LD |
2171 | /* |
2172 | * We can receive this interruption before having configured | |
2173 | * the second pdc buffer, so we need to reconfigure first and | |
2174 | * second buffers again | |
2175 | */ | |
2176 | if (host->data_size) { | |
2177 | atmci_pdc_set_both_buf(host, XFER_TRANSMIT); | |
7e8ba228 | 2178 | atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); |
796211b7 LD |
2179 | atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE); |
2180 | } else { | |
2181 | atmci_pdc_complete(host); | |
2182 | } | |
7e8ba228 | 2183 | } else if (pending & ATMCI_ENDTX) { |
6801c41a | 2184 | dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n"); |
7e8ba228 | 2185 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); |
796211b7 LD |
2186 | |
2187 | if (host->data_size) { | |
2188 | atmci_pdc_set_single_buf(host, | |
7e8ba228 LD |
2189 | XFER_TRANSMIT, PDC_SECOND_BUF); |
2190 | atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); | |
796211b7 LD |
2191 | } |
2192 | } | |
2193 | ||
2194 | if (pending & ATMCI_RXBUFF) { | |
6801c41a | 2195 | dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n"); |
796211b7 | 2196 | atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); |
7e8ba228 | 2197 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); |
796211b7 LD |
2198 | /* |
2199 | * We can receive this interruption before having configured | |
2200 | * the second pdc buffer, so we need to reconfigure first and | |
2201 | * second buffers again | |
2202 | */ | |
2203 | if (host->data_size) { | |
2204 | atmci_pdc_set_both_buf(host, XFER_RECEIVE); | |
7e8ba228 | 2205 | atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); |
796211b7 LD |
2206 | atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF); |
2207 | } else { | |
2208 | atmci_pdc_complete(host); | |
2209 | } | |
7e8ba228 | 2210 | } else if (pending & ATMCI_ENDRX) { |
6801c41a | 2211 | dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n"); |
7e8ba228 LD |
2212 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); |
2213 | ||
2214 | if (host->data_size) { | |
2215 | atmci_pdc_set_single_buf(host, | |
2216 | XFER_RECEIVE, PDC_SECOND_BUF); | |
2217 | atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); | |
2218 | } | |
796211b7 LD |
2219 | } |
2220 | ||
f5177547 LD |
2221 | /* |
2222 | * First mci IPs, so mainly the ones having pdc, have some | |
2223 | * issues with the notbusy signal. You can't get it after | |
2224 | * data transmission if you have not sent a stop command. | |
2225 | * The appropriate workaround is to use the BLKE signal. | |
2226 | */ | |
2227 | if (pending & ATMCI_BLKE) { | |
6801c41a | 2228 | dev_dbg(&host->pdev->dev, "IRQ: blke\n"); |
f5177547 LD |
2229 | atmci_writel(host, ATMCI_IDR, ATMCI_BLKE); |
2230 | smp_wmb(); | |
6801c41a | 2231 | dev_dbg(&host->pdev->dev, "set pending notbusy\n"); |
f5177547 LD |
2232 | atmci_set_pending(host, EVENT_NOTBUSY); |
2233 | tasklet_schedule(&host->tasklet); | |
2234 | } | |
7e8ba228 | 2235 | |
2c96a293 | 2236 | if (pending & ATMCI_NOTBUSY) { |
6801c41a | 2237 | dev_dbg(&host->pdev->dev, "IRQ: not_busy\n"); |
f5177547 | 2238 | atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY); |
965ebf33 | 2239 | smp_wmb(); |
6801c41a | 2240 | dev_dbg(&host->pdev->dev, "set pending notbusy\n"); |
f5177547 | 2241 | atmci_set_pending(host, EVENT_NOTBUSY); |
7d2be074 HS |
2242 | tasklet_schedule(&host->tasklet); |
2243 | } | |
f5177547 | 2244 | |
2c96a293 | 2245 | if (pending & ATMCI_RXRDY) |
7d2be074 | 2246 | atmci_read_data_pio(host); |
2c96a293 | 2247 | if (pending & ATMCI_TXRDY) |
7d2be074 HS |
2248 | atmci_write_data_pio(host); |
2249 | ||
f5177547 | 2250 | if (pending & ATMCI_CMDRDY) { |
6801c41a | 2251 | dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n"); |
f5177547 LD |
2252 | atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); |
2253 | host->cmd_status = status; | |
2254 | smp_wmb(); | |
6801c41a | 2255 | dev_dbg(&host->pdev->dev, "set pending cmd rdy\n"); |
f5177547 LD |
2256 | atmci_set_pending(host, EVENT_CMD_RDY); |
2257 | tasklet_schedule(&host->tasklet); | |
2258 | } | |
88ff82ed | 2259 | |
2c96a293 | 2260 | if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) |
88ff82ed AG |
2261 | atmci_sdio_interrupt(host, status); |
2262 | ||
7d2be074 HS |
2263 | } while (pass_count++ < 5); |
2264 | ||
7d2be074 HS |
2265 | return pass_count ? IRQ_HANDLED : IRQ_NONE; |
2266 | } | |
2267 | ||
2268 | static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) | |
2269 | { | |
965ebf33 | 2270 | struct atmel_mci_slot *slot = dev_id; |
7d2be074 HS |
2271 | |
2272 | /* | |
2273 | * Disable interrupts until the pin has stabilized and check | |
2274 | * the state then. Use mod_timer() since we may be in the | |
2275 | * middle of the timer routine when this interrupt triggers. | |
2276 | */ | |
2277 | disable_irq_nosync(irq); | |
965ebf33 | 2278 | mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); |
7d2be074 HS |
2279 | |
2280 | return IRQ_HANDLED; | |
2281 | } | |
2282 | ||
ab050b92 | 2283 | static int atmci_init_slot(struct atmel_mci *host, |
965ebf33 | 2284 | struct mci_slot_pdata *slot_data, unsigned int id, |
88ff82ed | 2285 | u32 sdc_reg, u32 sdio_irq) |
965ebf33 HS |
2286 | { |
2287 | struct mmc_host *mmc; | |
2288 | struct atmel_mci_slot *slot; | |
2289 | ||
2290 | mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); | |
2291 | if (!mmc) | |
2292 | return -ENOMEM; | |
2293 | ||
2294 | slot = mmc_priv(mmc); | |
2295 | slot->mmc = mmc; | |
2296 | slot->host = host; | |
2297 | slot->detect_pin = slot_data->detect_pin; | |
2298 | slot->wp_pin = slot_data->wp_pin; | |
1c1452be | 2299 | slot->detect_is_active_high = slot_data->detect_is_active_high; |
965ebf33 | 2300 | slot->sdc_reg = sdc_reg; |
88ff82ed | 2301 | slot->sdio_irq = sdio_irq; |
965ebf33 | 2302 | |
e919fd20 LD |
2303 | dev_dbg(&mmc->class_dev, |
2304 | "slot[%u]: bus_width=%u, detect_pin=%d, " | |
2305 | "detect_is_active_high=%s, wp_pin=%d\n", | |
2306 | id, slot_data->bus_width, slot_data->detect_pin, | |
2307 | slot_data->detect_is_active_high ? "true" : "false", | |
2308 | slot_data->wp_pin); | |
2309 | ||
965ebf33 HS |
2310 | mmc->ops = &atmci_ops; |
2311 | mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); | |
2312 | mmc->f_max = host->bus_hz / 2; | |
2313 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
88ff82ed AG |
2314 | if (sdio_irq) |
2315 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
796211b7 | 2316 | if (host->caps.has_highspeed) |
99ddffd8 | 2317 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
7a90dcc2 LD |
2318 | /* |
2319 | * Without the read/write proof capability, it is strongly suggested to | |
2320 | * use only one bit for data to prevent fifo underruns and overruns | |
2321 | * which will corrupt data. | |
2322 | */ | |
2323 | if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) | |
965ebf33 HS |
2324 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
2325 | ||
7a90dcc2 LD |
2326 | if (atmci_get_version(host) < 0x200) { |
2327 | mmc->max_segs = 256; | |
2328 | mmc->max_blk_size = 4095; | |
2329 | mmc->max_blk_count = 256; | |
2330 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
2331 | mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs; | |
2332 | } else { | |
2333 | mmc->max_segs = 64; | |
2334 | mmc->max_req_size = 32768 * 512; | |
2335 | mmc->max_blk_size = 32768; | |
2336 | mmc->max_blk_count = 512; | |
2337 | } | |
965ebf33 HS |
2338 | |
2339 | /* Assume card is present initially */ | |
2340 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
2341 | if (gpio_is_valid(slot->detect_pin)) { | |
7bca646e PG |
2342 | if (devm_gpio_request(&host->pdev->dev, slot->detect_pin, |
2343 | "mmc_detect")) { | |
965ebf33 HS |
2344 | dev_dbg(&mmc->class_dev, "no detect pin available\n"); |
2345 | slot->detect_pin = -EBUSY; | |
1c1452be JL |
2346 | } else if (gpio_get_value(slot->detect_pin) ^ |
2347 | slot->detect_is_active_high) { | |
965ebf33 HS |
2348 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); |
2349 | } | |
2350 | } | |
2351 | ||
76d55564 TK |
2352 | if (!gpio_is_valid(slot->detect_pin)) { |
2353 | if (slot_data->non_removable) | |
2354 | mmc->caps |= MMC_CAP_NONREMOVABLE; | |
2355 | else | |
2356 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
2357 | } | |
965ebf33 HS |
2358 | |
2359 | if (gpio_is_valid(slot->wp_pin)) { | |
7bca646e PG |
2360 | if (devm_gpio_request(&host->pdev->dev, slot->wp_pin, |
2361 | "mmc_wp")) { | |
965ebf33 HS |
2362 | dev_dbg(&mmc->class_dev, "no WP pin available\n"); |
2363 | slot->wp_pin = -EBUSY; | |
2364 | } | |
2365 | } | |
2366 | ||
2367 | host->slot[id] = slot; | |
9e7861f5 | 2368 | mmc_regulator_get_supply(mmc); |
965ebf33 HS |
2369 | mmc_add_host(mmc); |
2370 | ||
2371 | if (gpio_is_valid(slot->detect_pin)) { | |
2372 | int ret; | |
2373 | ||
2374 | setup_timer(&slot->detect_timer, atmci_detect_change, | |
2375 | (unsigned long)slot); | |
2376 | ||
2377 | ret = request_irq(gpio_to_irq(slot->detect_pin), | |
2378 | atmci_detect_interrupt, | |
2379 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | |
2380 | "mmc-detect", slot); | |
2381 | if (ret) { | |
2382 | dev_dbg(&mmc->class_dev, | |
2383 | "could not request IRQ %d for detect pin\n", | |
2384 | gpio_to_irq(slot->detect_pin)); | |
965ebf33 HS |
2385 | slot->detect_pin = -EBUSY; |
2386 | } | |
2387 | } | |
2388 | ||
2389 | atmci_init_debugfs(slot); | |
2390 | ||
2391 | return 0; | |
2392 | } | |
2393 | ||
5fef365b | 2394 | static void atmci_cleanup_slot(struct atmel_mci_slot *slot, |
965ebf33 HS |
2395 | unsigned int id) |
2396 | { | |
2397 | /* Debugfs stuff is cleaned up by mmc core */ | |
2398 | ||
2399 | set_bit(ATMCI_SHUTDOWN, &slot->flags); | |
2400 | smp_wmb(); | |
2401 | ||
2402 | mmc_remove_host(slot->mmc); | |
2403 | ||
2404 | if (gpio_is_valid(slot->detect_pin)) { | |
2405 | int pin = slot->detect_pin; | |
2406 | ||
2407 | free_irq(gpio_to_irq(pin), slot); | |
2408 | del_timer_sync(&slot->detect_timer); | |
965ebf33 | 2409 | } |
965ebf33 HS |
2410 | |
2411 | slot->host->slot[id] = NULL; | |
2412 | mmc_free_host(slot->mmc); | |
2413 | } | |
2414 | ||
467e081d | 2415 | static int atmci_configure_dma(struct atmel_mci *host) |
2635d1ba | 2416 | { |
467e081d | 2417 | host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev, |
2418 | "rxtx"); | |
74843787 MR |
2419 | |
2420 | if (PTR_ERR(host->dma.chan) == -ENODEV) { | |
2421 | struct mci_platform_data *pdata = host->pdev->dev.platform_data; | |
2422 | dma_cap_mask_t mask; | |
2423 | ||
93c77d29 | 2424 | if (!pdata || !pdata->dma_filter) |
74843787 MR |
2425 | return -ENODEV; |
2426 | ||
2427 | dma_cap_zero(mask); | |
2428 | dma_cap_set(DMA_SLAVE, mask); | |
2429 | ||
2430 | host->dma.chan = dma_request_channel(mask, pdata->dma_filter, | |
2431 | pdata->dma_slave); | |
2432 | if (!host->dma.chan) | |
2433 | host->dma.chan = ERR_PTR(-ENODEV); | |
2434 | } | |
2435 | ||
467e081d | 2436 | if (IS_ERR(host->dma.chan)) |
2437 | return PTR_ERR(host->dma.chan); | |
2438 | ||
2439 | dev_info(&host->pdev->dev, "using %s for DMA transfers\n", | |
2440 | dma_chan_name(host->dma.chan)); | |
2441 | ||
2442 | host->dma_conf.src_addr = host->mapbase + ATMCI_RDR; | |
2443 | host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
2444 | host->dma_conf.src_maxburst = 1; | |
2445 | host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR; | |
2446 | host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
2447 | host->dma_conf.dst_maxburst = 1; | |
2448 | host->dma_conf.device_fc = false; | |
2635d1ba | 2449 | |
467e081d | 2450 | return 0; |
2635d1ba | 2451 | } |
796211b7 | 2452 | |
796211b7 LD |
2453 | /* |
2454 | * HSMCI (High Speed MCI) module is not fully compatible with MCI module. | |
2455 | * HSMCI provides DMA support and a new config register but no more supports | |
2456 | * PDC. | |
2457 | */ | |
ab050b92 | 2458 | static void atmci_get_cap(struct atmel_mci *host) |
796211b7 LD |
2459 | { |
2460 | unsigned int version; | |
2461 | ||
2462 | version = atmci_get_version(host); | |
2463 | dev_info(&host->pdev->dev, | |
2464 | "version: 0x%x\n", version); | |
2465 | ||
ccdfe612 | 2466 | host->caps.has_dma_conf_reg = 0; |
6bf2af8c | 2467 | host->caps.has_pdc = ATMCI_PDC_CONNECTED; |
796211b7 LD |
2468 | host->caps.has_cfg_reg = 0; |
2469 | host->caps.has_cstor_reg = 0; | |
2470 | host->caps.has_highspeed = 0; | |
2471 | host->caps.has_rwproof = 0; | |
faf8180b | 2472 | host->caps.has_odd_clk_div = 0; |
24011f34 LD |
2473 | host->caps.has_bad_data_ordering = 1; |
2474 | host->caps.need_reset_after_xfer = 1; | |
2475 | host->caps.need_blksz_mul_4 = 1; | |
077d4073 | 2476 | host->caps.need_notbusy_for_read_ops = 0; |
796211b7 LD |
2477 | |
2478 | /* keep only major version number */ | |
2479 | switch (version & 0xf00) { | |
215ba399 | 2480 | case 0x600: |
796211b7 | 2481 | case 0x500: |
faf8180b LD |
2482 | host->caps.has_odd_clk_div = 1; |
2483 | case 0x400: | |
2484 | case 0x300: | |
ccdfe612 | 2485 | host->caps.has_dma_conf_reg = 1; |
faf8180b | 2486 | host->caps.has_pdc = 0; |
796211b7 LD |
2487 | host->caps.has_cfg_reg = 1; |
2488 | host->caps.has_cstor_reg = 1; | |
2489 | host->caps.has_highspeed = 1; | |
faf8180b | 2490 | case 0x200: |
796211b7 | 2491 | host->caps.has_rwproof = 1; |
24011f34 | 2492 | host->caps.need_blksz_mul_4 = 0; |
077d4073 | 2493 | host->caps.need_notbusy_for_read_ops = 1; |
faf8180b | 2494 | case 0x100: |
24011f34 LD |
2495 | host->caps.has_bad_data_ordering = 0; |
2496 | host->caps.need_reset_after_xfer = 0; | |
2497 | case 0x0: | |
796211b7 LD |
2498 | break; |
2499 | default: | |
faf8180b | 2500 | host->caps.has_pdc = 0; |
796211b7 LD |
2501 | dev_warn(&host->pdev->dev, |
2502 | "Unmanaged mci version, set minimum capabilities\n"); | |
2503 | break; | |
2504 | } | |
2505 | } | |
74465b4f | 2506 | |
ab050b92 | 2507 | static int atmci_probe(struct platform_device *pdev) |
7d2be074 HS |
2508 | { |
2509 | struct mci_platform_data *pdata; | |
965ebf33 HS |
2510 | struct atmel_mci *host; |
2511 | struct resource *regs; | |
2512 | unsigned int nr_slots; | |
2513 | int irq; | |
528bc780 | 2514 | int ret, i; |
7d2be074 HS |
2515 | |
2516 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2517 | if (!regs) | |
2518 | return -ENXIO; | |
2519 | pdata = pdev->dev.platform_data; | |
e919fd20 LD |
2520 | if (!pdata) { |
2521 | pdata = atmci_of_init(pdev); | |
2522 | if (IS_ERR(pdata)) { | |
2523 | dev_err(&pdev->dev, "platform data not available\n"); | |
2524 | return PTR_ERR(pdata); | |
2525 | } | |
2526 | } | |
2527 | ||
7d2be074 HS |
2528 | irq = platform_get_irq(pdev, 0); |
2529 | if (irq < 0) | |
2530 | return irq; | |
2531 | ||
7bca646e | 2532 | host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); |
965ebf33 | 2533 | if (!host) |
7d2be074 HS |
2534 | return -ENOMEM; |
2535 | ||
7d2be074 | 2536 | host->pdev = pdev; |
965ebf33 HS |
2537 | spin_lock_init(&host->lock); |
2538 | INIT_LIST_HEAD(&host->queue); | |
7d2be074 | 2539 | |
7bca646e PG |
2540 | host->mck = devm_clk_get(&pdev->dev, "mci_clk"); |
2541 | if (IS_ERR(host->mck)) | |
2542 | return PTR_ERR(host->mck); | |
7d2be074 | 2543 | |
7bca646e | 2544 | host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs)); |
7d2be074 | 2545 | if (!host->regs) |
7bca646e | 2546 | return -ENOMEM; |
7d2be074 | 2547 | |
b3894f26 BB |
2548 | ret = clk_prepare_enable(host->mck); |
2549 | if (ret) | |
7bca646e PG |
2550 | return ret; |
2551 | ||
03fc9a7f | 2552 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
7d2be074 | 2553 | host->bus_hz = clk_get_rate(host->mck); |
7d2be074 HS |
2554 | |
2555 | host->mapbase = regs->start; | |
2556 | ||
965ebf33 | 2557 | tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); |
7d2be074 | 2558 | |
89c8aa20 | 2559 | ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); |
ae552ab0 WY |
2560 | if (ret) { |
2561 | clk_disable_unprepare(host->mck); | |
7bca646e | 2562 | return ret; |
ae552ab0 | 2563 | } |
7d2be074 | 2564 | |
796211b7 LD |
2565 | /* Get MCI capabilities and set operations according to it */ |
2566 | atmci_get_cap(host); | |
467e081d | 2567 | ret = atmci_configure_dma(host); |
2568 | if (ret == -EPROBE_DEFER) | |
2569 | goto err_dma_probe_defer; | |
2570 | if (ret == 0) { | |
796211b7 LD |
2571 | host->prepare_data = &atmci_prepare_data_dma; |
2572 | host->submit_data = &atmci_submit_data_dma; | |
2573 | host->stop_transfer = &atmci_stop_transfer_dma; | |
2574 | } else if (host->caps.has_pdc) { | |
2575 | dev_info(&pdev->dev, "using PDC\n"); | |
2576 | host->prepare_data = &atmci_prepare_data_pdc; | |
2577 | host->submit_data = &atmci_submit_data_pdc; | |
2578 | host->stop_transfer = &atmci_stop_transfer_pdc; | |
2579 | } else { | |
ef878198 | 2580 | dev_info(&pdev->dev, "using PIO\n"); |
796211b7 LD |
2581 | host->prepare_data = &atmci_prepare_data; |
2582 | host->submit_data = &atmci_submit_data; | |
2583 | host->stop_transfer = &atmci_stop_transfer; | |
2584 | } | |
2585 | ||
7d2be074 HS |
2586 | platform_set_drvdata(pdev, host); |
2587 | ||
b87cc1b5 LD |
2588 | setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host); |
2589 | ||
ae552ab0 WY |
2590 | pm_runtime_get_noresume(&pdev->dev); |
2591 | pm_runtime_set_active(&pdev->dev); | |
2592 | pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY); | |
2593 | pm_runtime_use_autosuspend(&pdev->dev); | |
2594 | pm_runtime_enable(&pdev->dev); | |
2595 | ||
965ebf33 HS |
2596 | /* We need at least one slot to succeed */ |
2597 | nr_slots = 0; | |
2598 | ret = -ENODEV; | |
2599 | if (pdata->slot[0].bus_width) { | |
2600 | ret = atmci_init_slot(host, &pdata->slot[0], | |
2c96a293 | 2601 | 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); |
7a90dcc2 | 2602 | if (!ret) { |
965ebf33 | 2603 | nr_slots++; |
7a90dcc2 LD |
2604 | host->buf_size = host->slot[0]->mmc->max_req_size; |
2605 | } | |
965ebf33 HS |
2606 | } |
2607 | if (pdata->slot[1].bus_width) { | |
2608 | ret = atmci_init_slot(host, &pdata->slot[1], | |
2c96a293 | 2609 | 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); |
7a90dcc2 | 2610 | if (!ret) { |
965ebf33 | 2611 | nr_slots++; |
7a90dcc2 LD |
2612 | if (host->slot[1]->mmc->max_req_size > host->buf_size) |
2613 | host->buf_size = | |
2614 | host->slot[1]->mmc->max_req_size; | |
2615 | } | |
7d2be074 HS |
2616 | } |
2617 | ||
04d699c3 RE |
2618 | if (!nr_slots) { |
2619 | dev_err(&pdev->dev, "init failed: no slot defined\n"); | |
965ebf33 | 2620 | goto err_init_slot; |
04d699c3 | 2621 | } |
7d2be074 | 2622 | |
7a90dcc2 LD |
2623 | if (!host->caps.has_rwproof) { |
2624 | host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size, | |
2625 | &host->buf_phys_addr, | |
2626 | GFP_KERNEL); | |
2627 | if (!host->buffer) { | |
2628 | ret = -ENOMEM; | |
2629 | dev_err(&pdev->dev, "buffer allocation failed\n"); | |
528bc780 | 2630 | goto err_dma_alloc; |
7a90dcc2 LD |
2631 | } |
2632 | } | |
2633 | ||
965ebf33 HS |
2634 | dev_info(&pdev->dev, |
2635 | "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", | |
2636 | host->mapbase, irq, nr_slots); | |
deec9ae3 | 2637 | |
ae552ab0 WY |
2638 | pm_runtime_mark_last_busy(&host->pdev->dev); |
2639 | pm_runtime_put_autosuspend(&pdev->dev); | |
2640 | ||
7d2be074 HS |
2641 | return 0; |
2642 | ||
528bc780 PG |
2643 | err_dma_alloc: |
2644 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { | |
2645 | if (host->slot[i]) | |
2646 | atmci_cleanup_slot(host->slot[i], i); | |
2647 | } | |
965ebf33 | 2648 | err_init_slot: |
ae552ab0 WY |
2649 | clk_disable_unprepare(host->mck); |
2650 | ||
2651 | pm_runtime_disable(&pdev->dev); | |
2652 | pm_runtime_put_noidle(&pdev->dev); | |
2653 | ||
528bc780 | 2654 | del_timer_sync(&host->timer); |
467e081d | 2655 | if (!IS_ERR(host->dma.chan)) |
74465b4f | 2656 | dma_release_channel(host->dma.chan); |
467e081d | 2657 | err_dma_probe_defer: |
965ebf33 | 2658 | free_irq(irq, host); |
7d2be074 HS |
2659 | return ret; |
2660 | } | |
2661 | ||
ab050b92 | 2662 | static int atmci_remove(struct platform_device *pdev) |
7d2be074 | 2663 | { |
965ebf33 HS |
2664 | struct atmel_mci *host = platform_get_drvdata(pdev); |
2665 | unsigned int i; | |
7d2be074 | 2666 | |
ae552ab0 WY |
2667 | pm_runtime_get_sync(&pdev->dev); |
2668 | ||
7a90dcc2 LD |
2669 | if (host->buffer) |
2670 | dma_free_coherent(&pdev->dev, host->buf_size, | |
2671 | host->buffer, host->buf_phys_addr); | |
2672 | ||
2c96a293 | 2673 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
965ebf33 HS |
2674 | if (host->slot[i]) |
2675 | atmci_cleanup_slot(host->slot[i], i); | |
2676 | } | |
7d2be074 | 2677 | |
03fc9a7f LD |
2678 | atmci_writel(host, ATMCI_IDR, ~0UL); |
2679 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); | |
2680 | atmci_readl(host, ATMCI_SR); | |
7d2be074 | 2681 | |
528bc780 | 2682 | del_timer_sync(&host->timer); |
467e081d | 2683 | if (!IS_ERR(host->dma.chan)) |
74465b4f | 2684 | dma_release_channel(host->dma.chan); |
65e8b083 | 2685 | |
965ebf33 | 2686 | free_irq(platform_get_irq(pdev, 0), host); |
7d2be074 | 2687 | |
ae552ab0 WY |
2688 | clk_disable_unprepare(host->mck); |
2689 | ||
2690 | pm_runtime_disable(&pdev->dev); | |
2691 | pm_runtime_put_noidle(&pdev->dev); | |
2692 | ||
2693 | return 0; | |
2694 | } | |
2695 | ||
2696 | #ifdef CONFIG_PM | |
2697 | static int atmci_runtime_suspend(struct device *dev) | |
2698 | { | |
2699 | struct atmel_mci *host = dev_get_drvdata(dev); | |
2700 | ||
2701 | clk_disable_unprepare(host->mck); | |
2702 | ||
b5b64fa6 WY |
2703 | pinctrl_pm_select_sleep_state(dev); |
2704 | ||
7d2be074 HS |
2705 | return 0; |
2706 | } | |
2707 | ||
ae552ab0 WY |
2708 | static int atmci_runtime_resume(struct device *dev) |
2709 | { | |
2710 | struct atmel_mci *host = dev_get_drvdata(dev); | |
2711 | ||
b5b64fa6 WY |
2712 | pinctrl_pm_select_default_state(dev); |
2713 | ||
ae552ab0 WY |
2714 | return clk_prepare_enable(host->mck); |
2715 | } | |
2716 | #endif | |
2717 | ||
2718 | static const struct dev_pm_ops atmci_dev_pm_ops = { | |
2719 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
2720 | pm_runtime_force_resume) | |
c3cb6ba4 | 2721 | SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL) |
ae552ab0 WY |
2722 | }; |
2723 | ||
7d2be074 | 2724 | static struct platform_driver atmci_driver = { |
5e0fe897 | 2725 | .probe = atmci_probe, |
ab050b92 | 2726 | .remove = atmci_remove, |
7d2be074 HS |
2727 | .driver = { |
2728 | .name = "atmel_mci", | |
e919fd20 | 2729 | .of_match_table = of_match_ptr(atmci_dt_ids), |
ae552ab0 | 2730 | .pm = &atmci_dev_pm_ops, |
7d2be074 HS |
2731 | }, |
2732 | }; | |
5e0fe897 | 2733 | module_platform_driver(atmci_driver); |
7d2be074 HS |
2734 | |
2735 | MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); | |
e05503ef | 2736 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
7d2be074 | 2737 | MODULE_LICENSE("GPL v2"); |