[linux-2.6-block.git] / drivers / mmc / host / android-goldfish.c

/*
 *  Copyright 2007, Google Inc.
 *  Copyright 2012, Intel Inc.
 *
 *  based on omap.c driver, which was
 *  Copyright (C) 2004 Nokia Corporation
 *  Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
 *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
 *  Other hacks (DMA, SD, etc) by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/major.h>

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/interrupt.h>

#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/hdreg.h>
#include <linux/kdev_t.h>
#include <linux/blkdev.h>
#include <linux/mutex.h>
#include <linux/scatterlist.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/host.h>
#include <linux/mmc/card.h>

#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/timer.h>
#include <linux/clk.h>
#include <linux/scatterlist.h>

#include <asm/io.h>
#include <asm/irq.h>

#include <asm/types.h>
#include <asm/io.h>
#include <linux/uaccess.h>

#define DRIVER_NAME "goldfish_mmc"

#define BUFFER_SIZE   16384

#define GOLDFISH_MMC_READ(host, addr)   (readl(host->reg_base + addr))
#define GOLDFISH_MMC_WRITE(host, addr, x)   (writel(x, host->reg_base + addr))

enum {
	/* status register */
	MMC_INT_STATUS	        = 0x00,
	/* set this to enable IRQ */
	MMC_INT_ENABLE	        = 0x04,
	/* set this to specify buffer address */
	MMC_SET_BUFFER          = 0x08,

	/* MMC command number */
	MMC_CMD	                = 0x0C,

	/* MMC argument */
	MMC_ARG	                = 0x10,

	/* MMC response (or R2 bits 0 - 31) */
	MMC_RESP_0		        = 0x14,

	/* MMC R2 response bits 32 - 63 */
	MMC_RESP_1		        = 0x18,

	/* MMC R2 response bits 64 - 95 */
	MMC_RESP_2		        = 0x1C,

	/* MMC R2 response bits 96 - 127 */
	MMC_RESP_3		        = 0x20,

	MMC_BLOCK_LENGTH        = 0x24,
	MMC_BLOCK_COUNT         = 0x28,

	/* MMC state flags */
	MMC_STATE               = 0x2C,

	/* MMC_INT_STATUS bits */

	MMC_STAT_END_OF_CMD     = 1U << 0,
	MMC_STAT_END_OF_DATA    = 1U << 1,
	MMC_STAT_STATE_CHANGE   = 1U << 2,
	MMC_STAT_CMD_TIMEOUT    = 1U << 3,

	/* MMC_STATE bits */
	MMC_STATE_INSERTED     = 1U << 0,
	MMC_STATE_READ_ONLY    = 1U << 1,
};

/*
 * Command types
 */
#define OMAP_MMC_CMDTYPE_BC	0
#define OMAP_MMC_CMDTYPE_BCR	1
#define OMAP_MMC_CMDTYPE_AC	2
#define OMAP_MMC_CMDTYPE_ADTC	3


struct goldfish_mmc_host {
	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;
	struct mmc_host		*mmc;
	struct device		*dev;
	unsigned char		id; /* 16xx chips have 2 MMC blocks */
	void			*virt_base;
	unsigned int		phys_base;
	int			irq;
	unsigned char		bus_mode;
	unsigned char		hw_bus_mode;

	unsigned int		sg_len;
	unsigned		dma_done:1;
	unsigned		dma_in_use:1;

	void __iomem		*reg_base;
};

static inline int
goldfish_mmc_cover_is_open(struct goldfish_mmc_host *host)
{
	return 0;
}

static ssize_t
goldfish_mmc_show_cover_switch(struct device *dev,
			       struct device_attribute *attr, char *buf)
{
	struct goldfish_mmc_host *host = dev_get_drvdata(dev);

	return sprintf(buf, "%s\n", goldfish_mmc_cover_is_open(host) ? "open" :
		       "closed");
}

static DEVICE_ATTR(cover_switch, S_IRUGO, goldfish_mmc_show_cover_switch, NULL);

static void
goldfish_mmc_start_command(struct goldfish_mmc_host *host, struct mmc_command *cmd)
{
	u32 cmdreg;
	u32 resptype;
	u32 cmdtype;

	host->cmd = cmd;

	resptype = 0;
	cmdtype = 0;

	/* Our hardware needs to know exact type */
	switch (mmc_resp_type(cmd)) {
	case MMC_RSP_NONE:
		break;
	case MMC_RSP_R1:
	case MMC_RSP_R1B:
		/* resp 1, 1b, 6, 7 */
		resptype = 1;
		break;
	case MMC_RSP_R2:
		resptype = 2;
		break;
	case MMC_RSP_R3:
		resptype = 3;
		break;
	default:
		dev_err(mmc_dev(host->mmc),
			"Invalid response type: %04x\n", mmc_resp_type(cmd));
		break;
	}

	if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
		cmdtype = OMAP_MMC_CMDTYPE_ADTC;
	else if (mmc_cmd_type(cmd) == MMC_CMD_BC)
		cmdtype = OMAP_MMC_CMDTYPE_BC;
	else if (mmc_cmd_type(cmd) == MMC_CMD_BCR)
		cmdtype = OMAP_MMC_CMDTYPE_BCR;
	else
		cmdtype = OMAP_MMC_CMDTYPE_AC;

	cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);

	if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
		cmdreg |= 1 << 6;

	if (cmd->flags & MMC_RSP_BUSY)
		cmdreg |= 1 << 11;

	if (host->data && !(host->data->flags & MMC_DATA_WRITE))
		cmdreg |= 1 << 15;

	GOLDFISH_MMC_WRITE(host, MMC_ARG, cmd->arg);
	GOLDFISH_MMC_WRITE(host, MMC_CMD, cmdreg);
}

static void goldfish_mmc_xfer_done(struct goldfish_mmc_host *host,
				   struct mmc_data *data)
{
	if (host->dma_in_use) {
		enum dma_data_direction dma_data_dir;

		dma_data_dir = mmc_get_dma_dir(data);

		if (dma_data_dir == DMA_FROM_DEVICE) {
			/*
			 * We don't really have DMA, so we need
			 * to copy from our platform driver buffer
			 */
			uint8_t *dest = (uint8_t *)sg_virt(data->sg);
			memcpy(dest, host->virt_base, data->sg->length);
		}
		host->data->bytes_xfered += data->sg->length;
		dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
			     dma_data_dir);
	}

	host->data = NULL;
	host->sg_len = 0;

	/*
	 * NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
	 * dozens of requests until the card finishes writing data.
	 * It'd be cheaper to just wait till an EOFB interrupt arrives...
	 */

	if (!data->stop) {
		host->mrq = NULL;
		mmc_request_done(host->mmc, data->mrq);
		return;
	}

	goldfish_mmc_start_command(host, data->stop);
}

static void goldfish_mmc_end_of_data(struct goldfish_mmc_host *host,
				     struct mmc_data *data)
{
	if (!host->dma_in_use) {
		goldfish_mmc_xfer_done(host, data);
		return;
	}
	if (host->dma_done)
		goldfish_mmc_xfer_done(host, data);
}

static void goldfish_mmc_cmd_done(struct goldfish_mmc_host *host,
				  struct mmc_command *cmd)
{
	host->cmd = NULL;
	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136) {
			/* response type 2 */
			cmd->resp[3] =
				GOLDFISH_MMC_READ(host, MMC_RESP_0);
			cmd->resp[2] =
				GOLDFISH_MMC_READ(host, MMC_RESP_1);
			cmd->resp[1] =
				GOLDFISH_MMC_READ(host, MMC_RESP_2);
			cmd->resp[0] =
				GOLDFISH_MMC_READ(host, MMC_RESP_3);
		} else {
			/* response types 1, 1b, 3, 4, 5, 6 */
			cmd->resp[0] =
				GOLDFISH_MMC_READ(host, MMC_RESP_0);
		}
	}

	if (host->data == NULL || cmd->error) {
		host->mrq = NULL;
		mmc_request_done(host->mmc, cmd->mrq);
	}
}

static irqreturn_t goldfish_mmc_irq(int irq, void *dev_id)
{
	struct goldfish_mmc_host *host = (struct goldfish_mmc_host *)dev_id;
	u16 status;
	int end_command = 0;
	int end_transfer = 0;
	int state_changed = 0;
	int cmd_timeout = 0;

	while ((status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS)) != 0) {
		GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);

		if (status & MMC_STAT_END_OF_CMD)
			end_command = 1;

		if (status & MMC_STAT_END_OF_DATA)
			end_transfer = 1;

		if (status & MMC_STAT_STATE_CHANGE)
			state_changed = 1;

                if (status & MMC_STAT_CMD_TIMEOUT) {
			end_command = 0;
			cmd_timeout = 1;
                }
	}

	if (cmd_timeout) {
		struct mmc_request *mrq = host->mrq;
		mrq->cmd->error = -ETIMEDOUT;
		host->mrq = NULL;
		mmc_request_done(host->mmc, mrq);
	}

	if (end_command)
		goldfish_mmc_cmd_done(host, host->cmd);

	if (end_transfer) {
		host->dma_done = 1;
		goldfish_mmc_end_of_data(host, host->data);
	} else if (host->data != NULL) {
		/*
		 * WORKAROUND -- after porting this driver from 2.6 to 3.4,
		 * during device initialization, cases where host->data is
		 * non-null but end_transfer is false would occur. Doing
		 * nothing in such cases results in no further interrupts,
		 * and initialization failure.
		 * TODO -- find the real cause.
		 */
		host->dma_done = 1;
		goldfish_mmc_end_of_data(host, host->data);
	}

	if (state_changed) {
		u32 state = GOLDFISH_MMC_READ(host, MMC_STATE);
		pr_info("%s: Card detect now %d\n", __func__,
			(state & MMC_STATE_INSERTED));
		mmc_detect_change(host->mmc, 0);
	}

	if (!end_command && !end_transfer && !state_changed && !cmd_timeout) {
		status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS);
		dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
		if (status != 0) {
			GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
			GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE, 0);
		}
	}

	return IRQ_HANDLED;
}

static void goldfish_mmc_prepare_data(struct goldfish_mmc_host *host,
				      struct mmc_request *req)
{
	struct mmc_data *data = req->data;
	int block_size;
	unsigned sg_len;
	enum dma_data_direction dma_data_dir;

	host->data = data;
	if (data == NULL) {
		GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, 0);
		GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, 0);
		host->dma_in_use = 0;
		return;
	}

	block_size = data->blksz;

	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, data->blocks - 1);
	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, block_size - 1);

	/*
	 * Cope with calling layer confusion; it issues "single
	 * block" writes using multi-block scatterlists.
	 */
	sg_len = (data->blocks == 1) ? 1 : data->sg_len;

	dma_data_dir = mmc_get_dma_dir(data);

	host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
				  sg_len, dma_data_dir);
	host->dma_done = 0;
	host->dma_in_use = 1;

	if (dma_data_dir == DMA_TO_DEVICE) {
		/*
		 * We don't really have DMA, so we need to copy to our
		 * platform driver buffer
		 */
		const uint8_t *src = (uint8_t *)sg_virt(data->sg);
		memcpy(host->virt_base, src, data->sg->length);
	}
}

static void goldfish_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
{
	struct goldfish_mmc_host *host = mmc_priv(mmc);

	WARN_ON(host->mrq != NULL);

	host->mrq = req;
	goldfish_mmc_prepare_data(host, req);
	goldfish_mmc_start_command(host, req->cmd);

	/*
	 * This is to avoid accidentally being detected as an SDIO card
	 * in mmc_attach_sdio().
	 */
	if (req->cmd->opcode == SD_IO_SEND_OP_COND &&
	    req->cmd->flags == (MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR))
		req->cmd->error = -EINVAL;
}

static void goldfish_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct goldfish_mmc_host *host = mmc_priv(mmc);

	host->bus_mode = ios->bus_mode;
	host->hw_bus_mode = host->bus_mode;
}

static int goldfish_mmc_get_ro(struct mmc_host *mmc)
{
	uint32_t state;
	struct goldfish_mmc_host *host = mmc_priv(mmc);

	state = GOLDFISH_MMC_READ(host, MMC_STATE);
	return ((state & MMC_STATE_READ_ONLY) != 0);
}

static const struct mmc_host_ops goldfish_mmc_ops = {
	.request	= goldfish_mmc_request,
	.set_ios	= goldfish_mmc_set_ios,
	.get_ro		= goldfish_mmc_get_ro,
};

static int goldfish_mmc_probe(struct platform_device *pdev)
{
	struct mmc_host *mmc;
	struct goldfish_mmc_host *host = NULL;
	struct resource *res;
	int ret = 0;
	int irq;
	dma_addr_t buf_addr;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
	if (res == NULL || irq < 0)
		return -ENXIO;

	mmc = mmc_alloc_host(sizeof(struct goldfish_mmc_host), &pdev->dev);
	if (mmc == NULL) {
		ret = -ENOMEM;
		goto err_alloc_host_failed;
	}

	host = mmc_priv(mmc);
	host->mmc = mmc;

	pr_err("mmc: Mapping %lX to %lX\n", (long)res->start, (long)res->end);
	host->reg_base = ioremap(res->start, resource_size(res));
	if (host->reg_base == NULL) {
		ret = -ENOMEM;
		goto ioremap_failed;
	}
	host->virt_base = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
					     &buf_addr, GFP_KERNEL);

	if (host->virt_base == 0) {
		ret = -ENOMEM;
		goto dma_alloc_failed;
	}
	host->phys_base = buf_addr;

	host->id = pdev->id;
	host->irq = irq;

	mmc->ops = &goldfish_mmc_ops;
	mmc->f_min = 400000;
	mmc->f_max = 24000000;
	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
	mmc->caps = MMC_CAP_4_BIT_DATA;

	/* Use scatterlist DMA to reduce per-transfer costs.
	 * NOTE max_seg_size assumption that small blocks aren't
	 * normally used (except e.g. for reading SD registers).
	 */
	mmc->max_segs = 32;
	mmc->max_blk_size = 2048;	/* MMC_BLOCK_LENGTH is 11 bits (+1) */
	mmc->max_blk_count = 2048;	/* MMC_BLOCK_COUNT is 11 bits (+1) */
	mmc->max_req_size = BUFFER_SIZE;
	mmc->max_seg_size = mmc->max_req_size;

	ret = request_irq(host->irq, goldfish_mmc_irq, 0, DRIVER_NAME, host);
	if (ret) {
		dev_err(&pdev->dev, "Failed IRQ Adding goldfish MMC\n");
		goto err_request_irq_failed;
	}

	host->dev = &pdev->dev;
	platform_set_drvdata(pdev, host);

	ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
	if (ret)
		dev_warn(mmc_dev(host->mmc),
			 "Unable to create sysfs attributes\n");

	GOLDFISH_MMC_WRITE(host, MMC_SET_BUFFER, host->phys_base);
	GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE,
			   MMC_STAT_END_OF_CMD | MMC_STAT_END_OF_DATA |
			   MMC_STAT_STATE_CHANGE | MMC_STAT_CMD_TIMEOUT);

	mmc_add_host(mmc);
	return 0;

err_request_irq_failed:
	dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base,
			  host->phys_base);
dma_alloc_failed:
	iounmap(host->reg_base);
ioremap_failed:
	mmc_free_host(host->mmc);
err_alloc_host_failed:
	return ret;
}

static int goldfish_mmc_remove(struct platform_device *pdev)
{
	struct goldfish_mmc_host *host = platform_get_drvdata(pdev);

	BUG_ON(host == NULL);

	mmc_remove_host(host->mmc);
	free_irq(host->irq, host);
	dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
	iounmap(host->reg_base);
	mmc_free_host(host->mmc);
	return 0;
}

static struct platform_driver goldfish_mmc_driver = {
	.probe		= goldfish_mmc_probe,
	.remove		= goldfish_mmc_remove,
	.driver		= {
		.name	= DRIVER_NAME,
	},
};

module_platform_driver(goldfish_mmc_driver);
MODULE_LICENSE("GPL v2");
Commit	Line	Data
85c34d2e ML	1	/*
	2	* Copyright 2007, Google Inc.
	3	* Copyright 2012, Intel Inc.
	4	*
	5	* based on omap.c driver, which was
	6	* Copyright (C) 2004 Nokia Corporation
	7	* Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
	8	* Misc hacks here and there by Tony Lindgren <tony@atomide.com>
	9	* Other hacks (DMA, SD, etc) by David Brownell
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/major.h>
	19
	20	#include <linux/types.h>
	21	#include <linux/pci.h>
	22	#include <linux/interrupt.h>
	23
	24	#include <linux/kernel.h>
	25	#include <linux/fs.h>
	26	#include <linux/errno.h>
	27	#include <linux/hdreg.h>
	28	#include <linux/kdev_t.h>
	29	#include <linux/blkdev.h>
	30	#include <linux/mutex.h>
	31	#include <linux/scatterlist.h>
	32	#include <linux/mmc/mmc.h>
	33	#include <linux/mmc/sdio.h>
	34	#include <linux/mmc/host.h>
	35	#include <linux/mmc/card.h>
	36
	37	#include <linux/moduleparam.h>
	38	#include <linux/init.h>
	39	#include <linux/ioport.h>
	40	#include <linux/dma-mapping.h>
	41	#include <linux/delay.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/timer.h>
	44	#include <linux/clk.h>
84be456f	45	#include <linux/scatterlist.h>
85c34d2e ML	46
	47	#include <asm/io.h>
	48	#include <asm/irq.h>
85c34d2e ML	49
	50	#include <asm/types.h>
	51	#include <asm/io.h>
7c0f6ba6	52	#include <linux/uaccess.h>
85c34d2e ML	53
	54	#define DRIVER_NAME "goldfish_mmc"
	55
	56	#define BUFFER_SIZE 16384
	57
	58	#define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr))
	59	#define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr))
	60
	61	enum {
	62	/* status register */
	63	MMC_INT_STATUS = 0x00,
	64	/* set this to enable IRQ */
	65	MMC_INT_ENABLE = 0x04,
	66	/* set this to specify buffer address */
	67	MMC_SET_BUFFER = 0x08,
	68
	69	/* MMC command number */
	70	MMC_CMD = 0x0C,
	71
	72	/* MMC argument */
	73	MMC_ARG = 0x10,
	74
	75	/* MMC response (or R2 bits 0 - 31) */
	76	MMC_RESP_0 = 0x14,
	77
	78	/* MMC R2 response bits 32 - 63 */
	79	MMC_RESP_1 = 0x18,
	80
	81	/* MMC R2 response bits 64 - 95 */
	82	MMC_RESP_2 = 0x1C,
	83
	84	/* MMC R2 response bits 96 - 127 */
	85	MMC_RESP_3 = 0x20,
	86
	87	MMC_BLOCK_LENGTH = 0x24,
	88	MMC_BLOCK_COUNT = 0x28,
	89
	90	/* MMC state flags */
	91	MMC_STATE = 0x2C,
	92
	93	/* MMC_INT_STATUS bits */
	94
	95	MMC_STAT_END_OF_CMD = 1U << 0,
	96	MMC_STAT_END_OF_DATA = 1U << 1,
	97	MMC_STAT_STATE_CHANGE = 1U << 2,
	98	MMC_STAT_CMD_TIMEOUT = 1U << 3,
	99
	100	/* MMC_STATE bits */
	101	MMC_STATE_INSERTED = 1U << 0,
	102	MMC_STATE_READ_ONLY = 1U << 1,
	103	};
	104
	105	/*
	106	* Command types
	107	*/
	108	#define OMAP_MMC_CMDTYPE_BC 0
	109	#define OMAP_MMC_CMDTYPE_BCR 1
	110	#define OMAP_MMC_CMDTYPE_AC 2
	111	#define OMAP_MMC_CMDTYPE_ADTC 3
	112
	113
	114	struct goldfish_mmc_host {
	115	struct mmc_request *mrq;
	116	struct mmc_command *cmd;
117	struct mmc_data *data;
118	struct mmc_host *mmc;
119	struct device *dev;
120	unsigned char id; /* 16xx chips have 2 MMC blocks */
092b6dbe	121	void *virt_base;
85c34d2e ML	122	unsigned int phys_base;
	123	int irq;
	124	unsigned char bus_mode;
	125	unsigned char hw_bus_mode;
	126
	127	unsigned int sg_len;
	128	unsigned dma_done:1;
	129	unsigned dma_in_use:1;
	130
	131	void __iomem *reg_base;
	132	};
	133
	134	static inline int
	135	goldfish_mmc_cover_is_open(struct goldfish_mmc_host *host)
	136	{
	137	return 0;
	138	}
	139
	140	static ssize_t
	141	goldfish_mmc_show_cover_switch(struct device *dev,
	142	struct device_attribute attr, char buf)
	143	{
	144	struct goldfish_mmc_host *host = dev_get_drvdata(dev);
	145
	146	return sprintf(buf, "%s\n", goldfish_mmc_cover_is_open(host) ? "open" :
	147	"closed");
	148	}
	149
	150	static DEVICE_ATTR(cover_switch, S_IRUGO, goldfish_mmc_show_cover_switch, NULL);
	151
	152	static void
	153	goldfish_mmc_start_command(struct goldfish_mmc_host host, struct mmc_command cmd)
	154	{
	155	u32 cmdreg;
	156	u32 resptype;
	157	u32 cmdtype;
	158
	159	host->cmd = cmd;
	160
	161	resptype = 0;
	162	cmdtype = 0;
	163
	164	/* Our hardware needs to know exact type */
	165	switch (mmc_resp_type(cmd)) {
	166	case MMC_RSP_NONE:
	167	break;
	168	case MMC_RSP_R1:
	169	case MMC_RSP_R1B:
	170	/* resp 1, 1b, 6, 7 */
	171	resptype = 1;
	172	break;
	173	case MMC_RSP_R2:
	174	resptype = 2;
	175	break;
	176	case MMC_RSP_R3:
	177	resptype = 3;
	178	break;
	179	default:
	180	dev_err(mmc_dev(host->mmc),
	181	"Invalid response type: %04x\n", mmc_resp_type(cmd));
	182	break;
	183	}
	184
	185	if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
186	cmdtype = OMAP_MMC_CMDTYPE_ADTC;
187	else if (mmc_cmd_type(cmd) == MMC_CMD_BC)
188	cmdtype = OMAP_MMC_CMDTYPE_BC;
189	else if (mmc_cmd_type(cmd) == MMC_CMD_BCR)
190	cmdtype = OMAP_MMC_CMDTYPE_BCR;
191	else
192	cmdtype = OMAP_MMC_CMDTYPE_AC;
193
194	cmdreg = cmd->opcode \| (resptype << 8) \| (cmdtype << 12);
195
196	if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
197	cmdreg \|= 1 << 6;
198
199	if (cmd->flags & MMC_RSP_BUSY)
200	cmdreg \|= 1 << 11;
201
202	if (host->data && !(host->data->flags & MMC_DATA_WRITE))
203	cmdreg \|= 1 << 15;
204
205	GOLDFISH_MMC_WRITE(host, MMC_ARG, cmd->arg);
206	GOLDFISH_MMC_WRITE(host, MMC_CMD, cmdreg);
207	}
208
209	static void goldfish_mmc_xfer_done(struct goldfish_mmc_host *host,
210	struct mmc_data *data)
211	{
212	if (host->dma_in_use) {
213	enum dma_data_direction dma_data_dir;
214
feeef096	215	dma_data_dir = mmc_get_dma_dir(data);
85c34d2e ML	216
	217	if (dma_data_dir == DMA_FROM_DEVICE) {
	218	/*
	219	* We don't really have DMA, so we need
	220	* to copy from our platform driver buffer
	221	*/
	222	uint8_t dest = (uint8_t )sg_virt(data->sg);
	223	memcpy(dest, host->virt_base, data->sg->length);
	224	}
	225	host->data->bytes_xfered += data->sg->length;
	226	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
	227	dma_data_dir);
	228	}
	229
	230	host->data = NULL;
	231	host->sg_len = 0;
	232
	233	/*
	234	* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
	235	* dozens of requests until the card finishes writing data.
	236	* It'd be cheaper to just wait till an EOFB interrupt arrives...
	237	*/
	238
	239	if (!data->stop) {
	240	host->mrq = NULL;
	241	mmc_request_done(host->mmc, data->mrq);
	242	return;
	243	}
	244
	245	goldfish_mmc_start_command(host, data->stop);
	246	}
	247
	248	static void goldfish_mmc_end_of_data(struct goldfish_mmc_host *host,
	249	struct mmc_data *data)
	250	{
	251	if (!host->dma_in_use) {
	252	goldfish_mmc_xfer_done(host, data);
	253	return;
	254	}
	255	if (host->dma_done)
	256	goldfish_mmc_xfer_done(host, data);
	257	}
	258
	259	static void goldfish_mmc_cmd_done(struct goldfish_mmc_host *host,
	260	struct mmc_command *cmd)
	261	{
	262	host->cmd = NULL;
	263	if (cmd->flags & MMC_RSP_PRESENT) {
	264	if (cmd->flags & MMC_RSP_136) {
	265	/* response type 2 */
	266	cmd->resp[3] =
	267	GOLDFISH_MMC_READ(host, MMC_RESP_0);
	268	cmd->resp[2] =
	269	GOLDFISH_MMC_READ(host, MMC_RESP_1);
	270	cmd->resp[1] =
	271	GOLDFISH_MMC_READ(host, MMC_RESP_2);
	272	cmd->resp[0] =
	273	GOLDFISH_MMC_READ(host, MMC_RESP_3);
	274	} else {
	275	/* response types 1, 1b, 3, 4, 5, 6 */
	276	cmd->resp[0] =
	277	GOLDFISH_MMC_READ(host, MMC_RESP_0);
	278	}
	279	}
280
281	if (host->data == NULL \|\| cmd->error) {
282	host->mrq = NULL;
283	mmc_request_done(host->mmc, cmd->mrq);
284	}
285	}
286
287	static irqreturn_t goldfish_mmc_irq(int irq, void *dev_id)
288	{
289	struct goldfish_mmc_host host = (struct goldfish_mmc_host )dev_id;
290	u16 status;
291	int end_command = 0;
292	int end_transfer = 0;
85c34d2e ML	293	int state_changed = 0;
	294	int cmd_timeout = 0;
	295
	296	while ((status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS)) != 0) {
	297	GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
	298
	299	if (status & MMC_STAT_END_OF_CMD)
	300	end_command = 1;
	301
	302	if (status & MMC_STAT_END_OF_DATA)
	303	end_transfer = 1;
	304
	305	if (status & MMC_STAT_STATE_CHANGE)
	306	state_changed = 1;
	307
	308	if (status & MMC_STAT_CMD_TIMEOUT) {
	309	end_command = 0;
	310	cmd_timeout = 1;
	311	}
	312	}
	313
	314	if (cmd_timeout) {
	315	struct mmc_request *mrq = host->mrq;
	316	mrq->cmd->error = -ETIMEDOUT;
	317	host->mrq = NULL;
	318	mmc_request_done(host->mmc, mrq);
	319	}
	320
	321	if (end_command)
	322	goldfish_mmc_cmd_done(host, host->cmd);
	323
0f77934a	324	if (end_transfer) {
85c34d2e ML	325	host->dma_done = 1;
	326	goldfish_mmc_end_of_data(host, host->data);
	327	} else if (host->data != NULL) {
	328	/*
	329	* WORKAROUND -- after porting this driver from 2.6 to 3.4,
	330	* during device initialization, cases where host->data is
	331	* non-null but end_transfer is false would occur. Doing
	332	* nothing in such cases results in no further interrupts,
	333	* and initialization failure.
	334	* TODO -- find the real cause.
	335	*/
	336	host->dma_done = 1;
	337	goldfish_mmc_end_of_data(host, host->data);
	338	}
	339
	340	if (state_changed) {
	341	u32 state = GOLDFISH_MMC_READ(host, MMC_STATE);
	342	pr_info("%s: Card detect now %d\n", __func__,
	343	(state & MMC_STATE_INSERTED));
	344	mmc_detect_change(host->mmc, 0);
	345	}
	346
0f77934a	347	if (!end_command && !end_transfer && !state_changed && !cmd_timeout) {
85c34d2e ML	348	status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS);
	349	dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
	350	if (status != 0) {
	351	GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
	352	GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE, 0);
	353	}
	354	}
	355
	356	return IRQ_HANDLED;
	357	}
	358
	359	static void goldfish_mmc_prepare_data(struct goldfish_mmc_host *host,
	360	struct mmc_request *req)
	361	{
	362	struct mmc_data *data = req->data;
	363	int block_size;
	364	unsigned sg_len;
	365	enum dma_data_direction dma_data_dir;
	366
	367	host->data = data;
	368	if (data == NULL) {
	369	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, 0);
	370	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, 0);
	371	host->dma_in_use = 0;
	372	return;
	373	}
	374
	375	block_size = data->blksz;
	376
	377	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, data->blocks - 1);
	378	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, block_size - 1);
	379
	380	/*
	381	* Cope with calling layer confusion; it issues "single
	382	* block" writes using multi-block scatterlists.
	383	*/
	384	sg_len = (data->blocks == 1) ? 1 : data->sg_len;
	385
feeef096	386	dma_data_dir = mmc_get_dma_dir(data);
85c34d2e ML	387
	388	host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
	389	sg_len, dma_data_dir);
	390	host->dma_done = 0;
	391	host->dma_in_use = 1;
	392
	393	if (dma_data_dir == DMA_TO_DEVICE) {
	394	/*
	395	* We don't really have DMA, so we need to copy to our
	396	* platform driver buffer
	397	*/
	398	const uint8_t src = (uint8_t )sg_virt(data->sg);
	399	memcpy(host->virt_base, src, data->sg->length);
	400	}
	401	}
	402
	403	static void goldfish_mmc_request(struct mmc_host mmc, struct mmc_request req)
	404	{
	405	struct goldfish_mmc_host *host = mmc_priv(mmc);
	406
	407	WARN_ON(host->mrq != NULL);
	408
	409	host->mrq = req;
	410	goldfish_mmc_prepare_data(host, req);
	411	goldfish_mmc_start_command(host, req->cmd);
	412
	413	/*
	414	* This is to avoid accidentally being detected as an SDIO card
	415	* in mmc_attach_sdio().
	416	*/
	417	if (req->cmd->opcode == SD_IO_SEND_OP_COND &&
	418	req->cmd->flags == (MMC_RSP_SPI_R4 \| MMC_RSP_R4 \| MMC_CMD_BCR))
	419	req->cmd->error = -EINVAL;
	420	}
	421
	422	static void goldfish_mmc_set_ios(struct mmc_host mmc, struct mmc_ios ios)
	423	{
	424	struct goldfish_mmc_host *host = mmc_priv(mmc);
	425
	426	host->bus_mode = ios->bus_mode;
	427	host->hw_bus_mode = host->bus_mode;
	428	}
	429
	430	static int goldfish_mmc_get_ro(struct mmc_host *mmc)
	431	{
	432	uint32_t state;
	433	struct goldfish_mmc_host *host = mmc_priv(mmc);
	434
	435	state = GOLDFISH_MMC_READ(host, MMC_STATE);
	436	return ((state & MMC_STATE_READ_ONLY) != 0);
	437	}
	438
	439	static const struct mmc_host_ops goldfish_mmc_ops = {
	440	.request = goldfish_mmc_request,
	441	.set_ios = goldfish_mmc_set_ios,
	442	.get_ro = goldfish_mmc_get_ro,
	443	};
	444
	445	static int goldfish_mmc_probe(struct platform_device *pdev)
	446	{
	447	struct mmc_host *mmc;
	448	struct goldfish_mmc_host *host = NULL;
	449	struct resource *res;
	450	int ret = 0;
451	int irq;
452	dma_addr_t buf_addr;
453
454	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
455	irq = platform_get_irq(pdev, 0);
456	if (res == NULL \|\| irq < 0)
457	return -ENXIO;
458
459	mmc = mmc_alloc_host(sizeof(struct goldfish_mmc_host), &pdev->dev);
460	if (mmc == NULL) {
461	ret = -ENOMEM;
462	goto err_alloc_host_failed;
463	}
464
465	host = mmc_priv(mmc);
466	host->mmc = mmc;
467
468	pr_err("mmc: Mapping %lX to %lX\n", (long)res->start, (long)res->end);
6a966e06	469	host->reg_base = ioremap(res->start, resource_size(res));
85c34d2e ML	470	if (host->reg_base == NULL) {
	471	ret = -ENOMEM;
	472	goto ioremap_failed;
	473	}
	474	host->virt_base = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
	475	&buf_addr, GFP_KERNEL);
	476
	477	if (host->virt_base == 0) {
	478	ret = -ENOMEM;
	479	goto dma_alloc_failed;
	480	}
	481	host->phys_base = buf_addr;
	482
	483	host->id = pdev->id;
	484	host->irq = irq;
	485
	486	mmc->ops = &goldfish_mmc_ops;
	487	mmc->f_min = 400000;
	488	mmc->f_max = 24000000;
	489	mmc->ocr_avail = MMC_VDD_32_33 \| MMC_VDD_33_34;
	490	mmc->caps = MMC_CAP_4_BIT_DATA;
	491
	492	/* Use scatterlist DMA to reduce per-transfer costs.
	493	* NOTE max_seg_size assumption that small blocks aren't
	494	* normally used (except e.g. for reading SD registers).
	495	*/
	496	mmc->max_segs = 32;
	497	mmc->max_blk_size = 2048; /* MMC_BLOCK_LENGTH is 11 bits (+1) */
	498	mmc->max_blk_count = 2048; /* MMC_BLOCK_COUNT is 11 bits (+1) */
	499	mmc->max_req_size = BUFFER_SIZE;
	500	mmc->max_seg_size = mmc->max_req_size;
	501
	502	ret = request_irq(host->irq, goldfish_mmc_irq, 0, DRIVER_NAME, host);
	503	if (ret) {
	504	dev_err(&pdev->dev, "Failed IRQ Adding goldfish MMC\n");
	505	goto err_request_irq_failed;
	506	}
	507
	508	host->dev = &pdev->dev;
	509	platform_set_drvdata(pdev, host);
	510
	511	ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
	512	if (ret)
	513	dev_warn(mmc_dev(host->mmc),
	514	"Unable to create sysfs attributes\n");
	515
	516	GOLDFISH_MMC_WRITE(host, MMC_SET_BUFFER, host->phys_base);
	517	GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE,
	518	MMC_STAT_END_OF_CMD \| MMC_STAT_END_OF_DATA \|
	519	MMC_STAT_STATE_CHANGE \| MMC_STAT_CMD_TIMEOUT);
	520
	521	mmc_add_host(mmc);
	522	return 0;
	523
	524	err_request_irq_failed:
	525	dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base,
	526	host->phys_base);
	527	dma_alloc_failed:
	528	iounmap(host->reg_base);
	529	ioremap_failed:
	530	mmc_free_host(host->mmc);
	531	err_alloc_host_failed:
	532	return ret;
	533	}
534
535	static int goldfish_mmc_remove(struct platform_device *pdev)
536	{
537	struct goldfish_mmc_host *host = platform_get_drvdata(pdev);
538
85c34d2e ML	539	BUG_ON(host == NULL);
	540
	541	mmc_remove_host(host->mmc);
	542	free_irq(host->irq, host);
	543	dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
	544	iounmap(host->reg_base);
	545	mmc_free_host(host->mmc);
	546	return 0;
	547	}
	548
	549	static struct platform_driver goldfish_mmc_driver = {
	550	.probe = goldfish_mmc_probe,
	551	.remove = goldfish_mmc_remove,
	552	.driver = {
	553	.name = DRIVER_NAME,
	554	},
	555	};
	556
	557	module_platform_driver(goldfish_mmc_driver);
	558	MODULE_LICENSE("GPL v2");