[linux-2.6-block.git] / drivers / mmc / host / android-goldfish.c

/*
 *  Copyright 2007, Google Inc.
 *  Copyright 2012, Intel Inc.
 *
 *  based on omap.c driver, which was
 *  Copyright (C) 2004 Nokia Corporation
 *  Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
 *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
 *  Other hacks (DMA, SD, etc) by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/major.h>

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/interrupt.h>

#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/hdreg.h>
#include <linux/kdev_t.h>
#include <linux/blkdev.h>
#include <linux/mutex.h>
#include <linux/scatterlist.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/host.h>
#include <linux/mmc/card.h>

#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/timer.h>
#include <linux/clk.h>

#include <asm/io.h>
#include <asm/irq.h>

#include <asm/types.h>
#include <linux/uaccess.h>

#define DRIVER_NAME "goldfish_mmc"

#define BUFFER_SIZE   16384

#define GOLDFISH_MMC_READ(host, addr)   (readl(host->reg_base + addr))
#define GOLDFISH_MMC_WRITE(host, addr, x)   (writel(x, host->reg_base + addr))

enum {
	/* status register */
	MMC_INT_STATUS	        = 0x00,
	/* set this to enable IRQ */
	MMC_INT_ENABLE	        = 0x04,
	/* set this to specify buffer address */
	MMC_SET_BUFFER          = 0x08,

	/* MMC command number */
	MMC_CMD	                = 0x0C,

	/* MMC argument */
	MMC_ARG	                = 0x10,

	/* MMC response (or R2 bits 0 - 31) */
	MMC_RESP_0		        = 0x14,

	/* MMC R2 response bits 32 - 63 */
	MMC_RESP_1		        = 0x18,

	/* MMC R2 response bits 64 - 95 */
	MMC_RESP_2		        = 0x1C,

	/* MMC R2 response bits 96 - 127 */
	MMC_RESP_3		        = 0x20,

	MMC_BLOCK_LENGTH        = 0x24,
	MMC_BLOCK_COUNT         = 0x28,

	/* MMC state flags */
	MMC_STATE               = 0x2C,

	/* MMC_INT_STATUS bits */

	MMC_STAT_END_OF_CMD     = 1U << 0,
	MMC_STAT_END_OF_DATA    = 1U << 1,
	MMC_STAT_STATE_CHANGE   = 1U << 2,
	MMC_STAT_CMD_TIMEOUT    = 1U << 3,

	/* MMC_STATE bits */
	MMC_STATE_INSERTED     = 1U << 0,
	MMC_STATE_READ_ONLY    = 1U << 1,
};

/*
 * Command types
 */
#define OMAP_MMC_CMDTYPE_BC	0
#define OMAP_MMC_CMDTYPE_BCR	1
#define OMAP_MMC_CMDTYPE_AC	2
#define OMAP_MMC_CMDTYPE_ADTC	3


struct goldfish_mmc_host {
	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;
	struct mmc_host		*mmc;
	struct device		*dev;
	unsigned char		id; /* 16xx chips have 2 MMC blocks */
	void			*virt_base;
	unsigned int		phys_base;
	int			irq;
	unsigned char		bus_mode;
	unsigned char		hw_bus_mode;

	unsigned int		sg_len;
	unsigned		dma_done:1;
	unsigned		dma_in_use:1;

	void __iomem		*reg_base;
};

static inline int
goldfish_mmc_cover_is_open(struct goldfish_mmc_host *host)
{
	return 0;
}

static ssize_t
goldfish_mmc_show_cover_switch(struct device *dev,
			       struct device_attribute *attr, char *buf)
{
	struct goldfish_mmc_host *host = dev_get_drvdata(dev);

	return sprintf(buf, "%s\n", goldfish_mmc_cover_is_open(host) ? "open" :
		       "closed");
}

static DEVICE_ATTR(cover_switch, S_IRUGO, goldfish_mmc_show_cover_switch, NULL);

static void
goldfish_mmc_start_command(struct goldfish_mmc_host *host, struct mmc_command *cmd)
{
	u32 cmdreg;
	u32 resptype;
	u32 cmdtype;

	host->cmd = cmd;

	resptype = 0;
	cmdtype = 0;

	/* Our hardware needs to know exact type */
	switch (mmc_resp_type(cmd)) {
	case MMC_RSP_NONE:
		break;
	case MMC_RSP_R1:
	case MMC_RSP_R1B:
		/* resp 1, 1b, 6, 7 */
		resptype = 1;
		break;
	case MMC_RSP_R2:
		resptype = 2;
		break;
	case MMC_RSP_R3:
		resptype = 3;
		break;
	default:
		dev_err(mmc_dev(host->mmc),
			"Invalid response type: %04x\n", mmc_resp_type(cmd));
		break;
	}

	if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
		cmdtype = OMAP_MMC_CMDTYPE_ADTC;
	else if (mmc_cmd_type(cmd) == MMC_CMD_BC)
		cmdtype = OMAP_MMC_CMDTYPE_BC;
	else if (mmc_cmd_type(cmd) == MMC_CMD_BCR)
		cmdtype = OMAP_MMC_CMDTYPE_BCR;
	else
		cmdtype = OMAP_MMC_CMDTYPE_AC;

	cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);

	if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
		cmdreg |= 1 << 6;

	if (cmd->flags & MMC_RSP_BUSY)
		cmdreg |= 1 << 11;

	if (host->data && !(host->data->flags & MMC_DATA_WRITE))
		cmdreg |= 1 << 15;

	GOLDFISH_MMC_WRITE(host, MMC_ARG, cmd->arg);
	GOLDFISH_MMC_WRITE(host, MMC_CMD, cmdreg);
}

static void goldfish_mmc_xfer_done(struct goldfish_mmc_host *host,
				   struct mmc_data *data)
{
	if (host->dma_in_use) {
		enum dma_data_direction dma_data_dir;

		dma_data_dir = mmc_get_dma_dir(data);

		if (dma_data_dir == DMA_FROM_DEVICE) {
			/*
			 * We don't really have DMA, so we need
			 * to copy from our platform driver buffer
			 */
			uint8_t *dest = (uint8_t *)sg_virt(data->sg);
			memcpy(dest, host->virt_base, data->sg->length);
		}
		host->data->bytes_xfered += data->sg->length;
		dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
			     dma_data_dir);
	}

	host->data = NULL;
	host->sg_len = 0;

	/*
	 * NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
	 * dozens of requests until the card finishes writing data.
	 * It'd be cheaper to just wait till an EOFB interrupt arrives...
	 */

	if (!data->stop) {
		host->mrq = NULL;
		mmc_request_done(host->mmc, data->mrq);
		return;
	}

	goldfish_mmc_start_command(host, data->stop);
}

static void goldfish_mmc_end_of_data(struct goldfish_mmc_host *host,
				     struct mmc_data *data)
{
	if (!host->dma_in_use) {
		goldfish_mmc_xfer_done(host, data);
		return;
	}
	if (host->dma_done)
		goldfish_mmc_xfer_done(host, data);
}

static void goldfish_mmc_cmd_done(struct goldfish_mmc_host *host,
				  struct mmc_command *cmd)
{
	host->cmd = NULL;
	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136) {
			/* response type 2 */
			cmd->resp[3] =
				GOLDFISH_MMC_READ(host, MMC_RESP_0);
			cmd->resp[2] =
				GOLDFISH_MMC_READ(host, MMC_RESP_1);
			cmd->resp[1] =
				GOLDFISH_MMC_READ(host, MMC_RESP_2);
			cmd->resp[0] =
				GOLDFISH_MMC_READ(host, MMC_RESP_3);
		} else {
			/* response types 1, 1b, 3, 4, 5, 6 */
			cmd->resp[0] =
				GOLDFISH_MMC_READ(host, MMC_RESP_0);
		}
	}

	if (host->data == NULL || cmd->error) {
		host->mrq = NULL;
		mmc_request_done(host->mmc, cmd->mrq);
	}
}

static irqreturn_t goldfish_mmc_irq(int irq, void *dev_id)
{
	struct goldfish_mmc_host *host = (struct goldfish_mmc_host *)dev_id;
	u16 status;
	int end_command = 0;
	int end_transfer = 0;
	int state_changed = 0;
	int cmd_timeout = 0;

	while ((status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS)) != 0) {
		GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);

		if (status & MMC_STAT_END_OF_CMD)
			end_command = 1;

		if (status & MMC_STAT_END_OF_DATA)
			end_transfer = 1;

		if (status & MMC_STAT_STATE_CHANGE)
			state_changed = 1;

                if (status & MMC_STAT_CMD_TIMEOUT) {
			end_command = 0;
			cmd_timeout = 1;
                }
	}

	if (cmd_timeout) {
		struct mmc_request *mrq = host->mrq;
		mrq->cmd->error = -ETIMEDOUT;
		host->mrq = NULL;
		mmc_request_done(host->mmc, mrq);
	}

	if (end_command)
		goldfish_mmc_cmd_done(host, host->cmd);

	if (end_transfer) {
		host->dma_done = 1;
		goldfish_mmc_end_of_data(host, host->data);
	} else if (host->data != NULL) {
		/*
		 * WORKAROUND -- after porting this driver from 2.6 to 3.4,
		 * during device initialization, cases where host->data is
		 * non-null but end_transfer is false would occur. Doing
		 * nothing in such cases results in no further interrupts,
		 * and initialization failure.
		 * TODO -- find the real cause.
		 */
		host->dma_done = 1;
		goldfish_mmc_end_of_data(host, host->data);
	}

	if (state_changed) {
		u32 state = GOLDFISH_MMC_READ(host, MMC_STATE);
		pr_info("%s: Card detect now %d\n", __func__,
			(state & MMC_STATE_INSERTED));
		mmc_detect_change(host->mmc, 0);
	}

	if (!end_command && !end_transfer && !state_changed && !cmd_timeout) {
		status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS);
		dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
		if (status != 0) {
			GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
			GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE, 0);
		}
	}

	return IRQ_HANDLED;
}

static void goldfish_mmc_prepare_data(struct goldfish_mmc_host *host,
				      struct mmc_request *req)
{
	struct mmc_data *data = req->data;
	int block_size;
	unsigned sg_len;
	enum dma_data_direction dma_data_dir;

	host->data = data;
	if (data == NULL) {
		GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, 0);
		GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, 0);
		host->dma_in_use = 0;
		return;
	}

	block_size = data->blksz;

	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, data->blocks - 1);
	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, block_size - 1);

	/*
	 * Cope with calling layer confusion; it issues "single
	 * block" writes using multi-block scatterlists.
	 */
	sg_len = (data->blocks == 1) ? 1 : data->sg_len;

	dma_data_dir = mmc_get_dma_dir(data);

	host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
				  sg_len, dma_data_dir);
	host->dma_done = 0;
	host->dma_in_use = 1;

	if (dma_data_dir == DMA_TO_DEVICE) {
		/*
		 * We don't really have DMA, so we need to copy to our
		 * platform driver buffer
		 */
		const uint8_t *src = (uint8_t *)sg_virt(data->sg);
		memcpy(host->virt_base, src, data->sg->length);
	}
}

static void goldfish_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
{
	struct goldfish_mmc_host *host = mmc_priv(mmc);

	WARN_ON(host->mrq != NULL);

	host->mrq = req;
	goldfish_mmc_prepare_data(host, req);
	goldfish_mmc_start_command(host, req->cmd);

	/*
	 * This is to avoid accidentally being detected as an SDIO card
	 * in mmc_attach_sdio().
	 */
	if (req->cmd->opcode == SD_IO_SEND_OP_COND &&
	    req->cmd->flags == (MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR))
		req->cmd->error = -EINVAL;
}

static void goldfish_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct goldfish_mmc_host *host = mmc_priv(mmc);

	host->bus_mode = ios->bus_mode;
	host->hw_bus_mode = host->bus_mode;
}

static int goldfish_mmc_get_ro(struct mmc_host *mmc)
{
	uint32_t state;
	struct goldfish_mmc_host *host = mmc_priv(mmc);

	state = GOLDFISH_MMC_READ(host, MMC_STATE);
	return ((state & MMC_STATE_READ_ONLY) != 0);
}

static const struct mmc_host_ops goldfish_mmc_ops = {
	.request	= goldfish_mmc_request,
	.set_ios	= goldfish_mmc_set_ios,
	.get_ro		= goldfish_mmc_get_ro,
};

static int goldfish_mmc_probe(struct platform_device *pdev)
{
	struct mmc_host *mmc;
	struct goldfish_mmc_host *host = NULL;
	struct resource *res;
	int ret = 0;
	int irq;
	dma_addr_t buf_addr;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
	if (res == NULL || irq < 0)
		return -ENXIO;

	mmc = mmc_alloc_host(sizeof(struct goldfish_mmc_host), &pdev->dev);
	if (mmc == NULL) {
		ret = -ENOMEM;
		goto err_alloc_host_failed;
	}

	host = mmc_priv(mmc);
	host->mmc = mmc;

	pr_err("mmc: Mapping %lX to %lX\n", (long)res->start, (long)res->end);
	host->reg_base = ioremap(res->start, resource_size(res));
	if (host->reg_base == NULL) {
		ret = -ENOMEM;
		goto ioremap_failed;
	}
	host->virt_base = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
					     &buf_addr, GFP_KERNEL);

	if (host->virt_base == 0) {
		ret = -ENOMEM;
		goto dma_alloc_failed;
	}
	host->phys_base = buf_addr;

	host->id = pdev->id;
	host->irq = irq;

	mmc->ops = &goldfish_mmc_ops;
	mmc->f_min = 400000;
	mmc->f_max = 24000000;
	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
	mmc->caps = MMC_CAP_4_BIT_DATA;

	/* Use scatterlist DMA to reduce per-transfer costs.
	 * NOTE max_seg_size assumption that small blocks aren't
	 * normally used (except e.g. for reading SD registers).
	 */
	mmc->max_segs = 32;
	mmc->max_blk_size = 2048;	/* MMC_BLOCK_LENGTH is 11 bits (+1) */
	mmc->max_blk_count = 2048;	/* MMC_BLOCK_COUNT is 11 bits (+1) */
	mmc->max_req_size = BUFFER_SIZE;
	mmc->max_seg_size = mmc->max_req_size;

	ret = request_irq(host->irq, goldfish_mmc_irq, 0, DRIVER_NAME, host);
	if (ret) {
		dev_err(&pdev->dev, "Failed IRQ Adding goldfish MMC\n");
		goto err_request_irq_failed;
	}

	host->dev = &pdev->dev;
	platform_set_drvdata(pdev, host);

	ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
	if (ret)
		dev_warn(mmc_dev(host->mmc),
			 "Unable to create sysfs attributes\n");

	GOLDFISH_MMC_WRITE(host, MMC_SET_BUFFER, host->phys_base);
	GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE,
			   MMC_STAT_END_OF_CMD | MMC_STAT_END_OF_DATA |
			   MMC_STAT_STATE_CHANGE | MMC_STAT_CMD_TIMEOUT);

	mmc_add_host(mmc);
	return 0;

err_request_irq_failed:
	dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base,
			  host->phys_base);
dma_alloc_failed:
	iounmap(host->reg_base);
ioremap_failed:
	mmc_free_host(host->mmc);
err_alloc_host_failed:
	return ret;
}

static int goldfish_mmc_remove(struct platform_device *pdev)
{
	struct goldfish_mmc_host *host = platform_get_drvdata(pdev);

	BUG_ON(host == NULL);

	mmc_remove_host(host->mmc);
	free_irq(host->irq, host);
	dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
	iounmap(host->reg_base);
	mmc_free_host(host->mmc);
	return 0;
}

static struct platform_driver goldfish_mmc_driver = {
	.probe		= goldfish_mmc_probe,
	.remove		= goldfish_mmc_remove,
	.driver		= {
		.name	= DRIVER_NAME,
	},
};

module_platform_driver(goldfish_mmc_driver);
MODULE_LICENSE("GPL v2");
Commit	Line	Data
85c34d2e ML	1	/*
	2	* Copyright 2007, Google Inc.
	3	* Copyright 2012, Intel Inc.
	4	*
	5	* based on omap.c driver, which was
	6	* Copyright (C) 2004 Nokia Corporation
	7	* Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
	8	* Misc hacks here and there by Tony Lindgren <tony@atomide.com>
	9	* Other hacks (DMA, SD, etc) by David Brownell
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/major.h>
	19
	20	#include <linux/types.h>
	21	#include <linux/pci.h>
	22	#include <linux/interrupt.h>
	23
	24	#include <linux/kernel.h>
	25	#include <linux/fs.h>
	26	#include <linux/errno.h>
	27	#include <linux/hdreg.h>
	28	#include <linux/kdev_t.h>
	29	#include <linux/blkdev.h>
	30	#include <linux/mutex.h>
	31	#include <linux/scatterlist.h>
	32	#include <linux/mmc/mmc.h>
	33	#include <linux/mmc/sdio.h>
	34	#include <linux/mmc/host.h>
	35	#include <linux/mmc/card.h>
	36
	37	#include <linux/moduleparam.h>
	38	#include <linux/init.h>
	39	#include <linux/ioport.h>
	40	#include <linux/dma-mapping.h>
	41	#include <linux/delay.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/timer.h>
	44	#include <linux/clk.h>
	45
	46	#include <asm/io.h>
	47	#include <asm/irq.h>
85c34d2e ML	48
85c34d2e ML	49	#include <asm/types.h>
7c0f6ba6	50	#include <linux/uaccess.h>
85c34d2e ML	51
	52	#define DRIVER_NAME "goldfish_mmc"
	53
	54	#define BUFFER_SIZE 16384
	55
	56	#define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr))
	57	#define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr))
	58
	59	enum {
	60	/* status register */
	61	MMC_INT_STATUS = 0x00,
	62	/* set this to enable IRQ */
	63	MMC_INT_ENABLE = 0x04,
	64	/* set this to specify buffer address */
	65	MMC_SET_BUFFER = 0x08,
	66
	67	/* MMC command number */
	68	MMC_CMD = 0x0C,
	69
	70	/* MMC argument */
	71	MMC_ARG = 0x10,
	72
	73	/* MMC response (or R2 bits 0 - 31) */
	74	MMC_RESP_0 = 0x14,
	75
	76	/* MMC R2 response bits 32 - 63 */
	77	MMC_RESP_1 = 0x18,
	78
	79	/* MMC R2 response bits 64 - 95 */
	80	MMC_RESP_2 = 0x1C,
	81
	82	/* MMC R2 response bits 96 - 127 */
	83	MMC_RESP_3 = 0x20,
	84
	85	MMC_BLOCK_LENGTH = 0x24,
	86	MMC_BLOCK_COUNT = 0x28,
	87
	88	/* MMC state flags */
	89	MMC_STATE = 0x2C,
	90
	91	/* MMC_INT_STATUS bits */
	92
	93	MMC_STAT_END_OF_CMD = 1U << 0,
	94	MMC_STAT_END_OF_DATA = 1U << 1,
	95	MMC_STAT_STATE_CHANGE = 1U << 2,
	96	MMC_STAT_CMD_TIMEOUT = 1U << 3,
	97
	98	/* MMC_STATE bits */
	99	MMC_STATE_INSERTED = 1U << 0,
	100	MMC_STATE_READ_ONLY = 1U << 1,
	101	};
	102
	103	/*
	104	* Command types
	105	*/
	106	#define OMAP_MMC_CMDTYPE_BC 0
	107	#define OMAP_MMC_CMDTYPE_BCR 1
	108	#define OMAP_MMC_CMDTYPE_AC 2
	109	#define OMAP_MMC_CMDTYPE_ADTC 3
	110
	111
	112	struct goldfish_mmc_host {
	113	struct mmc_request *mrq;
	114	struct mmc_command *cmd;
115	struct mmc_data *data;
116	struct mmc_host *mmc;
117	struct device *dev;
118	unsigned char id; /* 16xx chips have 2 MMC blocks */
092b6dbe	119	void *virt_base;
85c34d2e ML	120	unsigned int phys_base;
	121	int irq;
	122	unsigned char bus_mode;
	123	unsigned char hw_bus_mode;
	124
	125	unsigned int sg_len;
	126	unsigned dma_done:1;
	127	unsigned dma_in_use:1;
	128
	129	void __iomem *reg_base;
	130	};
	131
	132	static inline int
	133	goldfish_mmc_cover_is_open(struct goldfish_mmc_host *host)
	134	{
	135	return 0;
	136	}
	137
	138	static ssize_t
	139	goldfish_mmc_show_cover_switch(struct device *dev,
	140	struct device_attribute attr, char buf)
	141	{
	142	struct goldfish_mmc_host *host = dev_get_drvdata(dev);
	143
	144	return sprintf(buf, "%s\n", goldfish_mmc_cover_is_open(host) ? "open" :
	145	"closed");
	146	}
	147
	148	static DEVICE_ATTR(cover_switch, S_IRUGO, goldfish_mmc_show_cover_switch, NULL);
	149
	150	static void
	151	goldfish_mmc_start_command(struct goldfish_mmc_host host, struct mmc_command cmd)
	152	{
	153	u32 cmdreg;
	154	u32 resptype;
	155	u32 cmdtype;
	156
	157	host->cmd = cmd;
	158
	159	resptype = 0;
	160	cmdtype = 0;
	161
	162	/* Our hardware needs to know exact type */
	163	switch (mmc_resp_type(cmd)) {
	164	case MMC_RSP_NONE:
	165	break;
	166	case MMC_RSP_R1:
	167	case MMC_RSP_R1B:
	168	/* resp 1, 1b, 6, 7 */
	169	resptype = 1;
	170	break;
	171	case MMC_RSP_R2:
	172	resptype = 2;
	173	break;
	174	case MMC_RSP_R3:
	175	resptype = 3;
	176	break;
	177	default:
	178	dev_err(mmc_dev(host->mmc),
	179	"Invalid response type: %04x\n", mmc_resp_type(cmd));
	180	break;
	181	}
	182
	183	if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
184	cmdtype = OMAP_MMC_CMDTYPE_ADTC;
185	else if (mmc_cmd_type(cmd) == MMC_CMD_BC)
186	cmdtype = OMAP_MMC_CMDTYPE_BC;
187	else if (mmc_cmd_type(cmd) == MMC_CMD_BCR)
188	cmdtype = OMAP_MMC_CMDTYPE_BCR;
189	else
190	cmdtype = OMAP_MMC_CMDTYPE_AC;
191
192	cmdreg = cmd->opcode \| (resptype << 8) \| (cmdtype << 12);
193
194	if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
195	cmdreg \|= 1 << 6;
196
197	if (cmd->flags & MMC_RSP_BUSY)
198	cmdreg \|= 1 << 11;
199
200	if (host->data && !(host->data->flags & MMC_DATA_WRITE))
201	cmdreg \|= 1 << 15;
202
203	GOLDFISH_MMC_WRITE(host, MMC_ARG, cmd->arg);
204	GOLDFISH_MMC_WRITE(host, MMC_CMD, cmdreg);
205	}
206
207	static void goldfish_mmc_xfer_done(struct goldfish_mmc_host *host,
208	struct mmc_data *data)
209	{
210	if (host->dma_in_use) {
211	enum dma_data_direction dma_data_dir;
212
feeef096	213	dma_data_dir = mmc_get_dma_dir(data);
85c34d2e ML	214
	215	if (dma_data_dir == DMA_FROM_DEVICE) {
	216	/*
	217	* We don't really have DMA, so we need
	218	* to copy from our platform driver buffer
	219	*/
	220	uint8_t dest = (uint8_t )sg_virt(data->sg);
	221	memcpy(dest, host->virt_base, data->sg->length);
	222	}
	223	host->data->bytes_xfered += data->sg->length;
	224	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
	225	dma_data_dir);
	226	}
	227
	228	host->data = NULL;
	229	host->sg_len = 0;
	230
	231	/*
	232	* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
	233	* dozens of requests until the card finishes writing data.
	234	* It'd be cheaper to just wait till an EOFB interrupt arrives...
	235	*/
	236
	237	if (!data->stop) {
	238	host->mrq = NULL;
	239	mmc_request_done(host->mmc, data->mrq);
	240	return;
	241	}
	242
	243	goldfish_mmc_start_command(host, data->stop);
	244	}
	245
	246	static void goldfish_mmc_end_of_data(struct goldfish_mmc_host *host,
	247	struct mmc_data *data)
	248	{
	249	if (!host->dma_in_use) {
	250	goldfish_mmc_xfer_done(host, data);
	251	return;
	252	}
	253	if (host->dma_done)
	254	goldfish_mmc_xfer_done(host, data);
	255	}
	256
	257	static void goldfish_mmc_cmd_done(struct goldfish_mmc_host *host,
	258	struct mmc_command *cmd)
	259	{
	260	host->cmd = NULL;
	261	if (cmd->flags & MMC_RSP_PRESENT) {
	262	if (cmd->flags & MMC_RSP_136) {
	263	/* response type 2 */
	264	cmd->resp[3] =
	265	GOLDFISH_MMC_READ(host, MMC_RESP_0);
	266	cmd->resp[2] =
	267	GOLDFISH_MMC_READ(host, MMC_RESP_1);
	268	cmd->resp[1] =
	269	GOLDFISH_MMC_READ(host, MMC_RESP_2);
	270	cmd->resp[0] =
	271	GOLDFISH_MMC_READ(host, MMC_RESP_3);
	272	} else {
	273	/* response types 1, 1b, 3, 4, 5, 6 */
	274	cmd->resp[0] =
	275	GOLDFISH_MMC_READ(host, MMC_RESP_0);
	276	}
	277	}
278
279	if (host->data == NULL \|\| cmd->error) {
280	host->mrq = NULL;
281	mmc_request_done(host->mmc, cmd->mrq);
282	}
283	}
284
285	static irqreturn_t goldfish_mmc_irq(int irq, void *dev_id)
286	{
287	struct goldfish_mmc_host host = (struct goldfish_mmc_host )dev_id;
288	u16 status;
289	int end_command = 0;
290	int end_transfer = 0;
85c34d2e ML	291	int state_changed = 0;
	292	int cmd_timeout = 0;
	293
	294	while ((status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS)) != 0) {
	295	GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
	296
	297	if (status & MMC_STAT_END_OF_CMD)
	298	end_command = 1;
	299
	300	if (status & MMC_STAT_END_OF_DATA)
	301	end_transfer = 1;
	302
	303	if (status & MMC_STAT_STATE_CHANGE)
	304	state_changed = 1;
	305
	306	if (status & MMC_STAT_CMD_TIMEOUT) {
	307	end_command = 0;
	308	cmd_timeout = 1;
	309	}
	310	}
	311
	312	if (cmd_timeout) {
	313	struct mmc_request *mrq = host->mrq;
	314	mrq->cmd->error = -ETIMEDOUT;
	315	host->mrq = NULL;
	316	mmc_request_done(host->mmc, mrq);
	317	}
	318
	319	if (end_command)
	320	goldfish_mmc_cmd_done(host, host->cmd);
	321
0f77934a	322	if (end_transfer) {
85c34d2e ML	323	host->dma_done = 1;
	324	goldfish_mmc_end_of_data(host, host->data);
	325	} else if (host->data != NULL) {
	326	/*
	327	* WORKAROUND -- after porting this driver from 2.6 to 3.4,
	328	* during device initialization, cases where host->data is
	329	* non-null but end_transfer is false would occur. Doing
	330	* nothing in such cases results in no further interrupts,
	331	* and initialization failure.
	332	* TODO -- find the real cause.
	333	*/
	334	host->dma_done = 1;
	335	goldfish_mmc_end_of_data(host, host->data);
	336	}
	337
	338	if (state_changed) {
	339	u32 state = GOLDFISH_MMC_READ(host, MMC_STATE);
	340	pr_info("%s: Card detect now %d\n", __func__,
	341	(state & MMC_STATE_INSERTED));
	342	mmc_detect_change(host->mmc, 0);
	343	}
	344
0f77934a	345	if (!end_command && !end_transfer && !state_changed && !cmd_timeout) {
85c34d2e ML	346	status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS);
	347	dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
	348	if (status != 0) {
	349	GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
	350	GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE, 0);
	351	}
	352	}
	353
	354	return IRQ_HANDLED;
	355	}
	356
	357	static void goldfish_mmc_prepare_data(struct goldfish_mmc_host *host,
	358	struct mmc_request *req)
	359	{
	360	struct mmc_data *data = req->data;
	361	int block_size;
	362	unsigned sg_len;
	363	enum dma_data_direction dma_data_dir;
	364
	365	host->data = data;
	366	if (data == NULL) {
	367	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, 0);
	368	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, 0);
	369	host->dma_in_use = 0;
	370	return;
	371	}
	372
	373	block_size = data->blksz;
	374
	375	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, data->blocks - 1);
	376	GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, block_size - 1);
	377
	378	/*
	379	* Cope with calling layer confusion; it issues "single
	380	* block" writes using multi-block scatterlists.
	381	*/
	382	sg_len = (data->blocks == 1) ? 1 : data->sg_len;
	383
feeef096	384	dma_data_dir = mmc_get_dma_dir(data);
85c34d2e ML	385
	386	host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
	387	sg_len, dma_data_dir);
	388	host->dma_done = 0;
	389	host->dma_in_use = 1;
	390
	391	if (dma_data_dir == DMA_TO_DEVICE) {
	392	/*
	393	* We don't really have DMA, so we need to copy to our
	394	* platform driver buffer
	395	*/
	396	const uint8_t src = (uint8_t )sg_virt(data->sg);
	397	memcpy(host->virt_base, src, data->sg->length);
	398	}
	399	}
	400
	401	static void goldfish_mmc_request(struct mmc_host mmc, struct mmc_request req)
	402	{
	403	struct goldfish_mmc_host *host = mmc_priv(mmc);
	404
	405	WARN_ON(host->mrq != NULL);
	406
	407	host->mrq = req;
	408	goldfish_mmc_prepare_data(host, req);
	409	goldfish_mmc_start_command(host, req->cmd);
	410
	411	/*
	412	* This is to avoid accidentally being detected as an SDIO card
	413	* in mmc_attach_sdio().
	414	*/
	415	if (req->cmd->opcode == SD_IO_SEND_OP_COND &&
	416	req->cmd->flags == (MMC_RSP_SPI_R4 \| MMC_RSP_R4 \| MMC_CMD_BCR))
	417	req->cmd->error = -EINVAL;
	418	}
	419
	420	static void goldfish_mmc_set_ios(struct mmc_host mmc, struct mmc_ios ios)
	421	{
	422	struct goldfish_mmc_host *host = mmc_priv(mmc);
	423
	424	host->bus_mode = ios->bus_mode;
	425	host->hw_bus_mode = host->bus_mode;
	426	}
	427
	428	static int goldfish_mmc_get_ro(struct mmc_host *mmc)
	429	{
	430	uint32_t state;
	431	struct goldfish_mmc_host *host = mmc_priv(mmc);
	432
	433	state = GOLDFISH_MMC_READ(host, MMC_STATE);
	434	return ((state & MMC_STATE_READ_ONLY) != 0);
	435	}
	436
	437	static const struct mmc_host_ops goldfish_mmc_ops = {
	438	.request = goldfish_mmc_request,
	439	.set_ios = goldfish_mmc_set_ios,
	440	.get_ro = goldfish_mmc_get_ro,
	441	};
	442
	443	static int goldfish_mmc_probe(struct platform_device *pdev)
	444	{
	445	struct mmc_host *mmc;
	446	struct goldfish_mmc_host *host = NULL;
	447	struct resource *res;
	448	int ret = 0;
449	int irq;
450	dma_addr_t buf_addr;
451
452	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
453	irq = platform_get_irq(pdev, 0);
454	if (res == NULL \|\| irq < 0)
455	return -ENXIO;
456
457	mmc = mmc_alloc_host(sizeof(struct goldfish_mmc_host), &pdev->dev);
458	if (mmc == NULL) {
459	ret = -ENOMEM;
460	goto err_alloc_host_failed;
461	}
462
463	host = mmc_priv(mmc);
464	host->mmc = mmc;
465
466	pr_err("mmc: Mapping %lX to %lX\n", (long)res->start, (long)res->end);
6a966e06	467	host->reg_base = ioremap(res->start, resource_size(res));
85c34d2e ML	468	if (host->reg_base == NULL) {
	469	ret = -ENOMEM;
	470	goto ioremap_failed;
	471	}
	472	host->virt_base = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
	473	&buf_addr, GFP_KERNEL);
	474
	475	if (host->virt_base == 0) {
	476	ret = -ENOMEM;
	477	goto dma_alloc_failed;
	478	}
	479	host->phys_base = buf_addr;
	480
	481	host->id = pdev->id;
	482	host->irq = irq;
	483
	484	mmc->ops = &goldfish_mmc_ops;
	485	mmc->f_min = 400000;
	486	mmc->f_max = 24000000;
	487	mmc->ocr_avail = MMC_VDD_32_33 \| MMC_VDD_33_34;
	488	mmc->caps = MMC_CAP_4_BIT_DATA;
	489
	490	/* Use scatterlist DMA to reduce per-transfer costs.
	491	* NOTE max_seg_size assumption that small blocks aren't
	492	* normally used (except e.g. for reading SD registers).
	493	*/
	494	mmc->max_segs = 32;
	495	mmc->max_blk_size = 2048; /* MMC_BLOCK_LENGTH is 11 bits (+1) */
	496	mmc->max_blk_count = 2048; /* MMC_BLOCK_COUNT is 11 bits (+1) */
	497	mmc->max_req_size = BUFFER_SIZE;
	498	mmc->max_seg_size = mmc->max_req_size;
	499
	500	ret = request_irq(host->irq, goldfish_mmc_irq, 0, DRIVER_NAME, host);
	501	if (ret) {
	502	dev_err(&pdev->dev, "Failed IRQ Adding goldfish MMC\n");
	503	goto err_request_irq_failed;
	504	}
	505
	506	host->dev = &pdev->dev;
	507	platform_set_drvdata(pdev, host);
	508
	509	ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
	510	if (ret)
	511	dev_warn(mmc_dev(host->mmc),
	512	"Unable to create sysfs attributes\n");
	513
	514	GOLDFISH_MMC_WRITE(host, MMC_SET_BUFFER, host->phys_base);
	515	GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE,
	516	MMC_STAT_END_OF_CMD \| MMC_STAT_END_OF_DATA \|
	517	MMC_STAT_STATE_CHANGE \| MMC_STAT_CMD_TIMEOUT);
	518
	519	mmc_add_host(mmc);
	520	return 0;
	521
	522	err_request_irq_failed:
	523	dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base,
	524	host->phys_base);
	525	dma_alloc_failed:
	526	iounmap(host->reg_base);
	527	ioremap_failed:
	528	mmc_free_host(host->mmc);
	529	err_alloc_host_failed:
	530	return ret;
	531	}
532
533	static int goldfish_mmc_remove(struct platform_device *pdev)
534	{
535	struct goldfish_mmc_host *host = platform_get_drvdata(pdev);
536
85c34d2e ML	537	BUG_ON(host == NULL);
	538
	539	mmc_remove_host(host->mmc);
	540	free_irq(host->irq, host);
	541	dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
	542	iounmap(host->reg_base);
	543	mmc_free_host(host->mmc);
	544	return 0;
	545	}
	546
	547	static struct platform_driver goldfish_mmc_driver = {
	548	.probe = goldfish_mmc_probe,
	549	.remove = goldfish_mmc_remove,
	550	.driver = {
	551	.name = DRIVER_NAME,
	552	},
	553	};
	554
	555	module_platform_driver(goldfish_mmc_driver);
	556	MODULE_LICENSE("GPL v2");