[linux-2.6-block.git] / drivers / misc / pci_endpoint_test.c

/**
 * Host side test driver to test endpoint functionality
 *
 * Copyright (C) 2017 Texas Instruments
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 of
 * the License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/crc32.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/random.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>

#include <linux/pci_regs.h>

#include <uapi/linux/pcitest.h>

#define DRV_MODULE_NAME				"pci-endpoint-test"

#define IRQ_TYPE_LEGACY				0
#define IRQ_TYPE_MSI				1

#define PCI_ENDPOINT_TEST_MAGIC			0x0

#define PCI_ENDPOINT_TEST_COMMAND		0x4
#define COMMAND_RAISE_LEGACY_IRQ		BIT(0)
#define COMMAND_RAISE_MSI_IRQ			BIT(1)
/* BIT(2) is reserved for raising MSI-X IRQ command */
#define COMMAND_READ				BIT(3)
#define COMMAND_WRITE				BIT(4)
#define COMMAND_COPY				BIT(5)

#define PCI_ENDPOINT_TEST_STATUS		0x8
#define STATUS_READ_SUCCESS			BIT(0)
#define STATUS_READ_FAIL			BIT(1)
#define STATUS_WRITE_SUCCESS			BIT(2)
#define STATUS_WRITE_FAIL			BIT(3)
#define STATUS_COPY_SUCCESS			BIT(4)
#define STATUS_COPY_FAIL			BIT(5)
#define STATUS_IRQ_RAISED			BIT(6)
#define STATUS_SRC_ADDR_INVALID			BIT(7)
#define STATUS_DST_ADDR_INVALID			BIT(8)

#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR	0x0c
#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR	0x10

#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR	0x14
#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR	0x18

#define PCI_ENDPOINT_TEST_SIZE			0x1c
#define PCI_ENDPOINT_TEST_CHECKSUM		0x20

#define PCI_ENDPOINT_TEST_IRQ_TYPE		0x24
#define PCI_ENDPOINT_TEST_IRQ_NUMBER		0x28

static DEFINE_IDA(pci_endpoint_test_ida);

#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
					    miscdev)

static bool no_msi;
module_param(no_msi, bool, 0444);
MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");

enum pci_barno {
	BAR_0,
	BAR_1,
	BAR_2,
	BAR_3,
	BAR_4,
	BAR_5,
};

struct pci_endpoint_test {
	struct pci_dev	*pdev;
	void __iomem	*base;
	void __iomem	*bar[6];
	struct completion irq_raised;
	int		last_irq;
	int		num_irqs;
	/* mutex to protect the ioctls */
	struct mutex	mutex;
	struct miscdevice miscdev;
	enum pci_barno test_reg_bar;
	size_t alignment;
};

struct pci_endpoint_test_data {
	enum pci_barno test_reg_bar;
	size_t alignment;
	bool no_msi;
};

static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
					  u32 offset)
{
	return readl(test->base + offset);
}

static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
					    u32 offset, u32 value)
{
	writel(value, test->base + offset);
}

static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
					      int bar, int offset)
{
	return readl(test->bar[bar] + offset);
}

static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
						int bar, u32 offset, u32 value)
{
	writel(value, test->bar[bar] + offset);
}

static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
{
	struct pci_endpoint_test *test = dev_id;
	u32 reg;

	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
	if (reg & STATUS_IRQ_RAISED) {
		test->last_irq = irq;
		complete(&test->irq_raised);
		reg &= ~STATUS_IRQ_RAISED;
	}
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
				 reg);

	return IRQ_HANDLED;
}

static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
				  enum pci_barno barno)
{
	int j;
	u32 val;
	int size;
	struct pci_dev *pdev = test->pdev;

	if (!test->bar[barno])
		return false;

	size = pci_resource_len(pdev, barno);

	if (barno == test->test_reg_bar)
		size = 0x4;

	for (j = 0; j < size; j += 4)
		pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);

	for (j = 0; j < size; j += 4) {
		val = pci_endpoint_test_bar_readl(test, barno, j);
		if (val != 0xA0A0A0A0)
			return false;
	}

	return true;
}

static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
{
	u32 val;

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
				 IRQ_TYPE_LEGACY);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 COMMAND_RAISE_LEGACY_IRQ);
	val = wait_for_completion_timeout(&test->irq_raised,
					  msecs_to_jiffies(1000));
	if (!val)
		return false;

	return true;
}

static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
				      u8 msi_num)
{
	u32 val;
	struct pci_dev *pdev = test->pdev;

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
				 IRQ_TYPE_MSI);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 COMMAND_RAISE_MSI_IRQ);
	val = wait_for_completion_timeout(&test->irq_raised,
					  msecs_to_jiffies(1000));
	if (!val)
		return false;

	if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
		return true;

	return false;
}

static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
{
	bool ret = false;
	void *src_addr;
	void *dst_addr;
	dma_addr_t src_phys_addr;
	dma_addr_t dst_phys_addr;
	struct pci_dev *pdev = test->pdev;
	struct device *dev = &pdev->dev;
	void *orig_src_addr;
	dma_addr_t orig_src_phys_addr;
	void *orig_dst_addr;
	dma_addr_t orig_dst_phys_addr;
	size_t offset;
	size_t alignment = test->alignment;
	u32 src_crc32;
	u32 dst_crc32;

	if (size > SIZE_MAX - alignment)
		goto err;

	orig_src_addr = dma_alloc_coherent(dev, size + alignment,
					   &orig_src_phys_addr, GFP_KERNEL);
	if (!orig_src_addr) {
		dev_err(dev, "Failed to allocate source buffer\n");
		ret = false;
		goto err;
	}

	if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
		src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
		offset = src_phys_addr - orig_src_phys_addr;
		src_addr = orig_src_addr + offset;
	} else {
		src_phys_addr = orig_src_phys_addr;
		src_addr = orig_src_addr;
	}

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
				 lower_32_bits(src_phys_addr));

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
				 upper_32_bits(src_phys_addr));

	get_random_bytes(src_addr, size);
	src_crc32 = crc32_le(~0, src_addr, size);

	orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
					   &orig_dst_phys_addr, GFP_KERNEL);
	if (!orig_dst_addr) {
		dev_err(dev, "Failed to allocate destination address\n");
		ret = false;
		goto err_orig_src_addr;
	}

	if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
		dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
		offset = dst_phys_addr - orig_dst_phys_addr;
		dst_addr = orig_dst_addr + offset;
	} else {
		dst_phys_addr = orig_dst_phys_addr;
		dst_addr = orig_dst_addr;
	}

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
				 lower_32_bits(dst_phys_addr));
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
				 upper_32_bits(dst_phys_addr));

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
				 size);

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
				 no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 COMMAND_COPY);

	wait_for_completion(&test->irq_raised);

	dst_crc32 = crc32_le(~0, dst_addr, size);
	if (dst_crc32 == src_crc32)
		ret = true;

	dma_free_coherent(dev, size + alignment, orig_dst_addr,
			  orig_dst_phys_addr);

err_orig_src_addr:
	dma_free_coherent(dev, size + alignment, orig_src_addr,
			  orig_src_phys_addr);

err:
	return ret;
}

static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
{
	bool ret = false;
	u32 reg;
	void *addr;
	dma_addr_t phys_addr;
	struct pci_dev *pdev = test->pdev;
	struct device *dev = &pdev->dev;
	void *orig_addr;
	dma_addr_t orig_phys_addr;
	size_t offset;
	size_t alignment = test->alignment;
	u32 crc32;

	if (size > SIZE_MAX - alignment)
		goto err;

	orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
				       GFP_KERNEL);
	if (!orig_addr) {
		dev_err(dev, "Failed to allocate address\n");
		ret = false;
		goto err;
	}

	if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
		phys_addr =  PTR_ALIGN(orig_phys_addr, alignment);
		offset = phys_addr - orig_phys_addr;
		addr = orig_addr + offset;
	} else {
		phys_addr = orig_phys_addr;
		addr = orig_addr;
	}

	get_random_bytes(addr, size);

	crc32 = crc32_le(~0, addr, size);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
				 crc32);

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
				 lower_32_bits(phys_addr));
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
				 upper_32_bits(phys_addr));

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
				 no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 COMMAND_READ);

	wait_for_completion(&test->irq_raised);

	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
	if (reg & STATUS_READ_SUCCESS)
		ret = true;

	dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);

err:
	return ret;
}

static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
{
	bool ret = false;
	void *addr;
	dma_addr_t phys_addr;
	struct pci_dev *pdev = test->pdev;
	struct device *dev = &pdev->dev;
	void *orig_addr;
	dma_addr_t orig_phys_addr;
	size_t offset;
	size_t alignment = test->alignment;
	u32 crc32;

	if (size > SIZE_MAX - alignment)
		goto err;

	orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
				       GFP_KERNEL);
	if (!orig_addr) {
		dev_err(dev, "Failed to allocate destination address\n");
		ret = false;
		goto err;
	}

	if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
		phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
		offset = phys_addr - orig_phys_addr;
		addr = orig_addr + offset;
	} else {
		phys_addr = orig_phys_addr;
		addr = orig_addr;
	}

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
				 lower_32_bits(phys_addr));
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
				 upper_32_bits(phys_addr));

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
				 no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 COMMAND_WRITE);

	wait_for_completion(&test->irq_raised);

	crc32 = crc32_le(~0, addr, size);
	if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
		ret = true;

	dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
err:
	return ret;
}

static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
				    unsigned long arg)
{
	int ret = -EINVAL;
	enum pci_barno bar;
	struct pci_endpoint_test *test = to_endpoint_test(file->private_data);

	mutex_lock(&test->mutex);
	switch (cmd) {
	case PCITEST_BAR:
		bar = arg;
		if (bar < 0 || bar > 5)
			goto ret;
		ret = pci_endpoint_test_bar(test, bar);
		break;
	case PCITEST_LEGACY_IRQ:
		ret = pci_endpoint_test_legacy_irq(test);
		break;
	case PCITEST_MSI:
		ret = pci_endpoint_test_msi_irq(test, arg);
		break;
	case PCITEST_WRITE:
		ret = pci_endpoint_test_write(test, arg);
		break;
	case PCITEST_READ:
		ret = pci_endpoint_test_read(test, arg);
		break;
	case PCITEST_COPY:
		ret = pci_endpoint_test_copy(test, arg);
		break;
	}

ret:
	mutex_unlock(&test->mutex);
	return ret;
}

static const struct file_operations pci_endpoint_test_fops = {
	.owner = THIS_MODULE,
	.unlocked_ioctl = pci_endpoint_test_ioctl,
};

static int pci_endpoint_test_probe(struct pci_dev *pdev,
				   const struct pci_device_id *ent)
{
	int i;
	int err;
	int irq = 0;
	int id;
	char name[20];
	enum pci_barno bar;
	void __iomem *base;
	struct device *dev = &pdev->dev;
	struct pci_endpoint_test *test;
	struct pci_endpoint_test_data *data;
	enum pci_barno test_reg_bar = BAR_0;
	struct miscdevice *misc_device;

	if (pci_is_bridge(pdev))
		return -ENODEV;

	test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
	if (!test)
		return -ENOMEM;

	test->test_reg_bar = 0;
	test->alignment = 0;
	test->pdev = pdev;

	data = (struct pci_endpoint_test_data *)ent->driver_data;
	if (data) {
		test_reg_bar = data->test_reg_bar;
		test->alignment = data->alignment;
		no_msi = data->no_msi;
	}

	init_completion(&test->irq_raised);
	mutex_init(&test->mutex);

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(dev, "Cannot enable PCI device\n");
		return err;
	}

	err = pci_request_regions(pdev, DRV_MODULE_NAME);
	if (err) {
		dev_err(dev, "Cannot obtain PCI resources\n");
		goto err_disable_pdev;
	}

	pci_set_master(pdev);

	if (!no_msi) {
		irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
		if (irq < 0)
			dev_err(dev, "Failed to get MSI interrupts\n");
		test->num_irqs = irq;
	}

	err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
			       IRQF_SHARED, DRV_MODULE_NAME, test);
	if (err) {
		dev_err(dev, "Failed to request IRQ %d\n", pdev->irq);
		goto err_disable_msi;
	}

	for (i = 1; i < irq; i++) {
		err = devm_request_irq(dev, pci_irq_vector(pdev, i),
				       pci_endpoint_test_irqhandler,
				       IRQF_SHARED, DRV_MODULE_NAME, test);
		if (err)
			dev_err(dev, "failed to request IRQ %d for MSI %d\n",
				pci_irq_vector(pdev, i), i + 1);
	}

	for (bar = BAR_0; bar <= BAR_5; bar++) {
		if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
			base = pci_ioremap_bar(pdev, bar);
			if (!base) {
				dev_err(dev, "Failed to read BAR%d\n", bar);
				WARN_ON(bar == test_reg_bar);
			}
			test->bar[bar] = base;
		}
	}

	test->base = test->bar[test_reg_bar];
	if (!test->base) {
		err = -ENOMEM;
		dev_err(dev, "Cannot perform PCI test without BAR%d\n",
			test_reg_bar);
		goto err_iounmap;
	}

	pci_set_drvdata(pdev, test);

	id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
	if (id < 0) {
		err = id;
		dev_err(dev, "Unable to get id\n");
		goto err_iounmap;
	}

	snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
	misc_device = &test->miscdev;
	misc_device->minor = MISC_DYNAMIC_MINOR;
	misc_device->name = kstrdup(name, GFP_KERNEL);
	if (!misc_device->name) {
		err = -ENOMEM;
		goto err_ida_remove;
	}
	misc_device->fops = &pci_endpoint_test_fops,

	err = misc_register(misc_device);
	if (err) {
		dev_err(dev, "Failed to register device\n");
		goto err_kfree_name;
	}

	return 0;

err_kfree_name:
	kfree(misc_device->name);

err_ida_remove:
	ida_simple_remove(&pci_endpoint_test_ida, id);

err_iounmap:
	for (bar = BAR_0; bar <= BAR_5; bar++) {
		if (test->bar[bar])
			pci_iounmap(pdev, test->bar[bar]);
	}

	for (i = 0; i < irq; i++)
		devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), test);

err_disable_msi:
	pci_disable_msi(pdev);
	pci_release_regions(pdev);

err_disable_pdev:
	pci_disable_device(pdev);

	return err;
}

static void pci_endpoint_test_remove(struct pci_dev *pdev)
{
	int id;
	int i;
	enum pci_barno bar;
	struct pci_endpoint_test *test = pci_get_drvdata(pdev);
	struct miscdevice *misc_device = &test->miscdev;

	if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
		return;
	if (id < 0)
		return;

	misc_deregister(&test->miscdev);
	kfree(misc_device->name);
	ida_simple_remove(&pci_endpoint_test_ida, id);
	for (bar = BAR_0; bar <= BAR_5; bar++) {
		if (test->bar[bar])
			pci_iounmap(pdev, test->bar[bar]);
	}
	for (i = 0; i < test->num_irqs; i++)
		devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), test);
	pci_disable_msi(pdev);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
}

static const struct pci_device_id pci_endpoint_test_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },
	{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);

static struct pci_driver pci_endpoint_test_driver = {
	.name		= DRV_MODULE_NAME,
	.id_table	= pci_endpoint_test_tbl,
	.probe		= pci_endpoint_test_probe,
	.remove		= pci_endpoint_test_remove,
};
module_pci_driver(pci_endpoint_test_driver);

MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2c156ac7 KVA	1	/**
	2	* Host side test driver to test endpoint functionality
	3	*
	4	* Copyright (C) 2017 Texas Instruments
	5	* Author: Kishon Vijay Abraham I <kishon@ti.com>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 of
	9	* the License as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/crc32.h>
	21	#include <linux/delay.h>
	22	#include <linux/fs.h>
	23	#include <linux/io.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/miscdevice.h>
	27	#include <linux/module.h>
	28	#include <linux/mutex.h>
	29	#include <linux/random.h>
	30	#include <linux/slab.h>
	31	#include <linux/pci.h>
	32	#include <linux/pci_ids.h>
	33
	34	#include <linux/pci_regs.h>
	35
	36	#include <uapi/linux/pcitest.h>
	37
e8817de7 GP	38	#define DRV_MODULE_NAME "pci-endpoint-test"
	39
	40	#define IRQ_TYPE_LEGACY 0
	41	#define IRQ_TYPE_MSI 1
	42
	43	#define PCI_ENDPOINT_TEST_MAGIC 0x0
	44
	45	#define PCI_ENDPOINT_TEST_COMMAND 0x4
	46	#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
	47	#define COMMAND_RAISE_MSI_IRQ BIT(1)
	48	/* BIT(2) is reserved for raising MSI-X IRQ command */
	49	#define COMMAND_READ BIT(3)
	50	#define COMMAND_WRITE BIT(4)
	51	#define COMMAND_COPY BIT(5)
	52
	53	#define PCI_ENDPOINT_TEST_STATUS 0x8
	54	#define STATUS_READ_SUCCESS BIT(0)
	55	#define STATUS_READ_FAIL BIT(1)
	56	#define STATUS_WRITE_SUCCESS BIT(2)
	57	#define STATUS_WRITE_FAIL BIT(3)
	58	#define STATUS_COPY_SUCCESS BIT(4)
	59	#define STATUS_COPY_FAIL BIT(5)
	60	#define STATUS_IRQ_RAISED BIT(6)
	61	#define STATUS_SRC_ADDR_INVALID BIT(7)
	62	#define STATUS_DST_ADDR_INVALID BIT(8)
	63
	64	#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
2c156ac7 KVA	65	#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
	66
	67	#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
	68	#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
	69
e8817de7 GP	70	#define PCI_ENDPOINT_TEST_SIZE 0x1c
	71	#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
	72
	73	#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
	74	#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
2c156ac7 KVA	75
	76	static DEFINE_IDA(pci_endpoint_test_ida);
	77
	78	#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
	79	miscdev)
0c8a5f9d KVA	80
	81	static bool no_msi;
	82	module_param(no_msi, bool, 0444);
	83	MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
	84
2c156ac7 KVA	85	enum pci_barno {
	86	BAR_0,
	87	BAR_1,
	88	BAR_2,
	89	BAR_3,
	90	BAR_4,
	91	BAR_5,
	92	};
	93
	94	struct pci_endpoint_test {
	95	struct pci_dev *pdev;
	96	void __iomem *base;
	97	void __iomem *bar[6];
	98	struct completion irq_raised;
	99	int last_irq;
b7636e81	100	int num_irqs;
2c156ac7 KVA	101	/* mutex to protect the ioctls */
	102	struct mutex mutex;
	103	struct miscdevice miscdev;
834b9051	104	enum pci_barno test_reg_bar;
13107c60	105	size_t alignment;
2c156ac7 KVA	106	};
2c156ac7 KVA	107
834b9051 KVA	108	struct pci_endpoint_test_data {
834b9051 KVA	109	enum pci_barno test_reg_bar;
13107c60	110	size_t alignment;
0b91516a	111	bool no_msi;
834b9051 KVA	112	};
834b9051 KVA	113
2c156ac7 KVA	114	static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
	115	u32 offset)
	116	{
	117	return readl(test->base + offset);
	118	}
	119
	120	static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
	121	u32 offset, u32 value)
	122	{
	123	writel(value, test->base + offset);
	124	}
	125
	126	static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
	127	int bar, int offset)
	128	{
	129	return readl(test->bar[bar] + offset);
	130	}
	131
	132	static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
	133	int bar, u32 offset, u32 value)
	134	{
	135	writel(value, test->bar[bar] + offset);
	136	}
	137
	138	static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
	139	{
	140	struct pci_endpoint_test *test = dev_id;
	141	u32 reg;
	142
	143	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
	144	if (reg & STATUS_IRQ_RAISED) {
	145	test->last_irq = irq;
	146	complete(&test->irq_raised);
	147	reg &= ~STATUS_IRQ_RAISED;
	148	}
	149	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
	150	reg);
	151
	152	return IRQ_HANDLED;
	153	}
	154
	155	static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
	156	enum pci_barno barno)
	157	{
	158	int j;
	159	u32 val;
	160	int size;
cda370ec	161	struct pci_dev *pdev = test->pdev;
2c156ac7 KVA	162
	163	if (!test->bar[barno])
	164	return false;
	165
cda370ec	166	size = pci_resource_len(pdev, barno);
2c156ac7	167
834b9051 KVA	168	if (barno == test->test_reg_bar)
	169	size = 0x4;
	170
2c156ac7 KVA	171	for (j = 0; j < size; j += 4)
	172	pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
	173
	174	for (j = 0; j < size; j += 4) {
	175	val = pci_endpoint_test_bar_readl(test, barno, j);
	176	if (val != 0xA0A0A0A0)
	177	return false;
	178	}
	179
	180	return true;
	181	}
	182
	183	static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
	184	{
	185	u32 val;
	186
e8817de7 GP	187	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
	188	IRQ_TYPE_LEGACY);
	189	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
2c156ac7 KVA	190	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
	191	COMMAND_RAISE_LEGACY_IRQ);
	192	val = wait_for_completion_timeout(&test->irq_raised,
	193	msecs_to_jiffies(1000));
	194	if (!val)
	195	return false;
	196
	197	return true;
	198	}
	199
	200	static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
	201	u8 msi_num)
	202	{
	203	u32 val;
	204	struct pci_dev *pdev = test->pdev;
	205
e8817de7 GP	206	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
	207	IRQ_TYPE_MSI);
	208	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
2c156ac7	209	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
2c156ac7 KVA	210	COMMAND_RAISE_MSI_IRQ);
	211	val = wait_for_completion_timeout(&test->irq_raised,
	212	msecs_to_jiffies(1000));
	213	if (!val)
	214	return false;
	215
ecc57efe	216	if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
2c156ac7 KVA	217	return true;
	218
	219	return false;
	220	}
	221
	222	static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
	223	{
	224	bool ret = false;
	225	void *src_addr;
	226	void *dst_addr;
	227	dma_addr_t src_phys_addr;
	228	dma_addr_t dst_phys_addr;
	229	struct pci_dev *pdev = test->pdev;
	230	struct device *dev = &pdev->dev;
13107c60 KVA	231	void *orig_src_addr;
	232	dma_addr_t orig_src_phys_addr;
	233	void *orig_dst_addr;
	234	dma_addr_t orig_dst_phys_addr;
	235	size_t offset;
	236	size_t alignment = test->alignment;
2c156ac7 KVA	237	u32 src_crc32;
	238	u32 dst_crc32;
	239
343dc693 DC	240	if (size > SIZE_MAX - alignment)
	241	goto err;
	242
13107c60 KVA	243	orig_src_addr = dma_alloc_coherent(dev, size + alignment,
	244	&orig_src_phys_addr, GFP_KERNEL);
	245	if (!orig_src_addr) {
0e52ea61	246	dev_err(dev, "Failed to allocate source buffer\n");
2c156ac7 KVA	247	ret = false;
	248	goto err;
	249	}
	250
13107c60 KVA	251	if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
	252	src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
	253	offset = src_phys_addr - orig_src_phys_addr;
	254	src_addr = orig_src_addr + offset;
	255	} else {
	256	src_phys_addr = orig_src_phys_addr;
	257	src_addr = orig_src_addr;
	258	}
	259
2c156ac7 KVA	260	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
	261	lower_32_bits(src_phys_addr));
	262
	263	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
	264	upper_32_bits(src_phys_addr));
	265
	266	get_random_bytes(src_addr, size);
	267	src_crc32 = crc32_le(~0, src_addr, size);
	268
13107c60 KVA	269	orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
	270	&orig_dst_phys_addr, GFP_KERNEL);
	271	if (!orig_dst_addr) {
0e52ea61	272	dev_err(dev, "Failed to allocate destination address\n");
2c156ac7	273	ret = false;
13107c60 KVA	274	goto err_orig_src_addr;
	275	}
	276
	277	if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
	278	dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
	279	offset = dst_phys_addr - orig_dst_phys_addr;
	280	dst_addr = orig_dst_addr + offset;
	281	} else {
	282	dst_phys_addr = orig_dst_phys_addr;
	283	dst_addr = orig_dst_addr;
2c156ac7 KVA	284	}
	285
	286	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
	287	lower_32_bits(dst_phys_addr));
	288	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
	289	upper_32_bits(dst_phys_addr));
	290
	291	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
	292	size);
	293
e8817de7 GP	294	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
	295	no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
	296	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
2c156ac7	297	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
e8817de7	298	COMMAND_COPY);
2c156ac7 KVA	299
	300	wait_for_completion(&test->irq_raised);
	301
	302	dst_crc32 = crc32_le(~0, dst_addr, size);
	303	if (dst_crc32 == src_crc32)
	304	ret = true;
	305
13107c60 KVA	306	dma_free_coherent(dev, size + alignment, orig_dst_addr,
13107c60 KVA	307	orig_dst_phys_addr);
2c156ac7	308
13107c60 KVA	309	err_orig_src_addr:
	310	dma_free_coherent(dev, size + alignment, orig_src_addr,
	311	orig_src_phys_addr);
2c156ac7 KVA	312
	313	err:
	314	return ret;
	315	}
	316
	317	static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
	318	{
	319	bool ret = false;
	320	u32 reg;
	321	void *addr;
	322	dma_addr_t phys_addr;
	323	struct pci_dev *pdev = test->pdev;
	324	struct device *dev = &pdev->dev;
13107c60 KVA	325	void *orig_addr;
	326	dma_addr_t orig_phys_addr;
	327	size_t offset;
	328	size_t alignment = test->alignment;
2c156ac7 KVA	329	u32 crc32;
2c156ac7 KVA	330
343dc693 DC	331	if (size > SIZE_MAX - alignment)
	332	goto err;
	333
13107c60 KVA	334	orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
	335	GFP_KERNEL);
	336	if (!orig_addr) {
0e52ea61	337	dev_err(dev, "Failed to allocate address\n");
2c156ac7 KVA	338	ret = false;
	339	goto err;
	340	}
	341
13107c60 KVA	342	if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
	343	phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
	344	offset = phys_addr - orig_phys_addr;
	345	addr = orig_addr + offset;
	346	} else {
	347	phys_addr = orig_phys_addr;
	348	addr = orig_addr;
	349	}
	350
2c156ac7 KVA	351	get_random_bytes(addr, size);
	352
	353	crc32 = crc32_le(~0, addr, size);
	354	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
	355	crc32);
	356
	357	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
	358	lower_32_bits(phys_addr));
	359	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
	360	upper_32_bits(phys_addr));
	361
	362	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
	363
e8817de7 GP	364	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
	365	no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
	366	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
2c156ac7	367	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
e8817de7	368	COMMAND_READ);
2c156ac7 KVA	369
	370	wait_for_completion(&test->irq_raised);
	371
	372	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
	373	if (reg & STATUS_READ_SUCCESS)
	374	ret = true;
	375
13107c60	376	dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
2c156ac7 KVA	377
	378	err:
	379	return ret;
	380	}
	381
	382	static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
	383	{
	384	bool ret = false;
	385	void *addr;
	386	dma_addr_t phys_addr;
	387	struct pci_dev *pdev = test->pdev;
	388	struct device *dev = &pdev->dev;
13107c60 KVA	389	void *orig_addr;
	390	dma_addr_t orig_phys_addr;
	391	size_t offset;
	392	size_t alignment = test->alignment;
2c156ac7 KVA	393	u32 crc32;
2c156ac7 KVA	394
343dc693 DC	395	if (size > SIZE_MAX - alignment)
	396	goto err;
	397
13107c60 KVA	398	orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
	399	GFP_KERNEL);
	400	if (!orig_addr) {
0e52ea61	401	dev_err(dev, "Failed to allocate destination address\n");
2c156ac7 KVA	402	ret = false;
	403	goto err;
	404	}
	405
13107c60 KVA	406	if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
	407	phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
	408	offset = phys_addr - orig_phys_addr;
	409	addr = orig_addr + offset;
	410	} else {
	411	phys_addr = orig_phys_addr;
	412	addr = orig_addr;
	413	}
	414
2c156ac7 KVA	415	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
	416	lower_32_bits(phys_addr));
	417	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
	418	upper_32_bits(phys_addr));
	419
	420	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
	421
e8817de7 GP	422	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
	423	no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
	424	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
2c156ac7	425	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
e8817de7	426	COMMAND_WRITE);
2c156ac7 KVA	427
	428	wait_for_completion(&test->irq_raised);
	429
	430	crc32 = crc32_le(~0, addr, size);
	431	if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
	432	ret = true;
	433
13107c60	434	dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
2c156ac7 KVA	435	err:
	436	return ret;
	437	}
	438
	439	static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
	440	unsigned long arg)
	441	{
	442	int ret = -EINVAL;
	443	enum pci_barno bar;
	444	struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
	445
	446	mutex_lock(&test->mutex);
	447	switch (cmd) {
	448	case PCITEST_BAR:
	449	bar = arg;
	450	if (bar < 0 \|\| bar > 5)
	451	goto ret;
	452	ret = pci_endpoint_test_bar(test, bar);
	453	break;
	454	case PCITEST_LEGACY_IRQ:
	455	ret = pci_endpoint_test_legacy_irq(test);
	456	break;
	457	case PCITEST_MSI:
	458	ret = pci_endpoint_test_msi_irq(test, arg);
	459	break;
	460	case PCITEST_WRITE:
	461	ret = pci_endpoint_test_write(test, arg);
	462	break;
	463	case PCITEST_READ:
	464	ret = pci_endpoint_test_read(test, arg);
	465	break;
	466	case PCITEST_COPY:
	467	ret = pci_endpoint_test_copy(test, arg);
	468	break;
	469	}
	470
	471	ret:
	472	mutex_unlock(&test->mutex);
	473	return ret;
	474	}
	475
	476	static const struct file_operations pci_endpoint_test_fops = {
	477	.owner = THIS_MODULE,
	478	.unlocked_ioctl = pci_endpoint_test_ioctl,
	479	};
	480
	481	static int pci_endpoint_test_probe(struct pci_dev *pdev,
	482	const struct pci_device_id *ent)
	483	{
	484	int i;
	485	int err;
0b91516a	486	int irq = 0;
2c156ac7 KVA	487	int id;
	488	char name[20];
	489	enum pci_barno bar;
	490	void __iomem *base;
	491	struct device *dev = &pdev->dev;
	492	struct pci_endpoint_test *test;
834b9051 KVA	493	struct pci_endpoint_test_data *data;
834b9051 KVA	494	enum pci_barno test_reg_bar = BAR_0;
2c156ac7 KVA	495	struct miscdevice *misc_device;
	496
	497	if (pci_is_bridge(pdev))
	498	return -ENODEV;
	499
	500	test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
	501	if (!test)
	502	return -ENOMEM;
	503
834b9051	504	test->test_reg_bar = 0;
13107c60	505	test->alignment = 0;
2c156ac7	506	test->pdev = pdev;
834b9051 KVA	507
834b9051 KVA	508	data = (struct pci_endpoint_test_data *)ent->driver_data;
13107c60	509	if (data) {
834b9051	510	test_reg_bar = data->test_reg_bar;
13107c60	511	test->alignment = data->alignment;
0b91516a	512	no_msi = data->no_msi;
13107c60	513	}
834b9051	514
2c156ac7 KVA	515	init_completion(&test->irq_raised);
	516	mutex_init(&test->mutex);
	517
	518	err = pci_enable_device(pdev);
	519	if (err) {
	520	dev_err(dev, "Cannot enable PCI device\n");
	521	return err;
	522	}
	523
	524	err = pci_request_regions(pdev, DRV_MODULE_NAME);
	525	if (err) {
	526	dev_err(dev, "Cannot obtain PCI resources\n");
	527	goto err_disable_pdev;
	528	}
	529
	530	pci_set_master(pdev);
	531
0b91516a KVA	532	if (!no_msi) {
	533	irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
	534	if (irq < 0)
0e52ea61	535	dev_err(dev, "Failed to get MSI interrupts\n");
b7636e81	536	test->num_irqs = irq;
0b91516a	537	}
2c156ac7 KVA	538
	539	err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
	540	IRQF_SHARED, DRV_MODULE_NAME, test);
	541	if (err) {
0e52ea61	542	dev_err(dev, "Failed to request IRQ %d\n", pdev->irq);
2c156ac7 KVA	543	goto err_disable_msi;
	544	}
	545
	546	for (i = 1; i < irq; i++) {
ecc57efe	547	err = devm_request_irq(dev, pci_irq_vector(pdev, i),
2c156ac7 KVA	548	pci_endpoint_test_irqhandler,
	549	IRQF_SHARED, DRV_MODULE_NAME, test);
	550	if (err)
	551	dev_err(dev, "failed to request IRQ %d for MSI %d\n",
ecc57efe	552	pci_irq_vector(pdev, i), i + 1);
2c156ac7 KVA	553	}
	554
	555	for (bar = BAR_0; bar <= BAR_5; bar++) {
16b17cad NC	556	if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
	557	base = pci_ioremap_bar(pdev, bar);
	558	if (!base) {
0e52ea61	559	dev_err(dev, "Failed to read BAR%d\n", bar);
16b17cad NC	560	WARN_ON(bar == test_reg_bar);
	561	}
	562	test->bar[bar] = base;
2c156ac7	563	}
2c156ac7 KVA	564	}
2c156ac7 KVA	565
834b9051	566	test->base = test->bar[test_reg_bar];
2c156ac7	567	if (!test->base) {
80068c93	568	err = -ENOMEM;
834b9051 KVA	569	dev_err(dev, "Cannot perform PCI test without BAR%d\n",
834b9051 KVA	570	test_reg_bar);
2c156ac7 KVA	571	goto err_iounmap;
	572	}
	573
	574	pci_set_drvdata(pdev, test);
	575
	576	id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
	577	if (id < 0) {
80068c93	578	err = id;
0e52ea61	579	dev_err(dev, "Unable to get id\n");
2c156ac7 KVA	580	goto err_iounmap;
	581	}
	582
	583	snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
	584	misc_device = &test->miscdev;
	585	misc_device->minor = MISC_DYNAMIC_MINOR;
139838ff KVA	586	misc_device->name = kstrdup(name, GFP_KERNEL);
	587	if (!misc_device->name) {
	588	err = -ENOMEM;
	589	goto err_ida_remove;
	590	}
2c156ac7 KVA	591	misc_device->fops = &pci_endpoint_test_fops,
	592
	593	err = misc_register(misc_device);
	594	if (err) {
0e52ea61	595	dev_err(dev, "Failed to register device\n");
139838ff	596	goto err_kfree_name;
2c156ac7 KVA	597	}
	598
	599	return 0;
	600
139838ff KVA	601	err_kfree_name:
	602	kfree(misc_device->name);
	603
2c156ac7 KVA	604	err_ida_remove:
	605	ida_simple_remove(&pci_endpoint_test_ida, id);
	606
	607	err_iounmap:
	608	for (bar = BAR_0; bar <= BAR_5; bar++) {
	609	if (test->bar[bar])
	610	pci_iounmap(pdev, test->bar[bar]);
	611	}
	612
b7636e81	613	for (i = 0; i < irq; i++)
ecc57efe	614	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), test);
b7636e81	615
2c156ac7 KVA	616	err_disable_msi:
	617	pci_disable_msi(pdev);
	618	pci_release_regions(pdev);
	619
	620	err_disable_pdev:
	621	pci_disable_device(pdev);
	622
	623	return err;
	624	}
	625
	626	static void pci_endpoint_test_remove(struct pci_dev *pdev)
	627	{
	628	int id;
b7636e81	629	int i;
2c156ac7 KVA	630	enum pci_barno bar;
	631	struct pci_endpoint_test *test = pci_get_drvdata(pdev);
	632	struct miscdevice *misc_device = &test->miscdev;
	633
	634	if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
	635	return;
a2db2663 DC	636	if (id < 0)
a2db2663 DC	637	return;
2c156ac7 KVA	638
2c156ac7 KVA	639	misc_deregister(&test->miscdev);
139838ff	640	kfree(misc_device->name);
2c156ac7 KVA	641	ida_simple_remove(&pci_endpoint_test_ida, id);
	642	for (bar = BAR_0; bar <= BAR_5; bar++) {
	643	if (test->bar[bar])
	644	pci_iounmap(pdev, test->bar[bar]);
	645	}
b7636e81	646	for (i = 0; i < test->num_irqs; i++)
ecc57efe	647	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), test);
2c156ac7 KVA	648	pci_disable_msi(pdev);
	649	pci_release_regions(pdev);
	650	pci_disable_device(pdev);
	651	}
	652
	653	static const struct pci_device_id pci_endpoint_test_tbl[] = {
	654	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
	655	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
14b06ddd	656	{ PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },
2c156ac7 KVA	657	{ }
	658	};
	659	MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
	660
	661	static struct pci_driver pci_endpoint_test_driver = {
	662	.name = DRV_MODULE_NAME,
	663	.id_table = pci_endpoint_test_tbl,
	664	.probe = pci_endpoint_test_probe,
	665	.remove = pci_endpoint_test_remove,
	666	};
	667	module_pci_driver(pci_endpoint_test_driver);
	668
	669	MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
	670	MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
	671	MODULE_LICENSE("GPL v2");