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2c156ac7 KVA |
1 | /** |
2 | * Host side test driver to test endpoint functionality | |
3 | * | |
4 | * Copyright (C) 2017 Texas Instruments | |
5 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 of | |
9 | * the License as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/crc32.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/fs.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/miscdevice.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/mutex.h> | |
29 | #include <linux/random.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/pci_ids.h> | |
33 | ||
34 | #include <linux/pci_regs.h> | |
35 | ||
36 | #include <uapi/linux/pcitest.h> | |
37 | ||
38 | #define DRV_MODULE_NAME "pci-endpoint-test" | |
39 | ||
40 | #define PCI_ENDPOINT_TEST_MAGIC 0x0 | |
41 | ||
42 | #define PCI_ENDPOINT_TEST_COMMAND 0x4 | |
43 | #define COMMAND_RAISE_LEGACY_IRQ BIT(0) | |
44 | #define COMMAND_RAISE_MSI_IRQ BIT(1) | |
45 | #define MSI_NUMBER_SHIFT 2 | |
46 | /* 6 bits for MSI number */ | |
47 | #define COMMAND_READ BIT(8) | |
48 | #define COMMAND_WRITE BIT(9) | |
49 | #define COMMAND_COPY BIT(10) | |
50 | ||
51 | #define PCI_ENDPOINT_TEST_STATUS 0x8 | |
52 | #define STATUS_READ_SUCCESS BIT(0) | |
53 | #define STATUS_READ_FAIL BIT(1) | |
54 | #define STATUS_WRITE_SUCCESS BIT(2) | |
55 | #define STATUS_WRITE_FAIL BIT(3) | |
56 | #define STATUS_COPY_SUCCESS BIT(4) | |
57 | #define STATUS_COPY_FAIL BIT(5) | |
58 | #define STATUS_IRQ_RAISED BIT(6) | |
59 | #define STATUS_SRC_ADDR_INVALID BIT(7) | |
60 | #define STATUS_DST_ADDR_INVALID BIT(8) | |
61 | ||
62 | #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc | |
63 | #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10 | |
64 | ||
65 | #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14 | |
66 | #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18 | |
67 | ||
68 | #define PCI_ENDPOINT_TEST_SIZE 0x1c | |
69 | #define PCI_ENDPOINT_TEST_CHECKSUM 0x20 | |
70 | ||
71 | static DEFINE_IDA(pci_endpoint_test_ida); | |
72 | ||
73 | #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ | |
74 | miscdev) | |
0c8a5f9d KVA |
75 | |
76 | static bool no_msi; | |
77 | module_param(no_msi, bool, 0444); | |
78 | MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test"); | |
79 | ||
2c156ac7 KVA |
80 | enum pci_barno { |
81 | BAR_0, | |
82 | BAR_1, | |
83 | BAR_2, | |
84 | BAR_3, | |
85 | BAR_4, | |
86 | BAR_5, | |
87 | }; | |
88 | ||
89 | struct pci_endpoint_test { | |
90 | struct pci_dev *pdev; | |
91 | void __iomem *base; | |
92 | void __iomem *bar[6]; | |
93 | struct completion irq_raised; | |
94 | int last_irq; | |
95 | /* mutex to protect the ioctls */ | |
96 | struct mutex mutex; | |
97 | struct miscdevice miscdev; | |
834b9051 | 98 | enum pci_barno test_reg_bar; |
13107c60 | 99 | size_t alignment; |
2c156ac7 KVA |
100 | }; |
101 | ||
834b9051 KVA |
102 | struct pci_endpoint_test_data { |
103 | enum pci_barno test_reg_bar; | |
13107c60 | 104 | size_t alignment; |
0b91516a | 105 | bool no_msi; |
834b9051 KVA |
106 | }; |
107 | ||
2c156ac7 KVA |
108 | static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test, |
109 | u32 offset) | |
110 | { | |
111 | return readl(test->base + offset); | |
112 | } | |
113 | ||
114 | static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test, | |
115 | u32 offset, u32 value) | |
116 | { | |
117 | writel(value, test->base + offset); | |
118 | } | |
119 | ||
120 | static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test, | |
121 | int bar, int offset) | |
122 | { | |
123 | return readl(test->bar[bar] + offset); | |
124 | } | |
125 | ||
126 | static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test, | |
127 | int bar, u32 offset, u32 value) | |
128 | { | |
129 | writel(value, test->bar[bar] + offset); | |
130 | } | |
131 | ||
132 | static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id) | |
133 | { | |
134 | struct pci_endpoint_test *test = dev_id; | |
135 | u32 reg; | |
136 | ||
137 | reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); | |
138 | if (reg & STATUS_IRQ_RAISED) { | |
139 | test->last_irq = irq; | |
140 | complete(&test->irq_raised); | |
141 | reg &= ~STATUS_IRQ_RAISED; | |
142 | } | |
143 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS, | |
144 | reg); | |
145 | ||
146 | return IRQ_HANDLED; | |
147 | } | |
148 | ||
149 | static bool pci_endpoint_test_bar(struct pci_endpoint_test *test, | |
150 | enum pci_barno barno) | |
151 | { | |
152 | int j; | |
153 | u32 val; | |
154 | int size; | |
cda370ec | 155 | struct pci_dev *pdev = test->pdev; |
2c156ac7 KVA |
156 | |
157 | if (!test->bar[barno]) | |
158 | return false; | |
159 | ||
cda370ec | 160 | size = pci_resource_len(pdev, barno); |
2c156ac7 | 161 | |
834b9051 KVA |
162 | if (barno == test->test_reg_bar) |
163 | size = 0x4; | |
164 | ||
2c156ac7 KVA |
165 | for (j = 0; j < size; j += 4) |
166 | pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0); | |
167 | ||
168 | for (j = 0; j < size; j += 4) { | |
169 | val = pci_endpoint_test_bar_readl(test, barno, j); | |
170 | if (val != 0xA0A0A0A0) | |
171 | return false; | |
172 | } | |
173 | ||
174 | return true; | |
175 | } | |
176 | ||
177 | static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test) | |
178 | { | |
179 | u32 val; | |
180 | ||
181 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | |
182 | COMMAND_RAISE_LEGACY_IRQ); | |
183 | val = wait_for_completion_timeout(&test->irq_raised, | |
184 | msecs_to_jiffies(1000)); | |
185 | if (!val) | |
186 | return false; | |
187 | ||
188 | return true; | |
189 | } | |
190 | ||
191 | static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test, | |
192 | u8 msi_num) | |
193 | { | |
194 | u32 val; | |
195 | struct pci_dev *pdev = test->pdev; | |
196 | ||
197 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | |
198 | msi_num << MSI_NUMBER_SHIFT | | |
199 | COMMAND_RAISE_MSI_IRQ); | |
200 | val = wait_for_completion_timeout(&test->irq_raised, | |
201 | msecs_to_jiffies(1000)); | |
202 | if (!val) | |
203 | return false; | |
204 | ||
205 | if (test->last_irq - pdev->irq == msi_num - 1) | |
206 | return true; | |
207 | ||
208 | return false; | |
209 | } | |
210 | ||
211 | static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size) | |
212 | { | |
213 | bool ret = false; | |
214 | void *src_addr; | |
215 | void *dst_addr; | |
216 | dma_addr_t src_phys_addr; | |
217 | dma_addr_t dst_phys_addr; | |
218 | struct pci_dev *pdev = test->pdev; | |
219 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
220 | void *orig_src_addr; |
221 | dma_addr_t orig_src_phys_addr; | |
222 | void *orig_dst_addr; | |
223 | dma_addr_t orig_dst_phys_addr; | |
224 | size_t offset; | |
225 | size_t alignment = test->alignment; | |
2c156ac7 KVA |
226 | u32 src_crc32; |
227 | u32 dst_crc32; | |
228 | ||
343dc693 DC |
229 | if (size > SIZE_MAX - alignment) |
230 | goto err; | |
231 | ||
13107c60 KVA |
232 | orig_src_addr = dma_alloc_coherent(dev, size + alignment, |
233 | &orig_src_phys_addr, GFP_KERNEL); | |
234 | if (!orig_src_addr) { | |
2c156ac7 KVA |
235 | dev_err(dev, "failed to allocate source buffer\n"); |
236 | ret = false; | |
237 | goto err; | |
238 | } | |
239 | ||
13107c60 KVA |
240 | if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) { |
241 | src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment); | |
242 | offset = src_phys_addr - orig_src_phys_addr; | |
243 | src_addr = orig_src_addr + offset; | |
244 | } else { | |
245 | src_phys_addr = orig_src_phys_addr; | |
246 | src_addr = orig_src_addr; | |
247 | } | |
248 | ||
2c156ac7 KVA |
249 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR, |
250 | lower_32_bits(src_phys_addr)); | |
251 | ||
252 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR, | |
253 | upper_32_bits(src_phys_addr)); | |
254 | ||
255 | get_random_bytes(src_addr, size); | |
256 | src_crc32 = crc32_le(~0, src_addr, size); | |
257 | ||
13107c60 KVA |
258 | orig_dst_addr = dma_alloc_coherent(dev, size + alignment, |
259 | &orig_dst_phys_addr, GFP_KERNEL); | |
260 | if (!orig_dst_addr) { | |
2c156ac7 KVA |
261 | dev_err(dev, "failed to allocate destination address\n"); |
262 | ret = false; | |
13107c60 KVA |
263 | goto err_orig_src_addr; |
264 | } | |
265 | ||
266 | if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) { | |
267 | dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment); | |
268 | offset = dst_phys_addr - orig_dst_phys_addr; | |
269 | dst_addr = orig_dst_addr + offset; | |
270 | } else { | |
271 | dst_phys_addr = orig_dst_phys_addr; | |
272 | dst_addr = orig_dst_addr; | |
2c156ac7 KVA |
273 | } |
274 | ||
275 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR, | |
276 | lower_32_bits(dst_phys_addr)); | |
277 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR, | |
278 | upper_32_bits(dst_phys_addr)); | |
279 | ||
280 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, | |
281 | size); | |
282 | ||
283 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | |
284 | 1 << MSI_NUMBER_SHIFT | COMMAND_COPY); | |
285 | ||
286 | wait_for_completion(&test->irq_raised); | |
287 | ||
288 | dst_crc32 = crc32_le(~0, dst_addr, size); | |
289 | if (dst_crc32 == src_crc32) | |
290 | ret = true; | |
291 | ||
13107c60 KVA |
292 | dma_free_coherent(dev, size + alignment, orig_dst_addr, |
293 | orig_dst_phys_addr); | |
2c156ac7 | 294 | |
13107c60 KVA |
295 | err_orig_src_addr: |
296 | dma_free_coherent(dev, size + alignment, orig_src_addr, | |
297 | orig_src_phys_addr); | |
2c156ac7 KVA |
298 | |
299 | err: | |
300 | return ret; | |
301 | } | |
302 | ||
303 | static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size) | |
304 | { | |
305 | bool ret = false; | |
306 | u32 reg; | |
307 | void *addr; | |
308 | dma_addr_t phys_addr; | |
309 | struct pci_dev *pdev = test->pdev; | |
310 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
311 | void *orig_addr; |
312 | dma_addr_t orig_phys_addr; | |
313 | size_t offset; | |
314 | size_t alignment = test->alignment; | |
2c156ac7 KVA |
315 | u32 crc32; |
316 | ||
343dc693 DC |
317 | if (size > SIZE_MAX - alignment) |
318 | goto err; | |
319 | ||
13107c60 KVA |
320 | orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr, |
321 | GFP_KERNEL); | |
322 | if (!orig_addr) { | |
2c156ac7 KVA |
323 | dev_err(dev, "failed to allocate address\n"); |
324 | ret = false; | |
325 | goto err; | |
326 | } | |
327 | ||
13107c60 KVA |
328 | if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) { |
329 | phys_addr = PTR_ALIGN(orig_phys_addr, alignment); | |
330 | offset = phys_addr - orig_phys_addr; | |
331 | addr = orig_addr + offset; | |
332 | } else { | |
333 | phys_addr = orig_phys_addr; | |
334 | addr = orig_addr; | |
335 | } | |
336 | ||
2c156ac7 KVA |
337 | get_random_bytes(addr, size); |
338 | ||
339 | crc32 = crc32_le(~0, addr, size); | |
340 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM, | |
341 | crc32); | |
342 | ||
343 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR, | |
344 | lower_32_bits(phys_addr)); | |
345 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR, | |
346 | upper_32_bits(phys_addr)); | |
347 | ||
348 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | |
349 | ||
350 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | |
351 | 1 << MSI_NUMBER_SHIFT | COMMAND_READ); | |
352 | ||
353 | wait_for_completion(&test->irq_raised); | |
354 | ||
355 | reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); | |
356 | if (reg & STATUS_READ_SUCCESS) | |
357 | ret = true; | |
358 | ||
13107c60 | 359 | dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr); |
2c156ac7 KVA |
360 | |
361 | err: | |
362 | return ret; | |
363 | } | |
364 | ||
365 | static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size) | |
366 | { | |
367 | bool ret = false; | |
368 | void *addr; | |
369 | dma_addr_t phys_addr; | |
370 | struct pci_dev *pdev = test->pdev; | |
371 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
372 | void *orig_addr; |
373 | dma_addr_t orig_phys_addr; | |
374 | size_t offset; | |
375 | size_t alignment = test->alignment; | |
2c156ac7 KVA |
376 | u32 crc32; |
377 | ||
343dc693 DC |
378 | if (size > SIZE_MAX - alignment) |
379 | goto err; | |
380 | ||
13107c60 KVA |
381 | orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr, |
382 | GFP_KERNEL); | |
383 | if (!orig_addr) { | |
2c156ac7 KVA |
384 | dev_err(dev, "failed to allocate destination address\n"); |
385 | ret = false; | |
386 | goto err; | |
387 | } | |
388 | ||
13107c60 KVA |
389 | if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) { |
390 | phys_addr = PTR_ALIGN(orig_phys_addr, alignment); | |
391 | offset = phys_addr - orig_phys_addr; | |
392 | addr = orig_addr + offset; | |
393 | } else { | |
394 | phys_addr = orig_phys_addr; | |
395 | addr = orig_addr; | |
396 | } | |
397 | ||
2c156ac7 KVA |
398 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR, |
399 | lower_32_bits(phys_addr)); | |
400 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR, | |
401 | upper_32_bits(phys_addr)); | |
402 | ||
403 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | |
404 | ||
405 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | |
406 | 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE); | |
407 | ||
408 | wait_for_completion(&test->irq_raised); | |
409 | ||
410 | crc32 = crc32_le(~0, addr, size); | |
411 | if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM)) | |
412 | ret = true; | |
413 | ||
13107c60 | 414 | dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr); |
2c156ac7 KVA |
415 | err: |
416 | return ret; | |
417 | } | |
418 | ||
419 | static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, | |
420 | unsigned long arg) | |
421 | { | |
422 | int ret = -EINVAL; | |
423 | enum pci_barno bar; | |
424 | struct pci_endpoint_test *test = to_endpoint_test(file->private_data); | |
425 | ||
426 | mutex_lock(&test->mutex); | |
427 | switch (cmd) { | |
428 | case PCITEST_BAR: | |
429 | bar = arg; | |
430 | if (bar < 0 || bar > 5) | |
431 | goto ret; | |
432 | ret = pci_endpoint_test_bar(test, bar); | |
433 | break; | |
434 | case PCITEST_LEGACY_IRQ: | |
435 | ret = pci_endpoint_test_legacy_irq(test); | |
436 | break; | |
437 | case PCITEST_MSI: | |
438 | ret = pci_endpoint_test_msi_irq(test, arg); | |
439 | break; | |
440 | case PCITEST_WRITE: | |
441 | ret = pci_endpoint_test_write(test, arg); | |
442 | break; | |
443 | case PCITEST_READ: | |
444 | ret = pci_endpoint_test_read(test, arg); | |
445 | break; | |
446 | case PCITEST_COPY: | |
447 | ret = pci_endpoint_test_copy(test, arg); | |
448 | break; | |
449 | } | |
450 | ||
451 | ret: | |
452 | mutex_unlock(&test->mutex); | |
453 | return ret; | |
454 | } | |
455 | ||
456 | static const struct file_operations pci_endpoint_test_fops = { | |
457 | .owner = THIS_MODULE, | |
458 | .unlocked_ioctl = pci_endpoint_test_ioctl, | |
459 | }; | |
460 | ||
461 | static int pci_endpoint_test_probe(struct pci_dev *pdev, | |
462 | const struct pci_device_id *ent) | |
463 | { | |
464 | int i; | |
465 | int err; | |
0b91516a | 466 | int irq = 0; |
2c156ac7 KVA |
467 | int id; |
468 | char name[20]; | |
469 | enum pci_barno bar; | |
470 | void __iomem *base; | |
471 | struct device *dev = &pdev->dev; | |
472 | struct pci_endpoint_test *test; | |
834b9051 KVA |
473 | struct pci_endpoint_test_data *data; |
474 | enum pci_barno test_reg_bar = BAR_0; | |
2c156ac7 KVA |
475 | struct miscdevice *misc_device; |
476 | ||
477 | if (pci_is_bridge(pdev)) | |
478 | return -ENODEV; | |
479 | ||
480 | test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL); | |
481 | if (!test) | |
482 | return -ENOMEM; | |
483 | ||
834b9051 | 484 | test->test_reg_bar = 0; |
13107c60 | 485 | test->alignment = 0; |
2c156ac7 | 486 | test->pdev = pdev; |
834b9051 KVA |
487 | |
488 | data = (struct pci_endpoint_test_data *)ent->driver_data; | |
13107c60 | 489 | if (data) { |
834b9051 | 490 | test_reg_bar = data->test_reg_bar; |
13107c60 | 491 | test->alignment = data->alignment; |
0b91516a | 492 | no_msi = data->no_msi; |
13107c60 | 493 | } |
834b9051 | 494 | |
2c156ac7 KVA |
495 | init_completion(&test->irq_raised); |
496 | mutex_init(&test->mutex); | |
497 | ||
498 | err = pci_enable_device(pdev); | |
499 | if (err) { | |
500 | dev_err(dev, "Cannot enable PCI device\n"); | |
501 | return err; | |
502 | } | |
503 | ||
504 | err = pci_request_regions(pdev, DRV_MODULE_NAME); | |
505 | if (err) { | |
506 | dev_err(dev, "Cannot obtain PCI resources\n"); | |
507 | goto err_disable_pdev; | |
508 | } | |
509 | ||
510 | pci_set_master(pdev); | |
511 | ||
0b91516a KVA |
512 | if (!no_msi) { |
513 | irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI); | |
514 | if (irq < 0) | |
515 | dev_err(dev, "failed to get MSI interrupts\n"); | |
516 | } | |
2c156ac7 KVA |
517 | |
518 | err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler, | |
519 | IRQF_SHARED, DRV_MODULE_NAME, test); | |
520 | if (err) { | |
521 | dev_err(dev, "failed to request IRQ %d\n", pdev->irq); | |
522 | goto err_disable_msi; | |
523 | } | |
524 | ||
525 | for (i = 1; i < irq; i++) { | |
526 | err = devm_request_irq(dev, pdev->irq + i, | |
527 | pci_endpoint_test_irqhandler, | |
528 | IRQF_SHARED, DRV_MODULE_NAME, test); | |
529 | if (err) | |
530 | dev_err(dev, "failed to request IRQ %d for MSI %d\n", | |
531 | pdev->irq + i, i + 1); | |
532 | } | |
533 | ||
534 | for (bar = BAR_0; bar <= BAR_5; bar++) { | |
535 | base = pci_ioremap_bar(pdev, bar); | |
536 | if (!base) { | |
537 | dev_err(dev, "failed to read BAR%d\n", bar); | |
834b9051 | 538 | WARN_ON(bar == test_reg_bar); |
2c156ac7 KVA |
539 | } |
540 | test->bar[bar] = base; | |
541 | } | |
542 | ||
834b9051 | 543 | test->base = test->bar[test_reg_bar]; |
2c156ac7 | 544 | if (!test->base) { |
80068c93 | 545 | err = -ENOMEM; |
834b9051 KVA |
546 | dev_err(dev, "Cannot perform PCI test without BAR%d\n", |
547 | test_reg_bar); | |
2c156ac7 KVA |
548 | goto err_iounmap; |
549 | } | |
550 | ||
551 | pci_set_drvdata(pdev, test); | |
552 | ||
553 | id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL); | |
554 | if (id < 0) { | |
80068c93 | 555 | err = id; |
2c156ac7 KVA |
556 | dev_err(dev, "unable to get id\n"); |
557 | goto err_iounmap; | |
558 | } | |
559 | ||
560 | snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id); | |
561 | misc_device = &test->miscdev; | |
562 | misc_device->minor = MISC_DYNAMIC_MINOR; | |
563 | misc_device->name = name; | |
564 | misc_device->fops = &pci_endpoint_test_fops, | |
565 | ||
566 | err = misc_register(misc_device); | |
567 | if (err) { | |
568 | dev_err(dev, "failed to register device\n"); | |
569 | goto err_ida_remove; | |
570 | } | |
571 | ||
572 | return 0; | |
573 | ||
574 | err_ida_remove: | |
575 | ida_simple_remove(&pci_endpoint_test_ida, id); | |
576 | ||
577 | err_iounmap: | |
578 | for (bar = BAR_0; bar <= BAR_5; bar++) { | |
579 | if (test->bar[bar]) | |
580 | pci_iounmap(pdev, test->bar[bar]); | |
581 | } | |
582 | ||
583 | err_disable_msi: | |
584 | pci_disable_msi(pdev); | |
585 | pci_release_regions(pdev); | |
586 | ||
587 | err_disable_pdev: | |
588 | pci_disable_device(pdev); | |
589 | ||
590 | return err; | |
591 | } | |
592 | ||
593 | static void pci_endpoint_test_remove(struct pci_dev *pdev) | |
594 | { | |
595 | int id; | |
596 | enum pci_barno bar; | |
597 | struct pci_endpoint_test *test = pci_get_drvdata(pdev); | |
598 | struct miscdevice *misc_device = &test->miscdev; | |
599 | ||
600 | if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1) | |
601 | return; | |
a2db2663 DC |
602 | if (id < 0) |
603 | return; | |
2c156ac7 KVA |
604 | |
605 | misc_deregister(&test->miscdev); | |
606 | ida_simple_remove(&pci_endpoint_test_ida, id); | |
607 | for (bar = BAR_0; bar <= BAR_5; bar++) { | |
608 | if (test->bar[bar]) | |
609 | pci_iounmap(pdev, test->bar[bar]); | |
610 | } | |
611 | pci_disable_msi(pdev); | |
612 | pci_release_regions(pdev); | |
613 | pci_disable_device(pdev); | |
614 | } | |
615 | ||
616 | static const struct pci_device_id pci_endpoint_test_tbl[] = { | |
617 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) }, | |
618 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) }, | |
619 | { } | |
620 | }; | |
621 | MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); | |
622 | ||
623 | static struct pci_driver pci_endpoint_test_driver = { | |
624 | .name = DRV_MODULE_NAME, | |
625 | .id_table = pci_endpoint_test_tbl, | |
626 | .probe = pci_endpoint_test_probe, | |
627 | .remove = pci_endpoint_test_remove, | |
628 | }; | |
629 | module_pci_driver(pci_endpoint_test_driver); | |
630 | ||
631 | MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER"); | |
632 | MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); | |
633 | MODULE_LICENSE("GPL v2"); |