Commit | Line | Data |
---|---|---|
6b1baefe | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1aa3f2b0 | 2 | /* |
2c156ac7 KVA |
3 | * Host side test driver to test endpoint functionality |
4 | * | |
5 | * Copyright (C) 2017 Texas Instruments | |
6 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | |
2c156ac7 KVA |
7 | */ |
8 | ||
9 | #include <linux/crc32.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/fs.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/mutex.h> | |
18 | #include <linux/random.h> | |
19 | #include <linux/slab.h> | |
cf376b4b | 20 | #include <linux/uaccess.h> |
2c156ac7 KVA |
21 | #include <linux/pci.h> |
22 | #include <linux/pci_ids.h> | |
23 | ||
24 | #include <linux/pci_regs.h> | |
25 | ||
26 | #include <uapi/linux/pcitest.h> | |
27 | ||
e8817de7 GP |
28 | #define DRV_MODULE_NAME "pci-endpoint-test" |
29 | ||
e0332712 | 30 | #define IRQ_TYPE_UNDEFINED -1 |
e8817de7 GP |
31 | #define IRQ_TYPE_LEGACY 0 |
32 | #define IRQ_TYPE_MSI 1 | |
c2e00e31 | 33 | #define IRQ_TYPE_MSIX 2 |
e8817de7 GP |
34 | |
35 | #define PCI_ENDPOINT_TEST_MAGIC 0x0 | |
36 | ||
37 | #define PCI_ENDPOINT_TEST_COMMAND 0x4 | |
38 | #define COMMAND_RAISE_LEGACY_IRQ BIT(0) | |
39 | #define COMMAND_RAISE_MSI_IRQ BIT(1) | |
c2e00e31 | 40 | #define COMMAND_RAISE_MSIX_IRQ BIT(2) |
e8817de7 GP |
41 | #define COMMAND_READ BIT(3) |
42 | #define COMMAND_WRITE BIT(4) | |
43 | #define COMMAND_COPY BIT(5) | |
44 | ||
45 | #define PCI_ENDPOINT_TEST_STATUS 0x8 | |
46 | #define STATUS_READ_SUCCESS BIT(0) | |
47 | #define STATUS_READ_FAIL BIT(1) | |
48 | #define STATUS_WRITE_SUCCESS BIT(2) | |
49 | #define STATUS_WRITE_FAIL BIT(3) | |
50 | #define STATUS_COPY_SUCCESS BIT(4) | |
51 | #define STATUS_COPY_FAIL BIT(5) | |
52 | #define STATUS_IRQ_RAISED BIT(6) | |
53 | #define STATUS_SRC_ADDR_INVALID BIT(7) | |
54 | #define STATUS_DST_ADDR_INVALID BIT(8) | |
55 | ||
56 | #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c | |
2c156ac7 KVA |
57 | #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10 |
58 | ||
59 | #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14 | |
60 | #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18 | |
61 | ||
e8817de7 GP |
62 | #define PCI_ENDPOINT_TEST_SIZE 0x1c |
63 | #define PCI_ENDPOINT_TEST_CHECKSUM 0x20 | |
64 | ||
65 | #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 | |
66 | #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 | |
2c156ac7 | 67 | |
cf376b4b KVA |
68 | #define PCI_ENDPOINT_TEST_FLAGS 0x2c |
69 | #define FLAG_USE_DMA BIT(0) | |
70 | ||
5bb04b19 | 71 | #define PCI_DEVICE_ID_TI_AM654 0xb00c |
7c52009d KVA |
72 | #define PCI_DEVICE_ID_TI_J7200 0xb00f |
73 | #define PCI_DEVICE_ID_TI_AM64 0xb010 | |
8293703a | 74 | #define PCI_DEVICE_ID_TI_J721S2 0xb013 |
6b8ab421 | 75 | #define PCI_DEVICE_ID_LS1088A 0x80c0 |
01ea5ede | 76 | #define PCI_DEVICE_ID_IMX8 0x0808 |
5bb04b19 KVA |
77 | |
78 | #define is_am654_pci_dev(pdev) \ | |
79 | ((pdev)->device == PCI_DEVICE_ID_TI_AM654) | |
80 | ||
cfb824dd LP |
81 | #define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028 |
82 | #define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b | |
b03025c5 | 83 | #define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d |
a63c5f3d | 84 | #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025 |
6c4b3993 | 85 | #define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031 |
b03025c5 | 86 | |
2c156ac7 KVA |
87 | static DEFINE_IDA(pci_endpoint_test_ida); |
88 | ||
89 | #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ | |
90 | miscdev) | |
0c8a5f9d KVA |
91 | |
92 | static bool no_msi; | |
93 | module_param(no_msi, bool, 0444); | |
94 | MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test"); | |
95 | ||
9133e394 GP |
96 | static int irq_type = IRQ_TYPE_MSI; |
97 | module_param(irq_type, int, 0444); | |
c2e00e31 | 98 | MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)"); |
9133e394 | 99 | |
2c156ac7 KVA |
100 | enum pci_barno { |
101 | BAR_0, | |
102 | BAR_1, | |
103 | BAR_2, | |
104 | BAR_3, | |
105 | BAR_4, | |
106 | BAR_5, | |
107 | }; | |
108 | ||
109 | struct pci_endpoint_test { | |
110 | struct pci_dev *pdev; | |
111 | void __iomem *base; | |
c9c13ba4 | 112 | void __iomem *bar[PCI_STD_NUM_BARS]; |
2c156ac7 KVA |
113 | struct completion irq_raised; |
114 | int last_irq; | |
b7636e81 | 115 | int num_irqs; |
b2ba9225 | 116 | int irq_type; |
2c156ac7 KVA |
117 | /* mutex to protect the ioctls */ |
118 | struct mutex mutex; | |
119 | struct miscdevice miscdev; | |
834b9051 | 120 | enum pci_barno test_reg_bar; |
13107c60 | 121 | size_t alignment; |
c2be14ab | 122 | const char *name; |
2c156ac7 KVA |
123 | }; |
124 | ||
834b9051 KVA |
125 | struct pci_endpoint_test_data { |
126 | enum pci_barno test_reg_bar; | |
13107c60 | 127 | size_t alignment; |
9133e394 | 128 | int irq_type; |
834b9051 KVA |
129 | }; |
130 | ||
2c156ac7 KVA |
131 | static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test, |
132 | u32 offset) | |
133 | { | |
134 | return readl(test->base + offset); | |
135 | } | |
136 | ||
137 | static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test, | |
138 | u32 offset, u32 value) | |
139 | { | |
140 | writel(value, test->base + offset); | |
141 | } | |
142 | ||
143 | static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test, | |
144 | int bar, int offset) | |
145 | { | |
146 | return readl(test->bar[bar] + offset); | |
147 | } | |
148 | ||
149 | static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test, | |
150 | int bar, u32 offset, u32 value) | |
151 | { | |
152 | writel(value, test->bar[bar] + offset); | |
153 | } | |
154 | ||
155 | static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id) | |
156 | { | |
157 | struct pci_endpoint_test *test = dev_id; | |
158 | u32 reg; | |
159 | ||
160 | reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); | |
161 | if (reg & STATUS_IRQ_RAISED) { | |
162 | test->last_irq = irq; | |
163 | complete(&test->irq_raised); | |
2c156ac7 | 164 | } |
2c156ac7 KVA |
165 | |
166 | return IRQ_HANDLED; | |
167 | } | |
168 | ||
e0332712 GP |
169 | static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test) |
170 | { | |
171 | struct pci_dev *pdev = test->pdev; | |
172 | ||
173 | pci_free_irq_vectors(pdev); | |
b2ba9225 | 174 | test->irq_type = IRQ_TYPE_UNDEFINED; |
e0332712 GP |
175 | } |
176 | ||
177 | static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test, | |
178 | int type) | |
179 | { | |
180 | int irq = -1; | |
181 | struct pci_dev *pdev = test->pdev; | |
182 | struct device *dev = &pdev->dev; | |
183 | bool res = true; | |
184 | ||
185 | switch (type) { | |
186 | case IRQ_TYPE_LEGACY: | |
187 | irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY); | |
188 | if (irq < 0) | |
189 | dev_err(dev, "Failed to get Legacy interrupt\n"); | |
190 | break; | |
191 | case IRQ_TYPE_MSI: | |
192 | irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI); | |
193 | if (irq < 0) | |
194 | dev_err(dev, "Failed to get MSI interrupts\n"); | |
195 | break; | |
196 | case IRQ_TYPE_MSIX: | |
197 | irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX); | |
198 | if (irq < 0) | |
199 | dev_err(dev, "Failed to get MSI-X interrupts\n"); | |
200 | break; | |
201 | default: | |
202 | dev_err(dev, "Invalid IRQ type selected\n"); | |
203 | } | |
204 | ||
205 | if (irq < 0) { | |
206 | irq = 0; | |
207 | res = false; | |
208 | } | |
b2ba9225 KVA |
209 | |
210 | test->irq_type = type; | |
e0332712 GP |
211 | test->num_irqs = irq; |
212 | ||
213 | return res; | |
214 | } | |
215 | ||
216 | static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test) | |
217 | { | |
218 | int i; | |
219 | struct pci_dev *pdev = test->pdev; | |
220 | struct device *dev = &pdev->dev; | |
221 | ||
222 | for (i = 0; i < test->num_irqs; i++) | |
223 | devm_free_irq(dev, pci_irq_vector(pdev, i), test); | |
224 | ||
225 | test->num_irqs = 0; | |
226 | } | |
227 | ||
228 | static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test) | |
229 | { | |
230 | int i; | |
231 | int err; | |
232 | struct pci_dev *pdev = test->pdev; | |
233 | struct device *dev = &pdev->dev; | |
234 | ||
235 | for (i = 0; i < test->num_irqs; i++) { | |
236 | err = devm_request_irq(dev, pci_irq_vector(pdev, i), | |
237 | pci_endpoint_test_irqhandler, | |
c2be14ab | 238 | IRQF_SHARED, test->name, test); |
e0332712 GP |
239 | if (err) |
240 | goto fail; | |
241 | } | |
242 | ||
243 | return true; | |
244 | ||
245 | fail: | |
246 | switch (irq_type) { | |
247 | case IRQ_TYPE_LEGACY: | |
248 | dev_err(dev, "Failed to request IRQ %d for Legacy\n", | |
249 | pci_irq_vector(pdev, i)); | |
250 | break; | |
251 | case IRQ_TYPE_MSI: | |
252 | dev_err(dev, "Failed to request IRQ %d for MSI %d\n", | |
253 | pci_irq_vector(pdev, i), | |
254 | i + 1); | |
255 | break; | |
256 | case IRQ_TYPE_MSIX: | |
257 | dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n", | |
258 | pci_irq_vector(pdev, i), | |
259 | i + 1); | |
260 | break; | |
261 | } | |
262 | ||
263 | return false; | |
264 | } | |
265 | ||
516f3664 NC |
266 | static const u32 bar_test_pattern[] = { |
267 | 0xA0A0A0A0, | |
268 | 0xA1A1A1A1, | |
269 | 0xA2A2A2A2, | |
270 | 0xA3A3A3A3, | |
271 | 0xA4A4A4A4, | |
272 | 0xA5A5A5A5, | |
273 | }; | |
274 | ||
2c156ac7 KVA |
275 | static bool pci_endpoint_test_bar(struct pci_endpoint_test *test, |
276 | enum pci_barno barno) | |
277 | { | |
278 | int j; | |
279 | u32 val; | |
280 | int size; | |
cda370ec | 281 | struct pci_dev *pdev = test->pdev; |
2c156ac7 KVA |
282 | |
283 | if (!test->bar[barno]) | |
284 | return false; | |
285 | ||
cda370ec | 286 | size = pci_resource_len(pdev, barno); |
2c156ac7 | 287 | |
834b9051 KVA |
288 | if (barno == test->test_reg_bar) |
289 | size = 0x4; | |
290 | ||
2c156ac7 | 291 | for (j = 0; j < size; j += 4) |
516f3664 NC |
292 | pci_endpoint_test_bar_writel(test, barno, j, |
293 | bar_test_pattern[barno]); | |
2c156ac7 KVA |
294 | |
295 | for (j = 0; j < size; j += 4) { | |
296 | val = pci_endpoint_test_bar_readl(test, barno, j); | |
516f3664 | 297 | if (val != bar_test_pattern[barno]) |
2c156ac7 KVA |
298 | return false; |
299 | } | |
300 | ||
301 | return true; | |
302 | } | |
303 | ||
304 | static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test) | |
305 | { | |
306 | u32 val; | |
307 | ||
e8817de7 GP |
308 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, |
309 | IRQ_TYPE_LEGACY); | |
310 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0); | |
2c156ac7 KVA |
311 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
312 | COMMAND_RAISE_LEGACY_IRQ); | |
313 | val = wait_for_completion_timeout(&test->irq_raised, | |
314 | msecs_to_jiffies(1000)); | |
315 | if (!val) | |
316 | return false; | |
317 | ||
318 | return true; | |
319 | } | |
320 | ||
321 | static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test, | |
c2e00e31 | 322 | u16 msi_num, bool msix) |
2c156ac7 KVA |
323 | { |
324 | u32 val; | |
325 | struct pci_dev *pdev = test->pdev; | |
326 | ||
e8817de7 | 327 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, |
4c50f933 | 328 | msix ? IRQ_TYPE_MSIX : IRQ_TYPE_MSI); |
e8817de7 | 329 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num); |
2c156ac7 | 330 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
4c50f933 DLM |
331 | msix ? COMMAND_RAISE_MSIX_IRQ : |
332 | COMMAND_RAISE_MSI_IRQ); | |
2c156ac7 KVA |
333 | val = wait_for_completion_timeout(&test->irq_raised, |
334 | msecs_to_jiffies(1000)); | |
335 | if (!val) | |
336 | return false; | |
337 | ||
4c50f933 | 338 | return pci_irq_vector(pdev, msi_num - 1) == test->last_irq; |
2c156ac7 KVA |
339 | } |
340 | ||
3e42deaa SM |
341 | static int pci_endpoint_test_validate_xfer_params(struct device *dev, |
342 | struct pci_endpoint_test_xfer_param *param, size_t alignment) | |
343 | { | |
8e30538e SM |
344 | if (!param->size) { |
345 | dev_dbg(dev, "Data size is zero\n"); | |
346 | return -EINVAL; | |
347 | } | |
348 | ||
3e42deaa SM |
349 | if (param->size > SIZE_MAX - alignment) { |
350 | dev_dbg(dev, "Maximum transfer data size exceeded\n"); | |
351 | return -EINVAL; | |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
cf376b4b KVA |
357 | static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, |
358 | unsigned long arg) | |
2c156ac7 | 359 | { |
cf376b4b | 360 | struct pci_endpoint_test_xfer_param param; |
2c156ac7 KVA |
361 | bool ret = false; |
362 | void *src_addr; | |
363 | void *dst_addr; | |
cf376b4b KVA |
364 | u32 flags = 0; |
365 | bool use_dma; | |
366 | size_t size; | |
2c156ac7 KVA |
367 | dma_addr_t src_phys_addr; |
368 | dma_addr_t dst_phys_addr; | |
369 | struct pci_dev *pdev = test->pdev; | |
370 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
371 | void *orig_src_addr; |
372 | dma_addr_t orig_src_phys_addr; | |
373 | void *orig_dst_addr; | |
374 | dma_addr_t orig_dst_phys_addr; | |
375 | size_t offset; | |
376 | size_t alignment = test->alignment; | |
b2ba9225 | 377 | int irq_type = test->irq_type; |
2c156ac7 KVA |
378 | u32 src_crc32; |
379 | u32 dst_crc32; | |
cf376b4b | 380 | int err; |
2c156ac7 | 381 | |
cf376b4b KVA |
382 | err = copy_from_user(¶m, (void __user *)arg, sizeof(param)); |
383 | if (err) { | |
384 | dev_err(dev, "Failed to get transfer param\n"); | |
385 | return false; | |
386 | } | |
387 | ||
3e42deaa SM |
388 | err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment); |
389 | if (err) | |
390 | return false; | |
391 | ||
cf376b4b | 392 | size = param.size; |
343dc693 | 393 | |
cf376b4b KVA |
394 | use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA); |
395 | if (use_dma) | |
396 | flags |= FLAG_USE_DMA; | |
397 | ||
e0332712 GP |
398 | if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) { |
399 | dev_err(dev, "Invalid IRQ type option\n"); | |
400 | goto err; | |
401 | } | |
402 | ||
0a121f9b | 403 | orig_src_addr = kzalloc(size + alignment, GFP_KERNEL); |
13107c60 | 404 | if (!orig_src_addr) { |
0e52ea61 | 405 | dev_err(dev, "Failed to allocate source buffer\n"); |
2c156ac7 KVA |
406 | ret = false; |
407 | goto err; | |
408 | } | |
409 | ||
0a121f9b KVA |
410 | get_random_bytes(orig_src_addr, size + alignment); |
411 | orig_src_phys_addr = dma_map_single(dev, orig_src_addr, | |
412 | size + alignment, DMA_TO_DEVICE); | |
413 | if (dma_mapping_error(dev, orig_src_phys_addr)) { | |
414 | dev_err(dev, "failed to map source buffer address\n"); | |
415 | ret = false; | |
416 | goto err_src_phys_addr; | |
417 | } | |
418 | ||
13107c60 KVA |
419 | if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) { |
420 | src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment); | |
421 | offset = src_phys_addr - orig_src_phys_addr; | |
422 | src_addr = orig_src_addr + offset; | |
423 | } else { | |
424 | src_phys_addr = orig_src_phys_addr; | |
425 | src_addr = orig_src_addr; | |
426 | } | |
427 | ||
2c156ac7 KVA |
428 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR, |
429 | lower_32_bits(src_phys_addr)); | |
430 | ||
431 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR, | |
432 | upper_32_bits(src_phys_addr)); | |
433 | ||
2c156ac7 KVA |
434 | src_crc32 = crc32_le(~0, src_addr, size); |
435 | ||
0a121f9b | 436 | orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL); |
13107c60 | 437 | if (!orig_dst_addr) { |
0e52ea61 | 438 | dev_err(dev, "Failed to allocate destination address\n"); |
2c156ac7 | 439 | ret = false; |
0a121f9b KVA |
440 | goto err_dst_addr; |
441 | } | |
442 | ||
443 | orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr, | |
444 | size + alignment, DMA_FROM_DEVICE); | |
445 | if (dma_mapping_error(dev, orig_dst_phys_addr)) { | |
446 | dev_err(dev, "failed to map destination buffer address\n"); | |
447 | ret = false; | |
448 | goto err_dst_phys_addr; | |
13107c60 KVA |
449 | } |
450 | ||
451 | if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) { | |
452 | dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment); | |
453 | offset = dst_phys_addr - orig_dst_phys_addr; | |
454 | dst_addr = orig_dst_addr + offset; | |
455 | } else { | |
456 | dst_phys_addr = orig_dst_phys_addr; | |
457 | dst_addr = orig_dst_addr; | |
2c156ac7 KVA |
458 | } |
459 | ||
460 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR, | |
461 | lower_32_bits(dst_phys_addr)); | |
462 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR, | |
463 | upper_32_bits(dst_phys_addr)); | |
464 | ||
465 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, | |
466 | size); | |
467 | ||
cf376b4b | 468 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags); |
9133e394 | 469 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type); |
e8817de7 | 470 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); |
2c156ac7 | 471 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
e8817de7 | 472 | COMMAND_COPY); |
2c156ac7 KVA |
473 | |
474 | wait_for_completion(&test->irq_raised); | |
475 | ||
0a121f9b KVA |
476 | dma_unmap_single(dev, orig_dst_phys_addr, size + alignment, |
477 | DMA_FROM_DEVICE); | |
478 | ||
2c156ac7 KVA |
479 | dst_crc32 = crc32_le(~0, dst_addr, size); |
480 | if (dst_crc32 == src_crc32) | |
481 | ret = true; | |
482 | ||
0a121f9b KVA |
483 | err_dst_phys_addr: |
484 | kfree(orig_dst_addr); | |
2c156ac7 | 485 | |
0a121f9b KVA |
486 | err_dst_addr: |
487 | dma_unmap_single(dev, orig_src_phys_addr, size + alignment, | |
488 | DMA_TO_DEVICE); | |
489 | ||
490 | err_src_phys_addr: | |
491 | kfree(orig_src_addr); | |
2c156ac7 KVA |
492 | |
493 | err: | |
494 | return ret; | |
495 | } | |
496 | ||
cf376b4b KVA |
497 | static bool pci_endpoint_test_write(struct pci_endpoint_test *test, |
498 | unsigned long arg) | |
2c156ac7 | 499 | { |
cf376b4b | 500 | struct pci_endpoint_test_xfer_param param; |
2c156ac7 | 501 | bool ret = false; |
cf376b4b KVA |
502 | u32 flags = 0; |
503 | bool use_dma; | |
2c156ac7 KVA |
504 | u32 reg; |
505 | void *addr; | |
506 | dma_addr_t phys_addr; | |
507 | struct pci_dev *pdev = test->pdev; | |
508 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
509 | void *orig_addr; |
510 | dma_addr_t orig_phys_addr; | |
511 | size_t offset; | |
512 | size_t alignment = test->alignment; | |
b2ba9225 | 513 | int irq_type = test->irq_type; |
cf376b4b | 514 | size_t size; |
2c156ac7 | 515 | u32 crc32; |
cf376b4b | 516 | int err; |
2c156ac7 | 517 | |
cf376b4b KVA |
518 | err = copy_from_user(¶m, (void __user *)arg, sizeof(param)); |
519 | if (err != 0) { | |
520 | dev_err(dev, "Failed to get transfer param\n"); | |
521 | return false; | |
522 | } | |
523 | ||
3e42deaa SM |
524 | err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment); |
525 | if (err) | |
526 | return false; | |
527 | ||
cf376b4b | 528 | size = param.size; |
343dc693 | 529 | |
cf376b4b KVA |
530 | use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA); |
531 | if (use_dma) | |
532 | flags |= FLAG_USE_DMA; | |
533 | ||
e0332712 GP |
534 | if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) { |
535 | dev_err(dev, "Invalid IRQ type option\n"); | |
536 | goto err; | |
537 | } | |
538 | ||
0a121f9b | 539 | orig_addr = kzalloc(size + alignment, GFP_KERNEL); |
13107c60 | 540 | if (!orig_addr) { |
0e52ea61 | 541 | dev_err(dev, "Failed to allocate address\n"); |
2c156ac7 KVA |
542 | ret = false; |
543 | goto err; | |
544 | } | |
545 | ||
0a121f9b KVA |
546 | get_random_bytes(orig_addr, size + alignment); |
547 | ||
548 | orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment, | |
549 | DMA_TO_DEVICE); | |
550 | if (dma_mapping_error(dev, orig_phys_addr)) { | |
551 | dev_err(dev, "failed to map source buffer address\n"); | |
552 | ret = false; | |
553 | goto err_phys_addr; | |
554 | } | |
555 | ||
13107c60 KVA |
556 | if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) { |
557 | phys_addr = PTR_ALIGN(orig_phys_addr, alignment); | |
558 | offset = phys_addr - orig_phys_addr; | |
559 | addr = orig_addr + offset; | |
560 | } else { | |
561 | phys_addr = orig_phys_addr; | |
562 | addr = orig_addr; | |
563 | } | |
564 | ||
2c156ac7 KVA |
565 | crc32 = crc32_le(~0, addr, size); |
566 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM, | |
567 | crc32); | |
568 | ||
569 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR, | |
570 | lower_32_bits(phys_addr)); | |
571 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR, | |
572 | upper_32_bits(phys_addr)); | |
573 | ||
574 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | |
575 | ||
cf376b4b | 576 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags); |
9133e394 | 577 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type); |
e8817de7 | 578 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); |
2c156ac7 | 579 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
e8817de7 | 580 | COMMAND_READ); |
2c156ac7 KVA |
581 | |
582 | wait_for_completion(&test->irq_raised); | |
583 | ||
584 | reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); | |
585 | if (reg & STATUS_READ_SUCCESS) | |
586 | ret = true; | |
587 | ||
0a121f9b KVA |
588 | dma_unmap_single(dev, orig_phys_addr, size + alignment, |
589 | DMA_TO_DEVICE); | |
590 | ||
591 | err_phys_addr: | |
592 | kfree(orig_addr); | |
2c156ac7 KVA |
593 | |
594 | err: | |
595 | return ret; | |
596 | } | |
597 | ||
cf376b4b KVA |
598 | static bool pci_endpoint_test_read(struct pci_endpoint_test *test, |
599 | unsigned long arg) | |
2c156ac7 | 600 | { |
cf376b4b | 601 | struct pci_endpoint_test_xfer_param param; |
2c156ac7 | 602 | bool ret = false; |
cf376b4b KVA |
603 | u32 flags = 0; |
604 | bool use_dma; | |
605 | size_t size; | |
2c156ac7 KVA |
606 | void *addr; |
607 | dma_addr_t phys_addr; | |
608 | struct pci_dev *pdev = test->pdev; | |
609 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
610 | void *orig_addr; |
611 | dma_addr_t orig_phys_addr; | |
612 | size_t offset; | |
613 | size_t alignment = test->alignment; | |
b2ba9225 | 614 | int irq_type = test->irq_type; |
2c156ac7 | 615 | u32 crc32; |
cf376b4b | 616 | int err; |
2c156ac7 | 617 | |
cf376b4b KVA |
618 | err = copy_from_user(¶m, (void __user *)arg, sizeof(param)); |
619 | if (err) { | |
620 | dev_err(dev, "Failed to get transfer param\n"); | |
621 | return false; | |
622 | } | |
623 | ||
3e42deaa SM |
624 | err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment); |
625 | if (err) | |
626 | return false; | |
627 | ||
cf376b4b | 628 | size = param.size; |
343dc693 | 629 | |
cf376b4b KVA |
630 | use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA); |
631 | if (use_dma) | |
632 | flags |= FLAG_USE_DMA; | |
633 | ||
e0332712 GP |
634 | if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) { |
635 | dev_err(dev, "Invalid IRQ type option\n"); | |
636 | goto err; | |
637 | } | |
638 | ||
0a121f9b | 639 | orig_addr = kzalloc(size + alignment, GFP_KERNEL); |
13107c60 | 640 | if (!orig_addr) { |
0e52ea61 | 641 | dev_err(dev, "Failed to allocate destination address\n"); |
2c156ac7 KVA |
642 | ret = false; |
643 | goto err; | |
644 | } | |
645 | ||
0a121f9b KVA |
646 | orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment, |
647 | DMA_FROM_DEVICE); | |
648 | if (dma_mapping_error(dev, orig_phys_addr)) { | |
649 | dev_err(dev, "failed to map source buffer address\n"); | |
650 | ret = false; | |
651 | goto err_phys_addr; | |
652 | } | |
653 | ||
13107c60 KVA |
654 | if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) { |
655 | phys_addr = PTR_ALIGN(orig_phys_addr, alignment); | |
656 | offset = phys_addr - orig_phys_addr; | |
657 | addr = orig_addr + offset; | |
658 | } else { | |
659 | phys_addr = orig_phys_addr; | |
660 | addr = orig_addr; | |
661 | } | |
662 | ||
2c156ac7 KVA |
663 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR, |
664 | lower_32_bits(phys_addr)); | |
665 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR, | |
666 | upper_32_bits(phys_addr)); | |
667 | ||
668 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | |
669 | ||
cf376b4b | 670 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags); |
9133e394 | 671 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type); |
e8817de7 | 672 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); |
2c156ac7 | 673 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
e8817de7 | 674 | COMMAND_WRITE); |
2c156ac7 KVA |
675 | |
676 | wait_for_completion(&test->irq_raised); | |
677 | ||
0a121f9b KVA |
678 | dma_unmap_single(dev, orig_phys_addr, size + alignment, |
679 | DMA_FROM_DEVICE); | |
680 | ||
2c156ac7 KVA |
681 | crc32 = crc32_le(~0, addr, size); |
682 | if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM)) | |
683 | ret = true; | |
684 | ||
0a121f9b KVA |
685 | err_phys_addr: |
686 | kfree(orig_addr); | |
2c156ac7 KVA |
687 | err: |
688 | return ret; | |
689 | } | |
690 | ||
475007f9 KVA |
691 | static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test) |
692 | { | |
693 | pci_endpoint_test_release_irq(test); | |
694 | pci_endpoint_test_free_irq_vectors(test); | |
695 | return true; | |
696 | } | |
697 | ||
e0332712 GP |
698 | static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test, |
699 | int req_irq_type) | |
700 | { | |
701 | struct pci_dev *pdev = test->pdev; | |
702 | struct device *dev = &pdev->dev; | |
703 | ||
704 | if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) { | |
705 | dev_err(dev, "Invalid IRQ type option\n"); | |
706 | return false; | |
707 | } | |
708 | ||
b2ba9225 | 709 | if (test->irq_type == req_irq_type) |
e0332712 GP |
710 | return true; |
711 | ||
712 | pci_endpoint_test_release_irq(test); | |
713 | pci_endpoint_test_free_irq_vectors(test); | |
714 | ||
715 | if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type)) | |
716 | goto err; | |
717 | ||
718 | if (!pci_endpoint_test_request_irq(test)) | |
719 | goto err; | |
720 | ||
e0332712 GP |
721 | return true; |
722 | ||
723 | err: | |
724 | pci_endpoint_test_free_irq_vectors(test); | |
e0332712 GP |
725 | return false; |
726 | } | |
727 | ||
2c156ac7 KVA |
728 | static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, |
729 | unsigned long arg) | |
730 | { | |
731 | int ret = -EINVAL; | |
732 | enum pci_barno bar; | |
733 | struct pci_endpoint_test *test = to_endpoint_test(file->private_data); | |
5bb04b19 | 734 | struct pci_dev *pdev = test->pdev; |
2c156ac7 KVA |
735 | |
736 | mutex_lock(&test->mutex); | |
fb620ae7 DLM |
737 | |
738 | reinit_completion(&test->irq_raised); | |
739 | test->last_irq = -ENODATA; | |
740 | ||
2c156ac7 KVA |
741 | switch (cmd) { |
742 | case PCITEST_BAR: | |
743 | bar = arg; | |
33fcc549 | 744 | if (bar > BAR_5) |
2c156ac7 | 745 | goto ret; |
5bb04b19 KVA |
746 | if (is_am654_pci_dev(pdev) && bar == BAR_0) |
747 | goto ret; | |
2c156ac7 KVA |
748 | ret = pci_endpoint_test_bar(test, bar); |
749 | break; | |
750 | case PCITEST_LEGACY_IRQ: | |
751 | ret = pci_endpoint_test_legacy_irq(test); | |
752 | break; | |
753 | case PCITEST_MSI: | |
c2e00e31 GP |
754 | case PCITEST_MSIX: |
755 | ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX); | |
2c156ac7 KVA |
756 | break; |
757 | case PCITEST_WRITE: | |
758 | ret = pci_endpoint_test_write(test, arg); | |
759 | break; | |
760 | case PCITEST_READ: | |
761 | ret = pci_endpoint_test_read(test, arg); | |
762 | break; | |
763 | case PCITEST_COPY: | |
764 | ret = pci_endpoint_test_copy(test, arg); | |
765 | break; | |
e0332712 GP |
766 | case PCITEST_SET_IRQTYPE: |
767 | ret = pci_endpoint_test_set_irq(test, arg); | |
768 | break; | |
769 | case PCITEST_GET_IRQTYPE: | |
770 | ret = irq_type; | |
771 | break; | |
475007f9 KVA |
772 | case PCITEST_CLEAR_IRQ: |
773 | ret = pci_endpoint_test_clear_irq(test); | |
774 | break; | |
2c156ac7 KVA |
775 | } |
776 | ||
777 | ret: | |
778 | mutex_unlock(&test->mutex); | |
779 | return ret; | |
780 | } | |
781 | ||
782 | static const struct file_operations pci_endpoint_test_fops = { | |
783 | .owner = THIS_MODULE, | |
784 | .unlocked_ioctl = pci_endpoint_test_ioctl, | |
785 | }; | |
786 | ||
787 | static int pci_endpoint_test_probe(struct pci_dev *pdev, | |
788 | const struct pci_device_id *ent) | |
789 | { | |
2c156ac7 | 790 | int err; |
2c156ac7 | 791 | int id; |
6b443e5c | 792 | char name[24]; |
2c156ac7 KVA |
793 | enum pci_barno bar; |
794 | void __iomem *base; | |
795 | struct device *dev = &pdev->dev; | |
796 | struct pci_endpoint_test *test; | |
834b9051 KVA |
797 | struct pci_endpoint_test_data *data; |
798 | enum pci_barno test_reg_bar = BAR_0; | |
2c156ac7 KVA |
799 | struct miscdevice *misc_device; |
800 | ||
801 | if (pci_is_bridge(pdev)) | |
802 | return -ENODEV; | |
803 | ||
804 | test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL); | |
805 | if (!test) | |
806 | return -ENOMEM; | |
807 | ||
834b9051 | 808 | test->test_reg_bar = 0; |
13107c60 | 809 | test->alignment = 0; |
2c156ac7 | 810 | test->pdev = pdev; |
b2ba9225 | 811 | test->irq_type = IRQ_TYPE_UNDEFINED; |
834b9051 | 812 | |
9133e394 GP |
813 | if (no_msi) |
814 | irq_type = IRQ_TYPE_LEGACY; | |
815 | ||
834b9051 | 816 | data = (struct pci_endpoint_test_data *)ent->driver_data; |
13107c60 | 817 | if (data) { |
834b9051 | 818 | test_reg_bar = data->test_reg_bar; |
8f220664 | 819 | test->test_reg_bar = test_reg_bar; |
13107c60 | 820 | test->alignment = data->alignment; |
9133e394 | 821 | irq_type = data->irq_type; |
13107c60 | 822 | } |
834b9051 | 823 | |
2c156ac7 KVA |
824 | init_completion(&test->irq_raised); |
825 | mutex_init(&test->mutex); | |
826 | ||
0a121f9b KVA |
827 | if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) && |
828 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { | |
829 | dev_err(dev, "Cannot set DMA mask\n"); | |
830 | return -EINVAL; | |
831 | } | |
832 | ||
2c156ac7 KVA |
833 | err = pci_enable_device(pdev); |
834 | if (err) { | |
835 | dev_err(dev, "Cannot enable PCI device\n"); | |
836 | return err; | |
837 | } | |
838 | ||
839 | err = pci_request_regions(pdev, DRV_MODULE_NAME); | |
840 | if (err) { | |
841 | dev_err(dev, "Cannot obtain PCI resources\n"); | |
842 | goto err_disable_pdev; | |
843 | } | |
844 | ||
845 | pci_set_master(pdev); | |
846 | ||
1749c904 XW |
847 | if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) { |
848 | err = -EINVAL; | |
e0332712 | 849 | goto err_disable_irq; |
1749c904 | 850 | } |
2c156ac7 | 851 | |
c9c13ba4 | 852 | for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { |
16b17cad NC |
853 | if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
854 | base = pci_ioremap_bar(pdev, bar); | |
855 | if (!base) { | |
0e52ea61 | 856 | dev_err(dev, "Failed to read BAR%d\n", bar); |
16b17cad NC |
857 | WARN_ON(bar == test_reg_bar); |
858 | } | |
859 | test->bar[bar] = base; | |
2c156ac7 | 860 | } |
2c156ac7 KVA |
861 | } |
862 | ||
834b9051 | 863 | test->base = test->bar[test_reg_bar]; |
2c156ac7 | 864 | if (!test->base) { |
80068c93 | 865 | err = -ENOMEM; |
834b9051 KVA |
866 | dev_err(dev, "Cannot perform PCI test without BAR%d\n", |
867 | test_reg_bar); | |
2c156ac7 KVA |
868 | goto err_iounmap; |
869 | } | |
870 | ||
871 | pci_set_drvdata(pdev, test); | |
872 | ||
873 | id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL); | |
874 | if (id < 0) { | |
80068c93 | 875 | err = id; |
0e52ea61 | 876 | dev_err(dev, "Unable to get id\n"); |
2c156ac7 KVA |
877 | goto err_iounmap; |
878 | } | |
879 | ||
880 | snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id); | |
c2be14ab KVA |
881 | test->name = kstrdup(name, GFP_KERNEL); |
882 | if (!test->name) { | |
883 | err = -ENOMEM; | |
884 | goto err_ida_remove; | |
885 | } | |
886 | ||
1749c904 XW |
887 | if (!pci_endpoint_test_request_irq(test)) { |
888 | err = -EINVAL; | |
c2be14ab | 889 | goto err_kfree_test_name; |
1749c904 | 890 | } |
c2be14ab | 891 | |
2c156ac7 KVA |
892 | misc_device = &test->miscdev; |
893 | misc_device->minor = MISC_DYNAMIC_MINOR; | |
139838ff KVA |
894 | misc_device->name = kstrdup(name, GFP_KERNEL); |
895 | if (!misc_device->name) { | |
896 | err = -ENOMEM; | |
c2be14ab | 897 | goto err_release_irq; |
139838ff | 898 | } |
74a03c20 | 899 | misc_device->parent = &pdev->dev; |
560dbc46 | 900 | misc_device->fops = &pci_endpoint_test_fops; |
2c156ac7 KVA |
901 | |
902 | err = misc_register(misc_device); | |
903 | if (err) { | |
0e52ea61 | 904 | dev_err(dev, "Failed to register device\n"); |
139838ff | 905 | goto err_kfree_name; |
2c156ac7 KVA |
906 | } |
907 | ||
908 | return 0; | |
909 | ||
139838ff KVA |
910 | err_kfree_name: |
911 | kfree(misc_device->name); | |
912 | ||
c2be14ab KVA |
913 | err_release_irq: |
914 | pci_endpoint_test_release_irq(test); | |
915 | ||
916 | err_kfree_test_name: | |
917 | kfree(test->name); | |
918 | ||
2c156ac7 KVA |
919 | err_ida_remove: |
920 | ida_simple_remove(&pci_endpoint_test_ida, id); | |
921 | ||
922 | err_iounmap: | |
c9c13ba4 | 923 | for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { |
2c156ac7 KVA |
924 | if (test->bar[bar]) |
925 | pci_iounmap(pdev, test->bar[bar]); | |
926 | } | |
927 | ||
e0332712 GP |
928 | err_disable_irq: |
929 | pci_endpoint_test_free_irq_vectors(test); | |
2c156ac7 KVA |
930 | pci_release_regions(pdev); |
931 | ||
932 | err_disable_pdev: | |
933 | pci_disable_device(pdev); | |
934 | ||
935 | return err; | |
936 | } | |
937 | ||
938 | static void pci_endpoint_test_remove(struct pci_dev *pdev) | |
939 | { | |
940 | int id; | |
941 | enum pci_barno bar; | |
942 | struct pci_endpoint_test *test = pci_get_drvdata(pdev); | |
943 | struct miscdevice *misc_device = &test->miscdev; | |
944 | ||
945 | if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1) | |
946 | return; | |
a2db2663 DC |
947 | if (id < 0) |
948 | return; | |
2c156ac7 | 949 | |
f61b7634 DLM |
950 | pci_endpoint_test_release_irq(test); |
951 | pci_endpoint_test_free_irq_vectors(test); | |
952 | ||
2c156ac7 | 953 | misc_deregister(&test->miscdev); |
139838ff | 954 | kfree(misc_device->name); |
c2be14ab | 955 | kfree(test->name); |
2c156ac7 | 956 | ida_simple_remove(&pci_endpoint_test_ida, id); |
c9c13ba4 | 957 | for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { |
2c156ac7 KVA |
958 | if (test->bar[bar]) |
959 | pci_iounmap(pdev, test->bar[bar]); | |
960 | } | |
e0332712 | 961 | |
2c156ac7 KVA |
962 | pci_release_regions(pdev); |
963 | pci_disable_device(pdev); | |
964 | } | |
965 | ||
0a121f9b KVA |
966 | static const struct pci_endpoint_test_data default_data = { |
967 | .test_reg_bar = BAR_0, | |
968 | .alignment = SZ_4K, | |
969 | .irq_type = IRQ_TYPE_MSI, | |
970 | }; | |
971 | ||
5bb04b19 KVA |
972 | static const struct pci_endpoint_test_data am654_data = { |
973 | .test_reg_bar = BAR_2, | |
974 | .alignment = SZ_64K, | |
975 | .irq_type = IRQ_TYPE_MSI, | |
976 | }; | |
977 | ||
6546ae29 KVA |
978 | static const struct pci_endpoint_test_data j721e_data = { |
979 | .alignment = 256, | |
980 | .irq_type = IRQ_TYPE_MSI, | |
981 | }; | |
982 | ||
2c156ac7 | 983 | static const struct pci_device_id pci_endpoint_test_tbl[] = { |
0a121f9b KVA |
984 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x), |
985 | .driver_data = (kernel_ulong_t)&default_data, | |
986 | }, | |
987 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x), | |
988 | .driver_data = (kernel_ulong_t)&default_data, | |
989 | }, | |
09fb37b3 HZ |
990 | { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0), |
991 | .driver_data = (kernel_ulong_t)&default_data, | |
992 | }, | |
01ea5ede | 993 | { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_IMX8),}, |
09fb37b3 HZ |
994 | { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A), |
995 | .driver_data = (kernel_ulong_t)&default_data, | |
996 | }, | |
1f418f46 | 997 | { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) }, |
5bb04b19 KVA |
998 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), |
999 | .driver_data = (kernel_ulong_t)&am654_data | |
1000 | }, | |
cfb824dd LP |
1001 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),}, |
1002 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),}, | |
1003 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),}, | |
a63c5f3d | 1004 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),}, |
6c4b3993 YS |
1005 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0), |
1006 | .driver_data = (kernel_ulong_t)&default_data, | |
1007 | }, | |
6546ae29 KVA |
1008 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E), |
1009 | .driver_data = (kernel_ulong_t)&j721e_data, | |
1010 | }, | |
7c52009d KVA |
1011 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200), |
1012 | .driver_data = (kernel_ulong_t)&j721e_data, | |
1013 | }, | |
1014 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64), | |
1015 | .driver_data = (kernel_ulong_t)&j721e_data, | |
1016 | }, | |
8293703a SV |
1017 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721S2), |
1018 | .driver_data = (kernel_ulong_t)&j721e_data, | |
1019 | }, | |
2c156ac7 KVA |
1020 | { } |
1021 | }; | |
1022 | MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); | |
1023 | ||
1024 | static struct pci_driver pci_endpoint_test_driver = { | |
1025 | .name = DRV_MODULE_NAME, | |
1026 | .id_table = pci_endpoint_test_tbl, | |
1027 | .probe = pci_endpoint_test_probe, | |
1028 | .remove = pci_endpoint_test_remove, | |
489b1f41 | 1029 | .sriov_configure = pci_sriov_configure_simple, |
2c156ac7 KVA |
1030 | }; |
1031 | module_pci_driver(pci_endpoint_test_driver); | |
1032 | ||
1033 | MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER"); | |
1034 | MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); | |
1035 | MODULE_LICENSE("GPL v2"); |