Commit | Line | Data |
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6b1baefe | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2c156ac7 KVA |
2 | /** |
3 | * Host side test driver to test endpoint functionality | |
4 | * | |
5 | * Copyright (C) 2017 Texas Instruments | |
6 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | |
2c156ac7 KVA |
7 | */ |
8 | ||
9 | #include <linux/crc32.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/fs.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/mutex.h> | |
18 | #include <linux/random.h> | |
19 | #include <linux/slab.h> | |
cf376b4b | 20 | #include <linux/uaccess.h> |
2c156ac7 KVA |
21 | #include <linux/pci.h> |
22 | #include <linux/pci_ids.h> | |
23 | ||
24 | #include <linux/pci_regs.h> | |
25 | ||
26 | #include <uapi/linux/pcitest.h> | |
27 | ||
e8817de7 GP |
28 | #define DRV_MODULE_NAME "pci-endpoint-test" |
29 | ||
e0332712 | 30 | #define IRQ_TYPE_UNDEFINED -1 |
e8817de7 GP |
31 | #define IRQ_TYPE_LEGACY 0 |
32 | #define IRQ_TYPE_MSI 1 | |
c2e00e31 | 33 | #define IRQ_TYPE_MSIX 2 |
e8817de7 GP |
34 | |
35 | #define PCI_ENDPOINT_TEST_MAGIC 0x0 | |
36 | ||
37 | #define PCI_ENDPOINT_TEST_COMMAND 0x4 | |
38 | #define COMMAND_RAISE_LEGACY_IRQ BIT(0) | |
39 | #define COMMAND_RAISE_MSI_IRQ BIT(1) | |
c2e00e31 | 40 | #define COMMAND_RAISE_MSIX_IRQ BIT(2) |
e8817de7 GP |
41 | #define COMMAND_READ BIT(3) |
42 | #define COMMAND_WRITE BIT(4) | |
43 | #define COMMAND_COPY BIT(5) | |
44 | ||
45 | #define PCI_ENDPOINT_TEST_STATUS 0x8 | |
46 | #define STATUS_READ_SUCCESS BIT(0) | |
47 | #define STATUS_READ_FAIL BIT(1) | |
48 | #define STATUS_WRITE_SUCCESS BIT(2) | |
49 | #define STATUS_WRITE_FAIL BIT(3) | |
50 | #define STATUS_COPY_SUCCESS BIT(4) | |
51 | #define STATUS_COPY_FAIL BIT(5) | |
52 | #define STATUS_IRQ_RAISED BIT(6) | |
53 | #define STATUS_SRC_ADDR_INVALID BIT(7) | |
54 | #define STATUS_DST_ADDR_INVALID BIT(8) | |
55 | ||
56 | #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c | |
2c156ac7 KVA |
57 | #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10 |
58 | ||
59 | #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14 | |
60 | #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18 | |
61 | ||
e8817de7 GP |
62 | #define PCI_ENDPOINT_TEST_SIZE 0x1c |
63 | #define PCI_ENDPOINT_TEST_CHECKSUM 0x20 | |
64 | ||
65 | #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 | |
66 | #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 | |
2c156ac7 | 67 | |
cf376b4b KVA |
68 | #define PCI_ENDPOINT_TEST_FLAGS 0x2c |
69 | #define FLAG_USE_DMA BIT(0) | |
70 | ||
5bb04b19 | 71 | #define PCI_DEVICE_ID_TI_AM654 0xb00c |
7c52009d KVA |
72 | #define PCI_DEVICE_ID_TI_J7200 0xb00f |
73 | #define PCI_DEVICE_ID_TI_AM64 0xb010 | |
6b8ab421 | 74 | #define PCI_DEVICE_ID_LS1088A 0x80c0 |
5bb04b19 KVA |
75 | |
76 | #define is_am654_pci_dev(pdev) \ | |
77 | ((pdev)->device == PCI_DEVICE_ID_TI_AM654) | |
78 | ||
cfb824dd LP |
79 | #define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028 |
80 | #define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b | |
b03025c5 | 81 | #define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d |
a63c5f3d | 82 | #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025 |
b03025c5 | 83 | |
2c156ac7 KVA |
84 | static DEFINE_IDA(pci_endpoint_test_ida); |
85 | ||
86 | #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ | |
87 | miscdev) | |
0c8a5f9d KVA |
88 | |
89 | static bool no_msi; | |
90 | module_param(no_msi, bool, 0444); | |
91 | MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test"); | |
92 | ||
9133e394 GP |
93 | static int irq_type = IRQ_TYPE_MSI; |
94 | module_param(irq_type, int, 0444); | |
c2e00e31 | 95 | MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)"); |
9133e394 | 96 | |
2c156ac7 KVA |
97 | enum pci_barno { |
98 | BAR_0, | |
99 | BAR_1, | |
100 | BAR_2, | |
101 | BAR_3, | |
102 | BAR_4, | |
103 | BAR_5, | |
104 | }; | |
105 | ||
106 | struct pci_endpoint_test { | |
107 | struct pci_dev *pdev; | |
108 | void __iomem *base; | |
c9c13ba4 | 109 | void __iomem *bar[PCI_STD_NUM_BARS]; |
2c156ac7 KVA |
110 | struct completion irq_raised; |
111 | int last_irq; | |
b7636e81 | 112 | int num_irqs; |
b2ba9225 | 113 | int irq_type; |
2c156ac7 KVA |
114 | /* mutex to protect the ioctls */ |
115 | struct mutex mutex; | |
116 | struct miscdevice miscdev; | |
834b9051 | 117 | enum pci_barno test_reg_bar; |
13107c60 | 118 | size_t alignment; |
c2be14ab | 119 | const char *name; |
2c156ac7 KVA |
120 | }; |
121 | ||
834b9051 KVA |
122 | struct pci_endpoint_test_data { |
123 | enum pci_barno test_reg_bar; | |
13107c60 | 124 | size_t alignment; |
9133e394 | 125 | int irq_type; |
834b9051 KVA |
126 | }; |
127 | ||
2c156ac7 KVA |
128 | static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test, |
129 | u32 offset) | |
130 | { | |
131 | return readl(test->base + offset); | |
132 | } | |
133 | ||
134 | static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test, | |
135 | u32 offset, u32 value) | |
136 | { | |
137 | writel(value, test->base + offset); | |
138 | } | |
139 | ||
140 | static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test, | |
141 | int bar, int offset) | |
142 | { | |
143 | return readl(test->bar[bar] + offset); | |
144 | } | |
145 | ||
146 | static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test, | |
147 | int bar, u32 offset, u32 value) | |
148 | { | |
149 | writel(value, test->bar[bar] + offset); | |
150 | } | |
151 | ||
152 | static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id) | |
153 | { | |
154 | struct pci_endpoint_test *test = dev_id; | |
155 | u32 reg; | |
156 | ||
157 | reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); | |
158 | if (reg & STATUS_IRQ_RAISED) { | |
159 | test->last_irq = irq; | |
160 | complete(&test->irq_raised); | |
161 | reg &= ~STATUS_IRQ_RAISED; | |
162 | } | |
163 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS, | |
164 | reg); | |
165 | ||
166 | return IRQ_HANDLED; | |
167 | } | |
168 | ||
e0332712 GP |
169 | static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test) |
170 | { | |
171 | struct pci_dev *pdev = test->pdev; | |
172 | ||
173 | pci_free_irq_vectors(pdev); | |
b2ba9225 | 174 | test->irq_type = IRQ_TYPE_UNDEFINED; |
e0332712 GP |
175 | } |
176 | ||
177 | static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test, | |
178 | int type) | |
179 | { | |
180 | int irq = -1; | |
181 | struct pci_dev *pdev = test->pdev; | |
182 | struct device *dev = &pdev->dev; | |
183 | bool res = true; | |
184 | ||
185 | switch (type) { | |
186 | case IRQ_TYPE_LEGACY: | |
187 | irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY); | |
188 | if (irq < 0) | |
189 | dev_err(dev, "Failed to get Legacy interrupt\n"); | |
190 | break; | |
191 | case IRQ_TYPE_MSI: | |
192 | irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI); | |
193 | if (irq < 0) | |
194 | dev_err(dev, "Failed to get MSI interrupts\n"); | |
195 | break; | |
196 | case IRQ_TYPE_MSIX: | |
197 | irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX); | |
198 | if (irq < 0) | |
199 | dev_err(dev, "Failed to get MSI-X interrupts\n"); | |
200 | break; | |
201 | default: | |
202 | dev_err(dev, "Invalid IRQ type selected\n"); | |
203 | } | |
204 | ||
205 | if (irq < 0) { | |
206 | irq = 0; | |
207 | res = false; | |
208 | } | |
b2ba9225 KVA |
209 | |
210 | test->irq_type = type; | |
e0332712 GP |
211 | test->num_irqs = irq; |
212 | ||
213 | return res; | |
214 | } | |
215 | ||
216 | static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test) | |
217 | { | |
218 | int i; | |
219 | struct pci_dev *pdev = test->pdev; | |
220 | struct device *dev = &pdev->dev; | |
221 | ||
222 | for (i = 0; i < test->num_irqs; i++) | |
223 | devm_free_irq(dev, pci_irq_vector(pdev, i), test); | |
224 | ||
225 | test->num_irqs = 0; | |
226 | } | |
227 | ||
228 | static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test) | |
229 | { | |
230 | int i; | |
231 | int err; | |
232 | struct pci_dev *pdev = test->pdev; | |
233 | struct device *dev = &pdev->dev; | |
234 | ||
235 | for (i = 0; i < test->num_irqs; i++) { | |
236 | err = devm_request_irq(dev, pci_irq_vector(pdev, i), | |
237 | pci_endpoint_test_irqhandler, | |
c2be14ab | 238 | IRQF_SHARED, test->name, test); |
e0332712 GP |
239 | if (err) |
240 | goto fail; | |
241 | } | |
242 | ||
243 | return true; | |
244 | ||
245 | fail: | |
246 | switch (irq_type) { | |
247 | case IRQ_TYPE_LEGACY: | |
248 | dev_err(dev, "Failed to request IRQ %d for Legacy\n", | |
249 | pci_irq_vector(pdev, i)); | |
250 | break; | |
251 | case IRQ_TYPE_MSI: | |
252 | dev_err(dev, "Failed to request IRQ %d for MSI %d\n", | |
253 | pci_irq_vector(pdev, i), | |
254 | i + 1); | |
255 | break; | |
256 | case IRQ_TYPE_MSIX: | |
257 | dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n", | |
258 | pci_irq_vector(pdev, i), | |
259 | i + 1); | |
260 | break; | |
261 | } | |
262 | ||
263 | return false; | |
264 | } | |
265 | ||
2c156ac7 KVA |
266 | static bool pci_endpoint_test_bar(struct pci_endpoint_test *test, |
267 | enum pci_barno barno) | |
268 | { | |
269 | int j; | |
270 | u32 val; | |
271 | int size; | |
cda370ec | 272 | struct pci_dev *pdev = test->pdev; |
2c156ac7 KVA |
273 | |
274 | if (!test->bar[barno]) | |
275 | return false; | |
276 | ||
cda370ec | 277 | size = pci_resource_len(pdev, barno); |
2c156ac7 | 278 | |
834b9051 KVA |
279 | if (barno == test->test_reg_bar) |
280 | size = 0x4; | |
281 | ||
2c156ac7 KVA |
282 | for (j = 0; j < size; j += 4) |
283 | pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0); | |
284 | ||
285 | for (j = 0; j < size; j += 4) { | |
286 | val = pci_endpoint_test_bar_readl(test, barno, j); | |
287 | if (val != 0xA0A0A0A0) | |
288 | return false; | |
289 | } | |
290 | ||
291 | return true; | |
292 | } | |
293 | ||
294 | static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test) | |
295 | { | |
296 | u32 val; | |
297 | ||
e8817de7 GP |
298 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, |
299 | IRQ_TYPE_LEGACY); | |
300 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0); | |
2c156ac7 KVA |
301 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
302 | COMMAND_RAISE_LEGACY_IRQ); | |
303 | val = wait_for_completion_timeout(&test->irq_raised, | |
304 | msecs_to_jiffies(1000)); | |
305 | if (!val) | |
306 | return false; | |
307 | ||
308 | return true; | |
309 | } | |
310 | ||
311 | static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test, | |
c2e00e31 | 312 | u16 msi_num, bool msix) |
2c156ac7 KVA |
313 | { |
314 | u32 val; | |
315 | struct pci_dev *pdev = test->pdev; | |
316 | ||
e8817de7 | 317 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, |
c2e00e31 GP |
318 | msix == false ? IRQ_TYPE_MSI : |
319 | IRQ_TYPE_MSIX); | |
e8817de7 | 320 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num); |
2c156ac7 | 321 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
c2e00e31 GP |
322 | msix == false ? COMMAND_RAISE_MSI_IRQ : |
323 | COMMAND_RAISE_MSIX_IRQ); | |
2c156ac7 KVA |
324 | val = wait_for_completion_timeout(&test->irq_raised, |
325 | msecs_to_jiffies(1000)); | |
326 | if (!val) | |
327 | return false; | |
328 | ||
ecc57efe | 329 | if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq) |
2c156ac7 KVA |
330 | return true; |
331 | ||
332 | return false; | |
333 | } | |
334 | ||
3e42deaa SM |
335 | static int pci_endpoint_test_validate_xfer_params(struct device *dev, |
336 | struct pci_endpoint_test_xfer_param *param, size_t alignment) | |
337 | { | |
8e30538e SM |
338 | if (!param->size) { |
339 | dev_dbg(dev, "Data size is zero\n"); | |
340 | return -EINVAL; | |
341 | } | |
342 | ||
3e42deaa SM |
343 | if (param->size > SIZE_MAX - alignment) { |
344 | dev_dbg(dev, "Maximum transfer data size exceeded\n"); | |
345 | return -EINVAL; | |
346 | } | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
cf376b4b KVA |
351 | static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, |
352 | unsigned long arg) | |
2c156ac7 | 353 | { |
cf376b4b | 354 | struct pci_endpoint_test_xfer_param param; |
2c156ac7 KVA |
355 | bool ret = false; |
356 | void *src_addr; | |
357 | void *dst_addr; | |
cf376b4b KVA |
358 | u32 flags = 0; |
359 | bool use_dma; | |
360 | size_t size; | |
2c156ac7 KVA |
361 | dma_addr_t src_phys_addr; |
362 | dma_addr_t dst_phys_addr; | |
363 | struct pci_dev *pdev = test->pdev; | |
364 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
365 | void *orig_src_addr; |
366 | dma_addr_t orig_src_phys_addr; | |
367 | void *orig_dst_addr; | |
368 | dma_addr_t orig_dst_phys_addr; | |
369 | size_t offset; | |
370 | size_t alignment = test->alignment; | |
b2ba9225 | 371 | int irq_type = test->irq_type; |
2c156ac7 KVA |
372 | u32 src_crc32; |
373 | u32 dst_crc32; | |
cf376b4b | 374 | int err; |
2c156ac7 | 375 | |
cf376b4b KVA |
376 | err = copy_from_user(¶m, (void __user *)arg, sizeof(param)); |
377 | if (err) { | |
378 | dev_err(dev, "Failed to get transfer param\n"); | |
379 | return false; | |
380 | } | |
381 | ||
3e42deaa SM |
382 | err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment); |
383 | if (err) | |
384 | return false; | |
385 | ||
cf376b4b | 386 | size = param.size; |
343dc693 | 387 | |
cf376b4b KVA |
388 | use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA); |
389 | if (use_dma) | |
390 | flags |= FLAG_USE_DMA; | |
391 | ||
e0332712 GP |
392 | if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) { |
393 | dev_err(dev, "Invalid IRQ type option\n"); | |
394 | goto err; | |
395 | } | |
396 | ||
0a121f9b | 397 | orig_src_addr = kzalloc(size + alignment, GFP_KERNEL); |
13107c60 | 398 | if (!orig_src_addr) { |
0e52ea61 | 399 | dev_err(dev, "Failed to allocate source buffer\n"); |
2c156ac7 KVA |
400 | ret = false; |
401 | goto err; | |
402 | } | |
403 | ||
0a121f9b KVA |
404 | get_random_bytes(orig_src_addr, size + alignment); |
405 | orig_src_phys_addr = dma_map_single(dev, orig_src_addr, | |
406 | size + alignment, DMA_TO_DEVICE); | |
407 | if (dma_mapping_error(dev, orig_src_phys_addr)) { | |
408 | dev_err(dev, "failed to map source buffer address\n"); | |
409 | ret = false; | |
410 | goto err_src_phys_addr; | |
411 | } | |
412 | ||
13107c60 KVA |
413 | if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) { |
414 | src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment); | |
415 | offset = src_phys_addr - orig_src_phys_addr; | |
416 | src_addr = orig_src_addr + offset; | |
417 | } else { | |
418 | src_phys_addr = orig_src_phys_addr; | |
419 | src_addr = orig_src_addr; | |
420 | } | |
421 | ||
2c156ac7 KVA |
422 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR, |
423 | lower_32_bits(src_phys_addr)); | |
424 | ||
425 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR, | |
426 | upper_32_bits(src_phys_addr)); | |
427 | ||
2c156ac7 KVA |
428 | src_crc32 = crc32_le(~0, src_addr, size); |
429 | ||
0a121f9b | 430 | orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL); |
13107c60 | 431 | if (!orig_dst_addr) { |
0e52ea61 | 432 | dev_err(dev, "Failed to allocate destination address\n"); |
2c156ac7 | 433 | ret = false; |
0a121f9b KVA |
434 | goto err_dst_addr; |
435 | } | |
436 | ||
437 | orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr, | |
438 | size + alignment, DMA_FROM_DEVICE); | |
439 | if (dma_mapping_error(dev, orig_dst_phys_addr)) { | |
440 | dev_err(dev, "failed to map destination buffer address\n"); | |
441 | ret = false; | |
442 | goto err_dst_phys_addr; | |
13107c60 KVA |
443 | } |
444 | ||
445 | if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) { | |
446 | dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment); | |
447 | offset = dst_phys_addr - orig_dst_phys_addr; | |
448 | dst_addr = orig_dst_addr + offset; | |
449 | } else { | |
450 | dst_phys_addr = orig_dst_phys_addr; | |
451 | dst_addr = orig_dst_addr; | |
2c156ac7 KVA |
452 | } |
453 | ||
454 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR, | |
455 | lower_32_bits(dst_phys_addr)); | |
456 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR, | |
457 | upper_32_bits(dst_phys_addr)); | |
458 | ||
459 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, | |
460 | size); | |
461 | ||
cf376b4b | 462 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags); |
9133e394 | 463 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type); |
e8817de7 | 464 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); |
2c156ac7 | 465 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
e8817de7 | 466 | COMMAND_COPY); |
2c156ac7 KVA |
467 | |
468 | wait_for_completion(&test->irq_raised); | |
469 | ||
0a121f9b KVA |
470 | dma_unmap_single(dev, orig_dst_phys_addr, size + alignment, |
471 | DMA_FROM_DEVICE); | |
472 | ||
2c156ac7 KVA |
473 | dst_crc32 = crc32_le(~0, dst_addr, size); |
474 | if (dst_crc32 == src_crc32) | |
475 | ret = true; | |
476 | ||
0a121f9b KVA |
477 | err_dst_phys_addr: |
478 | kfree(orig_dst_addr); | |
2c156ac7 | 479 | |
0a121f9b KVA |
480 | err_dst_addr: |
481 | dma_unmap_single(dev, orig_src_phys_addr, size + alignment, | |
482 | DMA_TO_DEVICE); | |
483 | ||
484 | err_src_phys_addr: | |
485 | kfree(orig_src_addr); | |
2c156ac7 KVA |
486 | |
487 | err: | |
488 | return ret; | |
489 | } | |
490 | ||
cf376b4b KVA |
491 | static bool pci_endpoint_test_write(struct pci_endpoint_test *test, |
492 | unsigned long arg) | |
2c156ac7 | 493 | { |
cf376b4b | 494 | struct pci_endpoint_test_xfer_param param; |
2c156ac7 | 495 | bool ret = false; |
cf376b4b KVA |
496 | u32 flags = 0; |
497 | bool use_dma; | |
2c156ac7 KVA |
498 | u32 reg; |
499 | void *addr; | |
500 | dma_addr_t phys_addr; | |
501 | struct pci_dev *pdev = test->pdev; | |
502 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
503 | void *orig_addr; |
504 | dma_addr_t orig_phys_addr; | |
505 | size_t offset; | |
506 | size_t alignment = test->alignment; | |
b2ba9225 | 507 | int irq_type = test->irq_type; |
cf376b4b | 508 | size_t size; |
2c156ac7 | 509 | u32 crc32; |
cf376b4b | 510 | int err; |
2c156ac7 | 511 | |
cf376b4b KVA |
512 | err = copy_from_user(¶m, (void __user *)arg, sizeof(param)); |
513 | if (err != 0) { | |
514 | dev_err(dev, "Failed to get transfer param\n"); | |
515 | return false; | |
516 | } | |
517 | ||
3e42deaa SM |
518 | err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment); |
519 | if (err) | |
520 | return false; | |
521 | ||
cf376b4b | 522 | size = param.size; |
343dc693 | 523 | |
cf376b4b KVA |
524 | use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA); |
525 | if (use_dma) | |
526 | flags |= FLAG_USE_DMA; | |
527 | ||
e0332712 GP |
528 | if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) { |
529 | dev_err(dev, "Invalid IRQ type option\n"); | |
530 | goto err; | |
531 | } | |
532 | ||
0a121f9b | 533 | orig_addr = kzalloc(size + alignment, GFP_KERNEL); |
13107c60 | 534 | if (!orig_addr) { |
0e52ea61 | 535 | dev_err(dev, "Failed to allocate address\n"); |
2c156ac7 KVA |
536 | ret = false; |
537 | goto err; | |
538 | } | |
539 | ||
0a121f9b KVA |
540 | get_random_bytes(orig_addr, size + alignment); |
541 | ||
542 | orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment, | |
543 | DMA_TO_DEVICE); | |
544 | if (dma_mapping_error(dev, orig_phys_addr)) { | |
545 | dev_err(dev, "failed to map source buffer address\n"); | |
546 | ret = false; | |
547 | goto err_phys_addr; | |
548 | } | |
549 | ||
13107c60 KVA |
550 | if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) { |
551 | phys_addr = PTR_ALIGN(orig_phys_addr, alignment); | |
552 | offset = phys_addr - orig_phys_addr; | |
553 | addr = orig_addr + offset; | |
554 | } else { | |
555 | phys_addr = orig_phys_addr; | |
556 | addr = orig_addr; | |
557 | } | |
558 | ||
2c156ac7 KVA |
559 | crc32 = crc32_le(~0, addr, size); |
560 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM, | |
561 | crc32); | |
562 | ||
563 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR, | |
564 | lower_32_bits(phys_addr)); | |
565 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR, | |
566 | upper_32_bits(phys_addr)); | |
567 | ||
568 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | |
569 | ||
cf376b4b | 570 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags); |
9133e394 | 571 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type); |
e8817de7 | 572 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); |
2c156ac7 | 573 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
e8817de7 | 574 | COMMAND_READ); |
2c156ac7 KVA |
575 | |
576 | wait_for_completion(&test->irq_raised); | |
577 | ||
578 | reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); | |
579 | if (reg & STATUS_READ_SUCCESS) | |
580 | ret = true; | |
581 | ||
0a121f9b KVA |
582 | dma_unmap_single(dev, orig_phys_addr, size + alignment, |
583 | DMA_TO_DEVICE); | |
584 | ||
585 | err_phys_addr: | |
586 | kfree(orig_addr); | |
2c156ac7 KVA |
587 | |
588 | err: | |
589 | return ret; | |
590 | } | |
591 | ||
cf376b4b KVA |
592 | static bool pci_endpoint_test_read(struct pci_endpoint_test *test, |
593 | unsigned long arg) | |
2c156ac7 | 594 | { |
cf376b4b | 595 | struct pci_endpoint_test_xfer_param param; |
2c156ac7 | 596 | bool ret = false; |
cf376b4b KVA |
597 | u32 flags = 0; |
598 | bool use_dma; | |
599 | size_t size; | |
2c156ac7 KVA |
600 | void *addr; |
601 | dma_addr_t phys_addr; | |
602 | struct pci_dev *pdev = test->pdev; | |
603 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
604 | void *orig_addr; |
605 | dma_addr_t orig_phys_addr; | |
606 | size_t offset; | |
607 | size_t alignment = test->alignment; | |
b2ba9225 | 608 | int irq_type = test->irq_type; |
2c156ac7 | 609 | u32 crc32; |
cf376b4b | 610 | int err; |
2c156ac7 | 611 | |
cf376b4b KVA |
612 | err = copy_from_user(¶m, (void __user *)arg, sizeof(param)); |
613 | if (err) { | |
614 | dev_err(dev, "Failed to get transfer param\n"); | |
615 | return false; | |
616 | } | |
617 | ||
3e42deaa SM |
618 | err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment); |
619 | if (err) | |
620 | return false; | |
621 | ||
cf376b4b | 622 | size = param.size; |
343dc693 | 623 | |
cf376b4b KVA |
624 | use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA); |
625 | if (use_dma) | |
626 | flags |= FLAG_USE_DMA; | |
627 | ||
e0332712 GP |
628 | if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) { |
629 | dev_err(dev, "Invalid IRQ type option\n"); | |
630 | goto err; | |
631 | } | |
632 | ||
0a121f9b | 633 | orig_addr = kzalloc(size + alignment, GFP_KERNEL); |
13107c60 | 634 | if (!orig_addr) { |
0e52ea61 | 635 | dev_err(dev, "Failed to allocate destination address\n"); |
2c156ac7 KVA |
636 | ret = false; |
637 | goto err; | |
638 | } | |
639 | ||
0a121f9b KVA |
640 | orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment, |
641 | DMA_FROM_DEVICE); | |
642 | if (dma_mapping_error(dev, orig_phys_addr)) { | |
643 | dev_err(dev, "failed to map source buffer address\n"); | |
644 | ret = false; | |
645 | goto err_phys_addr; | |
646 | } | |
647 | ||
13107c60 KVA |
648 | if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) { |
649 | phys_addr = PTR_ALIGN(orig_phys_addr, alignment); | |
650 | offset = phys_addr - orig_phys_addr; | |
651 | addr = orig_addr + offset; | |
652 | } else { | |
653 | phys_addr = orig_phys_addr; | |
654 | addr = orig_addr; | |
655 | } | |
656 | ||
2c156ac7 KVA |
657 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR, |
658 | lower_32_bits(phys_addr)); | |
659 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR, | |
660 | upper_32_bits(phys_addr)); | |
661 | ||
662 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | |
663 | ||
cf376b4b | 664 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags); |
9133e394 | 665 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type); |
e8817de7 | 666 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); |
2c156ac7 | 667 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
e8817de7 | 668 | COMMAND_WRITE); |
2c156ac7 KVA |
669 | |
670 | wait_for_completion(&test->irq_raised); | |
671 | ||
0a121f9b KVA |
672 | dma_unmap_single(dev, orig_phys_addr, size + alignment, |
673 | DMA_FROM_DEVICE); | |
674 | ||
2c156ac7 KVA |
675 | crc32 = crc32_le(~0, addr, size); |
676 | if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM)) | |
677 | ret = true; | |
678 | ||
0a121f9b KVA |
679 | err_phys_addr: |
680 | kfree(orig_addr); | |
2c156ac7 KVA |
681 | err: |
682 | return ret; | |
683 | } | |
684 | ||
475007f9 KVA |
685 | static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test) |
686 | { | |
687 | pci_endpoint_test_release_irq(test); | |
688 | pci_endpoint_test_free_irq_vectors(test); | |
689 | return true; | |
690 | } | |
691 | ||
e0332712 GP |
692 | static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test, |
693 | int req_irq_type) | |
694 | { | |
695 | struct pci_dev *pdev = test->pdev; | |
696 | struct device *dev = &pdev->dev; | |
697 | ||
698 | if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) { | |
699 | dev_err(dev, "Invalid IRQ type option\n"); | |
700 | return false; | |
701 | } | |
702 | ||
b2ba9225 | 703 | if (test->irq_type == req_irq_type) |
e0332712 GP |
704 | return true; |
705 | ||
706 | pci_endpoint_test_release_irq(test); | |
707 | pci_endpoint_test_free_irq_vectors(test); | |
708 | ||
709 | if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type)) | |
710 | goto err; | |
711 | ||
712 | if (!pci_endpoint_test_request_irq(test)) | |
713 | goto err; | |
714 | ||
e0332712 GP |
715 | return true; |
716 | ||
717 | err: | |
718 | pci_endpoint_test_free_irq_vectors(test); | |
e0332712 GP |
719 | return false; |
720 | } | |
721 | ||
2c156ac7 KVA |
722 | static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, |
723 | unsigned long arg) | |
724 | { | |
725 | int ret = -EINVAL; | |
726 | enum pci_barno bar; | |
727 | struct pci_endpoint_test *test = to_endpoint_test(file->private_data); | |
5bb04b19 | 728 | struct pci_dev *pdev = test->pdev; |
2c156ac7 KVA |
729 | |
730 | mutex_lock(&test->mutex); | |
731 | switch (cmd) { | |
732 | case PCITEST_BAR: | |
733 | bar = arg; | |
33fcc549 | 734 | if (bar > BAR_5) |
2c156ac7 | 735 | goto ret; |
5bb04b19 KVA |
736 | if (is_am654_pci_dev(pdev) && bar == BAR_0) |
737 | goto ret; | |
2c156ac7 KVA |
738 | ret = pci_endpoint_test_bar(test, bar); |
739 | break; | |
740 | case PCITEST_LEGACY_IRQ: | |
741 | ret = pci_endpoint_test_legacy_irq(test); | |
742 | break; | |
743 | case PCITEST_MSI: | |
c2e00e31 GP |
744 | case PCITEST_MSIX: |
745 | ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX); | |
2c156ac7 KVA |
746 | break; |
747 | case PCITEST_WRITE: | |
748 | ret = pci_endpoint_test_write(test, arg); | |
749 | break; | |
750 | case PCITEST_READ: | |
751 | ret = pci_endpoint_test_read(test, arg); | |
752 | break; | |
753 | case PCITEST_COPY: | |
754 | ret = pci_endpoint_test_copy(test, arg); | |
755 | break; | |
e0332712 GP |
756 | case PCITEST_SET_IRQTYPE: |
757 | ret = pci_endpoint_test_set_irq(test, arg); | |
758 | break; | |
759 | case PCITEST_GET_IRQTYPE: | |
760 | ret = irq_type; | |
761 | break; | |
475007f9 KVA |
762 | case PCITEST_CLEAR_IRQ: |
763 | ret = pci_endpoint_test_clear_irq(test); | |
764 | break; | |
2c156ac7 KVA |
765 | } |
766 | ||
767 | ret: | |
768 | mutex_unlock(&test->mutex); | |
769 | return ret; | |
770 | } | |
771 | ||
772 | static const struct file_operations pci_endpoint_test_fops = { | |
773 | .owner = THIS_MODULE, | |
774 | .unlocked_ioctl = pci_endpoint_test_ioctl, | |
775 | }; | |
776 | ||
777 | static int pci_endpoint_test_probe(struct pci_dev *pdev, | |
778 | const struct pci_device_id *ent) | |
779 | { | |
2c156ac7 | 780 | int err; |
2c156ac7 | 781 | int id; |
6b443e5c | 782 | char name[24]; |
2c156ac7 KVA |
783 | enum pci_barno bar; |
784 | void __iomem *base; | |
785 | struct device *dev = &pdev->dev; | |
786 | struct pci_endpoint_test *test; | |
834b9051 KVA |
787 | struct pci_endpoint_test_data *data; |
788 | enum pci_barno test_reg_bar = BAR_0; | |
2c156ac7 KVA |
789 | struct miscdevice *misc_device; |
790 | ||
791 | if (pci_is_bridge(pdev)) | |
792 | return -ENODEV; | |
793 | ||
794 | test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL); | |
795 | if (!test) | |
796 | return -ENOMEM; | |
797 | ||
834b9051 | 798 | test->test_reg_bar = 0; |
13107c60 | 799 | test->alignment = 0; |
2c156ac7 | 800 | test->pdev = pdev; |
b2ba9225 | 801 | test->irq_type = IRQ_TYPE_UNDEFINED; |
834b9051 | 802 | |
9133e394 GP |
803 | if (no_msi) |
804 | irq_type = IRQ_TYPE_LEGACY; | |
805 | ||
834b9051 | 806 | data = (struct pci_endpoint_test_data *)ent->driver_data; |
13107c60 | 807 | if (data) { |
834b9051 | 808 | test_reg_bar = data->test_reg_bar; |
8f220664 | 809 | test->test_reg_bar = test_reg_bar; |
13107c60 | 810 | test->alignment = data->alignment; |
9133e394 | 811 | irq_type = data->irq_type; |
13107c60 | 812 | } |
834b9051 | 813 | |
2c156ac7 KVA |
814 | init_completion(&test->irq_raised); |
815 | mutex_init(&test->mutex); | |
816 | ||
0a121f9b KVA |
817 | if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) && |
818 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { | |
819 | dev_err(dev, "Cannot set DMA mask\n"); | |
820 | return -EINVAL; | |
821 | } | |
822 | ||
2c156ac7 KVA |
823 | err = pci_enable_device(pdev); |
824 | if (err) { | |
825 | dev_err(dev, "Cannot enable PCI device\n"); | |
826 | return err; | |
827 | } | |
828 | ||
829 | err = pci_request_regions(pdev, DRV_MODULE_NAME); | |
830 | if (err) { | |
831 | dev_err(dev, "Cannot obtain PCI resources\n"); | |
832 | goto err_disable_pdev; | |
833 | } | |
834 | ||
835 | pci_set_master(pdev); | |
836 | ||
1749c904 XW |
837 | if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) { |
838 | err = -EINVAL; | |
e0332712 | 839 | goto err_disable_irq; |
1749c904 | 840 | } |
2c156ac7 | 841 | |
c9c13ba4 | 842 | for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { |
16b17cad NC |
843 | if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
844 | base = pci_ioremap_bar(pdev, bar); | |
845 | if (!base) { | |
0e52ea61 | 846 | dev_err(dev, "Failed to read BAR%d\n", bar); |
16b17cad NC |
847 | WARN_ON(bar == test_reg_bar); |
848 | } | |
849 | test->bar[bar] = base; | |
2c156ac7 | 850 | } |
2c156ac7 KVA |
851 | } |
852 | ||
834b9051 | 853 | test->base = test->bar[test_reg_bar]; |
2c156ac7 | 854 | if (!test->base) { |
80068c93 | 855 | err = -ENOMEM; |
834b9051 KVA |
856 | dev_err(dev, "Cannot perform PCI test without BAR%d\n", |
857 | test_reg_bar); | |
2c156ac7 KVA |
858 | goto err_iounmap; |
859 | } | |
860 | ||
861 | pci_set_drvdata(pdev, test); | |
862 | ||
863 | id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL); | |
864 | if (id < 0) { | |
80068c93 | 865 | err = id; |
0e52ea61 | 866 | dev_err(dev, "Unable to get id\n"); |
2c156ac7 KVA |
867 | goto err_iounmap; |
868 | } | |
869 | ||
870 | snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id); | |
c2be14ab KVA |
871 | test->name = kstrdup(name, GFP_KERNEL); |
872 | if (!test->name) { | |
873 | err = -ENOMEM; | |
874 | goto err_ida_remove; | |
875 | } | |
876 | ||
1749c904 XW |
877 | if (!pci_endpoint_test_request_irq(test)) { |
878 | err = -EINVAL; | |
c2be14ab | 879 | goto err_kfree_test_name; |
1749c904 | 880 | } |
c2be14ab | 881 | |
2c156ac7 KVA |
882 | misc_device = &test->miscdev; |
883 | misc_device->minor = MISC_DYNAMIC_MINOR; | |
139838ff KVA |
884 | misc_device->name = kstrdup(name, GFP_KERNEL); |
885 | if (!misc_device->name) { | |
886 | err = -ENOMEM; | |
c2be14ab | 887 | goto err_release_irq; |
139838ff | 888 | } |
74a03c20 | 889 | misc_device->parent = &pdev->dev; |
560dbc46 | 890 | misc_device->fops = &pci_endpoint_test_fops; |
2c156ac7 KVA |
891 | |
892 | err = misc_register(misc_device); | |
893 | if (err) { | |
0e52ea61 | 894 | dev_err(dev, "Failed to register device\n"); |
139838ff | 895 | goto err_kfree_name; |
2c156ac7 KVA |
896 | } |
897 | ||
898 | return 0; | |
899 | ||
139838ff KVA |
900 | err_kfree_name: |
901 | kfree(misc_device->name); | |
902 | ||
c2be14ab KVA |
903 | err_release_irq: |
904 | pci_endpoint_test_release_irq(test); | |
905 | ||
906 | err_kfree_test_name: | |
907 | kfree(test->name); | |
908 | ||
2c156ac7 KVA |
909 | err_ida_remove: |
910 | ida_simple_remove(&pci_endpoint_test_ida, id); | |
911 | ||
912 | err_iounmap: | |
c9c13ba4 | 913 | for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { |
2c156ac7 KVA |
914 | if (test->bar[bar]) |
915 | pci_iounmap(pdev, test->bar[bar]); | |
916 | } | |
917 | ||
e0332712 GP |
918 | err_disable_irq: |
919 | pci_endpoint_test_free_irq_vectors(test); | |
2c156ac7 KVA |
920 | pci_release_regions(pdev); |
921 | ||
922 | err_disable_pdev: | |
923 | pci_disable_device(pdev); | |
924 | ||
925 | return err; | |
926 | } | |
927 | ||
928 | static void pci_endpoint_test_remove(struct pci_dev *pdev) | |
929 | { | |
930 | int id; | |
931 | enum pci_barno bar; | |
932 | struct pci_endpoint_test *test = pci_get_drvdata(pdev); | |
933 | struct miscdevice *misc_device = &test->miscdev; | |
934 | ||
935 | if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1) | |
936 | return; | |
a2db2663 DC |
937 | if (id < 0) |
938 | return; | |
2c156ac7 KVA |
939 | |
940 | misc_deregister(&test->miscdev); | |
139838ff | 941 | kfree(misc_device->name); |
c2be14ab | 942 | kfree(test->name); |
2c156ac7 | 943 | ida_simple_remove(&pci_endpoint_test_ida, id); |
c9c13ba4 | 944 | for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { |
2c156ac7 KVA |
945 | if (test->bar[bar]) |
946 | pci_iounmap(pdev, test->bar[bar]); | |
947 | } | |
e0332712 GP |
948 | |
949 | pci_endpoint_test_release_irq(test); | |
950 | pci_endpoint_test_free_irq_vectors(test); | |
951 | ||
2c156ac7 KVA |
952 | pci_release_regions(pdev); |
953 | pci_disable_device(pdev); | |
954 | } | |
955 | ||
0a121f9b KVA |
956 | static const struct pci_endpoint_test_data default_data = { |
957 | .test_reg_bar = BAR_0, | |
958 | .alignment = SZ_4K, | |
959 | .irq_type = IRQ_TYPE_MSI, | |
960 | }; | |
961 | ||
5bb04b19 KVA |
962 | static const struct pci_endpoint_test_data am654_data = { |
963 | .test_reg_bar = BAR_2, | |
964 | .alignment = SZ_64K, | |
965 | .irq_type = IRQ_TYPE_MSI, | |
966 | }; | |
967 | ||
6546ae29 KVA |
968 | static const struct pci_endpoint_test_data j721e_data = { |
969 | .alignment = 256, | |
970 | .irq_type = IRQ_TYPE_MSI, | |
971 | }; | |
972 | ||
2c156ac7 | 973 | static const struct pci_device_id pci_endpoint_test_tbl[] = { |
0a121f9b KVA |
974 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x), |
975 | .driver_data = (kernel_ulong_t)&default_data, | |
976 | }, | |
977 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x), | |
978 | .driver_data = (kernel_ulong_t)&default_data, | |
979 | }, | |
09fb37b3 HZ |
980 | { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0), |
981 | .driver_data = (kernel_ulong_t)&default_data, | |
982 | }, | |
983 | { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A), | |
984 | .driver_data = (kernel_ulong_t)&default_data, | |
985 | }, | |
1f418f46 | 986 | { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) }, |
5bb04b19 KVA |
987 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), |
988 | .driver_data = (kernel_ulong_t)&am654_data | |
989 | }, | |
cfb824dd LP |
990 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),}, |
991 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),}, | |
992 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),}, | |
a63c5f3d | 993 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),}, |
6546ae29 KVA |
994 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E), |
995 | .driver_data = (kernel_ulong_t)&j721e_data, | |
996 | }, | |
7c52009d KVA |
997 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200), |
998 | .driver_data = (kernel_ulong_t)&j721e_data, | |
999 | }, | |
1000 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64), | |
1001 | .driver_data = (kernel_ulong_t)&j721e_data, | |
1002 | }, | |
2c156ac7 KVA |
1003 | { } |
1004 | }; | |
1005 | MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); | |
1006 | ||
1007 | static struct pci_driver pci_endpoint_test_driver = { | |
1008 | .name = DRV_MODULE_NAME, | |
1009 | .id_table = pci_endpoint_test_tbl, | |
1010 | .probe = pci_endpoint_test_probe, | |
1011 | .remove = pci_endpoint_test_remove, | |
489b1f41 | 1012 | .sriov_configure = pci_sriov_configure_simple, |
2c156ac7 KVA |
1013 | }; |
1014 | module_pci_driver(pci_endpoint_test_driver); | |
1015 | ||
1016 | MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER"); | |
1017 | MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); | |
1018 | MODULE_LICENSE("GPL v2"); |