Commit | Line | Data |
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6b1baefe | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2c156ac7 KVA |
2 | /** |
3 | * Host side test driver to test endpoint functionality | |
4 | * | |
5 | * Copyright (C) 2017 Texas Instruments | |
6 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | |
2c156ac7 KVA |
7 | */ |
8 | ||
9 | #include <linux/crc32.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/fs.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/mutex.h> | |
18 | #include <linux/random.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/pci_ids.h> | |
22 | ||
23 | #include <linux/pci_regs.h> | |
24 | ||
25 | #include <uapi/linux/pcitest.h> | |
26 | ||
e8817de7 GP |
27 | #define DRV_MODULE_NAME "pci-endpoint-test" |
28 | ||
e0332712 | 29 | #define IRQ_TYPE_UNDEFINED -1 |
e8817de7 GP |
30 | #define IRQ_TYPE_LEGACY 0 |
31 | #define IRQ_TYPE_MSI 1 | |
c2e00e31 | 32 | #define IRQ_TYPE_MSIX 2 |
e8817de7 GP |
33 | |
34 | #define PCI_ENDPOINT_TEST_MAGIC 0x0 | |
35 | ||
36 | #define PCI_ENDPOINT_TEST_COMMAND 0x4 | |
37 | #define COMMAND_RAISE_LEGACY_IRQ BIT(0) | |
38 | #define COMMAND_RAISE_MSI_IRQ BIT(1) | |
c2e00e31 | 39 | #define COMMAND_RAISE_MSIX_IRQ BIT(2) |
e8817de7 GP |
40 | #define COMMAND_READ BIT(3) |
41 | #define COMMAND_WRITE BIT(4) | |
42 | #define COMMAND_COPY BIT(5) | |
43 | ||
44 | #define PCI_ENDPOINT_TEST_STATUS 0x8 | |
45 | #define STATUS_READ_SUCCESS BIT(0) | |
46 | #define STATUS_READ_FAIL BIT(1) | |
47 | #define STATUS_WRITE_SUCCESS BIT(2) | |
48 | #define STATUS_WRITE_FAIL BIT(3) | |
49 | #define STATUS_COPY_SUCCESS BIT(4) | |
50 | #define STATUS_COPY_FAIL BIT(5) | |
51 | #define STATUS_IRQ_RAISED BIT(6) | |
52 | #define STATUS_SRC_ADDR_INVALID BIT(7) | |
53 | #define STATUS_DST_ADDR_INVALID BIT(8) | |
54 | ||
55 | #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c | |
2c156ac7 KVA |
56 | #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10 |
57 | ||
58 | #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14 | |
59 | #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18 | |
60 | ||
e8817de7 GP |
61 | #define PCI_ENDPOINT_TEST_SIZE 0x1c |
62 | #define PCI_ENDPOINT_TEST_CHECKSUM 0x20 | |
63 | ||
64 | #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 | |
65 | #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 | |
2c156ac7 | 66 | |
5bb04b19 KVA |
67 | #define PCI_DEVICE_ID_TI_AM654 0xb00c |
68 | ||
69 | #define is_am654_pci_dev(pdev) \ | |
70 | ((pdev)->device == PCI_DEVICE_ID_TI_AM654) | |
71 | ||
2c156ac7 KVA |
72 | static DEFINE_IDA(pci_endpoint_test_ida); |
73 | ||
74 | #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ | |
75 | miscdev) | |
0c8a5f9d KVA |
76 | |
77 | static bool no_msi; | |
78 | module_param(no_msi, bool, 0444); | |
79 | MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test"); | |
80 | ||
9133e394 GP |
81 | static int irq_type = IRQ_TYPE_MSI; |
82 | module_param(irq_type, int, 0444); | |
c2e00e31 | 83 | MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)"); |
9133e394 | 84 | |
2c156ac7 KVA |
85 | enum pci_barno { |
86 | BAR_0, | |
87 | BAR_1, | |
88 | BAR_2, | |
89 | BAR_3, | |
90 | BAR_4, | |
91 | BAR_5, | |
92 | }; | |
93 | ||
94 | struct pci_endpoint_test { | |
95 | struct pci_dev *pdev; | |
96 | void __iomem *base; | |
97 | void __iomem *bar[6]; | |
98 | struct completion irq_raised; | |
99 | int last_irq; | |
b7636e81 | 100 | int num_irqs; |
2c156ac7 KVA |
101 | /* mutex to protect the ioctls */ |
102 | struct mutex mutex; | |
103 | struct miscdevice miscdev; | |
834b9051 | 104 | enum pci_barno test_reg_bar; |
13107c60 | 105 | size_t alignment; |
2c156ac7 KVA |
106 | }; |
107 | ||
834b9051 KVA |
108 | struct pci_endpoint_test_data { |
109 | enum pci_barno test_reg_bar; | |
13107c60 | 110 | size_t alignment; |
9133e394 | 111 | int irq_type; |
834b9051 KVA |
112 | }; |
113 | ||
2c156ac7 KVA |
114 | static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test, |
115 | u32 offset) | |
116 | { | |
117 | return readl(test->base + offset); | |
118 | } | |
119 | ||
120 | static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test, | |
121 | u32 offset, u32 value) | |
122 | { | |
123 | writel(value, test->base + offset); | |
124 | } | |
125 | ||
126 | static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test, | |
127 | int bar, int offset) | |
128 | { | |
129 | return readl(test->bar[bar] + offset); | |
130 | } | |
131 | ||
132 | static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test, | |
133 | int bar, u32 offset, u32 value) | |
134 | { | |
135 | writel(value, test->bar[bar] + offset); | |
136 | } | |
137 | ||
138 | static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id) | |
139 | { | |
140 | struct pci_endpoint_test *test = dev_id; | |
141 | u32 reg; | |
142 | ||
143 | reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); | |
144 | if (reg & STATUS_IRQ_RAISED) { | |
145 | test->last_irq = irq; | |
146 | complete(&test->irq_raised); | |
147 | reg &= ~STATUS_IRQ_RAISED; | |
148 | } | |
149 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS, | |
150 | reg); | |
151 | ||
152 | return IRQ_HANDLED; | |
153 | } | |
154 | ||
e0332712 GP |
155 | static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test) |
156 | { | |
157 | struct pci_dev *pdev = test->pdev; | |
158 | ||
159 | pci_free_irq_vectors(pdev); | |
160 | } | |
161 | ||
162 | static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test, | |
163 | int type) | |
164 | { | |
165 | int irq = -1; | |
166 | struct pci_dev *pdev = test->pdev; | |
167 | struct device *dev = &pdev->dev; | |
168 | bool res = true; | |
169 | ||
170 | switch (type) { | |
171 | case IRQ_TYPE_LEGACY: | |
172 | irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY); | |
173 | if (irq < 0) | |
174 | dev_err(dev, "Failed to get Legacy interrupt\n"); | |
175 | break; | |
176 | case IRQ_TYPE_MSI: | |
177 | irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI); | |
178 | if (irq < 0) | |
179 | dev_err(dev, "Failed to get MSI interrupts\n"); | |
180 | break; | |
181 | case IRQ_TYPE_MSIX: | |
182 | irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX); | |
183 | if (irq < 0) | |
184 | dev_err(dev, "Failed to get MSI-X interrupts\n"); | |
185 | break; | |
186 | default: | |
187 | dev_err(dev, "Invalid IRQ type selected\n"); | |
188 | } | |
189 | ||
190 | if (irq < 0) { | |
191 | irq = 0; | |
192 | res = false; | |
193 | } | |
194 | test->num_irqs = irq; | |
195 | ||
196 | return res; | |
197 | } | |
198 | ||
199 | static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test) | |
200 | { | |
201 | int i; | |
202 | struct pci_dev *pdev = test->pdev; | |
203 | struct device *dev = &pdev->dev; | |
204 | ||
205 | for (i = 0; i < test->num_irqs; i++) | |
206 | devm_free_irq(dev, pci_irq_vector(pdev, i), test); | |
207 | ||
208 | test->num_irqs = 0; | |
209 | } | |
210 | ||
211 | static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test) | |
212 | { | |
213 | int i; | |
214 | int err; | |
215 | struct pci_dev *pdev = test->pdev; | |
216 | struct device *dev = &pdev->dev; | |
217 | ||
218 | for (i = 0; i < test->num_irqs; i++) { | |
219 | err = devm_request_irq(dev, pci_irq_vector(pdev, i), | |
220 | pci_endpoint_test_irqhandler, | |
221 | IRQF_SHARED, DRV_MODULE_NAME, test); | |
222 | if (err) | |
223 | goto fail; | |
224 | } | |
225 | ||
226 | return true; | |
227 | ||
228 | fail: | |
229 | switch (irq_type) { | |
230 | case IRQ_TYPE_LEGACY: | |
231 | dev_err(dev, "Failed to request IRQ %d for Legacy\n", | |
232 | pci_irq_vector(pdev, i)); | |
233 | break; | |
234 | case IRQ_TYPE_MSI: | |
235 | dev_err(dev, "Failed to request IRQ %d for MSI %d\n", | |
236 | pci_irq_vector(pdev, i), | |
237 | i + 1); | |
238 | break; | |
239 | case IRQ_TYPE_MSIX: | |
240 | dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n", | |
241 | pci_irq_vector(pdev, i), | |
242 | i + 1); | |
243 | break; | |
244 | } | |
245 | ||
246 | return false; | |
247 | } | |
248 | ||
2c156ac7 KVA |
249 | static bool pci_endpoint_test_bar(struct pci_endpoint_test *test, |
250 | enum pci_barno barno) | |
251 | { | |
252 | int j; | |
253 | u32 val; | |
254 | int size; | |
cda370ec | 255 | struct pci_dev *pdev = test->pdev; |
2c156ac7 KVA |
256 | |
257 | if (!test->bar[barno]) | |
258 | return false; | |
259 | ||
cda370ec | 260 | size = pci_resource_len(pdev, barno); |
2c156ac7 | 261 | |
834b9051 KVA |
262 | if (barno == test->test_reg_bar) |
263 | size = 0x4; | |
264 | ||
2c156ac7 KVA |
265 | for (j = 0; j < size; j += 4) |
266 | pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0); | |
267 | ||
268 | for (j = 0; j < size; j += 4) { | |
269 | val = pci_endpoint_test_bar_readl(test, barno, j); | |
270 | if (val != 0xA0A0A0A0) | |
271 | return false; | |
272 | } | |
273 | ||
274 | return true; | |
275 | } | |
276 | ||
277 | static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test) | |
278 | { | |
279 | u32 val; | |
280 | ||
e8817de7 GP |
281 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, |
282 | IRQ_TYPE_LEGACY); | |
283 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0); | |
2c156ac7 KVA |
284 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
285 | COMMAND_RAISE_LEGACY_IRQ); | |
286 | val = wait_for_completion_timeout(&test->irq_raised, | |
287 | msecs_to_jiffies(1000)); | |
288 | if (!val) | |
289 | return false; | |
290 | ||
291 | return true; | |
292 | } | |
293 | ||
294 | static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test, | |
c2e00e31 | 295 | u16 msi_num, bool msix) |
2c156ac7 KVA |
296 | { |
297 | u32 val; | |
298 | struct pci_dev *pdev = test->pdev; | |
299 | ||
e8817de7 | 300 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, |
c2e00e31 GP |
301 | msix == false ? IRQ_TYPE_MSI : |
302 | IRQ_TYPE_MSIX); | |
e8817de7 | 303 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num); |
2c156ac7 | 304 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
c2e00e31 GP |
305 | msix == false ? COMMAND_RAISE_MSI_IRQ : |
306 | COMMAND_RAISE_MSIX_IRQ); | |
2c156ac7 KVA |
307 | val = wait_for_completion_timeout(&test->irq_raised, |
308 | msecs_to_jiffies(1000)); | |
309 | if (!val) | |
310 | return false; | |
311 | ||
ecc57efe | 312 | if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq) |
2c156ac7 KVA |
313 | return true; |
314 | ||
315 | return false; | |
316 | } | |
317 | ||
318 | static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size) | |
319 | { | |
320 | bool ret = false; | |
321 | void *src_addr; | |
322 | void *dst_addr; | |
323 | dma_addr_t src_phys_addr; | |
324 | dma_addr_t dst_phys_addr; | |
325 | struct pci_dev *pdev = test->pdev; | |
326 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
327 | void *orig_src_addr; |
328 | dma_addr_t orig_src_phys_addr; | |
329 | void *orig_dst_addr; | |
330 | dma_addr_t orig_dst_phys_addr; | |
331 | size_t offset; | |
332 | size_t alignment = test->alignment; | |
2c156ac7 KVA |
333 | u32 src_crc32; |
334 | u32 dst_crc32; | |
335 | ||
343dc693 DC |
336 | if (size > SIZE_MAX - alignment) |
337 | goto err; | |
338 | ||
e0332712 GP |
339 | if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) { |
340 | dev_err(dev, "Invalid IRQ type option\n"); | |
341 | goto err; | |
342 | } | |
343 | ||
13107c60 KVA |
344 | orig_src_addr = dma_alloc_coherent(dev, size + alignment, |
345 | &orig_src_phys_addr, GFP_KERNEL); | |
346 | if (!orig_src_addr) { | |
0e52ea61 | 347 | dev_err(dev, "Failed to allocate source buffer\n"); |
2c156ac7 KVA |
348 | ret = false; |
349 | goto err; | |
350 | } | |
351 | ||
13107c60 KVA |
352 | if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) { |
353 | src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment); | |
354 | offset = src_phys_addr - orig_src_phys_addr; | |
355 | src_addr = orig_src_addr + offset; | |
356 | } else { | |
357 | src_phys_addr = orig_src_phys_addr; | |
358 | src_addr = orig_src_addr; | |
359 | } | |
360 | ||
2c156ac7 KVA |
361 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR, |
362 | lower_32_bits(src_phys_addr)); | |
363 | ||
364 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR, | |
365 | upper_32_bits(src_phys_addr)); | |
366 | ||
367 | get_random_bytes(src_addr, size); | |
368 | src_crc32 = crc32_le(~0, src_addr, size); | |
369 | ||
13107c60 KVA |
370 | orig_dst_addr = dma_alloc_coherent(dev, size + alignment, |
371 | &orig_dst_phys_addr, GFP_KERNEL); | |
372 | if (!orig_dst_addr) { | |
0e52ea61 | 373 | dev_err(dev, "Failed to allocate destination address\n"); |
2c156ac7 | 374 | ret = false; |
13107c60 KVA |
375 | goto err_orig_src_addr; |
376 | } | |
377 | ||
378 | if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) { | |
379 | dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment); | |
380 | offset = dst_phys_addr - orig_dst_phys_addr; | |
381 | dst_addr = orig_dst_addr + offset; | |
382 | } else { | |
383 | dst_phys_addr = orig_dst_phys_addr; | |
384 | dst_addr = orig_dst_addr; | |
2c156ac7 KVA |
385 | } |
386 | ||
387 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR, | |
388 | lower_32_bits(dst_phys_addr)); | |
389 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR, | |
390 | upper_32_bits(dst_phys_addr)); | |
391 | ||
392 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, | |
393 | size); | |
394 | ||
9133e394 | 395 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type); |
e8817de7 | 396 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); |
2c156ac7 | 397 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
e8817de7 | 398 | COMMAND_COPY); |
2c156ac7 KVA |
399 | |
400 | wait_for_completion(&test->irq_raised); | |
401 | ||
402 | dst_crc32 = crc32_le(~0, dst_addr, size); | |
403 | if (dst_crc32 == src_crc32) | |
404 | ret = true; | |
405 | ||
13107c60 KVA |
406 | dma_free_coherent(dev, size + alignment, orig_dst_addr, |
407 | orig_dst_phys_addr); | |
2c156ac7 | 408 | |
13107c60 KVA |
409 | err_orig_src_addr: |
410 | dma_free_coherent(dev, size + alignment, orig_src_addr, | |
411 | orig_src_phys_addr); | |
2c156ac7 KVA |
412 | |
413 | err: | |
414 | return ret; | |
415 | } | |
416 | ||
417 | static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size) | |
418 | { | |
419 | bool ret = false; | |
420 | u32 reg; | |
421 | void *addr; | |
422 | dma_addr_t phys_addr; | |
423 | struct pci_dev *pdev = test->pdev; | |
424 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
425 | void *orig_addr; |
426 | dma_addr_t orig_phys_addr; | |
427 | size_t offset; | |
428 | size_t alignment = test->alignment; | |
2c156ac7 KVA |
429 | u32 crc32; |
430 | ||
343dc693 DC |
431 | if (size > SIZE_MAX - alignment) |
432 | goto err; | |
433 | ||
e0332712 GP |
434 | if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) { |
435 | dev_err(dev, "Invalid IRQ type option\n"); | |
436 | goto err; | |
437 | } | |
438 | ||
13107c60 KVA |
439 | orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr, |
440 | GFP_KERNEL); | |
441 | if (!orig_addr) { | |
0e52ea61 | 442 | dev_err(dev, "Failed to allocate address\n"); |
2c156ac7 KVA |
443 | ret = false; |
444 | goto err; | |
445 | } | |
446 | ||
13107c60 KVA |
447 | if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) { |
448 | phys_addr = PTR_ALIGN(orig_phys_addr, alignment); | |
449 | offset = phys_addr - orig_phys_addr; | |
450 | addr = orig_addr + offset; | |
451 | } else { | |
452 | phys_addr = orig_phys_addr; | |
453 | addr = orig_addr; | |
454 | } | |
455 | ||
2c156ac7 KVA |
456 | get_random_bytes(addr, size); |
457 | ||
458 | crc32 = crc32_le(~0, addr, size); | |
459 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM, | |
460 | crc32); | |
461 | ||
462 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR, | |
463 | lower_32_bits(phys_addr)); | |
464 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR, | |
465 | upper_32_bits(phys_addr)); | |
466 | ||
467 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | |
468 | ||
9133e394 | 469 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type); |
e8817de7 | 470 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); |
2c156ac7 | 471 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
e8817de7 | 472 | COMMAND_READ); |
2c156ac7 KVA |
473 | |
474 | wait_for_completion(&test->irq_raised); | |
475 | ||
476 | reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); | |
477 | if (reg & STATUS_READ_SUCCESS) | |
478 | ret = true; | |
479 | ||
13107c60 | 480 | dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr); |
2c156ac7 KVA |
481 | |
482 | err: | |
483 | return ret; | |
484 | } | |
485 | ||
486 | static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size) | |
487 | { | |
488 | bool ret = false; | |
489 | void *addr; | |
490 | dma_addr_t phys_addr; | |
491 | struct pci_dev *pdev = test->pdev; | |
492 | struct device *dev = &pdev->dev; | |
13107c60 KVA |
493 | void *orig_addr; |
494 | dma_addr_t orig_phys_addr; | |
495 | size_t offset; | |
496 | size_t alignment = test->alignment; | |
2c156ac7 KVA |
497 | u32 crc32; |
498 | ||
343dc693 DC |
499 | if (size > SIZE_MAX - alignment) |
500 | goto err; | |
501 | ||
e0332712 GP |
502 | if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) { |
503 | dev_err(dev, "Invalid IRQ type option\n"); | |
504 | goto err; | |
505 | } | |
506 | ||
13107c60 KVA |
507 | orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr, |
508 | GFP_KERNEL); | |
509 | if (!orig_addr) { | |
0e52ea61 | 510 | dev_err(dev, "Failed to allocate destination address\n"); |
2c156ac7 KVA |
511 | ret = false; |
512 | goto err; | |
513 | } | |
514 | ||
13107c60 KVA |
515 | if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) { |
516 | phys_addr = PTR_ALIGN(orig_phys_addr, alignment); | |
517 | offset = phys_addr - orig_phys_addr; | |
518 | addr = orig_addr + offset; | |
519 | } else { | |
520 | phys_addr = orig_phys_addr; | |
521 | addr = orig_addr; | |
522 | } | |
523 | ||
2c156ac7 KVA |
524 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR, |
525 | lower_32_bits(phys_addr)); | |
526 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR, | |
527 | upper_32_bits(phys_addr)); | |
528 | ||
529 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | |
530 | ||
9133e394 | 531 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type); |
e8817de7 | 532 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); |
2c156ac7 | 533 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
e8817de7 | 534 | COMMAND_WRITE); |
2c156ac7 KVA |
535 | |
536 | wait_for_completion(&test->irq_raised); | |
537 | ||
538 | crc32 = crc32_le(~0, addr, size); | |
539 | if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM)) | |
540 | ret = true; | |
541 | ||
13107c60 | 542 | dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr); |
2c156ac7 KVA |
543 | err: |
544 | return ret; | |
545 | } | |
546 | ||
e0332712 GP |
547 | static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test, |
548 | int req_irq_type) | |
549 | { | |
550 | struct pci_dev *pdev = test->pdev; | |
551 | struct device *dev = &pdev->dev; | |
552 | ||
553 | if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) { | |
554 | dev_err(dev, "Invalid IRQ type option\n"); | |
555 | return false; | |
556 | } | |
557 | ||
558 | if (irq_type == req_irq_type) | |
559 | return true; | |
560 | ||
561 | pci_endpoint_test_release_irq(test); | |
562 | pci_endpoint_test_free_irq_vectors(test); | |
563 | ||
564 | if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type)) | |
565 | goto err; | |
566 | ||
567 | if (!pci_endpoint_test_request_irq(test)) | |
568 | goto err; | |
569 | ||
570 | irq_type = req_irq_type; | |
571 | return true; | |
572 | ||
573 | err: | |
574 | pci_endpoint_test_free_irq_vectors(test); | |
575 | irq_type = IRQ_TYPE_UNDEFINED; | |
576 | return false; | |
577 | } | |
578 | ||
2c156ac7 KVA |
579 | static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, |
580 | unsigned long arg) | |
581 | { | |
582 | int ret = -EINVAL; | |
583 | enum pci_barno bar; | |
584 | struct pci_endpoint_test *test = to_endpoint_test(file->private_data); | |
5bb04b19 | 585 | struct pci_dev *pdev = test->pdev; |
2c156ac7 KVA |
586 | |
587 | mutex_lock(&test->mutex); | |
588 | switch (cmd) { | |
589 | case PCITEST_BAR: | |
590 | bar = arg; | |
591 | if (bar < 0 || bar > 5) | |
592 | goto ret; | |
5bb04b19 KVA |
593 | if (is_am654_pci_dev(pdev) && bar == BAR_0) |
594 | goto ret; | |
2c156ac7 KVA |
595 | ret = pci_endpoint_test_bar(test, bar); |
596 | break; | |
597 | case PCITEST_LEGACY_IRQ: | |
598 | ret = pci_endpoint_test_legacy_irq(test); | |
599 | break; | |
600 | case PCITEST_MSI: | |
c2e00e31 GP |
601 | case PCITEST_MSIX: |
602 | ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX); | |
2c156ac7 KVA |
603 | break; |
604 | case PCITEST_WRITE: | |
605 | ret = pci_endpoint_test_write(test, arg); | |
606 | break; | |
607 | case PCITEST_READ: | |
608 | ret = pci_endpoint_test_read(test, arg); | |
609 | break; | |
610 | case PCITEST_COPY: | |
611 | ret = pci_endpoint_test_copy(test, arg); | |
612 | break; | |
e0332712 GP |
613 | case PCITEST_SET_IRQTYPE: |
614 | ret = pci_endpoint_test_set_irq(test, arg); | |
615 | break; | |
616 | case PCITEST_GET_IRQTYPE: | |
617 | ret = irq_type; | |
618 | break; | |
2c156ac7 KVA |
619 | } |
620 | ||
621 | ret: | |
622 | mutex_unlock(&test->mutex); | |
623 | return ret; | |
624 | } | |
625 | ||
626 | static const struct file_operations pci_endpoint_test_fops = { | |
627 | .owner = THIS_MODULE, | |
628 | .unlocked_ioctl = pci_endpoint_test_ioctl, | |
629 | }; | |
630 | ||
631 | static int pci_endpoint_test_probe(struct pci_dev *pdev, | |
632 | const struct pci_device_id *ent) | |
633 | { | |
2c156ac7 | 634 | int err; |
2c156ac7 KVA |
635 | int id; |
636 | char name[20]; | |
637 | enum pci_barno bar; | |
638 | void __iomem *base; | |
639 | struct device *dev = &pdev->dev; | |
640 | struct pci_endpoint_test *test; | |
834b9051 KVA |
641 | struct pci_endpoint_test_data *data; |
642 | enum pci_barno test_reg_bar = BAR_0; | |
2c156ac7 KVA |
643 | struct miscdevice *misc_device; |
644 | ||
645 | if (pci_is_bridge(pdev)) | |
646 | return -ENODEV; | |
647 | ||
648 | test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL); | |
649 | if (!test) | |
650 | return -ENOMEM; | |
651 | ||
834b9051 | 652 | test->test_reg_bar = 0; |
13107c60 | 653 | test->alignment = 0; |
2c156ac7 | 654 | test->pdev = pdev; |
834b9051 | 655 | |
9133e394 GP |
656 | if (no_msi) |
657 | irq_type = IRQ_TYPE_LEGACY; | |
658 | ||
834b9051 | 659 | data = (struct pci_endpoint_test_data *)ent->driver_data; |
13107c60 | 660 | if (data) { |
834b9051 | 661 | test_reg_bar = data->test_reg_bar; |
8f220664 | 662 | test->test_reg_bar = test_reg_bar; |
13107c60 | 663 | test->alignment = data->alignment; |
9133e394 | 664 | irq_type = data->irq_type; |
13107c60 | 665 | } |
834b9051 | 666 | |
2c156ac7 KVA |
667 | init_completion(&test->irq_raised); |
668 | mutex_init(&test->mutex); | |
669 | ||
670 | err = pci_enable_device(pdev); | |
671 | if (err) { | |
672 | dev_err(dev, "Cannot enable PCI device\n"); | |
673 | return err; | |
674 | } | |
675 | ||
676 | err = pci_request_regions(pdev, DRV_MODULE_NAME); | |
677 | if (err) { | |
678 | dev_err(dev, "Cannot obtain PCI resources\n"); | |
679 | goto err_disable_pdev; | |
680 | } | |
681 | ||
682 | pci_set_master(pdev); | |
683 | ||
e0332712 GP |
684 | if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) |
685 | goto err_disable_irq; | |
2c156ac7 | 686 | |
e0332712 GP |
687 | if (!pci_endpoint_test_request_irq(test)) |
688 | goto err_disable_irq; | |
2c156ac7 KVA |
689 | |
690 | for (bar = BAR_0; bar <= BAR_5; bar++) { | |
16b17cad NC |
691 | if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
692 | base = pci_ioremap_bar(pdev, bar); | |
693 | if (!base) { | |
0e52ea61 | 694 | dev_err(dev, "Failed to read BAR%d\n", bar); |
16b17cad NC |
695 | WARN_ON(bar == test_reg_bar); |
696 | } | |
697 | test->bar[bar] = base; | |
2c156ac7 | 698 | } |
2c156ac7 KVA |
699 | } |
700 | ||
834b9051 | 701 | test->base = test->bar[test_reg_bar]; |
2c156ac7 | 702 | if (!test->base) { |
80068c93 | 703 | err = -ENOMEM; |
834b9051 KVA |
704 | dev_err(dev, "Cannot perform PCI test without BAR%d\n", |
705 | test_reg_bar); | |
2c156ac7 KVA |
706 | goto err_iounmap; |
707 | } | |
708 | ||
709 | pci_set_drvdata(pdev, test); | |
710 | ||
711 | id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL); | |
712 | if (id < 0) { | |
80068c93 | 713 | err = id; |
0e52ea61 | 714 | dev_err(dev, "Unable to get id\n"); |
2c156ac7 KVA |
715 | goto err_iounmap; |
716 | } | |
717 | ||
718 | snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id); | |
719 | misc_device = &test->miscdev; | |
720 | misc_device->minor = MISC_DYNAMIC_MINOR; | |
139838ff KVA |
721 | misc_device->name = kstrdup(name, GFP_KERNEL); |
722 | if (!misc_device->name) { | |
723 | err = -ENOMEM; | |
724 | goto err_ida_remove; | |
725 | } | |
2c156ac7 KVA |
726 | misc_device->fops = &pci_endpoint_test_fops, |
727 | ||
728 | err = misc_register(misc_device); | |
729 | if (err) { | |
0e52ea61 | 730 | dev_err(dev, "Failed to register device\n"); |
139838ff | 731 | goto err_kfree_name; |
2c156ac7 KVA |
732 | } |
733 | ||
734 | return 0; | |
735 | ||
139838ff KVA |
736 | err_kfree_name: |
737 | kfree(misc_device->name); | |
738 | ||
2c156ac7 KVA |
739 | err_ida_remove: |
740 | ida_simple_remove(&pci_endpoint_test_ida, id); | |
741 | ||
742 | err_iounmap: | |
743 | for (bar = BAR_0; bar <= BAR_5; bar++) { | |
744 | if (test->bar[bar]) | |
745 | pci_iounmap(pdev, test->bar[bar]); | |
746 | } | |
e0332712 | 747 | pci_endpoint_test_release_irq(test); |
2c156ac7 | 748 | |
e0332712 GP |
749 | err_disable_irq: |
750 | pci_endpoint_test_free_irq_vectors(test); | |
2c156ac7 KVA |
751 | pci_release_regions(pdev); |
752 | ||
753 | err_disable_pdev: | |
754 | pci_disable_device(pdev); | |
755 | ||
756 | return err; | |
757 | } | |
758 | ||
759 | static void pci_endpoint_test_remove(struct pci_dev *pdev) | |
760 | { | |
761 | int id; | |
762 | enum pci_barno bar; | |
763 | struct pci_endpoint_test *test = pci_get_drvdata(pdev); | |
764 | struct miscdevice *misc_device = &test->miscdev; | |
765 | ||
766 | if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1) | |
767 | return; | |
a2db2663 DC |
768 | if (id < 0) |
769 | return; | |
2c156ac7 KVA |
770 | |
771 | misc_deregister(&test->miscdev); | |
139838ff | 772 | kfree(misc_device->name); |
2c156ac7 KVA |
773 | ida_simple_remove(&pci_endpoint_test_ida, id); |
774 | for (bar = BAR_0; bar <= BAR_5; bar++) { | |
775 | if (test->bar[bar]) | |
776 | pci_iounmap(pdev, test->bar[bar]); | |
777 | } | |
e0332712 GP |
778 | |
779 | pci_endpoint_test_release_irq(test); | |
780 | pci_endpoint_test_free_irq_vectors(test); | |
781 | ||
2c156ac7 KVA |
782 | pci_release_regions(pdev); |
783 | pci_disable_device(pdev); | |
784 | } | |
785 | ||
5bb04b19 KVA |
786 | static const struct pci_endpoint_test_data am654_data = { |
787 | .test_reg_bar = BAR_2, | |
788 | .alignment = SZ_64K, | |
789 | .irq_type = IRQ_TYPE_MSI, | |
790 | }; | |
791 | ||
2c156ac7 KVA |
792 | static const struct pci_device_id pci_endpoint_test_tbl[] = { |
793 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) }, | |
794 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) }, | |
85cef374 | 795 | { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) }, |
1f418f46 | 796 | { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) }, |
5bb04b19 KVA |
797 | { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), |
798 | .driver_data = (kernel_ulong_t)&am654_data | |
799 | }, | |
2c156ac7 KVA |
800 | { } |
801 | }; | |
802 | MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); | |
803 | ||
804 | static struct pci_driver pci_endpoint_test_driver = { | |
805 | .name = DRV_MODULE_NAME, | |
806 | .id_table = pci_endpoint_test_tbl, | |
807 | .probe = pci_endpoint_test_probe, | |
808 | .remove = pci_endpoint_test_remove, | |
809 | }; | |
810 | module_pci_driver(pci_endpoint_test_driver); | |
811 | ||
812 | MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER"); | |
813 | MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); | |
814 | MODULE_LICENSE("GPL v2"); |