[linux-block.git] / drivers / misc / mei / pci-me.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
 * Intel Management Engine Interface (Intel MEI) Linux driver
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/sched.h>
#include <linux/interrupt.h>

#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static const struct pci_device_id mei_me_pci_tbl[] = {
	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

#ifdef CONFIG_PM
static inline void mei_me_set_pm_domain(struct mei_device *dev);
static inline void mei_me_unset_pm_domain(struct mei_device *dev);
#else
static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
#endif /* CONFIG_PM */

static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
{
	struct pci_dev *pdev = to_pci_dev(dev->dev);

	return pci_read_config_dword(pdev, where, val);
}

/**
 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @cfg: per generation config
 *
 * Return: true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct mei_cfg *cfg)
{
	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
		return false;
	}

	return true;
}

/**
 * mei_me_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * Return: 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct mei_cfg *cfg;
	struct mei_device *dev;
	struct mei_me_hw *hw;
	unsigned int irqflags;
	int err;

	cfg = mei_me_get_cfg(ent->driver_data);
	if (!cfg)
		return -ENODEV;

	if (!mei_me_quirk_probe(pdev, cfg))
		return -ENODEV;

	/* enable pci dev */
	err = pcim_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions and mapping IO device memory for mei driver */
	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto end;
	}

	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto end;
	}

	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(&pdev->dev, cfg, false);
	if (!dev) {
		err = -ENOMEM;
		goto end;
	}
	hw = to_me_hw(dev);
	hw->mem_addr = pcim_iomap_table(pdev)[0];
	hw->read_fws = mei_me_read_fws;

	pci_enable_msi(pdev);

	hw->irq = pdev->irq;

	 /* request and enable interrupt */
	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);
	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto end;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);

	err = mei_register(dev, &pdev->dev);
	if (err)
		goto stop;

	pci_set_drvdata(pdev, dev);

	/*
	 * MEI requires to resume from runtime suspend mode
	 * in order to perform link reset flow upon system suspend.
	 */
	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);

	/*
	 * ME maps runtime suspend/resume to D0i states,
	 * hence we need to go around native PCI runtime service which
	 * eventually brings the device into D3cold/hot state,
	 * but the mei device cannot wake up from D3 unlike from D0i3.
	 * To get around the PCI device native runtime pm,
	 * ME uses runtime pm domain handlers which take precedence
	 * over the driver's pm handlers.
	 */
	mei_me_set_pm_domain(dev);

	if (mei_pg_is_enabled(dev)) {
		pm_runtime_put_noidle(&pdev->dev);
		if (hw->d0i3_supported)
			pm_runtime_allow(&pdev->dev);
	}

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

stop:
	mei_stop(dev);
release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_me_shutdown - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_shutdown is called from the reboot notifier
 * it's a simplified version of remove so we go down
 * faster.
 */
static void mei_me_shutdown(struct pci_dev *pdev)
{
	struct mei_device *dev = pci_get_drvdata(pdev);

	dev_dbg(&pdev->dev, "shutdown\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
}

/**
 * mei_me_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (mei_pg_is_enabled(dev))
		pm_runtime_get_noresume(&pdev->dev);

	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);

	mei_deregister(dev);
}

#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_prepare(struct device *device)
{
	pm_runtime_resume(device);
	return 0;
}

static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);
	unsigned int irqflags;
	int err;

	pci_enable_msi(pdev);

	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	/* request and enable interrupt */
	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err) {
		free_irq(pdev->irq, dev);
		return err;
	}

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}

static void mei_me_pci_complete(struct device *device)
{
	pm_runtime_suspend(device);
}
#else /* CONFIG_PM_SLEEP */

#define mei_me_pci_prepare NULL
#define mei_me_pci_complete NULL

#endif /* !CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int mei_me_pm_runtime_idle(struct device *device)
{
	struct mei_device *dev = dev_get_drvdata(device);

	dev_dbg(device, "rpm: me: runtime_idle\n");

	if (mei_write_is_idle(dev))
		pm_runtime_autosuspend(device);

	return -EBUSY;
}

static int mei_me_pm_runtime_suspend(struct device *device)
{
	struct mei_device *dev = dev_get_drvdata(device);
	int ret;

	dev_dbg(device, "rpm: me: runtime suspend\n");

	mutex_lock(&dev->device_lock);

	if (mei_write_is_idle(dev))
		ret = mei_me_pg_enter_sync(dev);
	else
		ret = -EAGAIN;

	mutex_unlock(&dev->device_lock);

	dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);

	if (ret && ret != -EAGAIN)
		schedule_work(&dev->reset_work);

	return ret;
}

static int mei_me_pm_runtime_resume(struct device *device)
{
	struct mei_device *dev = dev_get_drvdata(device);
	int ret;

	dev_dbg(device, "rpm: me: runtime resume\n");

	mutex_lock(&dev->device_lock);

	ret = mei_me_pg_exit_sync(dev);

	mutex_unlock(&dev->device_lock);

	dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);

	if (ret)
		schedule_work(&dev->reset_work);

	return ret;
}

/**
 * mei_me_set_pm_domain - fill and set pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_set_pm_domain(struct mei_device *dev)
{
	struct pci_dev *pdev  = to_pci_dev(dev->dev);

	if (pdev->dev.bus && pdev->dev.bus->pm) {
		dev->pg_domain.ops = *pdev->dev.bus->pm;

		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;

		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
	}
}

/**
 * mei_me_unset_pm_domain - clean pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_unset_pm_domain(struct mei_device *dev)
{
	/* stop using pm callbacks if any */
	dev_pm_domain_set(dev->dev, NULL);
}

static const struct dev_pm_ops mei_me_pm_ops = {
	.prepare = mei_me_pci_prepare,
	.complete = mei_me_pci_complete,
	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
				mei_me_pci_resume)
	SET_RUNTIME_PM_OPS(
		mei_me_pm_runtime_suspend,
		mei_me_pm_runtime_resume,
		mei_me_pm_runtime_idle)
};

#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_shutdown,
	.driver.pm = MEI_ME_PM_OPS,
	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fff0425	1	// SPDX-License-Identifier: GPL-2.0
2703d4b2	2	/*
95953618	3	* Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
2703d4b2	4	* Intel Management Engine Interface (Intel MEI) Linux driver
2703d4b2	5	*/
9fff0425	6
2703d4b2	7	#include <linux/module.h>
2703d4b2 TW	8	#include <linux/kernel.h>
2703d4b2 TW	9	#include <linux/device.h>
2703d4b2 TW	10	#include <linux/errno.h>
2703d4b2 TW	11	#include <linux/types.h>
2703d4b2	12	#include <linux/pci.h>
515a2f50	13	#include <linux/dma-mapping.h>
2703d4b2	14	#include <linux/sched.h>
2703d4b2	15	#include <linux/interrupt.h>
2703d4b2	16
989561de	17	#include <linux/pm_domain.h>
180ea05b TW	18	#include <linux/pm_runtime.h>
180ea05b TW	19
2703d4b2 TW	20	#include <linux/mei.h>
	21
	22	#include "mei_dev.h"
2703d4b2	23	#include "client.h"
6e4cd27a TW	24	#include "hw-me-regs.h"
6e4cd27a TW	25	#include "hw-me.h"
2703d4b2	26
2703d4b2	27	/* mei_pci_tbl - PCI Device ID Table */
a05f8f86	28	static const struct pci_device_id mei_me_pci_tbl[] = {
f5ac3c49 TW	29	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	30	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	31	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	32	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	33	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	34	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	35	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	36	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	37	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	38	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	39	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
	40
	41	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	42	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	43	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	44	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	45	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	46	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	47	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	48	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	49	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
	50
	51	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	52	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	53	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	54	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
	55
f8204f0d AU	56	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
f8204f0d AU	57	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
f5ac3c49 TW	58	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
f5ac3c49 TW	59	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
f8204f0d AU	60	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
	61	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
	62	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
f76d77f5 TW	63	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
f76d77f5 TW	64	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
f5ac3c49	65	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
f76d77f5	66	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
f5ac3c49 TW	67	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	68	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
	69
	70	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	71	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
2f79d3d1	72	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
f76d77f5 TW	73	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	74	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
	75	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
f5ac3c49 TW	76
	77	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	78	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
	79
f7ee8ead TW	80	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
f7ee8ead TW	81
688cb678 TW	82	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
688cb678 TW	83
f5ac3c49 TW	84	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
f5ac3c49 TW	85	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
4afc339e	86	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
ac182e8a	87
1dbfe7f2	88	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
2f79d3d1	89	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
f76d77f5	90	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
2f79d3d1	91	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
f8f4aa68	92
4d86dfd3	93	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
2f79d3d1	94	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
82b29b9f	95	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
559e575a	96	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
2f79d3d1	97	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
4d86dfd3	98
efe814e9	99	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
75c10c5e	100	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
efe814e9	101
52f6efdf	102	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
8c289ea0	103	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
587f1740	104
0db4a15d TW	105	{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
0db4a15d TW	106
52f6efdf	107	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
1be8624a AU	108	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
1be8624a AU	109
99397d33 AU	110	{MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
99397d33 AU	111
372726cb TW	112	{MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
372726cb TW	113
f7545efa	114	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
930c922a	115	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
0df74278	116	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
7bbbd084	117	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
f7545efa	118
0dc04112	119	{MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)},
3ed8c7d3	120
0c4d6826	121	{MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
7a9b9012	122	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
8436f258	123	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
0c4d6826	124
4108a30f AU	125	{MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)},
4108a30f AU	126
2703d4b2 TW	127	/* required last entry */
	128	{0, }
	129	};
	130
b68301e9	131	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
2703d4b2	132
bbd6d050	133	#ifdef CONFIG_PM
e13fa90c TW	134	static inline void mei_me_set_pm_domain(struct mei_device *dev);
	135	static inline void mei_me_unset_pm_domain(struct mei_device *dev);
	136	#else
	137	static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
	138	static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
bbd6d050	139	#endif /* CONFIG_PM */
e13fa90c	140
261e071a TW	141	static int mei_me_read_fws(const struct mei_device dev, int where, u32 val)
	142	{
	143	struct pci_dev *pdev = to_pci_dev(dev->dev);
	144
	145	return pci_read_config_dword(pdev, where, val);
	146	}
	147
2703d4b2	148	/**
ce23139c	149	* mei_me_quirk_probe - probe for devices that doesn't valid ME interface
393b148f	150	*
2703d4b2	151	* @pdev: PCI device structure
c919951d	152	* @cfg: per generation config
2703d4b2	153	*
a8605ea2	154	* Return: true if ME Interface is valid, false otherwise
2703d4b2	155	*/
b68301e9	156	static bool mei_me_quirk_probe(struct pci_dev *pdev,
c919951d	157	const struct mei_cfg *cfg)
2703d4b2	158	{
c919951d TW	159	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
	160	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	161	return false;
5e6533a6 TW	162	}
5e6533a6 TW	163
2703d4b2 TW	164	return true;
2703d4b2 TW	165	}
c919951d	166
2703d4b2	167	/**
ce23139c	168	* mei_me_probe - Device Initialization Routine
2703d4b2 TW	169	*
	170	* @pdev: PCI device structure
	171	* @ent: entry in kcs_pci_tbl
	172	*
a8605ea2	173	* Return: 0 on success, <0 on failure.
2703d4b2	174	*/
b68301e9	175	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
2703d4b2	176	{
f5ac3c49	177	const struct mei_cfg *cfg;
2703d4b2	178	struct mei_device *dev;
52c34561	179	struct mei_me_hw *hw;
1fa55b4e	180	unsigned int irqflags;
2703d4b2 TW	181	int err;
2703d4b2 TW	182
f5ac3c49 TW	183	cfg = mei_me_get_cfg(ent->driver_data);
	184	if (!cfg)
	185	return -ENODEV;
2703d4b2	186
c919951d TW	187	if (!mei_me_quirk_probe(pdev, cfg))
c919951d TW	188	return -ENODEV;
2703d4b2	189
2703d4b2	190	/* enable pci dev */
f8a09605	191	err = pcim_enable_device(pdev);
2703d4b2 TW	192	if (err) {
	193	dev_err(&pdev->dev, "failed to enable pci device.\n");
	194	goto end;
	195	}
	196	/* set PCI host mastering */
	197	pci_set_master(pdev);
f8a09605 TW	198	/* pci request regions and mapping IO device memory for mei driver */
f8a09605 TW	199	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
2703d4b2 TW	200	if (err) {
2703d4b2 TW	201	dev_err(&pdev->dev, "failed to get pci regions.\n");
f8a09605	202	goto end;
2703d4b2	203	}
3ecfb168	204
515a2f50	205	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3ecfb168 TW	206	if (err) {
3ecfb168 TW	207	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
f8a09605	208	goto end;
3ecfb168 TW	209	}
3ecfb168 TW	210
2703d4b2	211	/* allocates and initializes the mei dev structure */
95953618	212	dev = mei_me_dev_init(&pdev->dev, cfg, false);
2703d4b2 TW	213	if (!dev) {
2703d4b2 TW	214	err = -ENOMEM;
f8a09605	215	goto end;
2703d4b2	216	}
52c34561	217	hw = to_me_hw(dev);
f8a09605	218	hw->mem_addr = pcim_iomap_table(pdev)[0];
261e071a	219	hw->read_fws = mei_me_read_fws;
f8a09605	220
2703d4b2 TW	221	pci_enable_msi(pdev);
2703d4b2 TW	222
fec874a8 BL	223	hw->irq = pdev->irq;
fec874a8 BL	224
2703d4b2	225	/* request and enable interrupt */
1fa55b4e AU	226	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
	227
	228	err = request_threaded_irq(pdev->irq,
06ecd645 TW	229	mei_me_irq_quick_handler,
06ecd645 TW	230	mei_me_irq_thread_handler,
1fa55b4e	231	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	232	if (err) {
	233	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	234	pdev->irq);
f8a09605	235	goto end;
2703d4b2 TW	236	}
2703d4b2 TW	237
c4d589be	238	if (mei_start(dev)) {
2703d4b2 TW	239	dev_err(&pdev->dev, "init hw failure.\n");
	240	err = -ENODEV;
	241	goto release_irq;
	242	}
	243
180ea05b TW	244	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	245	pm_runtime_use_autosuspend(&pdev->dev);
	246
f3d8e878	247	err = mei_register(dev, &pdev->dev);
2703d4b2	248	if (err)
1f7e489a	249	goto stop;
2703d4b2	250
2703d4b2 TW	251	pci_set_drvdata(pdev, dev);
2703d4b2 TW	252
557909e1 AU	253	/*
	254	* MEI requires to resume from runtime suspend mode
	255	* in order to perform link reset flow upon system suspend.
	256	*/
e0751556	257	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
557909e1	258
e13fa90c	259	/*
b42dc063 AU	260	* ME maps runtime suspend/resume to D0i states,
	261	* hence we need to go around native PCI runtime service which
	262	* eventually brings the device into D3cold/hot state,
	263	* but the mei device cannot wake up from D3 unlike from D0i3.
	264	* To get around the PCI device native runtime pm,
	265	* ME uses runtime pm domain handlers which take precedence
	266	* over the driver's pm handlers.
	267	*/
	268	mei_me_set_pm_domain(dev);
e13fa90c	269
cc365dcf	270	if (mei_pg_is_enabled(dev)) {
180ea05b	271	pm_runtime_put_noidle(&pdev->dev);
cc365dcf TW	272	if (hw->d0i3_supported)
	273	pm_runtime_allow(&pdev->dev);
	274	}
180ea05b	275
c4e87b52	276	dev_dbg(&pdev->dev, "initialization successful.\n");
2703d4b2 TW	277
	278	return 0;
	279
1f7e489a AU	280	stop:
1f7e489a AU	281	mei_stop(dev);
2703d4b2	282	release_irq:
dc844b0d	283	mei_cancel_work(dev);
2703d4b2	284	mei_disable_interrupts(dev);
2703d4b2	285	free_irq(pdev->irq, dev);
2703d4b2	286	end:
2703d4b2 TW	287	dev_err(&pdev->dev, "initialization failed.\n");
	288	return err;
	289	}
	290
5c4c0106 TW	291	/**
	292	* mei_me_shutdown - Device Removal Routine
	293	*
	294	* @pdev: PCI device structure
	295	*
	296	* mei_me_shutdown is called from the reboot notifier
	297	* it's a simplified version of remove so we go down
	298	* faster.
	299	*/
	300	static void mei_me_shutdown(struct pci_dev *pdev)
	301	{
e37db17d	302	struct mei_device *dev = pci_get_drvdata(pdev);
5c4c0106 TW	303
	304	dev_dbg(&pdev->dev, "shutdown\n");
	305	mei_stop(dev);
	306
b42dc063	307	mei_me_unset_pm_domain(dev);
5c4c0106 TW	308
	309	mei_disable_interrupts(dev);
	310	free_irq(pdev->irq, dev);
	311	}
	312
2703d4b2	313	/**
ce23139c	314	* mei_me_remove - Device Removal Routine
2703d4b2 TW	315	*
	316	* @pdev: PCI device structure
	317	*
5c4c0106	318	* mei_me_remove is called by the PCI subsystem to alert the driver
2703d4b2 TW	319	* that it should release a PCI device.
2703d4b2 TW	320	*/
b68301e9	321	static void mei_me_remove(struct pci_dev *pdev)
2703d4b2	322	{
e37db17d	323	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2	324
180ea05b TW	325	if (mei_pg_is_enabled(dev))
	326	pm_runtime_get_noresume(&pdev->dev);
	327
ed6f7ac1	328	dev_dbg(&pdev->dev, "stop\n");
7cb035d9	329	mei_stop(dev);
2703d4b2	330
b42dc063	331	mei_me_unset_pm_domain(dev);
e13fa90c	332
2703d4b2 TW	333	mei_disable_interrupts(dev);
	334
	335	free_irq(pdev->irq, dev);
2703d4b2	336
30e53bb8	337	mei_deregister(dev);
2703d4b2	338	}
f8a09605	339
16833257	340	#ifdef CONFIG_PM_SLEEP
907deab2 AU	341	static int mei_me_pci_prepare(struct device *device)
	342	{
	343	pm_runtime_resume(device);
	344	return 0;
	345	}
	346
b68301e9	347	static int mei_me_pci_suspend(struct device *device)
2703d4b2 TW	348	{
	349	struct pci_dev *pdev = to_pci_dev(device);
	350	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2	351
ed6f7ac1	352	dev_dbg(&pdev->dev, "suspend\n");
2703d4b2	353
7cb035d9 TW	354	mei_stop(dev);
	355
	356	mei_disable_interrupts(dev);
2703d4b2 TW	357
	358	free_irq(pdev->irq, dev);
	359	pci_disable_msi(pdev);
	360
7cb035d9	361	return 0;
2703d4b2 TW	362	}
2703d4b2 TW	363
b68301e9	364	static int mei_me_pci_resume(struct device *device)
2703d4b2 TW	365	{
2703d4b2 TW	366	struct pci_dev *pdev = to_pci_dev(device);
e37db17d	367	struct mei_device *dev = pci_get_drvdata(pdev);
1fa55b4e	368	unsigned int irqflags;
2703d4b2 TW	369	int err;
2703d4b2 TW	370
2703d4b2 TW	371	pci_enable_msi(pdev);
2703d4b2 TW	372
1fa55b4e AU	373	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
1fa55b4e AU	374
2703d4b2	375	/* request and enable interrupt */
1fa55b4e	376	err = request_threaded_irq(pdev->irq,
06ecd645 TW	377	mei_me_irq_quick_handler,
06ecd645 TW	378	mei_me_irq_thread_handler,
1fa55b4e	379	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	380
	381	if (err) {
	382	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	383	pdev->irq);
	384	return err;
	385	}
	386
33ec0826	387	err = mei_restart(dev);
283cb234 TW	388	if (err) {
283cb234 TW	389	free_irq(pdev->irq, dev);
33ec0826	390	return err;
283cb234	391	}
2703d4b2 TW	392
	393	/* Start timer if stopped in suspend */
	394	schedule_delayed_work(&dev->timer_work, HZ);
	395
33ec0826	396	return 0;
2703d4b2	397	}
907deab2 AU	398
	399	static void mei_me_pci_complete(struct device *device)
	400	{
	401	pm_runtime_suspend(device);
	402	}
	403	#else /* CONFIG_PM_SLEEP */
	404
	405	#define mei_me_pci_prepare NULL
	406	#define mei_me_pci_complete NULL
	407
	408	#endif /* !CONFIG_PM_SLEEP */
180ea05b	409
bbd6d050	410	#ifdef CONFIG_PM
180ea05b TW	411	static int mei_me_pm_runtime_idle(struct device *device)
180ea05b TW	412	{
e37db17d	413	struct mei_device *dev = dev_get_drvdata(device);
180ea05b	414
ab81f3f3	415	dev_dbg(device, "rpm: me: runtime_idle\n");
180ea05b	416
180ea05b	417	if (mei_write_is_idle(dev))
d5d83f8a	418	pm_runtime_autosuspend(device);
180ea05b TW	419
	420	return -EBUSY;
	421	}
	422
	423	static int mei_me_pm_runtime_suspend(struct device *device)
	424	{
e37db17d	425	struct mei_device *dev = dev_get_drvdata(device);
180ea05b TW	426	int ret;
180ea05b TW	427
ab81f3f3	428	dev_dbg(device, "rpm: me: runtime suspend\n");
180ea05b	429
180ea05b TW	430	mutex_lock(&dev->device_lock);
	431
	432	if (mei_write_is_idle(dev))
2d1995fc	433	ret = mei_me_pg_enter_sync(dev);
180ea05b TW	434	else
	435	ret = -EAGAIN;
	436
	437	mutex_unlock(&dev->device_lock);
	438
ab81f3f3	439	dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
180ea05b	440
77537ad2 AU	441	if (ret && ret != -EAGAIN)
	442	schedule_work(&dev->reset_work);
	443
180ea05b TW	444	return ret;
	445	}
	446
	447	static int mei_me_pm_runtime_resume(struct device *device)
	448	{
e37db17d	449	struct mei_device *dev = dev_get_drvdata(device);
180ea05b TW	450	int ret;
180ea05b TW	451
ab81f3f3	452	dev_dbg(device, "rpm: me: runtime resume\n");
180ea05b	453
180ea05b TW	454	mutex_lock(&dev->device_lock);
180ea05b TW	455
2d1995fc	456	ret = mei_me_pg_exit_sync(dev);
180ea05b TW	457
	458	mutex_unlock(&dev->device_lock);
	459
ab81f3f3	460	dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
180ea05b	461
77537ad2 AU	462	if (ret)
	463	schedule_work(&dev->reset_work);
	464
180ea05b TW	465	return ret;
180ea05b TW	466	}
e13fa90c TW	467
e13fa90c TW	468	/**
7efceb55	469	* mei_me_set_pm_domain - fill and set pm domain structure for device
e13fa90c TW	470	*
	471	* @dev: mei_device
	472	*/
	473	static inline void mei_me_set_pm_domain(struct mei_device *dev)
	474	{
d08b8fc0	475	struct pci_dev *pdev = to_pci_dev(dev->dev);
e13fa90c TW	476
	477	if (pdev->dev.bus && pdev->dev.bus->pm) {
	478	dev->pg_domain.ops = *pdev->dev.bus->pm;
	479
	480	dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
	481	dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
	482	dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
	483
989561de	484	dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
e13fa90c TW	485	}
	486	}
	487
	488	/**
7efceb55	489	* mei_me_unset_pm_domain - clean pm domain structure for device
e13fa90c TW	490	*
	491	* @dev: mei_device
	492	*/
	493	static inline void mei_me_unset_pm_domain(struct mei_device *dev)
	494	{
	495	/* stop using pm callbacks if any */
989561de	496	dev_pm_domain_set(dev->dev, NULL);
e13fa90c	497	}
180ea05b	498
180ea05b	499	static const struct dev_pm_ops mei_me_pm_ops = {
907deab2 AU	500	.prepare = mei_me_pci_prepare,
907deab2 AU	501	.complete = mei_me_pci_complete,
180ea05b TW	502	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
	503	mei_me_pci_resume)
	504	SET_RUNTIME_PM_OPS(
	505	mei_me_pm_runtime_suspend,
	506	mei_me_pm_runtime_resume,
	507	mei_me_pm_runtime_idle)
	508	};
16833257	509
b68301e9	510	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
2703d4b2	511	#else
b68301e9	512	#define MEI_ME_PM_OPS NULL
180ea05b	513	#endif /* CONFIG_PM */
2703d4b2 TW	514	/*
	515	* PCI driver structure
	516	*/
b68301e9	517	static struct pci_driver mei_me_driver = {
2703d4b2	518	.name = KBUILD_MODNAME,
b68301e9 TW	519	.id_table = mei_me_pci_tbl,
	520	.probe = mei_me_probe,
	521	.remove = mei_me_remove,
5c4c0106	522	.shutdown = mei_me_shutdown,
b68301e9	523	.driver.pm = MEI_ME_PM_OPS,
67de6bf1	524	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
2703d4b2 TW	525	};
2703d4b2 TW	526
b68301e9	527	module_pci_driver(mei_me_driver);
2703d4b2 TW	528
	529	MODULE_AUTHOR("Intel Corporation");
	530	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	531	MODULE_LICENSE("GPL v2");